1 /** @file 2 Register names for PCH SPI device. 3 4 Conventions: 5 6 - Register definition format: 7 Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_RegisterName 8 - Prefix: 9 Definitions beginning with "R_" are registers 10 Definitions beginning with "B_" are bits within registers 11 Definitions beginning with "V_" are meaningful values within the bits 12 Definitions beginning with "S_" are register size 13 Definitions beginning with "N_" are the bit position 14 - [GenerationName]: 15 Three letter acronym of the generation is used (e.g. SKL,KBL,CNL etc.). 16 Register name without GenerationName applies to all generations. 17 - [ComponentName]: 18 This field indicates the component name that the register belongs to (e.g. PCH, SA etc.) 19 Register name without ComponentName applies to all components. 20 Register that is specific to -LP denoted by "_PCH_LP_" in component name. 21 - SubsystemName: 22 This field indicates the subsystem name of the component that the register belongs to 23 (e.g. PCIE, USB, SATA, GPIO, PMC etc.). 24 - RegisterSpace: 25 MEM - MMIO space register of subsystem. 26 IO - IO space register of subsystem. 27 PCR - Private configuration register of subsystem. 28 CFG - PCI configuration space register of subsystem. 29 - RegisterName: 30 Full register name. 31 32 Copyright (c) 2021, Intel Corporation. All rights reserved.<BR> 33 SPDX-License-Identifier: BSD-2-Clause-Patent 34 **/ 35 #ifndef _SPI_REGS_H_ 36 #define _SPI_REGS_H_ 37 38 // 39 // SPI Registers 40 // 41 #define R_SPI_CFG_BAR0 0x10 42 #define B_SPI_CFG_BAR0_MASK 0x0FFF 43 44 #define R_SPI_CFG_BDE 0xD8 45 46 #define R_SPI_CFG_BC 0xDC 47 #define S_SPI_CFG_BC 4 48 #define N_SPI_CFG_BC_ASE_BWP 11 49 #define B_SPI_CFG_BC_ASE_BWP BIT11 50 #define N_SPI_CFG_BC_ASYNC_SS 10 51 #define B_SPI_CFG_BC_ASYNC_SS BIT10 52 #define N_SPI_CFG_BC_SYNC_SS 8 53 #define B_SPI_CFG_BC_SYNC_SS BIT8 54 #define B_SPI_CFG_BC_BILD BIT7 55 #define B_SPI_CFG_BC_BBS BIT6 ///< Boot BIOS strap 56 #define N_SPI_CFG_BC_BBS 6 57 #define V_SPI_CFG_BC_BBS_SPI 0 ///< Boot BIOS strapped to SPI 58 #define B_SPI_CFG_BC_EISS BIT5 ///< Enable InSMM.STS 59 #define B_SPI_CFG_BC_TSS BIT4 60 #define B_SPI_CFG_BC_SRC (BIT3 | BIT2) 61 #define N_SPI_CFG_BC_SRC 2 62 #define V_SPI_CFG_BC_SRC_PREF_DIS_CACHE_DIS 0x01 ///< No prefetching and no caching 63 #define B_SPI_CFG_BC_LE BIT1 ///< Lock Enable 64 #define N_SPI_CFG_BC_BLE 1 65 #define B_SPI_CFG_BC_WPD BIT0 ///< Write Protect Disable 66 67 // 68 // BIOS Flash Program Registers (based on SPI_BAR0) 69 // 70 #define R_SPI_MEM_HSFSC 0x04 ///< Hardware Sequencing Flash Status and Control Register(32bits) 71 #define B_SPI_MEM_HSFSC_FDBC_MASK 0x3F000000 ///< Flash Data Byte Count ( <= 64), Count = (Value in this field) + 1. 72 #define N_SPI_MEM_HSFSC_FDBC 24 73 #define B_SPI_MEM_HSFSC_CYCLE_MASK 0x001E0000 ///< Flash Cycle. 74 #define N_SPI_MEM_HSFSC_CYCLE 17 75 #define V_SPI_MEM_HSFSC_CYCLE_READ 0 ///< Flash Cycle Read 76 #define V_SPI_MEM_HSFSC_CYCLE_WRITE 2 ///< Flash Cycle Write 77 #define V_SPI_MEM_HSFSC_CYCLE_4K_ERASE 3 ///< Flash Cycle 4K Block Erase 78 #define V_SPI_MEM_HSFSC_CYCLE_64K_ERASE 4 ///< Flash Cycle 64K Sector Erase 79 #define V_SPI_MEM_HSFSC_CYCLE_READ_SFDP 5 ///< Flash Cycle Read SFDP 80 #define V_SPI_MEM_HSFSC_CYCLE_READ_JEDEC_ID 6 ///< Flash Cycle Read JEDEC ID 81 #define V_SPI_MEM_HSFSC_CYCLE_WRITE_STATUS 7 ///< Flash Cycle Write Status 82 #define V_SPI_MEM_HSFSC_CYCLE_READ_STATUS 8 ///< Flash Cycle Read Status 83 #define B_SPI_MEM_HSFSC_CYCLE_FGO BIT16 ///< Flash Cycle Go. 84 #define B_SPI_MEM_HSFSC_FLOCKDN BIT15 ///< Flash Configuration Lock-Down 85 #define B_SPI_MEM_HSFSC_FDV BIT14 ///< Flash Descriptor Valid, once valid software can use hareware sequencing regs 86 #define B_SPI_MEM_HSFSC_FDOPSS BIT13 ///< Flash Descriptor Override Pin-Strap Status 87 #define B_SPI_MEM_HSFSC_WRSDIS BIT11 ///< Write Status Disable 88 #define B_SPI_MEM_HSFSC_SAF_MODE_ACTIVE BIT7 ///< Indicates flash is attached either directly to the PCH via the SPI bus or EC/BMC 89 #define B_SPI_MEM_HSFSC_SCIP BIT5 ///< SPI cycle in progress 90 #define B_SPI_MEM_HSFSC_SAF_DLE BIT4 ///< SAF Data length error 91 #define B_SPI_MEM_HSFSC_SAF_ERROR BIT3 ///< SAF Error 92 #define B_SPI_MEM_HSFSC_AEL BIT2 ///< Access Error Log 93 #define B_SPI_MEM_HSFSC_FCERR BIT1 ///< Flash Cycle Error 94 #define B_SPI_MEM_HSFSC_FDONE BIT0 ///< Flash Cycle Done 95 #define R_SPI_MEM_FADDR 0x08 ///< SPI Flash Address 96 #define B_SPI_MEM_FADDR_MASK 0x07FFFFFF ///< SPI Flash Address Mask (0~26bit) 97 #define R_SPI_MEM_DLOCK 0x0C ///< Discrete Lock Bits 98 #define B_SPI_MEM_DLOCK_PR0LOCKDN BIT8 ///< PR0LOCKDN 99 #define R_SPI_MEM_FDATA00 0x10 ///< SPI Data 00 (32 bits) 100 #define R_SPI_MEM_FRAP 0x50 ///< Flash Region Access Permissions Register 101 #define B_SPI_MEM_FRAP_BRWA_MASK 0x0000FF00 ///< BIOS Region Write Access MASK, Region0~7 - 0: Flash Descriptor; 1: BIOS; 2: ME; 3: GbE; 4: PlatformData 102 #define N_SPI_MEM_FRAP_BRWA 8 ///< BIOS Region Write Access bit position 103 #define B_SPI_MEM_FRAP_BRRA_MASK 0x000000FF ///< BIOS Region Read Access MASK, Region0~7 - 0: Flash Descriptor; 1: BIOS; 2: ME; 3: GbE; 4: PlatformData 104 #define B_SPI_MEM_FRAP_BMRAG_MASK 0x00FF0000 ///< BIOS Master Read Access Grant 105 #define B_SPI_MEM_FRAP_BMWAG_MASK 0xFF000000 ///< BIOS Master Write Access Grant 106 #define R_SPI_MEM_FREG0_FLASHD 0x54 ///< Flash Region 0(Flash Descriptor)(32bits) 107 #define R_SPI_MEM_FREG3_GBE 0x60 ///< Flash Region 3(GbE)(32bits) 108 #define S_SPI_MEM_FREGX 4 ///< Size of Flash Region register 109 #define B_SPI_MEM_FREGX_LIMIT_MASK 0x7FFF0000 ///< Flash Region Limit [30:16] represents [26:12], [11:0] are assumed to be FFFh 110 #define N_SPI_MEM_FREGX_LIMIT 16 ///< Region limit bit position 111 #define N_SPI_MEM_FREGX_LIMIT_REPR 12 ///< Region limit bit represents position 112 #define B_SPI_MEM_FREGX_BASE_MASK 0x00007FFF ///< Flash Region Base, [14:0] represents [26:12] 113 #define N_SPI_MEM_FREGX_BASE 0 ///< Region base bit position 114 #define N_SPI_MEM_FREGX_BASE_REPR 12 ///< Region base bit represents position 115 #define R_SPI_MEM_PR0 0x84 ///< Protected Region 0 Register 116 #define S_SPI_MEM_PRX 4 ///< Protected Region X Register size 117 #define B_SPI_MEM_PRX_WPE BIT31 ///< Write Protection Enable 118 #define B_SPI_MEM_PRX_PRL_MASK 0x7FFF0000 ///< Protected Range Limit Mask, [30:16] here represents upper limit of address [26:12] 119 #define N_SPI_MEM_PRX_PRL 16 ///< Protected Range Limit bit position 120 #define B_SPI_MEM_PRX_RPE BIT15 ///< Read Protection Enable 121 #define B_SPI_MEM_PRX_PRB_MASK 0x00007FFF ///< Protected Range Base Mask, [14:0] here represents base limit of address [26:12] 122 #define N_SPI_MEM_PRX_PRB 0 ///< Protected Range Base bit position 123 #define R_SPI_MEM_FDOC 0xB4 ///< Flash Descriptor Observability Control Register(32 bits) 124 #define B_SPI_MEM_FDOC_FDSS_MASK (BIT14 | BIT13 | BIT12) ///< Flash Descritor Section Select 125 #define V_SPI_MEM_FDOC_FDSS_FSDM 0x0000 ///< Flash Signature and Descriptor Map 126 #define V_SPI_MEM_FDOC_FDSS_COMP 0x1000 ///< Component 127 #define V_SPI_MEM_FDOC_FDSS_MSTR 0x3000 ///< Master 128 #define B_SPI_MEM_FDOC_FDSI_MASK 0x0FFC ///< Flash Descriptor Section Index 129 #define R_SPI_MEM_FDOD 0xB8 ///< Flash Descriptor Observability Data Register(32 bits) 130 #define R_SPI_MEM_SFDP0_VSCC0 0xC4 ///< Vendor Specific Component Capabilities Register(32 bits) 131 #define B_SPI_MEM_SFDPX_VSCCX_CPPTV BIT31 ///< Component Property Parameter Table Valid 132 #define B_SPI_MEM_SFDP0_VSCC0_VCL BIT30 ///< Vendor Component Lock 133 #define B_SPI_MEM_SFDPX_VSCCX_EO_64K BIT29 ///< 64k Erase valid (EO_64k_valid) 134 #define R_SPI_MEM_SFDP1_VSCC1 0xC8 ///< Vendor Specific Component Capabilities Register(32 bits) 135 136 #endif 137