1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ 2|* *| 3|* Global Instruction Selector for the X86 target *| 4|* *| 5|* Automatically generated file, do not edit! *| 6|* *| 7\*===----------------------------------------------------------------------===*/ 8 9#ifdef GET_GLOBALISEL_PREDICATE_BITSET 10const unsigned MAX_SUBTARGET_PREDICATES = 114; 11using PredicateBitset = llvm::PredicateBitsetImpl<MAX_SUBTARGET_PREDICATES>; 12#endif // ifdef GET_GLOBALISEL_PREDICATE_BITSET 13 14#ifdef GET_GLOBALISEL_TEMPORARIES_DECL 15 mutable MatcherState State; 16 typedef ComplexRendererFns(X86InstructionSelector::*ComplexMatcherMemFn)(MachineOperand &) const; 17 typedef void(X86InstructionSelector::*CustomRendererFn)(MachineInstrBuilder &, const MachineInstr&, int) const; 18 const ISelInfoTy<PredicateBitset, ComplexMatcherMemFn, CustomRendererFn> ISelInfo; 19 static X86InstructionSelector::ComplexMatcherMemFn ComplexPredicateFns[]; 20 static X86InstructionSelector::CustomRendererFn CustomRenderers[]; 21 bool testImmPredicate_I64(unsigned PredicateID, int64_t Imm) const override; 22 bool testImmPredicate_APInt(unsigned PredicateID, const APInt &Imm) const override; 23 bool testImmPredicate_APFloat(unsigned PredicateID, const APFloat &Imm) const override; 24 const int64_t *getMatchTable() const override; 25 bool testMIPredicate_MI(unsigned PredicateID, const MachineInstr &MI) const override; 26#endif // ifdef GET_GLOBALISEL_TEMPORARIES_DECL 27 28#ifdef GET_GLOBALISEL_TEMPORARIES_INIT 29, State(0), 30ISelInfo(TypeObjects, NumTypeObjects, FeatureBitsets, ComplexPredicateFns, CustomRenderers) 31#endif // ifdef GET_GLOBALISEL_TEMPORARIES_INIT 32 33#ifdef GET_GLOBALISEL_IMPL 34// Bits for subtarget features that participate in instruction matching. 35enum SubtargetFeatureBits : uint8_t { 36 Feature_TruePredicateBit = 49, 37 Feature_HasCMovBit = 20, 38 Feature_NoCMovBit = 102, 39 Feature_HasMMXBit = 83, 40 Feature_Has3DNowBit = 85, 41 Feature_HasSSE1Bit = 35, 42 Feature_UseSSE1Bit = 43, 43 Feature_HasSSE2Bit = 36, 44 Feature_UseSSE2Bit = 44, 45 Feature_HasSSE3Bit = 27, 46 Feature_UseSSE3Bit = 52, 47 Feature_HasSSSE3Bit = 84, 48 Feature_UseSSSE3Bit = 53, 49 Feature_UseSSE41Bit = 50, 50 Feature_HasSSE42Bit = 57, 51 Feature_UseSSE42Bit = 56, 52 Feature_HasSSE4ABit = 66, 53 Feature_NoAVXBit = 62, 54 Feature_HasAVXBit = 45, 55 Feature_HasAVX2Bit = 39, 56 Feature_HasAVX1OnlyBit = 37, 57 Feature_HasAVX512Bit = 69, 58 Feature_UseAVXBit = 41, 59 Feature_NoAVX512Bit = 32, 60 Feature_HasCDIBit = 73, 61 Feature_HasVPOPCNTDQBit = 77, 62 Feature_HasERIBit = 76, 63 Feature_HasDQIBit = 71, 64 Feature_NoDQIBit = 54, 65 Feature_HasBWIBit = 72, 66 Feature_NoBWIBit = 51, 67 Feature_HasVLXBit = 70, 68 Feature_NoVLXBit = 31, 69 Feature_NoVLX_Or_NoBWIBit = 48, 70 Feature_HasVNNIBit = 79, 71 Feature_HasVP2INTERSECTBit = 81, 72 Feature_HasBF16Bit = 82, 73 Feature_HasBITALGBit = 80, 74 Feature_HasPOPCNTBit = 55, 75 Feature_HasAESBit = 59, 76 Feature_HasVAESBit = 61, 77 Feature_NoVLX_Or_NoVAESBit = 60, 78 Feature_HasFXSRBit = 28, 79 Feature_HasXSAVEBit = 91, 80 Feature_HasXSAVEOPTBit = 92, 81 Feature_HasXSAVECBit = 93, 82 Feature_HasXSAVESBit = 94, 83 Feature_HasPCLMULBit = 63, 84 Feature_NoVLX_Or_NoVPCLMULQDQBit = 64, 85 Feature_HasVPCLMULQDQBit = 65, 86 Feature_HasGFNIBit = 68, 87 Feature_HasFMABit = 29, 88 Feature_HasFMA4Bit = 33, 89 Feature_NoFMA4Bit = 30, 90 Feature_HasXOPBit = 34, 91 Feature_HasTBMBit = 9, 92 Feature_NoTBMBit = 106, 93 Feature_HasLWPBit = 10, 94 Feature_HasMOVBEBit = 3, 95 Feature_HasRDRANDBit = 4, 96 Feature_HasF16CBit = 67, 97 Feature_HasFSGSBaseBit = 95, 98 Feature_HasLZCNTBit = 6, 99 Feature_HasBMIBit = 7, 100 Feature_HasBMI2Bit = 8, 101 Feature_NoBMI2Bit = 105, 102 Feature_HasVBMIBit = 74, 103 Feature_HasVBMI2Bit = 78, 104 Feature_HasIFMABit = 75, 105 Feature_HasRTMBit = 89, 106 Feature_HasSHABit = 58, 107 Feature_HasRDSEEDBit = 5, 108 Feature_HasSSEPrefetchBit = 46, 109 Feature_NoSSEPrefetchBit = 86, 110 Feature_HasPrefetchWBit = 87, 111 Feature_HasPREFETCHWT1Bit = 88, 112 Feature_HasLAHFSAHFBit = 2, 113 Feature_HasMWAITXBit = 11, 114 Feature_HasCLDEMOTEBit = 18, 115 Feature_HasMOVDIRIBit = 13, 116 Feature_HasMOVDIR64BBit = 14, 117 Feature_HasPTWRITEBit = 98, 118 Feature_FPStackf32Bit = 25, 119 Feature_FPStackf64Bit = 26, 120 Feature_HasCLFLUSHOPTBit = 16, 121 Feature_HasCLWBBit = 17, 122 Feature_HasWBNOINVDBit = 90, 123 Feature_HasRDPIDBit = 97, 124 Feature_HasWAITPKGBit = 12, 125 Feature_HasINVPCIDBit = 96, 126 Feature_HasCmpxchg8bBit = 103, 127 Feature_HasCmpxchg16bBit = 104, 128 Feature_HasENQCMDBit = 15, 129 Feature_Not64BitModeBit = 0, 130 Feature_In64BitModeBit = 1, 131 Feature_IsLP64Bit = 100, 132 Feature_NotLP64Bit = 99, 133 Feature_NotWin64WithoutFPBit = 101, 134 Feature_IsPS4Bit = 109, 135 Feature_NotPS4Bit = 108, 136 Feature_KernelCodeBit = 110, 137 Feature_NearDataBit = 112, 138 Feature_IsNotPICBit = 111, 139 Feature_OptForSizeBit = 40, 140 Feature_OptForMinSizeBit = 38, 141 Feature_OptForSpeedBit = 107, 142 Feature_UseIncDecBit = 19, 143 Feature_NoSSE41_Or_OptForSizeBit = 42, 144 Feature_CallImmAddrBit = 113, 145 Feature_FavorMemIndirectCallBit = 21, 146 Feature_HasFastSHLDRotateBit = 24, 147 Feature_HasMFenceBit = 47, 148 Feature_UseRetpolineIndirectCallsBit = 23, 149 Feature_NotUseRetpolineIndirectCallsBit = 22, 150}; 151 152PredicateBitset X86InstructionSelector:: 153computeAvailableModuleFeatures(const X86Subtarget *Subtarget) const { 154 PredicateBitset Features; 155 if (true) 156 Features.set(Feature_TruePredicateBit); 157 if (Subtarget->hasCMov()) 158 Features.set(Feature_HasCMovBit); 159 if (!Subtarget->hasCMov()) 160 Features.set(Feature_NoCMovBit); 161 if (Subtarget->hasMMX()) 162 Features.set(Feature_HasMMXBit); 163 if (Subtarget->has3DNow()) 164 Features.set(Feature_Has3DNowBit); 165 if (Subtarget->hasSSE1()) 166 Features.set(Feature_HasSSE1Bit); 167 if (Subtarget->hasSSE1() && !Subtarget->hasAVX()) 168 Features.set(Feature_UseSSE1Bit); 169 if (Subtarget->hasSSE2()) 170 Features.set(Feature_HasSSE2Bit); 171 if (Subtarget->hasSSE2() && !Subtarget->hasAVX()) 172 Features.set(Feature_UseSSE2Bit); 173 if (Subtarget->hasSSE3()) 174 Features.set(Feature_HasSSE3Bit); 175 if (Subtarget->hasSSE3() && !Subtarget->hasAVX()) 176 Features.set(Feature_UseSSE3Bit); 177 if (Subtarget->hasSSSE3()) 178 Features.set(Feature_HasSSSE3Bit); 179 if (Subtarget->hasSSSE3() && !Subtarget->hasAVX()) 180 Features.set(Feature_UseSSSE3Bit); 181 if (Subtarget->hasSSE41() && !Subtarget->hasAVX()) 182 Features.set(Feature_UseSSE41Bit); 183 if (Subtarget->hasSSE42()) 184 Features.set(Feature_HasSSE42Bit); 185 if (Subtarget->hasSSE42() && !Subtarget->hasAVX()) 186 Features.set(Feature_UseSSE42Bit); 187 if (Subtarget->hasSSE4A()) 188 Features.set(Feature_HasSSE4ABit); 189 if (!Subtarget->hasAVX()) 190 Features.set(Feature_NoAVXBit); 191 if (Subtarget->hasAVX()) 192 Features.set(Feature_HasAVXBit); 193 if (Subtarget->hasAVX2()) 194 Features.set(Feature_HasAVX2Bit); 195 if (Subtarget->hasAVX() && !Subtarget->hasAVX2()) 196 Features.set(Feature_HasAVX1OnlyBit); 197 if (Subtarget->hasAVX512()) 198 Features.set(Feature_HasAVX512Bit); 199 if (Subtarget->hasAVX() && !Subtarget->hasAVX512()) 200 Features.set(Feature_UseAVXBit); 201 if (!Subtarget->hasAVX512()) 202 Features.set(Feature_NoAVX512Bit); 203 if (Subtarget->hasCDI()) 204 Features.set(Feature_HasCDIBit); 205 if (Subtarget->hasVPOPCNTDQ()) 206 Features.set(Feature_HasVPOPCNTDQBit); 207 if (Subtarget->hasERI()) 208 Features.set(Feature_HasERIBit); 209 if (Subtarget->hasDQI()) 210 Features.set(Feature_HasDQIBit); 211 if (!Subtarget->hasDQI()) 212 Features.set(Feature_NoDQIBit); 213 if (Subtarget->hasBWI()) 214 Features.set(Feature_HasBWIBit); 215 if (!Subtarget->hasBWI()) 216 Features.set(Feature_NoBWIBit); 217 if (Subtarget->hasVLX()) 218 Features.set(Feature_HasVLXBit); 219 if (!Subtarget->hasVLX()) 220 Features.set(Feature_NoVLXBit); 221 if (!Subtarget->hasVLX() || !Subtarget->hasBWI()) 222 Features.set(Feature_NoVLX_Or_NoBWIBit); 223 if (Subtarget->hasVNNI()) 224 Features.set(Feature_HasVNNIBit); 225 if (Subtarget->hasVP2INTERSECT()) 226 Features.set(Feature_HasVP2INTERSECTBit); 227 if (Subtarget->hasBF16()) 228 Features.set(Feature_HasBF16Bit); 229 if (Subtarget->hasBITALG()) 230 Features.set(Feature_HasBITALGBit); 231 if (Subtarget->hasPOPCNT()) 232 Features.set(Feature_HasPOPCNTBit); 233 if (Subtarget->hasAES()) 234 Features.set(Feature_HasAESBit); 235 if (Subtarget->hasVAES()) 236 Features.set(Feature_HasVAESBit); 237 if (!Subtarget->hasVLX() || !Subtarget->hasVAES()) 238 Features.set(Feature_NoVLX_Or_NoVAESBit); 239 if (Subtarget->hasFXSR()) 240 Features.set(Feature_HasFXSRBit); 241 if (Subtarget->hasXSAVE()) 242 Features.set(Feature_HasXSAVEBit); 243 if (Subtarget->hasXSAVEOPT()) 244 Features.set(Feature_HasXSAVEOPTBit); 245 if (Subtarget->hasXSAVEC()) 246 Features.set(Feature_HasXSAVECBit); 247 if (Subtarget->hasXSAVES()) 248 Features.set(Feature_HasXSAVESBit); 249 if (Subtarget->hasPCLMUL()) 250 Features.set(Feature_HasPCLMULBit); 251 if (!Subtarget->hasVLX() || !Subtarget->hasVPCLMULQDQ()) 252 Features.set(Feature_NoVLX_Or_NoVPCLMULQDQBit); 253 if (Subtarget->hasVPCLMULQDQ()) 254 Features.set(Feature_HasVPCLMULQDQBit); 255 if (Subtarget->hasGFNI()) 256 Features.set(Feature_HasGFNIBit); 257 if (Subtarget->hasFMA()) 258 Features.set(Feature_HasFMABit); 259 if (Subtarget->hasFMA4()) 260 Features.set(Feature_HasFMA4Bit); 261 if (!Subtarget->hasFMA4()) 262 Features.set(Feature_NoFMA4Bit); 263 if (Subtarget->hasXOP()) 264 Features.set(Feature_HasXOPBit); 265 if (Subtarget->hasTBM()) 266 Features.set(Feature_HasTBMBit); 267 if (!Subtarget->hasTBM()) 268 Features.set(Feature_NoTBMBit); 269 if (Subtarget->hasLWP()) 270 Features.set(Feature_HasLWPBit); 271 if (Subtarget->hasMOVBE()) 272 Features.set(Feature_HasMOVBEBit); 273 if (Subtarget->hasRDRAND()) 274 Features.set(Feature_HasRDRANDBit); 275 if (Subtarget->hasF16C()) 276 Features.set(Feature_HasF16CBit); 277 if (Subtarget->hasFSGSBase()) 278 Features.set(Feature_HasFSGSBaseBit); 279 if (Subtarget->hasLZCNT()) 280 Features.set(Feature_HasLZCNTBit); 281 if (Subtarget->hasBMI()) 282 Features.set(Feature_HasBMIBit); 283 if (Subtarget->hasBMI2()) 284 Features.set(Feature_HasBMI2Bit); 285 if (!Subtarget->hasBMI2()) 286 Features.set(Feature_NoBMI2Bit); 287 if (Subtarget->hasVBMI()) 288 Features.set(Feature_HasVBMIBit); 289 if (Subtarget->hasVBMI2()) 290 Features.set(Feature_HasVBMI2Bit); 291 if (Subtarget->hasIFMA()) 292 Features.set(Feature_HasIFMABit); 293 if (Subtarget->hasRTM()) 294 Features.set(Feature_HasRTMBit); 295 if (Subtarget->hasSHA()) 296 Features.set(Feature_HasSHABit); 297 if (Subtarget->hasRDSEED()) 298 Features.set(Feature_HasRDSEEDBit); 299 if (Subtarget->hasSSEPrefetch()) 300 Features.set(Feature_HasSSEPrefetchBit); 301 if (!Subtarget->hasSSEPrefetch()) 302 Features.set(Feature_NoSSEPrefetchBit); 303 if (Subtarget->hasPRFCHW()) 304 Features.set(Feature_HasPrefetchWBit); 305 if (Subtarget->hasPREFETCHWT1()) 306 Features.set(Feature_HasPREFETCHWT1Bit); 307 if (Subtarget->hasLAHFSAHF()) 308 Features.set(Feature_HasLAHFSAHFBit); 309 if (Subtarget->hasMWAITX()) 310 Features.set(Feature_HasMWAITXBit); 311 if (Subtarget->hasCLDEMOTE()) 312 Features.set(Feature_HasCLDEMOTEBit); 313 if (Subtarget->hasMOVDIRI()) 314 Features.set(Feature_HasMOVDIRIBit); 315 if (Subtarget->hasMOVDIR64B()) 316 Features.set(Feature_HasMOVDIR64BBit); 317 if (Subtarget->hasPTWRITE()) 318 Features.set(Feature_HasPTWRITEBit); 319 if (!Subtarget->hasSSE1()) 320 Features.set(Feature_FPStackf32Bit); 321 if (!Subtarget->hasSSE2()) 322 Features.set(Feature_FPStackf64Bit); 323 if (Subtarget->hasCLFLUSHOPT()) 324 Features.set(Feature_HasCLFLUSHOPTBit); 325 if (Subtarget->hasCLWB()) 326 Features.set(Feature_HasCLWBBit); 327 if (Subtarget->hasWBNOINVD()) 328 Features.set(Feature_HasWBNOINVDBit); 329 if (Subtarget->hasRDPID()) 330 Features.set(Feature_HasRDPIDBit); 331 if (Subtarget->hasWAITPKG()) 332 Features.set(Feature_HasWAITPKGBit); 333 if (Subtarget->hasINVPCID()) 334 Features.set(Feature_HasINVPCIDBit); 335 if (Subtarget->hasCmpxchg8b()) 336 Features.set(Feature_HasCmpxchg8bBit); 337 if (Subtarget->hasCmpxchg16b()) 338 Features.set(Feature_HasCmpxchg16bBit); 339 if (Subtarget->hasENQCMD()) 340 Features.set(Feature_HasENQCMDBit); 341 if (!Subtarget->is64Bit()) 342 Features.set(Feature_Not64BitModeBit); 343 if (Subtarget->is64Bit()) 344 Features.set(Feature_In64BitModeBit); 345 if (Subtarget->isTarget64BitLP64()) 346 Features.set(Feature_IsLP64Bit); 347 if (!Subtarget->isTarget64BitLP64()) 348 Features.set(Feature_NotLP64Bit); 349 if (Subtarget->isTargetPS4()) 350 Features.set(Feature_IsPS4Bit); 351 if (!Subtarget->isTargetPS4()) 352 Features.set(Feature_NotPS4Bit); 353 if (TM.getCodeModel() == CodeModel::Kernel) 354 Features.set(Feature_KernelCodeBit); 355 if (TM.getCodeModel() == CodeModel::Small ||TM.getCodeModel() == CodeModel::Kernel) 356 Features.set(Feature_NearDataBit); 357 if (!TM.isPositionIndependent()) 358 Features.set(Feature_IsNotPICBit); 359 if (Subtarget->isLegalToCallImmediateAddr()) 360 Features.set(Feature_CallImmAddrBit); 361 if (!Subtarget->slowTwoMemOps()) 362 Features.set(Feature_FavorMemIndirectCallBit); 363 if (Subtarget->hasFastSHLDRotate()) 364 Features.set(Feature_HasFastSHLDRotateBit); 365 if (Subtarget->hasMFence()) 366 Features.set(Feature_HasMFenceBit); 367 if (Subtarget->useRetpolineIndirectCalls()) 368 Features.set(Feature_UseRetpolineIndirectCallsBit); 369 if (!Subtarget->useRetpolineIndirectCalls()) 370 Features.set(Feature_NotUseRetpolineIndirectCallsBit); 371 return Features; 372} 373 374void X86InstructionSelector::setupGeneratedPerFunctionState(MachineFunction &MF) { 375 AvailableFunctionFeatures = computeAvailableFunctionFeatures((const X86Subtarget*)&MF.getSubtarget(), &MF); 376} 377static bool shouldOptForSize(const MachineFunction *MF) { 378 return MF->getFunction().hasOptSize(); 379} 380 381PredicateBitset X86InstructionSelector:: 382computeAvailableFunctionFeatures(const X86Subtarget *Subtarget, const MachineFunction *MF) const { 383 PredicateBitset Features; 384 if (!Subtarget->isTargetWin64() ||Subtarget->getFrameLowering()->hasFP(*MF)) 385 Features.set(Feature_NotWin64WithoutFPBit); 386 if (shouldOptForSize(MF)) 387 Features.set(Feature_OptForSizeBit); 388 if (MF->getFunction().hasMinSize()) 389 Features.set(Feature_OptForMinSizeBit); 390 if (!shouldOptForSize(MF)) 391 Features.set(Feature_OptForSpeedBit); 392 if (!Subtarget->slowIncDec() || shouldOptForSize(MF)) 393 Features.set(Feature_UseIncDecBit); 394 if (shouldOptForSize(MF) || !Subtarget->hasSSE41()) 395 Features.set(Feature_NoSSE41_Or_OptForSizeBit); 396 return Features; 397} 398 399// LLT Objects. 400enum { 401 GILLT_s1, 402 GILLT_s8, 403 GILLT_s16, 404 GILLT_s32, 405 GILLT_s64, 406 GILLT_s80, 407 GILLT_s128, 408 GILLT_v2s1, 409 GILLT_v2s64, 410 GILLT_v4s1, 411 GILLT_v4s32, 412 GILLT_v4s64, 413 GILLT_v8s1, 414 GILLT_v8s16, 415 GILLT_v8s32, 416 GILLT_v8s64, 417 GILLT_v16s1, 418 GILLT_v16s8, 419 GILLT_v16s16, 420 GILLT_v16s32, 421 GILLT_v32s1, 422 GILLT_v32s8, 423 GILLT_v32s16, 424 GILLT_v64s1, 425 GILLT_v64s8, 426}; 427const static size_t NumTypeObjects = 25; 428const static LLT TypeObjects[] = { 429 LLT::scalar(1), 430 LLT::scalar(8), 431 LLT::scalar(16), 432 LLT::scalar(32), 433 LLT::scalar(64), 434 LLT::scalar(80), 435 LLT::scalar(128), 436 LLT::vector(2, 1), 437 LLT::vector(2, 64), 438 LLT::vector(4, 1), 439 LLT::vector(4, 32), 440 LLT::vector(4, 64), 441 LLT::vector(8, 1), 442 LLT::vector(8, 16), 443 LLT::vector(8, 32), 444 LLT::vector(8, 64), 445 LLT::vector(16, 1), 446 LLT::vector(16, 8), 447 LLT::vector(16, 16), 448 LLT::vector(16, 32), 449 LLT::vector(32, 1), 450 LLT::vector(32, 8), 451 LLT::vector(32, 16), 452 LLT::vector(64, 1), 453 LLT::vector(64, 8), 454}; 455 456// Feature bitsets. 457enum { 458 GIFBS_Invalid, 459 GIFBS_FPStackf32, 460 GIFBS_FPStackf64, 461 GIFBS_Has3DNow, 462 GIFBS_HasAVX, 463 GIFBS_HasAVX1Only, 464 GIFBS_HasAVX2, 465 GIFBS_HasAVX512, 466 GIFBS_HasBITALG, 467 GIFBS_HasBMI, 468 GIFBS_HasBMI2, 469 GIFBS_HasBWI, 470 GIFBS_HasCDI, 471 GIFBS_HasDQI, 472 GIFBS_HasLWP, 473 GIFBS_HasMFence, 474 GIFBS_HasMMX, 475 GIFBS_HasMOVBE, 476 GIFBS_HasMWAITX, 477 GIFBS_HasPTWRITE, 478 GIFBS_HasRTM, 479 GIFBS_HasSHA, 480 GIFBS_HasSSE1, 481 GIFBS_HasSSE2, 482 GIFBS_HasSSE3, 483 GIFBS_HasSSE42, 484 GIFBS_HasSSE4A, 485 GIFBS_HasTBM, 486 GIFBS_HasVLX, 487 GIFBS_HasVPOPCNTDQ, 488 GIFBS_HasWAITPKG, 489 GIFBS_HasWBNOINVD, 490 GIFBS_HasXOP, 491 GIFBS_HasXSAVE, 492 GIFBS_In64BitMode, 493 GIFBS_NoDQI, 494 GIFBS_Not64BitMode, 495 GIFBS_UseAVX, 496 GIFBS_UseIncDec, 497 GIFBS_UseSSE1, 498 GIFBS_UseSSE2, 499 GIFBS_UseSSE41, 500 GIFBS_UseSSSE3, 501 GIFBS_HasAES_HasAVX, 502 GIFBS_HasAES_NoAVX, 503 GIFBS_HasAVX_In64BitMode, 504 GIFBS_HasAVX_NoVLX, 505 GIFBS_HasAVX_NoVLX_Or_NoBWI, 506 GIFBS_HasAVX_Not64BitMode, 507 GIFBS_HasAVX2_NoVLX, 508 GIFBS_HasAVX2_NoVLX_Or_NoBWI, 509 GIFBS_HasAVX512_HasVAES, 510 GIFBS_HasAVX512_HasVLX, 511 GIFBS_HasAVX512_HasVPCLMULQDQ, 512 GIFBS_HasAVX512_NoBWI, 513 GIFBS_HasBITALG_HasVLX, 514 GIFBS_HasBWI_HasVLX, 515 GIFBS_HasCDI_HasVLX, 516 GIFBS_HasDQI_HasVLX, 517 GIFBS_HasDQI_NoBWI, 518 GIFBS_HasFSGSBase_In64BitMode, 519 GIFBS_HasPCLMUL_NoAVX, 520 GIFBS_HasPTWRITE_In64BitMode, 521 GIFBS_HasRDPID_Not64BitMode, 522 GIFBS_HasVAES_HasVLX, 523 GIFBS_HasVAES_NoVLX, 524 GIFBS_HasVLX_HasVPCLMULQDQ, 525 GIFBS_HasVLX_HasVPOPCNTDQ, 526 GIFBS_HasVPCLMULQDQ_NoVLX, 527 GIFBS_HasWAITPKG_In64BitMode, 528 GIFBS_HasWAITPKG_Not64BitMode, 529 GIFBS_In64BitMode_UseSSE2, 530 GIFBS_Not64BitMode_OptForSize, 531 GIFBS_Not64BitMode_UseSSE2, 532 GIFBS_NotWin64WithoutFP_OptForMinSize, 533 GIFBS_HasAES_HasAVX_NoVLX_Or_NoVAES, 534 GIFBS_HasAVX_HasPCLMUL_NoVLX_Or_NoVPCLMULQDQ, 535 GIFBS_HasDQI_HasVLX_NoBWI, 536}; 537const static PredicateBitset FeatureBitsets[] { 538 {}, // GIFBS_Invalid 539 {Feature_FPStackf32Bit, }, 540 {Feature_FPStackf64Bit, }, 541 {Feature_Has3DNowBit, }, 542 {Feature_HasAVXBit, }, 543 {Feature_HasAVX1OnlyBit, }, 544 {Feature_HasAVX2Bit, }, 545 {Feature_HasAVX512Bit, }, 546 {Feature_HasBITALGBit, }, 547 {Feature_HasBMIBit, }, 548 {Feature_HasBMI2Bit, }, 549 {Feature_HasBWIBit, }, 550 {Feature_HasCDIBit, }, 551 {Feature_HasDQIBit, }, 552 {Feature_HasLWPBit, }, 553 {Feature_HasMFenceBit, }, 554 {Feature_HasMMXBit, }, 555 {Feature_HasMOVBEBit, }, 556 {Feature_HasMWAITXBit, }, 557 {Feature_HasPTWRITEBit, }, 558 {Feature_HasRTMBit, }, 559 {Feature_HasSHABit, }, 560 {Feature_HasSSE1Bit, }, 561 {Feature_HasSSE2Bit, }, 562 {Feature_HasSSE3Bit, }, 563 {Feature_HasSSE42Bit, }, 564 {Feature_HasSSE4ABit, }, 565 {Feature_HasTBMBit, }, 566 {Feature_HasVLXBit, }, 567 {Feature_HasVPOPCNTDQBit, }, 568 {Feature_HasWAITPKGBit, }, 569 {Feature_HasWBNOINVDBit, }, 570 {Feature_HasXOPBit, }, 571 {Feature_HasXSAVEBit, }, 572 {Feature_In64BitModeBit, }, 573 {Feature_NoDQIBit, }, 574 {Feature_Not64BitModeBit, }, 575 {Feature_UseAVXBit, }, 576 {Feature_UseIncDecBit, }, 577 {Feature_UseSSE1Bit, }, 578 {Feature_UseSSE2Bit, }, 579 {Feature_UseSSE41Bit, }, 580 {Feature_UseSSSE3Bit, }, 581 {Feature_HasAESBit, Feature_HasAVXBit, }, 582 {Feature_HasAESBit, Feature_NoAVXBit, }, 583 {Feature_HasAVXBit, Feature_In64BitModeBit, }, 584 {Feature_HasAVXBit, Feature_NoVLXBit, }, 585 {Feature_HasAVXBit, Feature_NoVLX_Or_NoBWIBit, }, 586 {Feature_HasAVXBit, Feature_Not64BitModeBit, }, 587 {Feature_HasAVX2Bit, Feature_NoVLXBit, }, 588 {Feature_HasAVX2Bit, Feature_NoVLX_Or_NoBWIBit, }, 589 {Feature_HasAVX512Bit, Feature_HasVAESBit, }, 590 {Feature_HasAVX512Bit, Feature_HasVLXBit, }, 591 {Feature_HasAVX512Bit, Feature_HasVPCLMULQDQBit, }, 592 {Feature_HasAVX512Bit, Feature_NoBWIBit, }, 593 {Feature_HasBITALGBit, Feature_HasVLXBit, }, 594 {Feature_HasBWIBit, Feature_HasVLXBit, }, 595 {Feature_HasCDIBit, Feature_HasVLXBit, }, 596 {Feature_HasDQIBit, Feature_HasVLXBit, }, 597 {Feature_HasDQIBit, Feature_NoBWIBit, }, 598 {Feature_HasFSGSBaseBit, Feature_In64BitModeBit, }, 599 {Feature_HasPCLMULBit, Feature_NoAVXBit, }, 600 {Feature_HasPTWRITEBit, Feature_In64BitModeBit, }, 601 {Feature_HasRDPIDBit, Feature_Not64BitModeBit, }, 602 {Feature_HasVAESBit, Feature_HasVLXBit, }, 603 {Feature_HasVAESBit, Feature_NoVLXBit, }, 604 {Feature_HasVLXBit, Feature_HasVPCLMULQDQBit, }, 605 {Feature_HasVLXBit, Feature_HasVPOPCNTDQBit, }, 606 {Feature_HasVPCLMULQDQBit, Feature_NoVLXBit, }, 607 {Feature_HasWAITPKGBit, Feature_In64BitModeBit, }, 608 {Feature_HasWAITPKGBit, Feature_Not64BitModeBit, }, 609 {Feature_In64BitModeBit, Feature_UseSSE2Bit, }, 610 {Feature_Not64BitModeBit, Feature_OptForSizeBit, }, 611 {Feature_Not64BitModeBit, Feature_UseSSE2Bit, }, 612 {Feature_NotWin64WithoutFPBit, Feature_OptForMinSizeBit, }, 613 {Feature_HasAESBit, Feature_HasAVXBit, Feature_NoVLX_Or_NoVAESBit, }, 614 {Feature_HasAVXBit, Feature_HasPCLMULBit, Feature_NoVLX_Or_NoVPCLMULQDQBit, }, 615 {Feature_HasDQIBit, Feature_HasVLXBit, Feature_NoBWIBit, }, 616}; 617 618// ComplexPattern predicates. 619enum { 620 GICP_Invalid, 621}; 622// See constructor for table contents 623 624// PatFrag predicates. 625enum { 626 GIPFP_I64_Predicate_AndMask64 = GIPFP_I64_Invalid + 1, 627 GIPFP_I64_Predicate_BTCBTSMask64, 628 GIPFP_I64_Predicate_BTRMask64, 629 GIPFP_I64_Predicate_PrefetchWT1Level, 630 GIPFP_I64_Predicate_i16immSExt8, 631 GIPFP_I64_Predicate_i32immSExt8, 632 GIPFP_I64_Predicate_i64immSExt32, 633 GIPFP_I64_Predicate_i64immSExt8, 634 GIPFP_I64_Predicate_i64immZExt32, 635 GIPFP_I64_Predicate_i64immZExt32SExt8, 636 GIPFP_I64_Predicate_immff00_ffff, 637}; 638bool X86InstructionSelector::testImmPredicate_I64(unsigned PredicateID, int64_t Imm) const { 639 switch (PredicateID) { 640 case GIPFP_I64_Predicate_AndMask64: { 641 642 return isMask_64(Imm) && !isUInt<32>(Imm); 643 644 llvm_unreachable("ImmediateCode should have returned"); 645 return false; 646 } 647 case GIPFP_I64_Predicate_BTCBTSMask64: { 648 649 return !isInt<32>(Imm) && isPowerOf2_64(Imm); 650 651 llvm_unreachable("ImmediateCode should have returned"); 652 return false; 653 } 654 case GIPFP_I64_Predicate_BTRMask64: { 655 656 return !isUInt<32>(Imm) && !isInt<32>(Imm) && isPowerOf2_64(~Imm); 657 658 llvm_unreachable("ImmediateCode should have returned"); 659 return false; 660 } 661 case GIPFP_I64_Predicate_PrefetchWT1Level: { 662 663 return Imm < 3; 664 665 llvm_unreachable("ImmediateCode should have returned"); 666 return false; 667 } 668 case GIPFP_I64_Predicate_i16immSExt8: { 669 return isInt<8>(Imm); 670 llvm_unreachable("ImmediateCode should have returned"); 671 return false; 672 } 673 case GIPFP_I64_Predicate_i32immSExt8: { 674 return isInt<8>(Imm); 675 llvm_unreachable("ImmediateCode should have returned"); 676 return false; 677 } 678 case GIPFP_I64_Predicate_i64immSExt32: { 679 return isInt<32>(Imm); 680 llvm_unreachable("ImmediateCode should have returned"); 681 return false; 682 } 683 case GIPFP_I64_Predicate_i64immSExt8: { 684 return isInt<8>(Imm); 685 llvm_unreachable("ImmediateCode should have returned"); 686 return false; 687 } 688 case GIPFP_I64_Predicate_i64immZExt32: { 689 return isUInt<32>(Imm); 690 llvm_unreachable("ImmediateCode should have returned"); 691 return false; 692 } 693 case GIPFP_I64_Predicate_i64immZExt32SExt8: { 694 695 return isUInt<32>(Imm) && isInt<8>(static_cast<int32_t>(Imm)); 696 697 llvm_unreachable("ImmediateCode should have returned"); 698 return false; 699 } 700 case GIPFP_I64_Predicate_immff00_ffff: { 701 702 return Imm >= 0xff00 && Imm <= 0xffff; 703 704 llvm_unreachable("ImmediateCode should have returned"); 705 return false; 706 } 707 } 708 llvm_unreachable("Unknown predicate"); 709 return false; 710} 711// PatFrag predicates. 712enum { 713 GIPFP_APFloat_Predicate_fpimm0 = GIPFP_APFloat_Invalid + 1, 714 GIPFP_APFloat_Predicate_fpimm1, 715 GIPFP_APFloat_Predicate_fpimmneg0, 716 GIPFP_APFloat_Predicate_fpimmneg1, 717}; 718bool X86InstructionSelector::testImmPredicate_APFloat(unsigned PredicateID, const APFloat & Imm) const { 719 switch (PredicateID) { 720 case GIPFP_APFloat_Predicate_fpimm0: { 721 722 return Imm.isExactlyValue(+0.0); 723 724 llvm_unreachable("ImmediateCode should have returned"); 725 return false; 726 } 727 case GIPFP_APFloat_Predicate_fpimm1: { 728 729 return Imm.isExactlyValue(+1.0); 730 731 llvm_unreachable("ImmediateCode should have returned"); 732 return false; 733 } 734 case GIPFP_APFloat_Predicate_fpimmneg0: { 735 736 return Imm.isExactlyValue(-0.0); 737 738 llvm_unreachable("ImmediateCode should have returned"); 739 return false; 740 } 741 case GIPFP_APFloat_Predicate_fpimmneg1: { 742 743 return Imm.isExactlyValue(-1.0); 744 745 llvm_unreachable("ImmediateCode should have returned"); 746 return false; 747 } 748 } 749 llvm_unreachable("Unknown predicate"); 750 return false; 751} 752bool X86InstructionSelector::testImmPredicate_APInt(unsigned PredicateID, const APInt & Imm) const { 753 llvm_unreachable("Unknown predicate"); 754 return false; 755} 756bool X86InstructionSelector::testMIPredicate_MI(unsigned PredicateID, const MachineInstr & MI) const { 757 const MachineFunction &MF = *MI.getParent()->getParent(); 758 const MachineRegisterInfo &MRI = MF.getRegInfo(); 759 (void)MRI; 760 llvm_unreachable("Unknown predicate"); 761 return false; 762} 763 764X86InstructionSelector::ComplexMatcherMemFn 765X86InstructionSelector::ComplexPredicateFns[] = { 766 nullptr, // GICP_Invalid 767}; 768 769// Custom renderers. 770enum { 771 GICR_Invalid, 772}; 773X86InstructionSelector::CustomRendererFn 774X86InstructionSelector::CustomRenderers[] = { 775 nullptr, // GICR_Invalid 776}; 777 778bool X86InstructionSelector::selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const { 779 MachineFunction &MF = *I.getParent()->getParent(); 780 MachineRegisterInfo &MRI = MF.getRegInfo(); 781 const PredicateBitset AvailableFeatures = getAvailableFeatures(); 782 NewMIVector OutMIs; 783 State.MIs.clear(); 784 State.MIs.push_back(&I); 785 786 if (executeMatchTable(*this, OutMIs, State, ISelInfo, getMatchTable(), TII, MRI, TRI, RBI, AvailableFeatures, CoverageInfo)) { 787 return true; 788 } 789 790 return false; 791} 792 793const int64_t *X86InstructionSelector::getMatchTable() const { 794 constexpr static int64_t MatchTable0[] = { 795 GIM_SwitchOpcode, /*MI*/0, /*[*/35, 168, /*)*//*default:*//*Label 43*/ 37038, 796 /*TargetOpcode::G_ADD*//*Label 0*/ 138, 797 /*TargetOpcode::G_SUB*//*Label 1*/ 1755, 798 /*TargetOpcode::G_MUL*//*Label 2*/ 2836, 0, 0, 0, 0, 799 /*TargetOpcode::G_AND*//*Label 3*/ 3602, 800 /*TargetOpcode::G_OR*//*Label 4*/ 7119, 801 /*TargetOpcode::G_XOR*//*Label 5*/ 10989, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 802 /*TargetOpcode::G_CONCAT_VECTORS*//*Label 6*/ 14165, 0, 0, 803 /*TargetOpcode::G_BITCAST*//*Label 7*/ 14321, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 804 /*TargetOpcode::G_INTRINSIC*//*Label 8*/ 15051, 805 /*TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS*//*Label 9*/ 21028, 806 /*TargetOpcode::G_ANYEXT*//*Label 10*/ 22825, 807 /*TargetOpcode::G_TRUNC*//*Label 11*/ 23606, 808 /*TargetOpcode::G_CONSTANT*//*Label 12*/ 23989, 809 /*TargetOpcode::G_FCONSTANT*//*Label 13*/ 24192, 0, 0, 810 /*TargetOpcode::G_SEXT*//*Label 14*/ 24339, 0, 811 /*TargetOpcode::G_ZEXT*//*Label 15*/ 25144, 812 /*TargetOpcode::G_SHL*//*Label 16*/ 25877, 813 /*TargetOpcode::G_LSHR*//*Label 17*/ 26470, 814 /*TargetOpcode::G_ASHR*//*Label 18*/ 27047, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 815 /*TargetOpcode::G_UMULH*//*Label 19*/ 27624, 816 /*TargetOpcode::G_SMULH*//*Label 20*/ 27812, 817 /*TargetOpcode::G_FADD*//*Label 21*/ 28000, 818 /*TargetOpcode::G_FSUB*//*Label 22*/ 28676, 819 /*TargetOpcode::G_FMUL*//*Label 23*/ 29352, 0, 0, 820 /*TargetOpcode::G_FDIV*//*Label 24*/ 30028, 0, 0, 0, 0, 0, 0, 0, 821 /*TargetOpcode::G_FNEG*//*Label 25*/ 30704, 822 /*TargetOpcode::G_FPEXT*//*Label 26*/ 30793, 823 /*TargetOpcode::G_FPTRUNC*//*Label 27*/ 31081, 824 /*TargetOpcode::G_FPTOSI*//*Label 28*/ 31289, 825 /*TargetOpcode::G_FPTOUI*//*Label 29*/ 31645, 826 /*TargetOpcode::G_SITOFP*//*Label 30*/ 31760, 827 /*TargetOpcode::G_UITOFP*//*Label 31*/ 32632, 828 /*TargetOpcode::G_FABS*//*Label 32*/ 33110, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 829 /*TargetOpcode::G_SMIN*//*Label 33*/ 33199, 830 /*TargetOpcode::G_SMAX*//*Label 34*/ 33832, 831 /*TargetOpcode::G_UMIN*//*Label 35*/ 34465, 832 /*TargetOpcode::G_UMAX*//*Label 36*/ 35098, 833 /*TargetOpcode::G_BR*//*Label 37*/ 35731, 0, 0, 0, 0, 0, 834 /*TargetOpcode::G_CTTZ_ZERO_UNDEF*//*Label 38*/ 35744, 835 /*TargetOpcode::G_CTLZ*//*Label 39*/ 35829, 0, 836 /*TargetOpcode::G_CTPOP*//*Label 40*/ 35992, 837 /*TargetOpcode::G_BSWAP*//*Label 41*/ 36304, 0, 0, 0, 0, 838 /*TargetOpcode::G_FSQRT*//*Label 42*/ 36394, 839 // Label 0: @138 840 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 25, /*)*//*default:*//*Label 60*/ 1754, 841 /*GILLT_s8*//*Label 44*/ 168, 842 /*GILLT_s16*//*Label 45*/ 282, 843 /*GILLT_s32*//*Label 46*/ 454, 844 /*GILLT_s64*//*Label 47*/ 626, 0, 0, 0, 845 /*GILLT_v2s64*//*Label 48*/ 826, 0, 846 /*GILLT_v4s32*//*Label 49*/ 907, 847 /*GILLT_v4s64*//*Label 50*/ 1110, 0, 848 /*GILLT_v8s16*//*Label 51*/ 1168, 849 /*GILLT_v8s32*//*Label 52*/ 1371, 850 /*GILLT_v8s64*//*Label 53*/ 1429, 0, 851 /*GILLT_v16s8*//*Label 54*/ 1461, 852 /*GILLT_v16s16*//*Label 55*/ 1542, 853 /*GILLT_v16s32*//*Label 56*/ 1600, 0, 854 /*GILLT_v32s8*//*Label 57*/ 1632, 855 /*GILLT_v32s16*//*Label 58*/ 1690, 0, 856 /*GILLT_v64s8*//*Label 59*/ 1722, 857 // Label 44: @168 858 GIM_Try, /*On fail goto*//*Label 61*/ 281, 859 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s8, 860 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s8, 861 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR8RegClassID, 862 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR8RegClassID, 863 GIM_Try, /*On fail goto*//*Label 62*/ 210, // Rule ID 17335 // 864 GIM_CheckFeatures, GIFBS_UseIncDec, 865 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 1, 866 // (add:{ *:[i8] } GR8:{ *:[i8] }:$src, 1:{ *:[i8] }) => (INC8r:{ *:[i8] }:{ *:[i32] } GR8:{ *:[i8] }:$src) 867 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::INC8r, 868 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 869 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 870 GIR_EraseFromParent, /*InsnID*/0, 871 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 872 // GIR_Coverage, 17335, 873 GIR_Done, 874 // Label 62: @210 875 GIM_Try, /*On fail goto*//*Label 63*/ 234, // Rule ID 17339 // 876 GIM_CheckFeatures, GIFBS_UseIncDec, 877 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1, 878 // (add:{ *:[i8] } GR8:{ *:[i8] }:$src, -1:{ *:[i8] }) => (DEC8r:{ *:[i8] }:{ *:[i32] } GR8:{ *:[i8] }:$src) 879 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::DEC8r, 880 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 881 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 882 GIR_EraseFromParent, /*InsnID*/0, 883 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 884 // GIR_Coverage, 17339, 885 GIR_Done, 886 // Label 63: @234 887 GIM_Try, /*On fail goto*//*Label 64*/ 264, // Rule ID 17290 // 888 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 889 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 890 // MIs[1] Operand 1 891 // No operand predicates 892 GIM_CheckIsSafeToFold, /*InsnID*/1, 893 // (add:{ *:[i8] } GR8:{ *:[i8] }:$src1, (imm:{ *:[i8] }):$src2) => (ADD8ri:{ *:[i8] }:{ *:[i32] } GR8:{ *:[i8] }:$src1, (imm:{ *:[i8] }):$src2) 894 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::ADD8ri, 895 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 896 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 897 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2 898 GIR_EraseFromParent, /*InsnID*/0, 899 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 900 // GIR_Coverage, 17290, 901 GIR_Done, 902 // Label 64: @264 903 GIM_Try, /*On fail goto*//*Label 65*/ 280, // Rule ID 17282 // 904 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR8RegClassID, 905 // (add:{ *:[i8] } GR8:{ *:[i8] }:$src1, GR8:{ *:[i8] }:$src2) => (ADD8rr:{ *:[i8] }:{ *:[i32] } GR8:{ *:[i8] }:$src1, GR8:{ *:[i8] }:$src2) 906 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::ADD8rr, 907 GIR_AddImplicitDef, /*InsnID*/0, X86::EFLAGS, 908 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 909 // GIR_Coverage, 17282, 910 GIR_Done, 911 // Label 65: @280 912 GIM_Reject, 913 // Label 61: @281 914 GIM_Reject, 915 // Label 45: @282 916 GIM_Try, /*On fail goto*//*Label 66*/ 453, 917 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, 918 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16, 919 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR16RegClassID, 920 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR16RegClassID, 921 GIM_Try, /*On fail goto*//*Label 67*/ 325, // Rule ID 17144 // 922 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 128, 923 // (add:{ *:[i16] } GR16:{ *:[i16] }:$src1, 128:{ *:[i16] }) => (SUB16ri8:{ *:[i16] }:{ *:[i32] } GR16:{ *:[i16] }:$src1, -128:{ *:[i16] }) 924 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SUB16ri8, 925 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 926 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 927 GIR_AddImm, /*InsnID*/0, /*Imm*/-128, 928 GIR_EraseFromParent, /*InsnID*/0, 929 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 930 // GIR_Coverage, 17144, 931 GIR_Done, 932 // Label 67: @325 933 GIM_Try, /*On fail goto*//*Label 68*/ 349, // Rule ID 17336 // 934 GIM_CheckFeatures, GIFBS_UseIncDec, 935 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 1, 936 // (add:{ *:[i16] } GR16:{ *:[i16] }:$src, 1:{ *:[i16] }) => (INC16r:{ *:[i16] }:{ *:[i32] } GR16:{ *:[i16] }:$src) 937 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::INC16r, 938 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 939 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 940 GIR_EraseFromParent, /*InsnID*/0, 941 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 942 // GIR_Coverage, 17336, 943 GIR_Done, 944 // Label 68: @349 945 GIM_Try, /*On fail goto*//*Label 69*/ 373, // Rule ID 17340 // 946 GIM_CheckFeatures, GIFBS_UseIncDec, 947 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1, 948 // (add:{ *:[i16] } GR16:{ *:[i16] }:$src, -1:{ *:[i16] }) => (DEC16r:{ *:[i16] }:{ *:[i32] } GR16:{ *:[i16] }:$src) 949 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::DEC16r, 950 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 951 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 952 GIR_EraseFromParent, /*InsnID*/0, 953 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 954 // GIR_Coverage, 17340, 955 GIR_Done, 956 // Label 69: @373 957 GIM_Try, /*On fail goto*//*Label 70*/ 406, // Rule ID 17293 // 958 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 959 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 960 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_i16immSExt8, 961 // MIs[1] Operand 1 962 // No operand predicates 963 GIM_CheckIsSafeToFold, /*InsnID*/1, 964 // (add:{ *:[i16] } GR16:{ *:[i16] }:$src1, (imm:{ *:[i16] })<<P:Predicate_i16immSExt8>>:$src2) => (ADD16ri8:{ *:[i16] }:{ *:[i32] } GR16:{ *:[i16] }:$src1, (imm:{ *:[i16] })<<P:Predicate_i16immSExt8>>:$src2) 965 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::ADD16ri8, 966 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 967 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 968 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2 969 GIR_EraseFromParent, /*InsnID*/0, 970 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 971 // GIR_Coverage, 17293, 972 GIR_Done, 973 // Label 70: @406 974 GIM_Try, /*On fail goto*//*Label 71*/ 436, // Rule ID 17291 // 975 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 976 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 977 // MIs[1] Operand 1 978 // No operand predicates 979 GIM_CheckIsSafeToFold, /*InsnID*/1, 980 // (add:{ *:[i16] } GR16:{ *:[i16] }:$src1, (imm:{ *:[i16] }):$src2) => (ADD16ri:{ *:[i16] }:{ *:[i32] } GR16:{ *:[i16] }:$src1, (imm:{ *:[i16] }):$src2) 981 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::ADD16ri, 982 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 983 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 984 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2 985 GIR_EraseFromParent, /*InsnID*/0, 986 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 987 // GIR_Coverage, 17291, 988 GIR_Done, 989 // Label 71: @436 990 GIM_Try, /*On fail goto*//*Label 72*/ 452, // Rule ID 17283 // 991 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR16RegClassID, 992 // (add:{ *:[i16] } GR16:{ *:[i16] }:$src1, GR16:{ *:[i16] }:$src2) => (ADD16rr:{ *:[i16] }:{ *:[i32] } GR16:{ *:[i16] }:$src1, GR16:{ *:[i16] }:$src2) 993 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::ADD16rr, 994 GIR_AddImplicitDef, /*InsnID*/0, X86::EFLAGS, 995 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 996 // GIR_Coverage, 17283, 997 GIR_Done, 998 // Label 72: @452 999 GIM_Reject, 1000 // Label 66: @453 1001 GIM_Reject, 1002 // Label 46: @454 1003 GIM_Try, /*On fail goto*//*Label 73*/ 625, 1004 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 1005 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 1006 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 1007 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR32RegClassID, 1008 GIM_Try, /*On fail goto*//*Label 74*/ 497, // Rule ID 17146 // 1009 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 128, 1010 // (add:{ *:[i32] } GR32:{ *:[i32] }:$src1, 128:{ *:[i32] }) => (SUB32ri8:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src1, -128:{ *:[i32] }) 1011 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SUB32ri8, 1012 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 1013 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 1014 GIR_AddImm, /*InsnID*/0, /*Imm*/-128, 1015 GIR_EraseFromParent, /*InsnID*/0, 1016 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1017 // GIR_Coverage, 17146, 1018 GIR_Done, 1019 // Label 74: @497 1020 GIM_Try, /*On fail goto*//*Label 75*/ 521, // Rule ID 17337 // 1021 GIM_CheckFeatures, GIFBS_UseIncDec, 1022 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 1, 1023 // (add:{ *:[i32] } GR32:{ *:[i32] }:$src, 1:{ *:[i32] }) => (INC32r:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src) 1024 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::INC32r, 1025 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 1026 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 1027 GIR_EraseFromParent, /*InsnID*/0, 1028 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1029 // GIR_Coverage, 17337, 1030 GIR_Done, 1031 // Label 75: @521 1032 GIM_Try, /*On fail goto*//*Label 76*/ 545, // Rule ID 17341 // 1033 GIM_CheckFeatures, GIFBS_UseIncDec, 1034 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1, 1035 // (add:{ *:[i32] } GR32:{ *:[i32] }:$src, -1:{ *:[i32] }) => (DEC32r:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src) 1036 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::DEC32r, 1037 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 1038 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 1039 GIR_EraseFromParent, /*InsnID*/0, 1040 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1041 // GIR_Coverage, 17341, 1042 GIR_Done, 1043 // Label 76: @545 1044 GIM_Try, /*On fail goto*//*Label 77*/ 578, // Rule ID 17294 // 1045 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 1046 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 1047 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_i32immSExt8, 1048 // MIs[1] Operand 1 1049 // No operand predicates 1050 GIM_CheckIsSafeToFold, /*InsnID*/1, 1051 // (add:{ *:[i32] } GR32:{ *:[i32] }:$src1, (imm:{ *:[i32] })<<P:Predicate_i32immSExt8>>:$src2) => (ADD32ri8:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src1, (imm:{ *:[i32] })<<P:Predicate_i32immSExt8>>:$src2) 1052 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::ADD32ri8, 1053 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 1054 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 1055 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2 1056 GIR_EraseFromParent, /*InsnID*/0, 1057 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1058 // GIR_Coverage, 17294, 1059 GIR_Done, 1060 // Label 77: @578 1061 GIM_Try, /*On fail goto*//*Label 78*/ 608, // Rule ID 17292 // 1062 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 1063 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 1064 // MIs[1] Operand 1 1065 // No operand predicates 1066 GIM_CheckIsSafeToFold, /*InsnID*/1, 1067 // (add:{ *:[i32] } GR32:{ *:[i32] }:$src1, (imm:{ *:[i32] }):$src2) => (ADD32ri:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src1, (imm:{ *:[i32] }):$src2) 1068 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::ADD32ri, 1069 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 1070 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 1071 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2 1072 GIR_EraseFromParent, /*InsnID*/0, 1073 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1074 // GIR_Coverage, 17292, 1075 GIR_Done, 1076 // Label 78: @608 1077 GIM_Try, /*On fail goto*//*Label 79*/ 624, // Rule ID 17284 // 1078 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR32RegClassID, 1079 // (add:{ *:[i32] } GR32:{ *:[i32] }:$src1, GR32:{ *:[i32] }:$src2) => (ADD32rr:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src1, GR32:{ *:[i32] }:$src2) 1080 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::ADD32rr, 1081 GIR_AddImplicitDef, /*InsnID*/0, X86::EFLAGS, 1082 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1083 // GIR_Coverage, 17284, 1084 GIR_Done, 1085 // Label 79: @624 1086 GIM_Reject, 1087 // Label 73: @625 1088 GIM_Reject, 1089 // Label 47: @626 1090 GIM_Try, /*On fail goto*//*Label 80*/ 825, 1091 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 1092 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 1093 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID, 1094 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR64RegClassID, 1095 GIM_Try, /*On fail goto*//*Label 81*/ 669, // Rule ID 17148 // 1096 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 128, 1097 // (add:{ *:[i64] } GR64:{ *:[i64] }:$src1, 128:{ *:[i64] }) => (SUB64ri8:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src1, -128:{ *:[i64] }) 1098 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SUB64ri8, 1099 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 1100 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 1101 GIR_AddImm, /*InsnID*/0, /*Imm*/-128, 1102 GIR_EraseFromParent, /*InsnID*/0, 1103 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1104 // GIR_Coverage, 17148, 1105 GIR_Done, 1106 // Label 81: @669 1107 GIM_Try, /*On fail goto*//*Label 82*/ 694, // Rule ID 17153 // 1108 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 2147483648, 1109 // (add:{ *:[i64] } GR64:{ *:[i64] }:$src1, 2147483648:{ *:[i64] }) => (SUB64ri32:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src1, -2147483648:{ *:[i64] }) 1110 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SUB64ri32, 1111 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 1112 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 1113 GIR_AddImm, /*InsnID*/0, /*Imm*/-2147483648, 1114 GIR_EraseFromParent, /*InsnID*/0, 1115 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1116 // GIR_Coverage, 17153, 1117 GIR_Done, 1118 // Label 82: @694 1119 GIM_Try, /*On fail goto*//*Label 83*/ 718, // Rule ID 17338 // 1120 GIM_CheckFeatures, GIFBS_UseIncDec, 1121 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 1, 1122 // (add:{ *:[i64] } GR64:{ *:[i64] }:$src, 1:{ *:[i64] }) => (INC64r:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src) 1123 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::INC64r, 1124 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 1125 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 1126 GIR_EraseFromParent, /*InsnID*/0, 1127 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1128 // GIR_Coverage, 17338, 1129 GIR_Done, 1130 // Label 83: @718 1131 GIM_Try, /*On fail goto*//*Label 84*/ 742, // Rule ID 17342 // 1132 GIM_CheckFeatures, GIFBS_UseIncDec, 1133 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1, 1134 // (add:{ *:[i64] } GR64:{ *:[i64] }:$src, -1:{ *:[i64] }) => (DEC64r:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src) 1135 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::DEC64r, 1136 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 1137 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 1138 GIR_EraseFromParent, /*InsnID*/0, 1139 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1140 // GIR_Coverage, 17342, 1141 GIR_Done, 1142 // Label 84: @742 1143 GIM_Try, /*On fail goto*//*Label 85*/ 775, // Rule ID 17295 // 1144 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 1145 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 1146 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_i64immSExt8, 1147 // MIs[1] Operand 1 1148 // No operand predicates 1149 GIM_CheckIsSafeToFold, /*InsnID*/1, 1150 // (add:{ *:[i64] } GR64:{ *:[i64] }:$src1, (imm:{ *:[i64] })<<P:Predicate_i64immSExt8>>:$src2) => (ADD64ri8:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src1, (imm:{ *:[i64] })<<P:Predicate_i64immSExt8>>:$src2) 1151 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::ADD64ri8, 1152 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 1153 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 1154 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2 1155 GIR_EraseFromParent, /*InsnID*/0, 1156 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1157 // GIR_Coverage, 17295, 1158 GIR_Done, 1159 // Label 85: @775 1160 GIM_Try, /*On fail goto*//*Label 86*/ 808, // Rule ID 17296 // 1161 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 1162 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 1163 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_i64immSExt32, 1164 // MIs[1] Operand 1 1165 // No operand predicates 1166 GIM_CheckIsSafeToFold, /*InsnID*/1, 1167 // (add:{ *:[i64] } GR64:{ *:[i64] }:$src1, (imm:{ *:[i64] })<<P:Predicate_i64immSExt32>>:$src2) => (ADD64ri32:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src1, (imm:{ *:[i64] })<<P:Predicate_i64immSExt32>>:$src2) 1168 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::ADD64ri32, 1169 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 1170 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 1171 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2 1172 GIR_EraseFromParent, /*InsnID*/0, 1173 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1174 // GIR_Coverage, 17296, 1175 GIR_Done, 1176 // Label 86: @808 1177 GIM_Try, /*On fail goto*//*Label 87*/ 824, // Rule ID 17285 // 1178 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR64RegClassID, 1179 // (add:{ *:[i64] } GR64:{ *:[i64] }:$src1, GR64:{ *:[i64] }:$src2) => (ADD64rr:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src1, GR64:{ *:[i64] }:$src2) 1180 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::ADD64rr, 1181 GIR_AddImplicitDef, /*InsnID*/0, X86::EFLAGS, 1182 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1183 // GIR_Coverage, 17285, 1184 GIR_Done, 1185 // Label 87: @824 1186 GIM_Reject, 1187 // Label 80: @825 1188 GIM_Reject, 1189 // Label 48: @826 1190 GIM_Try, /*On fail goto*//*Label 88*/ 906, 1191 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, 1192 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 1193 GIM_Try, /*On fail goto*//*Label 89*/ 859, // Rule ID 1999 // 1194 GIM_CheckFeatures, GIFBS_HasAVX_NoVLX, 1195 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 1196 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 1197 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 1198 // (add:{ *:[v2i64] } VR128:{ *:[v2i64] }:$src1, VR128:{ *:[v2i64] }:$src2) => (VPADDQrr:{ *:[v2i64] } VR128:{ *:[v2i64] }:$src1, VR128:{ *:[v2i64] }:$src2) 1199 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPADDQrr, 1200 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1201 // GIR_Coverage, 1999, 1202 GIR_Done, 1203 // Label 89: @859 1204 GIM_Try, /*On fail goto*//*Label 90*/ 882, // Rule ID 2001 // 1205 GIM_CheckFeatures, GIFBS_UseSSE2, 1206 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 1207 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 1208 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 1209 // (add:{ *:[v2i64] } VR128:{ *:[v2i64] }:$src1, VR128:{ *:[v2i64] }:$src2) => (PADDQrr:{ *:[v2i64] } VR128:{ *:[v2i64] }:$src1, VR128:{ *:[v2i64] }:$src2) 1210 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::PADDQrr, 1211 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1212 // GIR_Coverage, 2001, 1213 GIR_Done, 1214 // Label 90: @882 1215 GIM_Try, /*On fail goto*//*Label 91*/ 905, // Rule ID 3913 // 1216 GIM_CheckFeatures, GIFBS_HasAVX512_HasVLX, 1217 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 1218 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 1219 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128XRegClassID, 1220 // (add:{ *:[v2i64] } VR128X:{ *:[v2i64] }:$src1, VR128X:{ *:[v2i64] }:$src2) => (VPADDQZ128rr:{ *:[v2i64] } VR128X:{ *:[v2i64] }:$src1, VR128X:{ *:[v2i64] }:$src2) 1221 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPADDQZ128rr, 1222 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1223 // GIR_Coverage, 3913, 1224 GIR_Done, 1225 // Label 91: @905 1226 GIM_Reject, 1227 // Label 88: @906 1228 GIM_Reject, 1229 // Label 49: @907 1230 GIM_Try, /*On fail goto*//*Label 92*/ 1109, 1231 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 1232 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 1233 GIM_Try, /*On fail goto*//*Label 93*/ 978, // Rule ID 13212 // 1234 GIM_CheckFeatures, GIFBS_HasXOP, 1235 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 1236 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 1237 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL, 1238 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, 1239 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, 1240 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::VR128RegClassID, 1241 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/X86::VR128RegClassID, 1242 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 1243 GIM_CheckIsSafeToFold, /*InsnID*/1, 1244 // (add:{ *:[v4i32] } (mul:{ *:[v4i32] } VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2), VR128:{ *:[v4i32] }:$src3) => (VPMACSDDrr:{ *:[v4i32] } VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2, VR128:{ *:[v4i32] }:$src3) 1245 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VPMACSDDrr, 1246 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 1247 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1 1248 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src2 1249 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src3 1250 GIR_EraseFromParent, /*InsnID*/0, 1251 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1252 // GIR_Coverage, 13212, 1253 GIR_Done, 1254 // Label 93: @978 1255 GIM_Try, /*On fail goto*//*Label 94*/ 1039, // Rule ID 19275 // 1256 GIM_CheckFeatures, GIFBS_HasXOP, 1257 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 1258 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 1259 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 1260 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL, 1261 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, 1262 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, 1263 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::VR128RegClassID, 1264 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/X86::VR128RegClassID, 1265 GIM_CheckIsSafeToFold, /*InsnID*/1, 1266 // (add:{ *:[v4i32] } VR128:{ *:[v4i32] }:$src3, (mul:{ *:[v4i32] } VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2)) => (VPMACSDDrr:{ *:[v4i32] } VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2, VR128:{ *:[v4i32] }:$src3) 1267 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VPMACSDDrr, 1268 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 1269 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1 1270 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src2 1271 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src3 1272 GIR_EraseFromParent, /*InsnID*/0, 1273 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1274 // GIR_Coverage, 19275, 1275 GIR_Done, 1276 // Label 94: @1039 1277 GIM_Try, /*On fail goto*//*Label 95*/ 1062, // Rule ID 1993 // 1278 GIM_CheckFeatures, GIFBS_HasAVX_NoVLX, 1279 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 1280 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 1281 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 1282 // (add:{ *:[v4i32] } VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2) => (VPADDDrr:{ *:[v4i32] } VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2) 1283 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPADDDrr, 1284 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1285 // GIR_Coverage, 1993, 1286 GIR_Done, 1287 // Label 95: @1062 1288 GIM_Try, /*On fail goto*//*Label 96*/ 1085, // Rule ID 1995 // 1289 GIM_CheckFeatures, GIFBS_UseSSE2, 1290 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 1291 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 1292 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 1293 // (add:{ *:[v4i32] } VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2) => (PADDDrr:{ *:[v4i32] } VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2) 1294 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::PADDDrr, 1295 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1296 // GIR_Coverage, 1995, 1297 GIR_Done, 1298 // Label 96: @1085 1299 GIM_Try, /*On fail goto*//*Label 97*/ 1108, // Rule ID 3940 // 1300 GIM_CheckFeatures, GIFBS_HasAVX512_HasVLX, 1301 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 1302 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 1303 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128XRegClassID, 1304 // (add:{ *:[v4i32] } VR128X:{ *:[v4i32] }:$src1, VR128X:{ *:[v4i32] }:$src2) => (VPADDDZ128rr:{ *:[v4i32] } VR128X:{ *:[v4i32] }:$src1, VR128X:{ *:[v4i32] }:$src2) 1305 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPADDDZ128rr, 1306 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1307 // GIR_Coverage, 3940, 1308 GIR_Done, 1309 // Label 97: @1108 1310 GIM_Reject, 1311 // Label 92: @1109 1312 GIM_Reject, 1313 // Label 50: @1110 1314 GIM_Try, /*On fail goto*//*Label 98*/ 1167, 1315 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s64, 1316 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s64, 1317 GIM_Try, /*On fail goto*//*Label 99*/ 1143, // Rule ID 2003 // 1318 GIM_CheckFeatures, GIFBS_HasAVX2_NoVLX, 1319 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID, 1320 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256RegClassID, 1321 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID, 1322 // (add:{ *:[v4i64] } VR256:{ *:[v4i64] }:$src1, VR256:{ *:[v4i64] }:$src2) => (VPADDQYrr:{ *:[v4i64] } VR256:{ *:[v4i64] }:$src1, VR256:{ *:[v4i64] }:$src2) 1323 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPADDQYrr, 1324 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1325 // GIR_Coverage, 2003, 1326 GIR_Done, 1327 // Label 99: @1143 1328 GIM_Try, /*On fail goto*//*Label 100*/ 1166, // Rule ID 3904 // 1329 GIM_CheckFeatures, GIFBS_HasAVX512_HasVLX, 1330 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 1331 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 1332 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256XRegClassID, 1333 // (add:{ *:[v4i64] } VR256X:{ *:[v4i64] }:$src1, VR256X:{ *:[v4i64] }:$src2) => (VPADDQZ256rr:{ *:[v4i64] } VR256X:{ *:[v4i64] }:$src1, VR256X:{ *:[v4i64] }:$src2) 1334 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPADDQZ256rr, 1335 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1336 // GIR_Coverage, 3904, 1337 GIR_Done, 1338 // Label 100: @1166 1339 GIM_Reject, 1340 // Label 98: @1167 1341 GIM_Reject, 1342 // Label 51: @1168 1343 GIM_Try, /*On fail goto*//*Label 101*/ 1370, 1344 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, 1345 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 1346 GIM_Try, /*On fail goto*//*Label 102*/ 1239, // Rule ID 13211 // 1347 GIM_CheckFeatures, GIFBS_HasXOP, 1348 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 1349 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 1350 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL, 1351 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, 1352 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, 1353 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::VR128RegClassID, 1354 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/X86::VR128RegClassID, 1355 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 1356 GIM_CheckIsSafeToFold, /*InsnID*/1, 1357 // (add:{ *:[v8i16] } (mul:{ *:[v8i16] } VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2), VR128:{ *:[v8i16] }:$src3) => (VPMACSWWrr:{ *:[v8i16] } VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2, VR128:{ *:[v8i16] }:$src3) 1358 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VPMACSWWrr, 1359 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 1360 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1 1361 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src2 1362 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src3 1363 GIR_EraseFromParent, /*InsnID*/0, 1364 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1365 // GIR_Coverage, 13211, 1366 GIR_Done, 1367 // Label 102: @1239 1368 GIM_Try, /*On fail goto*//*Label 103*/ 1300, // Rule ID 19274 // 1369 GIM_CheckFeatures, GIFBS_HasXOP, 1370 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 1371 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 1372 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 1373 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL, 1374 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, 1375 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, 1376 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::VR128RegClassID, 1377 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/X86::VR128RegClassID, 1378 GIM_CheckIsSafeToFold, /*InsnID*/1, 1379 // (add:{ *:[v8i16] } VR128:{ *:[v8i16] }:$src3, (mul:{ *:[v8i16] } VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2)) => (VPMACSWWrr:{ *:[v8i16] } VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2, VR128:{ *:[v8i16] }:$src3) 1380 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VPMACSWWrr, 1381 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 1382 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1 1383 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src2 1384 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src3 1385 GIR_EraseFromParent, /*InsnID*/0, 1386 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1387 // GIR_Coverage, 19274, 1388 GIR_Done, 1389 // Label 103: @1300 1390 GIM_Try, /*On fail goto*//*Label 104*/ 1323, // Rule ID 1987 // 1391 GIM_CheckFeatures, GIFBS_HasAVX_NoVLX_Or_NoBWI, 1392 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 1393 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 1394 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 1395 // (add:{ *:[v8i16] } VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2) => (VPADDWrr:{ *:[v8i16] } VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2) 1396 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPADDWrr, 1397 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1398 // GIR_Coverage, 1987, 1399 GIR_Done, 1400 // Label 104: @1323 1401 GIM_Try, /*On fail goto*//*Label 105*/ 1346, // Rule ID 1989 // 1402 GIM_CheckFeatures, GIFBS_UseSSE2, 1403 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 1404 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 1405 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 1406 // (add:{ *:[v8i16] } VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2) => (PADDWrr:{ *:[v8i16] } VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2) 1407 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::PADDWrr, 1408 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1409 // GIR_Coverage, 1989, 1410 GIR_Done, 1411 // Label 105: @1346 1412 GIM_Try, /*On fail goto*//*Label 106*/ 1369, // Rule ID 3961 // 1413 GIM_CheckFeatures, GIFBS_HasBWI_HasVLX, 1414 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 1415 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 1416 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128XRegClassID, 1417 // (add:{ *:[v8i16] } VR128X:{ *:[v8i16] }:$src1, VR128X:{ *:[v8i16] }:$src2) => (VPADDWZ128rr:{ *:[v8i16] } VR128X:{ *:[v8i16] }:$src1, VR128X:{ *:[v8i16] }:$src2) 1418 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPADDWZ128rr, 1419 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1420 // GIR_Coverage, 3961, 1421 GIR_Done, 1422 // Label 106: @1369 1423 GIM_Reject, 1424 // Label 101: @1370 1425 GIM_Reject, 1426 // Label 52: @1371 1427 GIM_Try, /*On fail goto*//*Label 107*/ 1428, 1428 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s32, 1429 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s32, 1430 GIM_Try, /*On fail goto*//*Label 108*/ 1404, // Rule ID 1997 // 1431 GIM_CheckFeatures, GIFBS_HasAVX2_NoVLX, 1432 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID, 1433 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256RegClassID, 1434 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID, 1435 // (add:{ *:[v8i32] } VR256:{ *:[v8i32] }:$src1, VR256:{ *:[v8i32] }:$src2) => (VPADDDYrr:{ *:[v8i32] } VR256:{ *:[v8i32] }:$src1, VR256:{ *:[v8i32] }:$src2) 1436 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPADDDYrr, 1437 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1438 // GIR_Coverage, 1997, 1439 GIR_Done, 1440 // Label 108: @1404 1441 GIM_Try, /*On fail goto*//*Label 109*/ 1427, // Rule ID 3931 // 1442 GIM_CheckFeatures, GIFBS_HasAVX512_HasVLX, 1443 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 1444 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 1445 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256XRegClassID, 1446 // (add:{ *:[v8i32] } VR256X:{ *:[v8i32] }:$src1, VR256X:{ *:[v8i32] }:$src2) => (VPADDDZ256rr:{ *:[v8i32] } VR256X:{ *:[v8i32] }:$src1, VR256X:{ *:[v8i32] }:$src2) 1447 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPADDDZ256rr, 1448 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1449 // GIR_Coverage, 3931, 1450 GIR_Done, 1451 // Label 109: @1427 1452 GIM_Reject, 1453 // Label 107: @1428 1454 GIM_Reject, 1455 // Label 53: @1429 1456 GIM_Try, /*On fail goto*//*Label 110*/ 1460, // Rule ID 3895 // 1457 GIM_CheckFeatures, GIFBS_HasAVX512, 1458 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s64, 1459 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s64, 1460 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 1461 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID, 1462 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR512RegClassID, 1463 // (add:{ *:[v8i64] } VR512:{ *:[v8i64] }:$src1, VR512:{ *:[v8i64] }:$src2) => (VPADDQZrr:{ *:[v8i64] } VR512:{ *:[v8i64] }:$src1, VR512:{ *:[v8i64] }:$src2) 1464 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPADDQZrr, 1465 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1466 // GIR_Coverage, 3895, 1467 GIR_Done, 1468 // Label 110: @1460 1469 GIM_Reject, 1470 // Label 54: @1461 1471 GIM_Try, /*On fail goto*//*Label 111*/ 1541, 1472 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, 1473 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 1474 GIM_Try, /*On fail goto*//*Label 112*/ 1494, // Rule ID 1981 // 1475 GIM_CheckFeatures, GIFBS_HasAVX_NoVLX_Or_NoBWI, 1476 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 1477 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 1478 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 1479 // (add:{ *:[v16i8] } VR128:{ *:[v16i8] }:$src1, VR128:{ *:[v16i8] }:$src2) => (VPADDBrr:{ *:[v16i8] } VR128:{ *:[v16i8] }:$src1, VR128:{ *:[v16i8] }:$src2) 1480 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPADDBrr, 1481 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1482 // GIR_Coverage, 1981, 1483 GIR_Done, 1484 // Label 112: @1494 1485 GIM_Try, /*On fail goto*//*Label 113*/ 1517, // Rule ID 1983 // 1486 GIM_CheckFeatures, GIFBS_UseSSE2, 1487 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 1488 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 1489 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 1490 // (add:{ *:[v16i8] } VR128:{ *:[v16i8] }:$src1, VR128:{ *:[v16i8] }:$src2) => (PADDBrr:{ *:[v16i8] } VR128:{ *:[v16i8] }:$src1, VR128:{ *:[v16i8] }:$src2) 1491 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::PADDBrr, 1492 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1493 // GIR_Coverage, 1983, 1494 GIR_Done, 1495 // Label 113: @1517 1496 GIM_Try, /*On fail goto*//*Label 114*/ 1540, // Rule ID 3979 // 1497 GIM_CheckFeatures, GIFBS_HasBWI_HasVLX, 1498 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 1499 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 1500 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128XRegClassID, 1501 // (add:{ *:[v16i8] } VR128X:{ *:[v16i8] }:$src1, VR128X:{ *:[v16i8] }:$src2) => (VPADDBZ128rr:{ *:[v16i8] } VR128X:{ *:[v16i8] }:$src1, VR128X:{ *:[v16i8] }:$src2) 1502 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPADDBZ128rr, 1503 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1504 // GIR_Coverage, 3979, 1505 GIR_Done, 1506 // Label 114: @1540 1507 GIM_Reject, 1508 // Label 111: @1541 1509 GIM_Reject, 1510 // Label 55: @1542 1511 GIM_Try, /*On fail goto*//*Label 115*/ 1599, 1512 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s16, 1513 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s16, 1514 GIM_Try, /*On fail goto*//*Label 116*/ 1575, // Rule ID 1991 // 1515 GIM_CheckFeatures, GIFBS_HasAVX2_NoVLX_Or_NoBWI, 1516 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID, 1517 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256RegClassID, 1518 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID, 1519 // (add:{ *:[v16i16] } VR256:{ *:[v16i16] }:$src1, VR256:{ *:[v16i16] }:$src2) => (VPADDWYrr:{ *:[v16i16] } VR256:{ *:[v16i16] }:$src1, VR256:{ *:[v16i16] }:$src2) 1520 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPADDWYrr, 1521 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1522 // GIR_Coverage, 1991, 1523 GIR_Done, 1524 // Label 116: @1575 1525 GIM_Try, /*On fail goto*//*Label 117*/ 1598, // Rule ID 3955 // 1526 GIM_CheckFeatures, GIFBS_HasBWI_HasVLX, 1527 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 1528 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 1529 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256XRegClassID, 1530 // (add:{ *:[v16i16] } VR256X:{ *:[v16i16] }:$src1, VR256X:{ *:[v16i16] }:$src2) => (VPADDWZ256rr:{ *:[v16i16] } VR256X:{ *:[v16i16] }:$src1, VR256X:{ *:[v16i16] }:$src2) 1531 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPADDWZ256rr, 1532 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1533 // GIR_Coverage, 3955, 1534 GIR_Done, 1535 // Label 117: @1598 1536 GIM_Reject, 1537 // Label 115: @1599 1538 GIM_Reject, 1539 // Label 56: @1600 1540 GIM_Try, /*On fail goto*//*Label 118*/ 1631, // Rule ID 3922 // 1541 GIM_CheckFeatures, GIFBS_HasAVX512, 1542 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s32, 1543 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s32, 1544 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 1545 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID, 1546 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR512RegClassID, 1547 // (add:{ *:[v16i32] } VR512:{ *:[v16i32] }:$src1, VR512:{ *:[v16i32] }:$src2) => (VPADDDZrr:{ *:[v16i32] } VR512:{ *:[v16i32] }:$src1, VR512:{ *:[v16i32] }:$src2) 1548 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPADDDZrr, 1549 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1550 // GIR_Coverage, 3922, 1551 GIR_Done, 1552 // Label 118: @1631 1553 GIM_Reject, 1554 // Label 57: @1632 1555 GIM_Try, /*On fail goto*//*Label 119*/ 1689, 1556 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v32s8, 1557 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v32s8, 1558 GIM_Try, /*On fail goto*//*Label 120*/ 1665, // Rule ID 1985 // 1559 GIM_CheckFeatures, GIFBS_HasAVX2_NoVLX_Or_NoBWI, 1560 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID, 1561 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256RegClassID, 1562 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID, 1563 // (add:{ *:[v32i8] } VR256:{ *:[v32i8] }:$src1, VR256:{ *:[v32i8] }:$src2) => (VPADDBYrr:{ *:[v32i8] } VR256:{ *:[v32i8] }:$src1, VR256:{ *:[v32i8] }:$src2) 1564 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPADDBYrr, 1565 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1566 // GIR_Coverage, 1985, 1567 GIR_Done, 1568 // Label 120: @1665 1569 GIM_Try, /*On fail goto*//*Label 121*/ 1688, // Rule ID 3973 // 1570 GIM_CheckFeatures, GIFBS_HasBWI_HasVLX, 1571 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 1572 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 1573 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256XRegClassID, 1574 // (add:{ *:[v32i8] } VR256X:{ *:[v32i8] }:$src1, VR256X:{ *:[v32i8] }:$src2) => (VPADDBZ256rr:{ *:[v32i8] } VR256X:{ *:[v32i8] }:$src1, VR256X:{ *:[v32i8] }:$src2) 1575 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPADDBZ256rr, 1576 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1577 // GIR_Coverage, 3973, 1578 GIR_Done, 1579 // Label 121: @1688 1580 GIM_Reject, 1581 // Label 119: @1689 1582 GIM_Reject, 1583 // Label 58: @1690 1584 GIM_Try, /*On fail goto*//*Label 122*/ 1721, // Rule ID 3949 // 1585 GIM_CheckFeatures, GIFBS_HasBWI, 1586 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v32s16, 1587 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v32s16, 1588 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 1589 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID, 1590 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR512RegClassID, 1591 // (add:{ *:[v32i16] } VR512:{ *:[v32i16] }:$src1, VR512:{ *:[v32i16] }:$src2) => (VPADDWZrr:{ *:[v32i16] } VR512:{ *:[v32i16] }:$src1, VR512:{ *:[v32i16] }:$src2) 1592 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPADDWZrr, 1593 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1594 // GIR_Coverage, 3949, 1595 GIR_Done, 1596 // Label 122: @1721 1597 GIM_Reject, 1598 // Label 59: @1722 1599 GIM_Try, /*On fail goto*//*Label 123*/ 1753, // Rule ID 3967 // 1600 GIM_CheckFeatures, GIFBS_HasBWI, 1601 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v64s8, 1602 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v64s8, 1603 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 1604 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID, 1605 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR512RegClassID, 1606 // (add:{ *:[v64i8] } VR512:{ *:[v64i8] }:$src1, VR512:{ *:[v64i8] }:$src2) => (VPADDBZrr:{ *:[v64i8] } VR512:{ *:[v64i8] }:$src1, VR512:{ *:[v64i8] }:$src2) 1607 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPADDBZrr, 1608 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1609 // GIR_Coverage, 3967, 1610 GIR_Done, 1611 // Label 123: @1753 1612 GIM_Reject, 1613 // Label 60: @1754 1614 GIM_Reject, 1615 // Label 1: @1755 1616 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 25, /*)*//*default:*//*Label 140*/ 2835, 1617 /*GILLT_s8*//*Label 124*/ 1785, 1618 /*GILLT_s16*//*Label 125*/ 1851, 1619 /*GILLT_s32*//*Label 126*/ 1950, 1620 /*GILLT_s64*//*Label 127*/ 2049, 0, 0, 0, 1621 /*GILLT_v2s64*//*Label 128*/ 2151, 0, 1622 /*GILLT_v4s32*//*Label 129*/ 2232, 1623 /*GILLT_v4s64*//*Label 130*/ 2313, 0, 1624 /*GILLT_v8s16*//*Label 131*/ 2371, 1625 /*GILLT_v8s32*//*Label 132*/ 2452, 1626 /*GILLT_v8s64*//*Label 133*/ 2510, 0, 1627 /*GILLT_v16s8*//*Label 134*/ 2542, 1628 /*GILLT_v16s16*//*Label 135*/ 2623, 1629 /*GILLT_v16s32*//*Label 136*/ 2681, 0, 1630 /*GILLT_v32s8*//*Label 137*/ 2713, 1631 /*GILLT_v32s16*//*Label 138*/ 2771, 0, 1632 /*GILLT_v64s8*//*Label 139*/ 2803, 1633 // Label 124: @1785 1634 GIM_Try, /*On fail goto*//*Label 141*/ 1850, 1635 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s8, 1636 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s8, 1637 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR8RegClassID, 1638 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR8RegClassID, 1639 GIM_Try, /*On fail goto*//*Label 142*/ 1833, // Rule ID 17305 // 1640 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 1641 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 1642 // MIs[1] Operand 1 1643 // No operand predicates 1644 GIM_CheckIsSafeToFold, /*InsnID*/1, 1645 // (sub:{ *:[i8] } GR8:{ *:[i8] }:$src1, (imm:{ *:[i8] }):$src2) => (SUB8ri:{ *:[i8] }:{ *:[i32] } GR8:{ *:[i8] }:$src1, (imm:{ *:[i8] }):$src2) 1646 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SUB8ri, 1647 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 1648 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 1649 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2 1650 GIR_EraseFromParent, /*InsnID*/0, 1651 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1652 // GIR_Coverage, 17305, 1653 GIR_Done, 1654 // Label 142: @1833 1655 GIM_Try, /*On fail goto*//*Label 143*/ 1849, // Rule ID 17297 // 1656 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR8RegClassID, 1657 // (sub:{ *:[i8] } GR8:{ *:[i8] }:$src1, GR8:{ *:[i8] }:$src2) => (SUB8rr:{ *:[i8] }:{ *:[i32] } GR8:{ *:[i8] }:$src1, GR8:{ *:[i8] }:$src2) 1658 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::SUB8rr, 1659 GIR_AddImplicitDef, /*InsnID*/0, X86::EFLAGS, 1660 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1661 // GIR_Coverage, 17297, 1662 GIR_Done, 1663 // Label 143: @1849 1664 GIM_Reject, 1665 // Label 141: @1850 1666 GIM_Reject, 1667 // Label 125: @1851 1668 GIM_Try, /*On fail goto*//*Label 144*/ 1949, 1669 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, 1670 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16, 1671 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR16RegClassID, 1672 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR16RegClassID, 1673 GIM_Try, /*On fail goto*//*Label 145*/ 1902, // Rule ID 17308 // 1674 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 1675 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 1676 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_i16immSExt8, 1677 // MIs[1] Operand 1 1678 // No operand predicates 1679 GIM_CheckIsSafeToFold, /*InsnID*/1, 1680 // (sub:{ *:[i16] } GR16:{ *:[i16] }:$src1, (imm:{ *:[i16] })<<P:Predicate_i16immSExt8>>:$src2) => (SUB16ri8:{ *:[i16] }:{ *:[i32] } GR16:{ *:[i16] }:$src1, (imm:{ *:[i16] })<<P:Predicate_i16immSExt8>>:$src2) 1681 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SUB16ri8, 1682 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 1683 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 1684 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2 1685 GIR_EraseFromParent, /*InsnID*/0, 1686 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1687 // GIR_Coverage, 17308, 1688 GIR_Done, 1689 // Label 145: @1902 1690 GIM_Try, /*On fail goto*//*Label 146*/ 1932, // Rule ID 17306 // 1691 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 1692 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 1693 // MIs[1] Operand 1 1694 // No operand predicates 1695 GIM_CheckIsSafeToFold, /*InsnID*/1, 1696 // (sub:{ *:[i16] } GR16:{ *:[i16] }:$src1, (imm:{ *:[i16] }):$src2) => (SUB16ri:{ *:[i16] }:{ *:[i32] } GR16:{ *:[i16] }:$src1, (imm:{ *:[i16] }):$src2) 1697 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SUB16ri, 1698 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 1699 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 1700 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2 1701 GIR_EraseFromParent, /*InsnID*/0, 1702 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1703 // GIR_Coverage, 17306, 1704 GIR_Done, 1705 // Label 146: @1932 1706 GIM_Try, /*On fail goto*//*Label 147*/ 1948, // Rule ID 17298 // 1707 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR16RegClassID, 1708 // (sub:{ *:[i16] } GR16:{ *:[i16] }:$src1, GR16:{ *:[i16] }:$src2) => (SUB16rr:{ *:[i16] }:{ *:[i32] } GR16:{ *:[i16] }:$src1, GR16:{ *:[i16] }:$src2) 1709 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::SUB16rr, 1710 GIR_AddImplicitDef, /*InsnID*/0, X86::EFLAGS, 1711 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1712 // GIR_Coverage, 17298, 1713 GIR_Done, 1714 // Label 147: @1948 1715 GIM_Reject, 1716 // Label 144: @1949 1717 GIM_Reject, 1718 // Label 126: @1950 1719 GIM_Try, /*On fail goto*//*Label 148*/ 2048, 1720 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 1721 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 1722 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 1723 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR32RegClassID, 1724 GIM_Try, /*On fail goto*//*Label 149*/ 2001, // Rule ID 17309 // 1725 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 1726 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 1727 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_i32immSExt8, 1728 // MIs[1] Operand 1 1729 // No operand predicates 1730 GIM_CheckIsSafeToFold, /*InsnID*/1, 1731 // (sub:{ *:[i32] } GR32:{ *:[i32] }:$src1, (imm:{ *:[i32] })<<P:Predicate_i32immSExt8>>:$src2) => (SUB32ri8:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src1, (imm:{ *:[i32] })<<P:Predicate_i32immSExt8>>:$src2) 1732 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SUB32ri8, 1733 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 1734 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 1735 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2 1736 GIR_EraseFromParent, /*InsnID*/0, 1737 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1738 // GIR_Coverage, 17309, 1739 GIR_Done, 1740 // Label 149: @2001 1741 GIM_Try, /*On fail goto*//*Label 150*/ 2031, // Rule ID 17307 // 1742 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 1743 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 1744 // MIs[1] Operand 1 1745 // No operand predicates 1746 GIM_CheckIsSafeToFold, /*InsnID*/1, 1747 // (sub:{ *:[i32] } GR32:{ *:[i32] }:$src1, (imm:{ *:[i32] }):$src2) => (SUB32ri:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src1, (imm:{ *:[i32] }):$src2) 1748 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SUB32ri, 1749 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 1750 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 1751 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2 1752 GIR_EraseFromParent, /*InsnID*/0, 1753 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1754 // GIR_Coverage, 17307, 1755 GIR_Done, 1756 // Label 150: @2031 1757 GIM_Try, /*On fail goto*//*Label 151*/ 2047, // Rule ID 17299 // 1758 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR32RegClassID, 1759 // (sub:{ *:[i32] } GR32:{ *:[i32] }:$src1, GR32:{ *:[i32] }:$src2) => (SUB32rr:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src1, GR32:{ *:[i32] }:$src2) 1760 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::SUB32rr, 1761 GIR_AddImplicitDef, /*InsnID*/0, X86::EFLAGS, 1762 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1763 // GIR_Coverage, 17299, 1764 GIR_Done, 1765 // Label 151: @2047 1766 GIM_Reject, 1767 // Label 148: @2048 1768 GIM_Reject, 1769 // Label 127: @2049 1770 GIM_Try, /*On fail goto*//*Label 152*/ 2150, 1771 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 1772 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 1773 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID, 1774 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR64RegClassID, 1775 GIM_Try, /*On fail goto*//*Label 153*/ 2100, // Rule ID 17310 // 1776 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 1777 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 1778 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_i64immSExt8, 1779 // MIs[1] Operand 1 1780 // No operand predicates 1781 GIM_CheckIsSafeToFold, /*InsnID*/1, 1782 // (sub:{ *:[i64] } GR64:{ *:[i64] }:$src1, (imm:{ *:[i64] })<<P:Predicate_i64immSExt8>>:$src2) => (SUB64ri8:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src1, (imm:{ *:[i64] })<<P:Predicate_i64immSExt8>>:$src2) 1783 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SUB64ri8, 1784 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 1785 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 1786 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2 1787 GIR_EraseFromParent, /*InsnID*/0, 1788 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1789 // GIR_Coverage, 17310, 1790 GIR_Done, 1791 // Label 153: @2100 1792 GIM_Try, /*On fail goto*//*Label 154*/ 2133, // Rule ID 17311 // 1793 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 1794 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 1795 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_i64immSExt32, 1796 // MIs[1] Operand 1 1797 // No operand predicates 1798 GIM_CheckIsSafeToFold, /*InsnID*/1, 1799 // (sub:{ *:[i64] } GR64:{ *:[i64] }:$src1, (imm:{ *:[i64] })<<P:Predicate_i64immSExt32>>:$src2) => (SUB64ri32:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src1, (imm:{ *:[i64] })<<P:Predicate_i64immSExt32>>:$src2) 1800 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SUB64ri32, 1801 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 1802 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 1803 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2 1804 GIR_EraseFromParent, /*InsnID*/0, 1805 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1806 // GIR_Coverage, 17311, 1807 GIR_Done, 1808 // Label 154: @2133 1809 GIM_Try, /*On fail goto*//*Label 155*/ 2149, // Rule ID 17300 // 1810 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR64RegClassID, 1811 // (sub:{ *:[i64] } GR64:{ *:[i64] }:$src1, GR64:{ *:[i64] }:$src2) => (SUB64rr:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src1, GR64:{ *:[i64] }:$src2) 1812 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::SUB64rr, 1813 GIR_AddImplicitDef, /*InsnID*/0, X86::EFLAGS, 1814 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1815 // GIR_Coverage, 17300, 1816 GIR_Done, 1817 // Label 155: @2149 1818 GIM_Reject, 1819 // Label 152: @2150 1820 GIM_Reject, 1821 // Label 128: @2151 1822 GIM_Try, /*On fail goto*//*Label 156*/ 2231, 1823 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, 1824 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 1825 GIM_Try, /*On fail goto*//*Label 157*/ 2184, // Rule ID 2065 // 1826 GIM_CheckFeatures, GIFBS_HasAVX_NoVLX, 1827 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 1828 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 1829 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 1830 // (sub:{ *:[v2i64] } VR128:{ *:[v2i64] }:$src1, VR128:{ *:[v2i64] }:$src2) => (VPSUBQrr:{ *:[v2i64] } VR128:{ *:[v2i64] }:$src1, VR128:{ *:[v2i64] }:$src2) 1831 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPSUBQrr, 1832 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1833 // GIR_Coverage, 2065, 1834 GIR_Done, 1835 // Label 157: @2184 1836 GIM_Try, /*On fail goto*//*Label 158*/ 2207, // Rule ID 2067 // 1837 GIM_CheckFeatures, GIFBS_UseSSE2, 1838 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 1839 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 1840 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 1841 // (sub:{ *:[v2i64] } VR128:{ *:[v2i64] }:$src1, VR128:{ *:[v2i64] }:$src2) => (PSUBQrr:{ *:[v2i64] } VR128:{ *:[v2i64] }:$src1, VR128:{ *:[v2i64] }:$src2) 1842 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::PSUBQrr, 1843 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1844 // GIR_Coverage, 2067, 1845 GIR_Done, 1846 // Label 158: @2207 1847 GIM_Try, /*On fail goto*//*Label 159*/ 2230, // Rule ID 4003 // 1848 GIM_CheckFeatures, GIFBS_HasAVX512_HasVLX, 1849 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 1850 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 1851 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128XRegClassID, 1852 // (sub:{ *:[v2i64] } VR128X:{ *:[v2i64] }:$src1, VR128X:{ *:[v2i64] }:$src2) => (VPSUBQZ128rr:{ *:[v2i64] } VR128X:{ *:[v2i64] }:$src1, VR128X:{ *:[v2i64] }:$src2) 1853 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPSUBQZ128rr, 1854 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1855 // GIR_Coverage, 4003, 1856 GIR_Done, 1857 // Label 159: @2230 1858 GIM_Reject, 1859 // Label 156: @2231 1860 GIM_Reject, 1861 // Label 129: @2232 1862 GIM_Try, /*On fail goto*//*Label 160*/ 2312, 1863 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 1864 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 1865 GIM_Try, /*On fail goto*//*Label 161*/ 2265, // Rule ID 2059 // 1866 GIM_CheckFeatures, GIFBS_HasAVX_NoVLX, 1867 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 1868 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 1869 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 1870 // (sub:{ *:[v4i32] } VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2) => (VPSUBDrr:{ *:[v4i32] } VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2) 1871 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPSUBDrr, 1872 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1873 // GIR_Coverage, 2059, 1874 GIR_Done, 1875 // Label 161: @2265 1876 GIM_Try, /*On fail goto*//*Label 162*/ 2288, // Rule ID 2061 // 1877 GIM_CheckFeatures, GIFBS_UseSSE2, 1878 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 1879 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 1880 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 1881 // (sub:{ *:[v4i32] } VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2) => (PSUBDrr:{ *:[v4i32] } VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2) 1882 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::PSUBDrr, 1883 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1884 // GIR_Coverage, 2061, 1885 GIR_Done, 1886 // Label 162: @2288 1887 GIM_Try, /*On fail goto*//*Label 163*/ 2311, // Rule ID 4030 // 1888 GIM_CheckFeatures, GIFBS_HasAVX512_HasVLX, 1889 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 1890 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 1891 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128XRegClassID, 1892 // (sub:{ *:[v4i32] } VR128X:{ *:[v4i32] }:$src1, VR128X:{ *:[v4i32] }:$src2) => (VPSUBDZ128rr:{ *:[v4i32] } VR128X:{ *:[v4i32] }:$src1, VR128X:{ *:[v4i32] }:$src2) 1893 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPSUBDZ128rr, 1894 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1895 // GIR_Coverage, 4030, 1896 GIR_Done, 1897 // Label 163: @2311 1898 GIM_Reject, 1899 // Label 160: @2312 1900 GIM_Reject, 1901 // Label 130: @2313 1902 GIM_Try, /*On fail goto*//*Label 164*/ 2370, 1903 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s64, 1904 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s64, 1905 GIM_Try, /*On fail goto*//*Label 165*/ 2346, // Rule ID 2069 // 1906 GIM_CheckFeatures, GIFBS_HasAVX2_NoVLX, 1907 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID, 1908 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256RegClassID, 1909 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID, 1910 // (sub:{ *:[v4i64] } VR256:{ *:[v4i64] }:$src1, VR256:{ *:[v4i64] }:$src2) => (VPSUBQYrr:{ *:[v4i64] } VR256:{ *:[v4i64] }:$src1, VR256:{ *:[v4i64] }:$src2) 1911 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPSUBQYrr, 1912 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1913 // GIR_Coverage, 2069, 1914 GIR_Done, 1915 // Label 165: @2346 1916 GIM_Try, /*On fail goto*//*Label 166*/ 2369, // Rule ID 3994 // 1917 GIM_CheckFeatures, GIFBS_HasAVX512_HasVLX, 1918 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 1919 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 1920 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256XRegClassID, 1921 // (sub:{ *:[v4i64] } VR256X:{ *:[v4i64] }:$src1, VR256X:{ *:[v4i64] }:$src2) => (VPSUBQZ256rr:{ *:[v4i64] } VR256X:{ *:[v4i64] }:$src1, VR256X:{ *:[v4i64] }:$src2) 1922 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPSUBQZ256rr, 1923 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1924 // GIR_Coverage, 3994, 1925 GIR_Done, 1926 // Label 166: @2369 1927 GIM_Reject, 1928 // Label 164: @2370 1929 GIM_Reject, 1930 // Label 131: @2371 1931 GIM_Try, /*On fail goto*//*Label 167*/ 2451, 1932 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, 1933 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 1934 GIM_Try, /*On fail goto*//*Label 168*/ 2404, // Rule ID 2053 // 1935 GIM_CheckFeatures, GIFBS_HasAVX_NoVLX_Or_NoBWI, 1936 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 1937 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 1938 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 1939 // (sub:{ *:[v8i16] } VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2) => (VPSUBWrr:{ *:[v8i16] } VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2) 1940 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPSUBWrr, 1941 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1942 // GIR_Coverage, 2053, 1943 GIR_Done, 1944 // Label 168: @2404 1945 GIM_Try, /*On fail goto*//*Label 169*/ 2427, // Rule ID 2055 // 1946 GIM_CheckFeatures, GIFBS_UseSSE2, 1947 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 1948 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 1949 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 1950 // (sub:{ *:[v8i16] } VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2) => (PSUBWrr:{ *:[v8i16] } VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2) 1951 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::PSUBWrr, 1952 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1953 // GIR_Coverage, 2055, 1954 GIR_Done, 1955 // Label 169: @2427 1956 GIM_Try, /*On fail goto*//*Label 170*/ 2450, // Rule ID 4051 // 1957 GIM_CheckFeatures, GIFBS_HasBWI_HasVLX, 1958 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 1959 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 1960 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128XRegClassID, 1961 // (sub:{ *:[v8i16] } VR128X:{ *:[v8i16] }:$src1, VR128X:{ *:[v8i16] }:$src2) => (VPSUBWZ128rr:{ *:[v8i16] } VR128X:{ *:[v8i16] }:$src1, VR128X:{ *:[v8i16] }:$src2) 1962 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPSUBWZ128rr, 1963 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1964 // GIR_Coverage, 4051, 1965 GIR_Done, 1966 // Label 170: @2450 1967 GIM_Reject, 1968 // Label 167: @2451 1969 GIM_Reject, 1970 // Label 132: @2452 1971 GIM_Try, /*On fail goto*//*Label 171*/ 2509, 1972 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s32, 1973 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s32, 1974 GIM_Try, /*On fail goto*//*Label 172*/ 2485, // Rule ID 2063 // 1975 GIM_CheckFeatures, GIFBS_HasAVX2_NoVLX, 1976 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID, 1977 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256RegClassID, 1978 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID, 1979 // (sub:{ *:[v8i32] } VR256:{ *:[v8i32] }:$src1, VR256:{ *:[v8i32] }:$src2) => (VPSUBDYrr:{ *:[v8i32] } VR256:{ *:[v8i32] }:$src1, VR256:{ *:[v8i32] }:$src2) 1980 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPSUBDYrr, 1981 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1982 // GIR_Coverage, 2063, 1983 GIR_Done, 1984 // Label 172: @2485 1985 GIM_Try, /*On fail goto*//*Label 173*/ 2508, // Rule ID 4021 // 1986 GIM_CheckFeatures, GIFBS_HasAVX512_HasVLX, 1987 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 1988 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 1989 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256XRegClassID, 1990 // (sub:{ *:[v8i32] } VR256X:{ *:[v8i32] }:$src1, VR256X:{ *:[v8i32] }:$src2) => (VPSUBDZ256rr:{ *:[v8i32] } VR256X:{ *:[v8i32] }:$src1, VR256X:{ *:[v8i32] }:$src2) 1991 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPSUBDZ256rr, 1992 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1993 // GIR_Coverage, 4021, 1994 GIR_Done, 1995 // Label 173: @2508 1996 GIM_Reject, 1997 // Label 171: @2509 1998 GIM_Reject, 1999 // Label 133: @2510 2000 GIM_Try, /*On fail goto*//*Label 174*/ 2541, // Rule ID 3985 // 2001 GIM_CheckFeatures, GIFBS_HasAVX512, 2002 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s64, 2003 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s64, 2004 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 2005 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID, 2006 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR512RegClassID, 2007 // (sub:{ *:[v8i64] } VR512:{ *:[v8i64] }:$src1, VR512:{ *:[v8i64] }:$src2) => (VPSUBQZrr:{ *:[v8i64] } VR512:{ *:[v8i64] }:$src1, VR512:{ *:[v8i64] }:$src2) 2008 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPSUBQZrr, 2009 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2010 // GIR_Coverage, 3985, 2011 GIR_Done, 2012 // Label 174: @2541 2013 GIM_Reject, 2014 // Label 134: @2542 2015 GIM_Try, /*On fail goto*//*Label 175*/ 2622, 2016 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, 2017 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 2018 GIM_Try, /*On fail goto*//*Label 176*/ 2575, // Rule ID 2047 // 2019 GIM_CheckFeatures, GIFBS_HasAVX_NoVLX_Or_NoBWI, 2020 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 2021 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 2022 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 2023 // (sub:{ *:[v16i8] } VR128:{ *:[v16i8] }:$src1, VR128:{ *:[v16i8] }:$src2) => (VPSUBBrr:{ *:[v16i8] } VR128:{ *:[v16i8] }:$src1, VR128:{ *:[v16i8] }:$src2) 2024 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPSUBBrr, 2025 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2026 // GIR_Coverage, 2047, 2027 GIR_Done, 2028 // Label 176: @2575 2029 GIM_Try, /*On fail goto*//*Label 177*/ 2598, // Rule ID 2049 // 2030 GIM_CheckFeatures, GIFBS_UseSSE2, 2031 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 2032 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 2033 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 2034 // (sub:{ *:[v16i8] } VR128:{ *:[v16i8] }:$src1, VR128:{ *:[v16i8] }:$src2) => (PSUBBrr:{ *:[v16i8] } VR128:{ *:[v16i8] }:$src1, VR128:{ *:[v16i8] }:$src2) 2035 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::PSUBBrr, 2036 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2037 // GIR_Coverage, 2049, 2038 GIR_Done, 2039 // Label 177: @2598 2040 GIM_Try, /*On fail goto*//*Label 178*/ 2621, // Rule ID 4069 // 2041 GIM_CheckFeatures, GIFBS_HasBWI_HasVLX, 2042 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 2043 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 2044 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128XRegClassID, 2045 // (sub:{ *:[v16i8] } VR128X:{ *:[v16i8] }:$src1, VR128X:{ *:[v16i8] }:$src2) => (VPSUBBZ128rr:{ *:[v16i8] } VR128X:{ *:[v16i8] }:$src1, VR128X:{ *:[v16i8] }:$src2) 2046 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPSUBBZ128rr, 2047 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2048 // GIR_Coverage, 4069, 2049 GIR_Done, 2050 // Label 178: @2621 2051 GIM_Reject, 2052 // Label 175: @2622 2053 GIM_Reject, 2054 // Label 135: @2623 2055 GIM_Try, /*On fail goto*//*Label 179*/ 2680, 2056 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s16, 2057 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s16, 2058 GIM_Try, /*On fail goto*//*Label 180*/ 2656, // Rule ID 2057 // 2059 GIM_CheckFeatures, GIFBS_HasAVX2_NoVLX_Or_NoBWI, 2060 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID, 2061 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256RegClassID, 2062 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID, 2063 // (sub:{ *:[v16i16] } VR256:{ *:[v16i16] }:$src1, VR256:{ *:[v16i16] }:$src2) => (VPSUBWYrr:{ *:[v16i16] } VR256:{ *:[v16i16] }:$src1, VR256:{ *:[v16i16] }:$src2) 2064 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPSUBWYrr, 2065 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2066 // GIR_Coverage, 2057, 2067 GIR_Done, 2068 // Label 180: @2656 2069 GIM_Try, /*On fail goto*//*Label 181*/ 2679, // Rule ID 4045 // 2070 GIM_CheckFeatures, GIFBS_HasBWI_HasVLX, 2071 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 2072 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 2073 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256XRegClassID, 2074 // (sub:{ *:[v16i16] } VR256X:{ *:[v16i16] }:$src1, VR256X:{ *:[v16i16] }:$src2) => (VPSUBWZ256rr:{ *:[v16i16] } VR256X:{ *:[v16i16] }:$src1, VR256X:{ *:[v16i16] }:$src2) 2075 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPSUBWZ256rr, 2076 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2077 // GIR_Coverage, 4045, 2078 GIR_Done, 2079 // Label 181: @2679 2080 GIM_Reject, 2081 // Label 179: @2680 2082 GIM_Reject, 2083 // Label 136: @2681 2084 GIM_Try, /*On fail goto*//*Label 182*/ 2712, // Rule ID 4012 // 2085 GIM_CheckFeatures, GIFBS_HasAVX512, 2086 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s32, 2087 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s32, 2088 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 2089 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID, 2090 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR512RegClassID, 2091 // (sub:{ *:[v16i32] } VR512:{ *:[v16i32] }:$src1, VR512:{ *:[v16i32] }:$src2) => (VPSUBDZrr:{ *:[v16i32] } VR512:{ *:[v16i32] }:$src1, VR512:{ *:[v16i32] }:$src2) 2092 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPSUBDZrr, 2093 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2094 // GIR_Coverage, 4012, 2095 GIR_Done, 2096 // Label 182: @2712 2097 GIM_Reject, 2098 // Label 137: @2713 2099 GIM_Try, /*On fail goto*//*Label 183*/ 2770, 2100 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v32s8, 2101 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v32s8, 2102 GIM_Try, /*On fail goto*//*Label 184*/ 2746, // Rule ID 2051 // 2103 GIM_CheckFeatures, GIFBS_HasAVX2_NoVLX_Or_NoBWI, 2104 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID, 2105 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256RegClassID, 2106 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID, 2107 // (sub:{ *:[v32i8] } VR256:{ *:[v32i8] }:$src1, VR256:{ *:[v32i8] }:$src2) => (VPSUBBYrr:{ *:[v32i8] } VR256:{ *:[v32i8] }:$src1, VR256:{ *:[v32i8] }:$src2) 2108 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPSUBBYrr, 2109 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2110 // GIR_Coverage, 2051, 2111 GIR_Done, 2112 // Label 184: @2746 2113 GIM_Try, /*On fail goto*//*Label 185*/ 2769, // Rule ID 4063 // 2114 GIM_CheckFeatures, GIFBS_HasBWI_HasVLX, 2115 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 2116 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 2117 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256XRegClassID, 2118 // (sub:{ *:[v32i8] } VR256X:{ *:[v32i8] }:$src1, VR256X:{ *:[v32i8] }:$src2) => (VPSUBBZ256rr:{ *:[v32i8] } VR256X:{ *:[v32i8] }:$src1, VR256X:{ *:[v32i8] }:$src2) 2119 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPSUBBZ256rr, 2120 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2121 // GIR_Coverage, 4063, 2122 GIR_Done, 2123 // Label 185: @2769 2124 GIM_Reject, 2125 // Label 183: @2770 2126 GIM_Reject, 2127 // Label 138: @2771 2128 GIM_Try, /*On fail goto*//*Label 186*/ 2802, // Rule ID 4039 // 2129 GIM_CheckFeatures, GIFBS_HasBWI, 2130 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v32s16, 2131 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v32s16, 2132 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 2133 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID, 2134 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR512RegClassID, 2135 // (sub:{ *:[v32i16] } VR512:{ *:[v32i16] }:$src1, VR512:{ *:[v32i16] }:$src2) => (VPSUBWZrr:{ *:[v32i16] } VR512:{ *:[v32i16] }:$src1, VR512:{ *:[v32i16] }:$src2) 2136 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPSUBWZrr, 2137 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2138 // GIR_Coverage, 4039, 2139 GIR_Done, 2140 // Label 186: @2802 2141 GIM_Reject, 2142 // Label 139: @2803 2143 GIM_Try, /*On fail goto*//*Label 187*/ 2834, // Rule ID 4057 // 2144 GIM_CheckFeatures, GIFBS_HasBWI, 2145 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v64s8, 2146 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v64s8, 2147 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 2148 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID, 2149 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR512RegClassID, 2150 // (sub:{ *:[v64i8] } VR512:{ *:[v64i8] }:$src1, VR512:{ *:[v64i8] }:$src2) => (VPSUBBZrr:{ *:[v64i8] } VR512:{ *:[v64i8] }:$src1, VR512:{ *:[v64i8] }:$src2) 2151 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPSUBBZrr, 2152 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2153 // GIR_Coverage, 4057, 2154 GIR_Done, 2155 // Label 187: @2834 2156 GIM_Reject, 2157 // Label 140: @2835 2158 GIM_Reject, 2159 // Label 2: @2836 2160 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/2, 23, /*)*//*default:*//*Label 200*/ 3601, 2161 /*GILLT_s16*//*Label 188*/ 2863, 2162 /*GILLT_s32*//*Label 189*/ 2962, 2163 /*GILLT_s64*//*Label 190*/ 3061, 0, 0, 0, 2164 /*GILLT_v2s64*//*Label 191*/ 3163, 0, 2165 /*GILLT_v4s32*//*Label 192*/ 3195, 2166 /*GILLT_v4s64*//*Label 193*/ 3276, 0, 2167 /*GILLT_v8s16*//*Label 194*/ 3308, 2168 /*GILLT_v8s32*//*Label 195*/ 3389, 2169 /*GILLT_v8s64*//*Label 196*/ 3447, 0, 0, 2170 /*GILLT_v16s16*//*Label 197*/ 3479, 2171 /*GILLT_v16s32*//*Label 198*/ 3537, 0, 0, 2172 /*GILLT_v32s16*//*Label 199*/ 3569, 2173 // Label 188: @2863 2174 GIM_Try, /*On fail goto*//*Label 201*/ 2961, 2175 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, 2176 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16, 2177 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR16RegClassID, 2178 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR16RegClassID, 2179 GIM_Try, /*On fail goto*//*Label 202*/ 2914, // Rule ID 17325 // 2180 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 2181 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 2182 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_i16immSExt8, 2183 // MIs[1] Operand 1 2184 // No operand predicates 2185 GIM_CheckIsSafeToFold, /*InsnID*/1, 2186 // (mul:{ *:[i16] } GR16:{ *:[i16] }:$src1, (imm:{ *:[i16] })<<P:Predicate_i16immSExt8>>:$src2) => (IMUL16rri8:{ *:[i16] }:{ *:[i32] } GR16:{ *:[i16] }:$src1, (imm:{ *:[i16] })<<P:Predicate_i16immSExt8>>:$src2) 2187 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::IMUL16rri8, 2188 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 2189 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 2190 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2 2191 GIR_EraseFromParent, /*InsnID*/0, 2192 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2193 // GIR_Coverage, 17325, 2194 GIR_Done, 2195 // Label 202: @2914 2196 GIM_Try, /*On fail goto*//*Label 203*/ 2944, // Rule ID 17323 // 2197 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 2198 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 2199 // MIs[1] Operand 1 2200 // No operand predicates 2201 GIM_CheckIsSafeToFold, /*InsnID*/1, 2202 // (mul:{ *:[i16] } GR16:{ *:[i16] }:$src1, (imm:{ *:[i16] }):$src2) => (IMUL16rri:{ *:[i16] }:{ *:[i32] } GR16:{ *:[i16] }:$src1, (imm:{ *:[i16] }):$src2) 2203 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::IMUL16rri, 2204 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 2205 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 2206 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2 2207 GIR_EraseFromParent, /*InsnID*/0, 2208 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2209 // GIR_Coverage, 17323, 2210 GIR_Done, 2211 // Label 203: @2944 2212 GIM_Try, /*On fail goto*//*Label 204*/ 2960, // Rule ID 17317 // 2213 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR16RegClassID, 2214 // (mul:{ *:[i16] } GR16:{ *:[i16] }:$src1, GR16:{ *:[i16] }:$src2) => (IMUL16rr:{ *:[i16] }:{ *:[i32] } GR16:{ *:[i16] }:$src1, GR16:{ *:[i16] }:$src2) 2215 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::IMUL16rr, 2216 GIR_AddImplicitDef, /*InsnID*/0, X86::EFLAGS, 2217 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2218 // GIR_Coverage, 17317, 2219 GIR_Done, 2220 // Label 204: @2960 2221 GIM_Reject, 2222 // Label 201: @2961 2223 GIM_Reject, 2224 // Label 189: @2962 2225 GIM_Try, /*On fail goto*//*Label 205*/ 3060, 2226 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 2227 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 2228 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 2229 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR32RegClassID, 2230 GIM_Try, /*On fail goto*//*Label 206*/ 3013, // Rule ID 17326 // 2231 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 2232 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 2233 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_i32immSExt8, 2234 // MIs[1] Operand 1 2235 // No operand predicates 2236 GIM_CheckIsSafeToFold, /*InsnID*/1, 2237 // (mul:{ *:[i32] } GR32:{ *:[i32] }:$src1, (imm:{ *:[i32] })<<P:Predicate_i32immSExt8>>:$src2) => (IMUL32rri8:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src1, (imm:{ *:[i32] })<<P:Predicate_i32immSExt8>>:$src2) 2238 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::IMUL32rri8, 2239 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 2240 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 2241 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2 2242 GIR_EraseFromParent, /*InsnID*/0, 2243 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2244 // GIR_Coverage, 17326, 2245 GIR_Done, 2246 // Label 206: @3013 2247 GIM_Try, /*On fail goto*//*Label 207*/ 3043, // Rule ID 17324 // 2248 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 2249 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 2250 // MIs[1] Operand 1 2251 // No operand predicates 2252 GIM_CheckIsSafeToFold, /*InsnID*/1, 2253 // (mul:{ *:[i32] } GR32:{ *:[i32] }:$src1, (imm:{ *:[i32] }):$src2) => (IMUL32rri:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src1, (imm:{ *:[i32] }):$src2) 2254 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::IMUL32rri, 2255 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 2256 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 2257 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2 2258 GIR_EraseFromParent, /*InsnID*/0, 2259 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2260 // GIR_Coverage, 17324, 2261 GIR_Done, 2262 // Label 207: @3043 2263 GIM_Try, /*On fail goto*//*Label 208*/ 3059, // Rule ID 17318 // 2264 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR32RegClassID, 2265 // (mul:{ *:[i32] } GR32:{ *:[i32] }:$src1, GR32:{ *:[i32] }:$src2) => (IMUL32rr:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src1, GR32:{ *:[i32] }:$src2) 2266 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::IMUL32rr, 2267 GIR_AddImplicitDef, /*InsnID*/0, X86::EFLAGS, 2268 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2269 // GIR_Coverage, 17318, 2270 GIR_Done, 2271 // Label 208: @3059 2272 GIM_Reject, 2273 // Label 205: @3060 2274 GIM_Reject, 2275 // Label 190: @3061 2276 GIM_Try, /*On fail goto*//*Label 209*/ 3162, 2277 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 2278 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 2279 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID, 2280 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR64RegClassID, 2281 GIM_Try, /*On fail goto*//*Label 210*/ 3112, // Rule ID 17327 // 2282 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 2283 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 2284 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_i64immSExt8, 2285 // MIs[1] Operand 1 2286 // No operand predicates 2287 GIM_CheckIsSafeToFold, /*InsnID*/1, 2288 // (mul:{ *:[i64] } GR64:{ *:[i64] }:$src1, (imm:{ *:[i64] })<<P:Predicate_i64immSExt8>>:$src2) => (IMUL64rri8:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src1, (imm:{ *:[i64] })<<P:Predicate_i64immSExt8>>:$src2) 2289 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::IMUL64rri8, 2290 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 2291 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 2292 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2 2293 GIR_EraseFromParent, /*InsnID*/0, 2294 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2295 // GIR_Coverage, 17327, 2296 GIR_Done, 2297 // Label 210: @3112 2298 GIM_Try, /*On fail goto*//*Label 211*/ 3145, // Rule ID 17328 // 2299 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 2300 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 2301 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_i64immSExt32, 2302 // MIs[1] Operand 1 2303 // No operand predicates 2304 GIM_CheckIsSafeToFold, /*InsnID*/1, 2305 // (mul:{ *:[i64] } GR64:{ *:[i64] }:$src1, (imm:{ *:[i64] })<<P:Predicate_i64immSExt32>>:$src2) => (IMUL64rri32:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src1, (imm:{ *:[i64] })<<P:Predicate_i64immSExt32>>:$src2) 2306 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::IMUL64rri32, 2307 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 2308 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 2309 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2 2310 GIR_EraseFromParent, /*InsnID*/0, 2311 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2312 // GIR_Coverage, 17328, 2313 GIR_Done, 2314 // Label 211: @3145 2315 GIM_Try, /*On fail goto*//*Label 212*/ 3161, // Rule ID 17319 // 2316 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR64RegClassID, 2317 // (mul:{ *:[i64] } GR64:{ *:[i64] }:$src1, GR64:{ *:[i64] }:$src2) => (IMUL64rr:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src1, GR64:{ *:[i64] }:$src2) 2318 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::IMUL64rr, 2319 GIR_AddImplicitDef, /*InsnID*/0, X86::EFLAGS, 2320 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2321 // GIR_Coverage, 17319, 2322 GIR_Done, 2323 // Label 212: @3161 2324 GIM_Reject, 2325 // Label 209: @3162 2326 GIM_Reject, 2327 // Label 191: @3163 2328 GIM_Try, /*On fail goto*//*Label 213*/ 3194, // Rule ID 4282 // 2329 GIM_CheckFeatures, GIFBS_HasDQI_HasVLX, 2330 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, 2331 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 2332 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 2333 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 2334 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128XRegClassID, 2335 // (mul:{ *:[v2i64] } VR128X:{ *:[v2i64] }:$src1, VR128X:{ *:[v2i64] }:$src2) => (VPMULLQZ128rr:{ *:[v2i64] } VR128X:{ *:[v2i64] }:$src1, VR128X:{ *:[v2i64] }:$src2) 2336 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMULLQZ128rr, 2337 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2338 // GIR_Coverage, 4282, 2339 GIR_Done, 2340 // Label 213: @3194 2341 GIM_Reject, 2342 // Label 192: @3195 2343 GIM_Try, /*On fail goto*//*Label 214*/ 3275, 2344 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 2345 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 2346 GIM_Try, /*On fail goto*//*Label 215*/ 3228, // Rule ID 2690 // 2347 GIM_CheckFeatures, GIFBS_HasAVX_NoVLX, 2348 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 2349 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 2350 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 2351 // (mul:{ *:[v4i32] } VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2) => (VPMULLDrr:{ *:[v4i32] } VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2) 2352 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMULLDrr, 2353 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2354 // GIR_Coverage, 2690, 2355 GIR_Done, 2356 // Label 215: @3228 2357 GIM_Try, /*On fail goto*//*Label 216*/ 3251, // Rule ID 2698 // 2358 GIM_CheckFeatures, GIFBS_UseSSE41, 2359 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 2360 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 2361 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 2362 // (mul:{ *:[v4i32] } VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2) => (PMULLDrr:{ *:[v4i32] } VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2) 2363 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::PMULLDrr, 2364 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2365 // GIR_Coverage, 2698, 2366 GIR_Done, 2367 // Label 216: @3251 2368 GIM_Try, /*On fail goto*//*Label 217*/ 3274, // Rule ID 4237 // 2369 GIM_CheckFeatures, GIFBS_HasAVX512_HasVLX, 2370 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 2371 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 2372 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128XRegClassID, 2373 // (mul:{ *:[v4i32] } VR128X:{ *:[v4i32] }:$src1, VR128X:{ *:[v4i32] }:$src2) => (VPMULLDZ128rr:{ *:[v4i32] } VR128X:{ *:[v4i32] }:$src1, VR128X:{ *:[v4i32] }:$src2) 2374 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMULLDZ128rr, 2375 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2376 // GIR_Coverage, 4237, 2377 GIR_Done, 2378 // Label 217: @3274 2379 GIM_Reject, 2380 // Label 214: @3275 2381 GIM_Reject, 2382 // Label 193: @3276 2383 GIM_Try, /*On fail goto*//*Label 218*/ 3307, // Rule ID 4273 // 2384 GIM_CheckFeatures, GIFBS_HasDQI_HasVLX, 2385 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s64, 2386 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s64, 2387 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 2388 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 2389 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256XRegClassID, 2390 // (mul:{ *:[v4i64] } VR256X:{ *:[v4i64] }:$src1, VR256X:{ *:[v4i64] }:$src2) => (VPMULLQZ256rr:{ *:[v4i64] } VR256X:{ *:[v4i64] }:$src1, VR256X:{ *:[v4i64] }:$src2) 2391 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMULLQZ256rr, 2392 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2393 // GIR_Coverage, 4273, 2394 GIR_Done, 2395 // Label 218: @3307 2396 GIM_Reject, 2397 // Label 194: @3308 2398 GIM_Try, /*On fail goto*//*Label 219*/ 3388, 2399 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, 2400 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 2401 GIM_Try, /*On fail goto*//*Label 220*/ 3341, // Rule ID 2029 // 2402 GIM_CheckFeatures, GIFBS_HasAVX_NoVLX_Or_NoBWI, 2403 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 2404 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 2405 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 2406 // (mul:{ *:[v8i16] } VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2) => (VPMULLWrr:{ *:[v8i16] } VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2) 2407 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMULLWrr, 2408 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2409 // GIR_Coverage, 2029, 2410 GIR_Done, 2411 // Label 220: @3341 2412 GIM_Try, /*On fail goto*//*Label 221*/ 3364, // Rule ID 2031 // 2413 GIM_CheckFeatures, GIFBS_UseSSE2, 2414 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 2415 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 2416 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 2417 // (mul:{ *:[v8i16] } VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2) => (PMULLWrr:{ *:[v8i16] } VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2) 2418 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::PMULLWrr, 2419 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2420 // GIR_Coverage, 2031, 2421 GIR_Done, 2422 // Label 221: @3364 2423 GIM_Try, /*On fail goto*//*Label 222*/ 3387, // Rule ID 4258 // 2424 GIM_CheckFeatures, GIFBS_HasBWI_HasVLX, 2425 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 2426 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 2427 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128XRegClassID, 2428 // (mul:{ *:[v8i16] } VR128X:{ *:[v8i16] }:$src1, VR128X:{ *:[v8i16] }:$src2) => (VPMULLWZ128rr:{ *:[v8i16] } VR128X:{ *:[v8i16] }:$src1, VR128X:{ *:[v8i16] }:$src2) 2429 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMULLWZ128rr, 2430 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2431 // GIR_Coverage, 4258, 2432 GIR_Done, 2433 // Label 222: @3387 2434 GIM_Reject, 2435 // Label 219: @3388 2436 GIM_Reject, 2437 // Label 195: @3389 2438 GIM_Try, /*On fail goto*//*Label 223*/ 3446, 2439 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s32, 2440 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s32, 2441 GIM_Try, /*On fail goto*//*Label 224*/ 3422, // Rule ID 2694 // 2442 GIM_CheckFeatures, GIFBS_HasAVX2_NoVLX, 2443 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID, 2444 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256RegClassID, 2445 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID, 2446 // (mul:{ *:[v8i32] } VR256:{ *:[v8i32] }:$src1, VR256:{ *:[v8i32] }:$src2) => (VPMULLDYrr:{ *:[v8i32] } VR256:{ *:[v8i32] }:$src1, VR256:{ *:[v8i32] }:$src2) 2447 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMULLDYrr, 2448 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2449 // GIR_Coverage, 2694, 2450 GIR_Done, 2451 // Label 224: @3422 2452 GIM_Try, /*On fail goto*//*Label 225*/ 3445, // Rule ID 4228 // 2453 GIM_CheckFeatures, GIFBS_HasAVX512_HasVLX, 2454 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 2455 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 2456 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256XRegClassID, 2457 // (mul:{ *:[v8i32] } VR256X:{ *:[v8i32] }:$src1, VR256X:{ *:[v8i32] }:$src2) => (VPMULLDZ256rr:{ *:[v8i32] } VR256X:{ *:[v8i32] }:$src1, VR256X:{ *:[v8i32] }:$src2) 2458 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMULLDZ256rr, 2459 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2460 // GIR_Coverage, 4228, 2461 GIR_Done, 2462 // Label 225: @3445 2463 GIM_Reject, 2464 // Label 223: @3446 2465 GIM_Reject, 2466 // Label 196: @3447 2467 GIM_Try, /*On fail goto*//*Label 226*/ 3478, // Rule ID 4264 // 2468 GIM_CheckFeatures, GIFBS_HasDQI, 2469 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s64, 2470 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s64, 2471 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 2472 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID, 2473 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR512RegClassID, 2474 // (mul:{ *:[v8i64] } VR512:{ *:[v8i64] }:$src1, VR512:{ *:[v8i64] }:$src2) => (VPMULLQZrr:{ *:[v8i64] } VR512:{ *:[v8i64] }:$src1, VR512:{ *:[v8i64] }:$src2) 2475 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMULLQZrr, 2476 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2477 // GIR_Coverage, 4264, 2478 GIR_Done, 2479 // Label 226: @3478 2480 GIM_Reject, 2481 // Label 197: @3479 2482 GIM_Try, /*On fail goto*//*Label 227*/ 3536, 2483 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s16, 2484 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s16, 2485 GIM_Try, /*On fail goto*//*Label 228*/ 3512, // Rule ID 2033 // 2486 GIM_CheckFeatures, GIFBS_HasAVX2_NoVLX_Or_NoBWI, 2487 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID, 2488 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256RegClassID, 2489 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID, 2490 // (mul:{ *:[v16i16] } VR256:{ *:[v16i16] }:$src1, VR256:{ *:[v16i16] }:$src2) => (VPMULLWYrr:{ *:[v16i16] } VR256:{ *:[v16i16] }:$src1, VR256:{ *:[v16i16] }:$src2) 2491 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMULLWYrr, 2492 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2493 // GIR_Coverage, 2033, 2494 GIR_Done, 2495 // Label 228: @3512 2496 GIM_Try, /*On fail goto*//*Label 229*/ 3535, // Rule ID 4252 // 2497 GIM_CheckFeatures, GIFBS_HasBWI_HasVLX, 2498 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 2499 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 2500 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256XRegClassID, 2501 // (mul:{ *:[v16i16] } VR256X:{ *:[v16i16] }:$src1, VR256X:{ *:[v16i16] }:$src2) => (VPMULLWZ256rr:{ *:[v16i16] } VR256X:{ *:[v16i16] }:$src1, VR256X:{ *:[v16i16] }:$src2) 2502 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMULLWZ256rr, 2503 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2504 // GIR_Coverage, 4252, 2505 GIR_Done, 2506 // Label 229: @3535 2507 GIM_Reject, 2508 // Label 227: @3536 2509 GIM_Reject, 2510 // Label 198: @3537 2511 GIM_Try, /*On fail goto*//*Label 230*/ 3568, // Rule ID 4219 // 2512 GIM_CheckFeatures, GIFBS_HasAVX512, 2513 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s32, 2514 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s32, 2515 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 2516 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID, 2517 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR512RegClassID, 2518 // (mul:{ *:[v16i32] } VR512:{ *:[v16i32] }:$src1, VR512:{ *:[v16i32] }:$src2) => (VPMULLDZrr:{ *:[v16i32] } VR512:{ *:[v16i32] }:$src1, VR512:{ *:[v16i32] }:$src2) 2519 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMULLDZrr, 2520 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2521 // GIR_Coverage, 4219, 2522 GIR_Done, 2523 // Label 230: @3568 2524 GIM_Reject, 2525 // Label 199: @3569 2526 GIM_Try, /*On fail goto*//*Label 231*/ 3600, // Rule ID 4246 // 2527 GIM_CheckFeatures, GIFBS_HasBWI, 2528 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v32s16, 2529 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v32s16, 2530 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 2531 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID, 2532 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR512RegClassID, 2533 // (mul:{ *:[v32i16] } VR512:{ *:[v32i16] }:$src1, VR512:{ *:[v32i16] }:$src2) => (VPMULLWZrr:{ *:[v32i16] } VR512:{ *:[v32i16] }:$src1, VR512:{ *:[v32i16] }:$src2) 2534 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMULLWZrr, 2535 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2536 // GIR_Coverage, 4246, 2537 GIR_Done, 2538 // Label 231: @3600 2539 GIM_Reject, 2540 // Label 200: @3601 2541 GIM_Reject, 2542 // Label 3: @3602 2543 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 25, /*)*//*default:*//*Label 255*/ 7118, 2544 /*GILLT_s1*//*Label 232*/ 3633, 2545 /*GILLT_s8*//*Label 233*/ 3931, 2546 /*GILLT_s16*//*Label 234*/ 3997, 2547 /*GILLT_s32*//*Label 235*/ 4096, 2548 /*GILLT_s64*//*Label 236*/ 5079, 0, 0, 2549 /*GILLT_v2s1*//*Label 237*/ 5951, 2550 /*GILLT_v2s64*//*Label 238*/ 6044, 2551 /*GILLT_v4s1*//*Label 239*/ 6125, 2552 /*GILLT_v4s32*//*Label 240*/ 6218, 2553 /*GILLT_v4s64*//*Label 241*/ 6299, 2554 /*GILLT_v8s1*//*Label 242*/ 6380, 2555 /*GILLT_v8s16*//*Label 243*/ 6489, 2556 /*GILLT_v8s32*//*Label 244*/ 6570, 2557 /*GILLT_v8s64*//*Label 245*/ 6651, 2558 /*GILLT_v16s1*//*Label 246*/ 6683, 2559 /*GILLT_v16s8*//*Label 247*/ 6715, 2560 /*GILLT_v16s16*//*Label 248*/ 6796, 2561 /*GILLT_v16s32*//*Label 249*/ 6877, 2562 /*GILLT_v32s1*//*Label 250*/ 6909, 2563 /*GILLT_v32s8*//*Label 251*/ 6941, 2564 /*GILLT_v32s16*//*Label 252*/ 7022, 2565 /*GILLT_v64s1*//*Label 253*/ 7054, 2566 /*GILLT_v64s8*//*Label 254*/ 7086, 2567 // Label 232: @3633 2568 GIM_Try, /*On fail goto*//*Label 256*/ 3930, 2569 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s1, 2570 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s1, 2571 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VK1RegClassID, 2572 GIM_Try, /*On fail goto*//*Label 257*/ 3748, // Rule ID 14590 // 2573 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 2574 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, 2575 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s1, 2576 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s1, 2577 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::VK1RegClassID, 2578 GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, 2579 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VK1RegClassID, 2580 GIM_CheckIsSafeToFold, /*InsnID*/1, 2581 // (and:{ *:[v1i1] } (xor:{ *:[v1i1] } VK1:{ *:[v1i1] }:$src1, -1:{ *:[v1i1] }), VK1:{ *:[v1i1] }:$src2) => (COPY_TO_REGCLASS:{ *:[v1i1] } (KANDNWrr:{ *:[v16i1] } (COPY_TO_REGCLASS:{ *:[v16i1] } VK1:{ *:[v1i1] }:$src1, VK16:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v16i1] } VK1:{ *:[v1i1] }:$src2, VK16:{ *:[i32] })), VK1:{ *:[i32] }) 2582 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s1, 2583 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s1, 2584 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s1, 2585 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY, 2586 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, 2587 GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // src2 2588 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, 2589 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY, 2590 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 2591 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // src1 2592 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 2593 GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::KANDNWrr, 2594 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 2595 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 2596 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0, 2597 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 2598 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 2599 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 2600 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 2601 GIR_EraseFromParent, /*InsnID*/0, 2602 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VK1*/8, 2603 // GIR_Coverage, 14590, 2604 GIR_Done, 2605 // Label 257: @3748 2606 GIM_Try, /*On fail goto*//*Label 258*/ 3849, // Rule ID 19443 // 2607 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VK1RegClassID, 2608 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 2609 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, 2610 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s1, 2611 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s1, 2612 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::VK1RegClassID, 2613 GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, 2614 GIM_CheckIsSafeToFold, /*InsnID*/1, 2615 // (and:{ *:[v1i1] } VK1:{ *:[v1i1] }:$src2, (xor:{ *:[v1i1] } VK1:{ *:[v1i1] }:$src1, -1:{ *:[v1i1] })) => (COPY_TO_REGCLASS:{ *:[v1i1] } (KANDNWrr:{ *:[v16i1] } (COPY_TO_REGCLASS:{ *:[v16i1] } VK1:{ *:[v1i1] }:$src1, VK16:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v16i1] } VK1:{ *:[v1i1] }:$src2, VK16:{ *:[i32] })), VK1:{ *:[i32] }) 2616 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s1, 2617 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s1, 2618 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s1, 2619 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY, 2620 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, 2621 GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // src2 2622 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, 2623 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY, 2624 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 2625 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // src1 2626 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 2627 GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::KANDNWrr, 2628 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 2629 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 2630 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0, 2631 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 2632 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 2633 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 2634 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 2635 GIR_EraseFromParent, /*InsnID*/0, 2636 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VK1*/8, 2637 // GIR_Coverage, 19443, 2638 GIR_Done, 2639 // Label 258: @3849 2640 GIM_Try, /*On fail goto*//*Label 259*/ 3929, // Rule ID 14586 // 2641 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VK1RegClassID, 2642 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VK1RegClassID, 2643 // (and:{ *:[v1i1] } VK1:{ *:[v1i1] }:$src1, VK1:{ *:[v1i1] }:$src2) => (COPY_TO_REGCLASS:{ *:[v1i1] } (KANDWrr:{ *:[v16i1] } (COPY_TO_REGCLASS:{ *:[v16i1] } VK1:{ *:[v1i1] }:$src1, VK16:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v16i1] } VK1:{ *:[v1i1] }:$src2, VK16:{ *:[i32] })), VK1:{ *:[i32] }) 2644 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s1, 2645 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s1, 2646 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s1, 2647 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY, 2648 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, 2649 GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // src2 2650 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, 2651 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY, 2652 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 2653 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src1 2654 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 2655 GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::KANDWrr, 2656 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 2657 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 2658 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0, 2659 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 2660 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 2661 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 2662 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 2663 GIR_EraseFromParent, /*InsnID*/0, 2664 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VK1*/8, 2665 // GIR_Coverage, 14586, 2666 GIR_Done, 2667 // Label 259: @3929 2668 GIM_Reject, 2669 // Label 256: @3930 2670 GIM_Reject, 2671 // Label 233: @3931 2672 GIM_Try, /*On fail goto*//*Label 260*/ 3996, 2673 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s8, 2674 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s8, 2675 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR8RegClassID, 2676 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR8RegClassID, 2677 GIM_Try, /*On fail goto*//*Label 261*/ 3979, // Rule ID 17389 // 2678 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 2679 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 2680 // MIs[1] Operand 1 2681 // No operand predicates 2682 GIM_CheckIsSafeToFold, /*InsnID*/1, 2683 // (and:{ *:[i8] } GR8:{ *:[i8] }:$src1, (imm:{ *:[i8] }):$src2) => (AND8ri:{ *:[i8] }:{ *:[i32] } GR8:{ *:[i8] }:$src1, (imm:{ *:[i8] }):$src2) 2684 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::AND8ri, 2685 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 2686 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 2687 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2 2688 GIR_EraseFromParent, /*InsnID*/0, 2689 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2690 // GIR_Coverage, 17389, 2691 GIR_Done, 2692 // Label 261: @3979 2693 GIM_Try, /*On fail goto*//*Label 262*/ 3995, // Rule ID 17381 // 2694 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR8RegClassID, 2695 // (and:{ *:[i8] } GR8:{ *:[i8] }:$src1, GR8:{ *:[i8] }:$src2) => (AND8rr:{ *:[i8] }:{ *:[i32] } GR8:{ *:[i8] }:$src1, GR8:{ *:[i8] }:$src2) 2696 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::AND8rr, 2697 GIR_AddImplicitDef, /*InsnID*/0, X86::EFLAGS, 2698 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2699 // GIR_Coverage, 17381, 2700 GIR_Done, 2701 // Label 262: @3995 2702 GIM_Reject, 2703 // Label 260: @3996 2704 GIM_Reject, 2705 // Label 234: @3997 2706 GIM_Try, /*On fail goto*//*Label 263*/ 4095, 2707 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, 2708 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16, 2709 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR16RegClassID, 2710 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR16RegClassID, 2711 GIM_Try, /*On fail goto*//*Label 264*/ 4048, // Rule ID 17392 // 2712 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 2713 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 2714 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_i16immSExt8, 2715 // MIs[1] Operand 1 2716 // No operand predicates 2717 GIM_CheckIsSafeToFold, /*InsnID*/1, 2718 // (and:{ *:[i16] } GR16:{ *:[i16] }:$src1, (imm:{ *:[i16] })<<P:Predicate_i16immSExt8>>:$src2) => (AND16ri8:{ *:[i16] }:{ *:[i32] } GR16:{ *:[i16] }:$src1, (imm:{ *:[i16] })<<P:Predicate_i16immSExt8>>:$src2) 2719 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::AND16ri8, 2720 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 2721 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 2722 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2 2723 GIR_EraseFromParent, /*InsnID*/0, 2724 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2725 // GIR_Coverage, 17392, 2726 GIR_Done, 2727 // Label 264: @4048 2728 GIM_Try, /*On fail goto*//*Label 265*/ 4078, // Rule ID 17390 // 2729 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 2730 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 2731 // MIs[1] Operand 1 2732 // No operand predicates 2733 GIM_CheckIsSafeToFold, /*InsnID*/1, 2734 // (and:{ *:[i16] } GR16:{ *:[i16] }:$src1, (imm:{ *:[i16] }):$src2) => (AND16ri:{ *:[i16] }:{ *:[i32] } GR16:{ *:[i16] }:$src1, (imm:{ *:[i16] }):$src2) 2735 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::AND16ri, 2736 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 2737 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 2738 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2 2739 GIR_EraseFromParent, /*InsnID*/0, 2740 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2741 // GIR_Coverage, 17390, 2742 GIR_Done, 2743 // Label 265: @4078 2744 GIM_Try, /*On fail goto*//*Label 266*/ 4094, // Rule ID 17382 // 2745 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR16RegClassID, 2746 // (and:{ *:[i16] } GR16:{ *:[i16] }:$src1, GR16:{ *:[i16] }:$src2) => (AND16rr:{ *:[i16] }:{ *:[i32] } GR16:{ *:[i16] }:$src1, GR16:{ *:[i16] }:$src2) 2747 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::AND16rr, 2748 GIR_AddImplicitDef, /*InsnID*/0, X86::EFLAGS, 2749 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2750 // GIR_Coverage, 17382, 2751 GIR_Done, 2752 // Label 266: @4094 2753 GIM_Reject, 2754 // Label 263: @4095 2755 GIM_Reject, 2756 // Label 235: @4096 2757 GIM_Try, /*On fail goto*//*Label 267*/ 5078, 2758 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 2759 GIM_Try, /*On fail goto*//*Label 268*/ 4177, // Rule ID 19188 // 2760 GIM_CheckFeatures, GIFBS_HasTBM, 2761 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 2762 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 2763 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 2764 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD, 2765 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, 2766 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, 2767 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::GR32RegClassID, 2768 GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 1, 2769 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] 2770 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_XOR, 2771 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, 2772 // MIs[2] src 2773 GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, 2774 GIM_CheckConstantInt, /*MI*/2, /*Op*/2, -1, 2775 GIM_CheckIsSafeToFold, /*InsnID*/1, 2776 GIM_CheckIsSafeToFold, /*InsnID*/2, 2777 // (and:{ *:[i32] } (add:{ *:[i32] } GR32:{ *:[i32] }:$src, 1:{ *:[i32] }), (xor:{ *:[i32] } GR32:{ *:[i32] }:$src, -1:{ *:[i32] })) => (BLCIC32rr:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src) 2778 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLCIC32rr, 2779 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 2780 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src 2781 GIR_EraseFromParent, /*InsnID*/0, 2782 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2783 // GIR_Coverage, 19188, 2784 GIR_Done, 2785 // Label 268: @4177 2786 GIM_Try, /*On fail goto*//*Label 269*/ 4252, // Rule ID 19200 // 2787 GIM_CheckFeatures, GIFBS_HasTBM, 2788 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 2789 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 2790 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 2791 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD, 2792 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, 2793 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, 2794 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::GR32RegClassID, 2795 GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, 2796 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] 2797 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_XOR, 2798 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, 2799 // MIs[2] src 2800 GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, 2801 GIM_CheckConstantInt, /*MI*/2, /*Op*/2, -1, 2802 GIM_CheckIsSafeToFold, /*InsnID*/1, 2803 GIM_CheckIsSafeToFold, /*InsnID*/2, 2804 // (and:{ *:[i32] } (add:{ *:[i32] } GR32:{ *:[i32] }:$src, -1:{ *:[i32] }), (xor:{ *:[i32] } GR32:{ *:[i32] }:$src, -1:{ *:[i32] })) => (TZMSK32rr:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src) 2805 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::TZMSK32rr, 2806 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 2807 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src 2808 GIR_EraseFromParent, /*InsnID*/0, 2809 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2810 // GIR_Coverage, 19200, 2811 GIR_Done, 2812 // Label 269: @4252 2813 GIM_Try, /*On fail goto*//*Label 270*/ 4327, // Rule ID 13009 // 2814 GIM_CheckFeatures, GIFBS_HasTBM, 2815 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 2816 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 2817 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 2818 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, 2819 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, 2820 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, 2821 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::GR32RegClassID, 2822 GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, 2823 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] 2824 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ADD, 2825 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, 2826 // MIs[2] src 2827 GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, 2828 GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 1, 2829 GIM_CheckIsSafeToFold, /*InsnID*/1, 2830 GIM_CheckIsSafeToFold, /*InsnID*/2, 2831 // (and:{ *:[i32] } (xor:{ *:[i32] } GR32:{ *:[i32] }:$src, -1:{ *:[i32] }), (add:{ *:[i32] } GR32:{ *:[i32] }:$src, 1:{ *:[i32] })) => (BLCIC32rr:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src) 2832 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLCIC32rr, 2833 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 2834 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src 2835 GIR_EraseFromParent, /*InsnID*/0, 2836 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2837 // GIR_Coverage, 13009, 2838 GIR_Done, 2839 // Label 270: @4327 2840 GIM_Try, /*On fail goto*//*Label 271*/ 4402, // Rule ID 13021 // 2841 GIM_CheckFeatures, GIFBS_HasTBM, 2842 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 2843 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 2844 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 2845 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, 2846 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, 2847 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, 2848 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::GR32RegClassID, 2849 GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, 2850 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] 2851 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ADD, 2852 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, 2853 // MIs[2] src 2854 GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, 2855 GIM_CheckConstantInt, /*MI*/2, /*Op*/2, -1, 2856 GIM_CheckIsSafeToFold, /*InsnID*/1, 2857 GIM_CheckIsSafeToFold, /*InsnID*/2, 2858 // (and:{ *:[i32] } (xor:{ *:[i32] } GR32:{ *:[i32] }:$src, -1:{ *:[i32] }), (add:{ *:[i32] } GR32:{ *:[i32] }:$src, -1:{ *:[i32] })) => (TZMSK32rr:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src) 2859 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::TZMSK32rr, 2860 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 2861 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src 2862 GIR_EraseFromParent, /*InsnID*/0, 2863 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2864 // GIR_Coverage, 13021, 2865 GIR_Done, 2866 // Label 271: @4402 2867 GIM_Try, /*On fail goto*//*Label 272*/ 4456, // Rule ID 19170 // 2868 GIM_CheckFeatures, GIFBS_HasBMI, 2869 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 2870 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 2871 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD, 2872 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, 2873 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, 2874 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::GR32RegClassID, 2875 GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, 2876 // MIs[0] src 2877 GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, 2878 GIM_CheckIsSafeToFold, /*InsnID*/1, 2879 // (and:{ *:[i32] } (add:{ *:[i32] } GR32:{ *:[i32] }:$src, -1:{ *:[i32] }), GR32:{ *:[i32] }:$src) => (BLSR32rr:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src) 2880 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLSR32rr, 2881 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 2882 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src 2883 GIR_EraseFromParent, /*InsnID*/0, 2884 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2885 // GIR_Coverage, 19170, 2886 GIR_Done, 2887 // Label 272: @4456 2888 GIM_Try, /*On fail goto*//*Label 273*/ 4510, // Rule ID 19182 // 2889 GIM_CheckFeatures, GIFBS_HasTBM, 2890 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 2891 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 2892 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD, 2893 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, 2894 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, 2895 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::GR32RegClassID, 2896 GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 1, 2897 // MIs[0] src 2898 GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, 2899 GIM_CheckIsSafeToFold, /*InsnID*/1, 2900 // (and:{ *:[i32] } (add:{ *:[i32] } GR32:{ *:[i32] }:$src, 1:{ *:[i32] }), GR32:{ *:[i32] }:$src) => (BLCFILL32rr:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src) 2901 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLCFILL32rr, 2902 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 2903 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src 2904 GIR_EraseFromParent, /*InsnID*/0, 2905 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2906 // GIR_Coverage, 19182, 2907 GIR_Done, 2908 // Label 273: @4510 2909 GIM_Try, /*On fail goto*//*Label 274*/ 4564, // Rule ID 19174 // 2910 GIM_CheckFeatures, GIFBS_HasBMI, 2911 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 2912 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 2913 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SUB, 2914 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, 2915 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, 2916 GIM_CheckConstantInt, /*MI*/1, /*Op*/1, 0, 2917 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/X86::GR32RegClassID, 2918 // MIs[0] src 2919 GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, 2920 GIM_CheckIsSafeToFold, /*InsnID*/1, 2921 // (and:{ *:[i32] } (sub:{ *:[i32] } 0:{ *:[i32] }, GR32:{ *:[i32] }:$src), GR32:{ *:[i32] }:$src) => (BLSI32rr:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src) 2922 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLSI32rr, 2923 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 2924 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src 2925 GIR_EraseFromParent, /*InsnID*/0, 2926 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2927 // GIR_Coverage, 19174, 2928 GIR_Done, 2929 // Label 274: @4564 2930 GIM_Try, /*On fail goto*//*Label 275*/ 4618, // Rule ID 12985 // 2931 GIM_CheckFeatures, GIFBS_HasBMI, 2932 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 2933 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 2934 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR32RegClassID, 2935 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 2936 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD, 2937 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, 2938 // MIs[1] src 2939 GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/1, /*OtherMI*/0, /*OtherOpIdx*/1, 2940 GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, 2941 GIM_CheckIsSafeToFold, /*InsnID*/1, 2942 // (and:{ *:[i32] } GR32:{ *:[i32] }:$src, (add:{ *:[i32] } GR32:{ *:[i32] }:$src, -1:{ *:[i32] })) => (BLSR32rr:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src) 2943 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLSR32rr, 2944 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 2945 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 2946 GIR_EraseFromParent, /*InsnID*/0, 2947 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2948 // GIR_Coverage, 12985, 2949 GIR_Done, 2950 // Label 275: @4618 2951 GIM_Try, /*On fail goto*//*Label 276*/ 4672, // Rule ID 13003 // 2952 GIM_CheckFeatures, GIFBS_HasTBM, 2953 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 2954 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 2955 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR32RegClassID, 2956 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 2957 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD, 2958 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, 2959 // MIs[1] src 2960 GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/1, /*OtherMI*/0, /*OtherOpIdx*/1, 2961 GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 1, 2962 GIM_CheckIsSafeToFold, /*InsnID*/1, 2963 // (and:{ *:[i32] } GR32:{ *:[i32] }:$src, (add:{ *:[i32] } GR32:{ *:[i32] }:$src, 1:{ *:[i32] })) => (BLCFILL32rr:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src) 2964 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLCFILL32rr, 2965 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 2966 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 2967 GIR_EraseFromParent, /*InsnID*/0, 2968 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2969 // GIR_Coverage, 13003, 2970 GIR_Done, 2971 // Label 276: @4672 2972 GIM_Try, /*On fail goto*//*Label 277*/ 4726, // Rule ID 12989 // 2973 GIM_CheckFeatures, GIFBS_HasBMI, 2974 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 2975 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 2976 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR32RegClassID, 2977 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 2978 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SUB, 2979 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, 2980 GIM_CheckConstantInt, /*MI*/1, /*Op*/1, 0, 2981 // MIs[1] src 2982 GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/2, /*OtherMI*/0, /*OtherOpIdx*/1, 2983 GIM_CheckIsSafeToFold, /*InsnID*/1, 2984 // (and:{ *:[i32] } GR32:{ *:[i32] }:$src, (sub:{ *:[i32] } 0:{ *:[i32] }, GR32:{ *:[i32] }:$src)) => (BLSI32rr:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src) 2985 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLSI32rr, 2986 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 2987 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 2988 GIR_EraseFromParent, /*InsnID*/0, 2989 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2990 // GIR_Coverage, 12989, 2991 GIR_Done, 2992 // Label 277: @4726 2993 GIM_Try, /*On fail goto*//*Label 278*/ 4783, // Rule ID 17158 // 2994 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 2995 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 2996 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR32RegClassID, 2997 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 65535, 2998 // (and:{ *:[i32] } GR32:{ *:[i32] }:$src1, 65535:{ *:[i32] }) => (MOVZX32rr16:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i16] } GR32:{ *:[i32] }:$src1, sub_16bit:{ *:[i32] })) 2999 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, 3000 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, 3001 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 3002 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/4, // src1 3003 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, /*RC GR16*/6, 3004 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, /*RC GR32*/33, 3005 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::MOVZX32rr16, 3006 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 3007 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 3008 GIR_EraseFromParent, /*InsnID*/0, 3009 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3010 // GIR_Coverage, 17158, 3011 GIR_Done, 3012 // Label 278: @4783 3013 GIM_Try, /*On fail goto*//*Label 279*/ 4840, // Rule ID 17159 // 3014 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 3015 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 3016 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR32RegClassID, 3017 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 255, 3018 // (and:{ *:[i32] } GR32:{ *:[i32] }:$src1, 255:{ *:[i32] }) => (MOVZX32rr8:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i8] } GR32:{ *:[i32] }:$src1, sub_8bit:{ *:[i32] })) 3019 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s8, 3020 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, 3021 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 3022 GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/1, // src1 3023 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, /*RC GR8*/0, 3024 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, /*RC GR32*/33, 3025 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::MOVZX32rr8, 3026 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 3027 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 3028 GIR_EraseFromParent, /*InsnID*/0, 3029 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3030 // GIR_Coverage, 17159, 3031 GIR_Done, 3032 // Label 279: @4840 3033 GIM_Try, /*On fail goto*//*Label 280*/ 4885, // Rule ID 17393 // 3034 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 3035 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 3036 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR32RegClassID, 3037 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 3038 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 3039 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_i32immSExt8, 3040 // MIs[1] Operand 1 3041 // No operand predicates 3042 GIM_CheckIsSafeToFold, /*InsnID*/1, 3043 // (and:{ *:[i32] } GR32:{ *:[i32] }:$src1, (imm:{ *:[i32] })<<P:Predicate_i32immSExt8>>:$src2) => (AND32ri8:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src1, (imm:{ *:[i32] })<<P:Predicate_i32immSExt8>>:$src2) 3044 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::AND32ri8, 3045 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 3046 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 3047 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2 3048 GIR_EraseFromParent, /*InsnID*/0, 3049 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3050 // GIR_Coverage, 17393, 3051 GIR_Done, 3052 // Label 280: @4885 3053 GIM_Try, /*On fail goto*//*Label 281*/ 4927, // Rule ID 17391 // 3054 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 3055 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 3056 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR32RegClassID, 3057 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 3058 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 3059 // MIs[1] Operand 1 3060 // No operand predicates 3061 GIM_CheckIsSafeToFold, /*InsnID*/1, 3062 // (and:{ *:[i32] } GR32:{ *:[i32] }:$src1, (imm:{ *:[i32] }):$src2) => (AND32ri:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src1, (imm:{ *:[i32] }):$src2) 3063 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::AND32ri, 3064 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 3065 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 3066 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2 3067 GIR_EraseFromParent, /*InsnID*/0, 3068 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3069 // GIR_Coverage, 17391, 3070 GIR_Done, 3071 // Label 281: @4927 3072 GIM_Try, /*On fail goto*//*Label 282*/ 4988, // Rule ID 13049 // 3073 GIM_CheckFeatures, GIFBS_HasBMI, 3074 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 3075 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 3076 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 3077 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, 3078 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, 3079 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, 3080 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::GR32RegClassID, 3081 GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, 3082 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR32RegClassID, 3083 GIM_CheckIsSafeToFold, /*InsnID*/1, 3084 // (and:{ *:[i32] } (xor:{ *:[i32] } GR32:{ *:[i32] }:$src1, -1:{ *:[i32] }), GR32:{ *:[i32] }:$src2) => (ANDN32rr:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src1, GR32:{ *:[i32] }:$src2) 3085 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::ANDN32rr, 3086 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 3087 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1 3088 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src2 3089 GIR_EraseFromParent, /*InsnID*/0, 3090 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3091 // GIR_Coverage, 13049, 3092 GIR_Done, 3093 // Label 282: @4988 3094 GIM_Try, /*On fail goto*//*Label 283*/ 5049, // Rule ID 19220 // 3095 GIM_CheckFeatures, GIFBS_HasBMI, 3096 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 3097 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 3098 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR32RegClassID, 3099 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 3100 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, 3101 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, 3102 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, 3103 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::GR32RegClassID, 3104 GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, 3105 GIM_CheckIsSafeToFold, /*InsnID*/1, 3106 // (and:{ *:[i32] } GR32:{ *:[i32] }:$src2, (xor:{ *:[i32] } GR32:{ *:[i32] }:$src1, -1:{ *:[i32] })) => (ANDN32rr:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src1, GR32:{ *:[i32] }:$src2) 3107 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::ANDN32rr, 3108 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 3109 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1 3110 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src2 3111 GIR_EraseFromParent, /*InsnID*/0, 3112 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3113 // GIR_Coverage, 19220, 3114 GIR_Done, 3115 // Label 283: @5049 3116 GIM_Try, /*On fail goto*//*Label 284*/ 5077, // Rule ID 17383 // 3117 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 3118 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 3119 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR32RegClassID, 3120 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR32RegClassID, 3121 // (and:{ *:[i32] } GR32:{ *:[i32] }:$src1, GR32:{ *:[i32] }:$src2) => (AND32rr:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src1, GR32:{ *:[i32] }:$src2) 3122 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::AND32rr, 3123 GIR_AddImplicitDef, /*InsnID*/0, X86::EFLAGS, 3124 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3125 // GIR_Coverage, 17383, 3126 GIR_Done, 3127 // Label 284: @5077 3128 GIM_Reject, 3129 // Label 267: @5078 3130 GIM_Reject, 3131 // Label 236: @5079 3132 GIM_Try, /*On fail goto*//*Label 285*/ 5950, 3133 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 3134 GIM_Try, /*On fail goto*//*Label 286*/ 5160, // Rule ID 19189 // 3135 GIM_CheckFeatures, GIFBS_HasTBM, 3136 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 3137 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID, 3138 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 3139 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD, 3140 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, 3141 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, 3142 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::GR64RegClassID, 3143 GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 1, 3144 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] 3145 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_XOR, 3146 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, 3147 // MIs[2] src 3148 GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, 3149 GIM_CheckConstantInt, /*MI*/2, /*Op*/2, -1, 3150 GIM_CheckIsSafeToFold, /*InsnID*/1, 3151 GIM_CheckIsSafeToFold, /*InsnID*/2, 3152 // (and:{ *:[i64] } (add:{ *:[i64] } GR64:{ *:[i64] }:$src, 1:{ *:[i64] }), (xor:{ *:[i64] } GR64:{ *:[i64] }:$src, -1:{ *:[i64] })) => (BLCIC64rr:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src) 3153 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLCIC64rr, 3154 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 3155 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src 3156 GIR_EraseFromParent, /*InsnID*/0, 3157 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3158 // GIR_Coverage, 19189, 3159 GIR_Done, 3160 // Label 286: @5160 3161 GIM_Try, /*On fail goto*//*Label 287*/ 5235, // Rule ID 19201 // 3162 GIM_CheckFeatures, GIFBS_HasTBM, 3163 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 3164 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID, 3165 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 3166 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD, 3167 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, 3168 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, 3169 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::GR64RegClassID, 3170 GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, 3171 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] 3172 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_XOR, 3173 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, 3174 // MIs[2] src 3175 GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, 3176 GIM_CheckConstantInt, /*MI*/2, /*Op*/2, -1, 3177 GIM_CheckIsSafeToFold, /*InsnID*/1, 3178 GIM_CheckIsSafeToFold, /*InsnID*/2, 3179 // (and:{ *:[i64] } (add:{ *:[i64] } GR64:{ *:[i64] }:$src, -1:{ *:[i64] }), (xor:{ *:[i64] } GR64:{ *:[i64] }:$src, -1:{ *:[i64] })) => (TZMSK64rr:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src) 3180 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::TZMSK64rr, 3181 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 3182 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src 3183 GIR_EraseFromParent, /*InsnID*/0, 3184 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3185 // GIR_Coverage, 19201, 3186 GIR_Done, 3187 // Label 287: @5235 3188 GIM_Try, /*On fail goto*//*Label 288*/ 5310, // Rule ID 13010 // 3189 GIM_CheckFeatures, GIFBS_HasTBM, 3190 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 3191 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID, 3192 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 3193 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, 3194 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, 3195 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, 3196 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::GR64RegClassID, 3197 GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, 3198 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] 3199 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ADD, 3200 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, 3201 // MIs[2] src 3202 GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, 3203 GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 1, 3204 GIM_CheckIsSafeToFold, /*InsnID*/1, 3205 GIM_CheckIsSafeToFold, /*InsnID*/2, 3206 // (and:{ *:[i64] } (xor:{ *:[i64] } GR64:{ *:[i64] }:$src, -1:{ *:[i64] }), (add:{ *:[i64] } GR64:{ *:[i64] }:$src, 1:{ *:[i64] })) => (BLCIC64rr:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src) 3207 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLCIC64rr, 3208 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 3209 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src 3210 GIR_EraseFromParent, /*InsnID*/0, 3211 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3212 // GIR_Coverage, 13010, 3213 GIR_Done, 3214 // Label 288: @5310 3215 GIM_Try, /*On fail goto*//*Label 289*/ 5385, // Rule ID 13022 // 3216 GIM_CheckFeatures, GIFBS_HasTBM, 3217 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 3218 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID, 3219 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 3220 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, 3221 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, 3222 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, 3223 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::GR64RegClassID, 3224 GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, 3225 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] 3226 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ADD, 3227 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, 3228 // MIs[2] src 3229 GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, 3230 GIM_CheckConstantInt, /*MI*/2, /*Op*/2, -1, 3231 GIM_CheckIsSafeToFold, /*InsnID*/1, 3232 GIM_CheckIsSafeToFold, /*InsnID*/2, 3233 // (and:{ *:[i64] } (xor:{ *:[i64] } GR64:{ *:[i64] }:$src, -1:{ *:[i64] }), (add:{ *:[i64] } GR64:{ *:[i64] }:$src, -1:{ *:[i64] })) => (TZMSK64rr:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src) 3234 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::TZMSK64rr, 3235 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 3236 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src 3237 GIR_EraseFromParent, /*InsnID*/0, 3238 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3239 // GIR_Coverage, 13022, 3240 GIR_Done, 3241 // Label 289: @5385 3242 GIM_Try, /*On fail goto*//*Label 290*/ 5439, // Rule ID 19171 // 3243 GIM_CheckFeatures, GIFBS_HasBMI, 3244 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID, 3245 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 3246 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD, 3247 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, 3248 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, 3249 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::GR64RegClassID, 3250 GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, 3251 // MIs[0] src 3252 GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, 3253 GIM_CheckIsSafeToFold, /*InsnID*/1, 3254 // (and:{ *:[i64] } (add:{ *:[i64] } GR64:{ *:[i64] }:$src, -1:{ *:[i64] }), GR64:{ *:[i64] }:$src) => (BLSR64rr:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src) 3255 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLSR64rr, 3256 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 3257 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src 3258 GIR_EraseFromParent, /*InsnID*/0, 3259 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3260 // GIR_Coverage, 19171, 3261 GIR_Done, 3262 // Label 290: @5439 3263 GIM_Try, /*On fail goto*//*Label 291*/ 5493, // Rule ID 19183 // 3264 GIM_CheckFeatures, GIFBS_HasTBM, 3265 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID, 3266 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 3267 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD, 3268 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, 3269 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, 3270 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::GR64RegClassID, 3271 GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 1, 3272 // MIs[0] src 3273 GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, 3274 GIM_CheckIsSafeToFold, /*InsnID*/1, 3275 // (and:{ *:[i64] } (add:{ *:[i64] } GR64:{ *:[i64] }:$src, 1:{ *:[i64] }), GR64:{ *:[i64] }:$src) => (BLCFILL64rr:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src) 3276 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLCFILL64rr, 3277 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 3278 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src 3279 GIR_EraseFromParent, /*InsnID*/0, 3280 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3281 // GIR_Coverage, 19183, 3282 GIR_Done, 3283 // Label 291: @5493 3284 GIM_Try, /*On fail goto*//*Label 292*/ 5547, // Rule ID 19175 // 3285 GIM_CheckFeatures, GIFBS_HasBMI, 3286 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID, 3287 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 3288 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SUB, 3289 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, 3290 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, 3291 GIM_CheckConstantInt, /*MI*/1, /*Op*/1, 0, 3292 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/X86::GR64RegClassID, 3293 // MIs[0] src 3294 GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, 3295 GIM_CheckIsSafeToFold, /*InsnID*/1, 3296 // (and:{ *:[i64] } (sub:{ *:[i64] } 0:{ *:[i64] }, GR64:{ *:[i64] }:$src), GR64:{ *:[i64] }:$src) => (BLSI64rr:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src) 3297 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLSI64rr, 3298 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 3299 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src 3300 GIR_EraseFromParent, /*InsnID*/0, 3301 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3302 // GIR_Coverage, 19175, 3303 GIR_Done, 3304 // Label 292: @5547 3305 GIM_Try, /*On fail goto*//*Label 293*/ 5601, // Rule ID 12986 // 3306 GIM_CheckFeatures, GIFBS_HasBMI, 3307 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 3308 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID, 3309 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR64RegClassID, 3310 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 3311 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD, 3312 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, 3313 // MIs[1] src 3314 GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/1, /*OtherMI*/0, /*OtherOpIdx*/1, 3315 GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, 3316 GIM_CheckIsSafeToFold, /*InsnID*/1, 3317 // (and:{ *:[i64] } GR64:{ *:[i64] }:$src, (add:{ *:[i64] } GR64:{ *:[i64] }:$src, -1:{ *:[i64] })) => (BLSR64rr:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src) 3318 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLSR64rr, 3319 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 3320 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 3321 GIR_EraseFromParent, /*InsnID*/0, 3322 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3323 // GIR_Coverage, 12986, 3324 GIR_Done, 3325 // Label 293: @5601 3326 GIM_Try, /*On fail goto*//*Label 294*/ 5655, // Rule ID 13004 // 3327 GIM_CheckFeatures, GIFBS_HasTBM, 3328 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 3329 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID, 3330 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR64RegClassID, 3331 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 3332 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD, 3333 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, 3334 // MIs[1] src 3335 GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/1, /*OtherMI*/0, /*OtherOpIdx*/1, 3336 GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 1, 3337 GIM_CheckIsSafeToFold, /*InsnID*/1, 3338 // (and:{ *:[i64] } GR64:{ *:[i64] }:$src, (add:{ *:[i64] } GR64:{ *:[i64] }:$src, 1:{ *:[i64] })) => (BLCFILL64rr:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src) 3339 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLCFILL64rr, 3340 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 3341 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 3342 GIR_EraseFromParent, /*InsnID*/0, 3343 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3344 // GIR_Coverage, 13004, 3345 GIR_Done, 3346 // Label 294: @5655 3347 GIM_Try, /*On fail goto*//*Label 295*/ 5709, // Rule ID 12990 // 3348 GIM_CheckFeatures, GIFBS_HasBMI, 3349 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 3350 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID, 3351 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR64RegClassID, 3352 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 3353 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SUB, 3354 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, 3355 GIM_CheckConstantInt, /*MI*/1, /*Op*/1, 0, 3356 // MIs[1] src 3357 GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/2, /*OtherMI*/0, /*OtherOpIdx*/1, 3358 GIM_CheckIsSafeToFold, /*InsnID*/1, 3359 // (and:{ *:[i64] } GR64:{ *:[i64] }:$src, (sub:{ *:[i64] } 0:{ *:[i64] }, GR64:{ *:[i64] }:$src)) => (BLSI64rr:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src) 3360 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLSI64rr, 3361 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 3362 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 3363 GIR_EraseFromParent, /*InsnID*/0, 3364 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3365 // GIR_Coverage, 12990, 3366 GIR_Done, 3367 // Label 295: @5709 3368 GIM_Try, /*On fail goto*//*Label 296*/ 5754, // Rule ID 17394 // 3369 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 3370 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID, 3371 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR64RegClassID, 3372 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 3373 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 3374 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_i64immSExt8, 3375 // MIs[1] Operand 1 3376 // No operand predicates 3377 GIM_CheckIsSafeToFold, /*InsnID*/1, 3378 // (and:{ *:[i64] } GR64:{ *:[i64] }:$src1, (imm:{ *:[i64] })<<P:Predicate_i64immSExt8>>:$src2) => (AND64ri8:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src1, (imm:{ *:[i64] })<<P:Predicate_i64immSExt8>>:$src2) 3379 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::AND64ri8, 3380 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 3381 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 3382 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2 3383 GIR_EraseFromParent, /*InsnID*/0, 3384 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3385 // GIR_Coverage, 17394, 3386 GIR_Done, 3387 // Label 296: @5754 3388 GIM_Try, /*On fail goto*//*Label 297*/ 5799, // Rule ID 17395 // 3389 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 3390 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID, 3391 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR64RegClassID, 3392 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 3393 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 3394 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_i64immSExt32, 3395 // MIs[1] Operand 1 3396 // No operand predicates 3397 GIM_CheckIsSafeToFold, /*InsnID*/1, 3398 // (and:{ *:[i64] } GR64:{ *:[i64] }:$src1, (imm:{ *:[i64] })<<P:Predicate_i64immSExt32>>:$src2) => (AND64ri32:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src1, (imm:{ *:[i64] })<<P:Predicate_i64immSExt32>>:$src2) 3399 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::AND64ri32, 3400 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 3401 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 3402 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2 3403 GIR_EraseFromParent, /*InsnID*/0, 3404 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3405 // GIR_Coverage, 17395, 3406 GIR_Done, 3407 // Label 297: @5799 3408 GIM_Try, /*On fail goto*//*Label 298*/ 5860, // Rule ID 13050 // 3409 GIM_CheckFeatures, GIFBS_HasBMI, 3410 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 3411 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID, 3412 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 3413 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, 3414 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, 3415 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, 3416 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::GR64RegClassID, 3417 GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, 3418 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR64RegClassID, 3419 GIM_CheckIsSafeToFold, /*InsnID*/1, 3420 // (and:{ *:[i64] } (xor:{ *:[i64] } GR64:{ *:[i64] }:$src1, -1:{ *:[i64] }), GR64:{ *:[i64] }:$src2) => (ANDN64rr:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src1, GR64:{ *:[i64] }:$src2) 3421 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::ANDN64rr, 3422 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 3423 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1 3424 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src2 3425 GIR_EraseFromParent, /*InsnID*/0, 3426 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3427 // GIR_Coverage, 13050, 3428 GIR_Done, 3429 // Label 298: @5860 3430 GIM_Try, /*On fail goto*//*Label 299*/ 5921, // Rule ID 19221 // 3431 GIM_CheckFeatures, GIFBS_HasBMI, 3432 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 3433 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID, 3434 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR64RegClassID, 3435 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 3436 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, 3437 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, 3438 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, 3439 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::GR64RegClassID, 3440 GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, 3441 GIM_CheckIsSafeToFold, /*InsnID*/1, 3442 // (and:{ *:[i64] } GR64:{ *:[i64] }:$src2, (xor:{ *:[i64] } GR64:{ *:[i64] }:$src1, -1:{ *:[i64] })) => (ANDN64rr:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src1, GR64:{ *:[i64] }:$src2) 3443 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::ANDN64rr, 3444 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 3445 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1 3446 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src2 3447 GIR_EraseFromParent, /*InsnID*/0, 3448 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3449 // GIR_Coverage, 19221, 3450 GIR_Done, 3451 // Label 299: @5921 3452 GIM_Try, /*On fail goto*//*Label 300*/ 5949, // Rule ID 17384 // 3453 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 3454 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID, 3455 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR64RegClassID, 3456 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR64RegClassID, 3457 // (and:{ *:[i64] } GR64:{ *:[i64] }:$src1, GR64:{ *:[i64] }:$src2) => (AND64rr:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src1, GR64:{ *:[i64] }:$src2) 3458 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::AND64rr, 3459 GIR_AddImplicitDef, /*InsnID*/0, X86::EFLAGS, 3460 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3461 // GIR_Coverage, 17384, 3462 GIR_Done, 3463 // Label 300: @5949 3464 GIM_Reject, 3465 // Label 285: @5950 3466 GIM_Reject, 3467 // Label 237: @5951 3468 GIM_Try, /*On fail goto*//*Label 301*/ 6043, // Rule ID 14587 // 3469 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s1, 3470 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s1, 3471 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VK1RegClassID, 3472 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VK2RegClassID, 3473 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VK2RegClassID, 3474 // (and:{ *:[v2i1] } VK2:{ *:[v2i1] }:$src1, VK2:{ *:[v2i1] }:$src2) => (COPY_TO_REGCLASS:{ *:[v2i1] } (KANDWrr:{ *:[v16i1] } (COPY_TO_REGCLASS:{ *:[v16i1] } VK2:{ *:[v2i1] }:$src1, VK16:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v16i1] } VK2:{ *:[v2i1] }:$src2, VK16:{ *:[i32] })), VK1:{ *:[i32] }) 3475 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s1, 3476 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s1, 3477 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s1, 3478 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY, 3479 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, 3480 GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // src2 3481 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, 3482 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY, 3483 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 3484 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src1 3485 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 3486 GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::KANDWrr, 3487 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 3488 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 3489 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0, 3490 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 3491 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 3492 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 3493 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 3494 GIR_EraseFromParent, /*InsnID*/0, 3495 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VK1*/8, 3496 // GIR_Coverage, 14587, 3497 GIR_Done, 3498 // Label 301: @6043 3499 GIM_Reject, 3500 // Label 238: @6044 3501 GIM_Try, /*On fail goto*//*Label 302*/ 6124, 3502 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, 3503 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 3504 GIM_Try, /*On fail goto*//*Label 303*/ 6077, // Rule ID 1625 // 3505 GIM_CheckFeatures, GIFBS_HasAVX_NoVLX, 3506 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 3507 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 3508 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 3509 // (and:{ *:[v2i64] } VR128:{ *:[v2i64] }:$src1, VR128:{ *:[v2i64] }:$src2) => (VPANDrr:{ *:[v2i64] } VR128:{ *:[v2i64] }:$src1, VR128:{ *:[v2i64] }:$src2) 3510 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPANDrr, 3511 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3512 // GIR_Coverage, 1625, 3513 GIR_Done, 3514 // Label 303: @6077 3515 GIM_Try, /*On fail goto*//*Label 304*/ 6100, // Rule ID 1627 // 3516 GIM_CheckFeatures, GIFBS_UseSSE2, 3517 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 3518 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 3519 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 3520 // (and:{ *:[v2i64] } VR128:{ *:[v2i64] }:$src1, VR128:{ *:[v2i64] }:$src2) => (PANDrr:{ *:[v2i64] } VR128:{ *:[v2i64] }:$src1, VR128:{ *:[v2i64] }:$src2) 3521 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::PANDrr, 3522 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3523 // GIR_Coverage, 1627, 3524 GIR_Done, 3525 // Label 304: @6100 3526 GIM_Try, /*On fail goto*//*Label 305*/ 6123, // Rule ID 4966 // 3527 GIM_CheckFeatures, GIFBS_HasAVX512_HasVLX, 3528 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 3529 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 3530 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128XRegClassID, 3531 // (and:{ *:[v2i64] } VR128X:{ *:[v2i64] }:$src1, VR128X:{ *:[v2i64] }:$src2) => (VPANDQZ128rr:{ *:[v2i64] } VR128X:{ *:[v2i64] }:$src1, VR128X:{ *:[v2i64] }:$src2) 3532 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPANDQZ128rr, 3533 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3534 // GIR_Coverage, 4966, 3535 GIR_Done, 3536 // Label 305: @6123 3537 GIM_Reject, 3538 // Label 302: @6124 3539 GIM_Reject, 3540 // Label 239: @6125 3541 GIM_Try, /*On fail goto*//*Label 306*/ 6217, // Rule ID 14588 // 3542 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s1, 3543 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s1, 3544 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VK1RegClassID, 3545 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VK4RegClassID, 3546 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VK4RegClassID, 3547 // (and:{ *:[v4i1] } VK4:{ *:[v4i1] }:$src1, VK4:{ *:[v4i1] }:$src2) => (COPY_TO_REGCLASS:{ *:[v4i1] } (KANDWrr:{ *:[v16i1] } (COPY_TO_REGCLASS:{ *:[v16i1] } VK4:{ *:[v4i1] }:$src1, VK16:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v16i1] } VK4:{ *:[v4i1] }:$src2, VK16:{ *:[i32] })), VK1:{ *:[i32] }) 3548 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s1, 3549 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s1, 3550 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s1, 3551 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY, 3552 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, 3553 GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // src2 3554 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, 3555 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY, 3556 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 3557 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src1 3558 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 3559 GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::KANDWrr, 3560 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 3561 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 3562 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0, 3563 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 3564 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 3565 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 3566 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 3567 GIR_EraseFromParent, /*InsnID*/0, 3568 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VK1*/8, 3569 // GIR_Coverage, 14588, 3570 GIR_Done, 3571 // Label 306: @6217 3572 GIM_Reject, 3573 // Label 240: @6218 3574 GIM_Try, /*On fail goto*//*Label 307*/ 6298, 3575 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 3576 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 3577 GIM_Try, /*On fail goto*//*Label 308*/ 6251, // Rule ID 4993 // 3578 GIM_CheckFeatures, GIFBS_HasAVX512_HasVLX, 3579 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 3580 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 3581 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128XRegClassID, 3582 // (and:{ *:[v4i32] } VR128X:{ *:[v4i32] }:$src1, VR128X:{ *:[v4i32] }:$src2) => (VPANDDZ128rr:{ *:[v4i32] } VR128X:{ *:[v4i32] }:$src1, VR128X:{ *:[v4i32] }:$src2) 3583 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPANDDZ128rr, 3584 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3585 // GIR_Coverage, 4993, 3586 GIR_Done, 3587 // Label 308: @6251 3588 GIM_Try, /*On fail goto*//*Label 309*/ 6274, // Rule ID 13465 // 3589 GIM_CheckFeatures, GIFBS_HasAVX_NoVLX, 3590 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 3591 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 3592 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 3593 // (and:{ *:[v4i32] } VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2) => (VPANDrr:{ *:[v4i32] } VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2) 3594 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPANDrr, 3595 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3596 // GIR_Coverage, 13465, 3597 GIR_Done, 3598 // Label 309: @6274 3599 GIM_Try, /*On fail goto*//*Label 310*/ 6297, // Rule ID 13489 // 3600 GIM_CheckFeatures, GIFBS_UseSSE2, 3601 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 3602 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 3603 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 3604 // (and:{ *:[v4i32] } VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2) => (PANDrr:{ *:[v4i32] } VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2) 3605 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::PANDrr, 3606 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3607 // GIR_Coverage, 13489, 3608 GIR_Done, 3609 // Label 310: @6297 3610 GIM_Reject, 3611 // Label 307: @6298 3612 GIM_Reject, 3613 // Label 241: @6299 3614 GIM_Try, /*On fail goto*//*Label 311*/ 6379, 3615 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s64, 3616 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s64, 3617 GIM_Try, /*On fail goto*//*Label 312*/ 6332, // Rule ID 1629 // 3618 GIM_CheckFeatures, GIFBS_HasAVX2_NoVLX, 3619 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID, 3620 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256RegClassID, 3621 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID, 3622 // (and:{ *:[v4i64] } VR256:{ *:[v4i64] }:$src1, VR256:{ *:[v4i64] }:$src2) => (VPANDYrr:{ *:[v4i64] } VR256:{ *:[v4i64] }:$src1, VR256:{ *:[v4i64] }:$src2) 3623 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPANDYrr, 3624 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3625 // GIR_Coverage, 1629, 3626 GIR_Done, 3627 // Label 312: @6332 3628 GIM_Try, /*On fail goto*//*Label 313*/ 6355, // Rule ID 4957 // 3629 GIM_CheckFeatures, GIFBS_HasAVX512_HasVLX, 3630 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 3631 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 3632 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256XRegClassID, 3633 // (and:{ *:[v4i64] } VR256X:{ *:[v4i64] }:$src1, VR256X:{ *:[v4i64] }:$src2) => (VPANDQZ256rr:{ *:[v4i64] } VR256X:{ *:[v4i64] }:$src1, VR256X:{ *:[v4i64] }:$src2) 3634 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPANDQZ256rr, 3635 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3636 // GIR_Coverage, 4957, 3637 GIR_Done, 3638 // Label 313: @6355 3639 GIM_Try, /*On fail goto*//*Label 314*/ 6378, // Rule ID 13434 // 3640 GIM_CheckFeatures, GIFBS_HasAVX1Only, 3641 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID, 3642 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256RegClassID, 3643 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID, 3644 // (and:{ *:[v4i64] } VR256:{ *:[v4i64] }:$src1, VR256:{ *:[v4i64] }:$src2) => (VANDPSYrr:{ *:[v4i64] } VR256:{ *:[v4i64] }:$src1, VR256:{ *:[v4i64] }:$src2) 3645 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VANDPSYrr, 3646 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3647 // GIR_Coverage, 13434, 3648 GIR_Done, 3649 // Label 314: @6378 3650 GIM_Reject, 3651 // Label 311: @6379 3652 GIM_Reject, 3653 // Label 242: @6380 3654 GIM_Try, /*On fail goto*//*Label 315*/ 6488, 3655 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s1, 3656 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s1, 3657 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VK8RegClassID, 3658 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VK8RegClassID, 3659 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VK8RegClassID, 3660 GIM_Try, /*On fail goto*//*Label 316*/ 6413, // Rule ID 3683 // 3661 GIM_CheckFeatures, GIFBS_HasDQI, 3662 // (and:{ *:[v8i1] } VK8:{ *:[v8i1] }:$src1, VK8:{ *:[v8i1] }:$src2) => (KANDBrr:{ *:[v8i1] } VK8:{ *:[v8i1] }:$src1, VK8:{ *:[v8i1] }:$src2) 3663 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::KANDBrr, 3664 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3665 // GIR_Coverage, 3683, 3666 GIR_Done, 3667 // Label 316: @6413 3668 GIM_Try, /*On fail goto*//*Label 317*/ 6487, // Rule ID 14585 // 3669 GIM_CheckFeatures, GIFBS_NoDQI, 3670 // (and:{ *:[v8i1] } VK8:{ *:[v8i1] }:$src1, VK8:{ *:[v8i1] }:$src2) => (COPY_TO_REGCLASS:{ *:[v8i1] } (KANDWrr:{ *:[v16i1] } (COPY_TO_REGCLASS:{ *:[v16i1] } VK8:{ *:[v8i1] }:$src1, VK16:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v16i1] } VK8:{ *:[v8i1] }:$src2, VK16:{ *:[i32] })), VK8:{ *:[i32] }) 3671 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s1, 3672 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s1, 3673 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s1, 3674 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY, 3675 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, 3676 GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // src2 3677 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, 3678 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY, 3679 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 3680 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src1 3681 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 3682 GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::KANDWrr, 3683 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 3684 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 3685 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0, 3686 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 3687 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 3688 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 3689 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 3690 GIR_EraseFromParent, /*InsnID*/0, 3691 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VK8*/12, 3692 // GIR_Coverage, 14585, 3693 GIR_Done, 3694 // Label 317: @6487 3695 GIM_Reject, 3696 // Label 315: @6488 3697 GIM_Reject, 3698 // Label 243: @6489 3699 GIM_Try, /*On fail goto*//*Label 318*/ 6569, 3700 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, 3701 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 3702 GIM_Try, /*On fail goto*//*Label 319*/ 6522, // Rule ID 13464 // 3703 GIM_CheckFeatures, GIFBS_HasAVX_NoVLX, 3704 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 3705 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 3706 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 3707 // (and:{ *:[v8i16] } VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2) => (VPANDrr:{ *:[v8i16] } VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2) 3708 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPANDrr, 3709 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3710 // GIR_Coverage, 13464, 3711 GIR_Done, 3712 // Label 319: @6522 3713 GIM_Try, /*On fail goto*//*Label 320*/ 6545, // Rule ID 13488 // 3714 GIM_CheckFeatures, GIFBS_UseSSE2, 3715 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 3716 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 3717 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 3718 // (and:{ *:[v8i16] } VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2) => (PANDrr:{ *:[v8i16] } VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2) 3719 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::PANDrr, 3720 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3721 // GIR_Coverage, 13488, 3722 GIR_Done, 3723 // Label 320: @6545 3724 GIM_Try, /*On fail goto*//*Label 321*/ 6568, // Rule ID 15056 // 3725 GIM_CheckFeatures, GIFBS_HasVLX, 3726 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 3727 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 3728 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128XRegClassID, 3729 // (and:{ *:[v8i16] } VR128X:{ *:[v8i16] }:$src1, VR128X:{ *:[v8i16] }:$src2) => (VPANDQZ128rr:{ *:[v8i16] } VR128X:{ *:[v8i16] }:$src1, VR128X:{ *:[v8i16] }:$src2) 3730 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPANDQZ128rr, 3731 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3732 // GIR_Coverage, 15056, 3733 GIR_Done, 3734 // Label 321: @6568 3735 GIM_Reject, 3736 // Label 318: @6569 3737 GIM_Reject, 3738 // Label 244: @6570 3739 GIM_Try, /*On fail goto*//*Label 322*/ 6650, 3740 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s32, 3741 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s32, 3742 GIM_Try, /*On fail goto*//*Label 323*/ 6603, // Rule ID 4984 // 3743 GIM_CheckFeatures, GIFBS_HasAVX512_HasVLX, 3744 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 3745 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 3746 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256XRegClassID, 3747 // (and:{ *:[v8i32] } VR256X:{ *:[v8i32] }:$src1, VR256X:{ *:[v8i32] }:$src2) => (VPANDDZ256rr:{ *:[v8i32] } VR256X:{ *:[v8i32] }:$src1, VR256X:{ *:[v8i32] }:$src2) 3748 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPANDDZ256rr, 3749 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3750 // GIR_Coverage, 4984, 3751 GIR_Done, 3752 // Label 323: @6603 3753 GIM_Try, /*On fail goto*//*Label 324*/ 6626, // Rule ID 13409 // 3754 GIM_CheckFeatures, GIFBS_HasAVX2_NoVLX, 3755 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID, 3756 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256RegClassID, 3757 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID, 3758 // (and:{ *:[v8i32] } VR256:{ *:[v8i32] }:$src1, VR256:{ *:[v8i32] }:$src2) => (VPANDYrr:{ *:[v8i32] } VR256:{ *:[v8i32] }:$src1, VR256:{ *:[v8i32] }:$src2) 3759 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPANDYrr, 3760 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3761 // GIR_Coverage, 13409, 3762 GIR_Done, 3763 // Label 324: @6626 3764 GIM_Try, /*On fail goto*//*Label 325*/ 6649, // Rule ID 13433 // 3765 GIM_CheckFeatures, GIFBS_HasAVX1Only, 3766 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID, 3767 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256RegClassID, 3768 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID, 3769 // (and:{ *:[v8i32] } VR256:{ *:[v8i32] }:$src1, VR256:{ *:[v8i32] }:$src2) => (VANDPSYrr:{ *:[v8i32] } VR256:{ *:[v8i32] }:$src1, VR256:{ *:[v8i32] }:$src2) 3770 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VANDPSYrr, 3771 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3772 // GIR_Coverage, 13433, 3773 GIR_Done, 3774 // Label 325: @6649 3775 GIM_Reject, 3776 // Label 322: @6650 3777 GIM_Reject, 3778 // Label 245: @6651 3779 GIM_Try, /*On fail goto*//*Label 326*/ 6682, // Rule ID 4948 // 3780 GIM_CheckFeatures, GIFBS_HasAVX512, 3781 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s64, 3782 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s64, 3783 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 3784 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID, 3785 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR512RegClassID, 3786 // (and:{ *:[v8i64] } VR512:{ *:[v8i64] }:$src1, VR512:{ *:[v8i64] }:$src2) => (VPANDQZrr:{ *:[v8i64] } VR512:{ *:[v8i64] }:$src1, VR512:{ *:[v8i64] }:$src2) 3787 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPANDQZrr, 3788 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3789 // GIR_Coverage, 4948, 3790 GIR_Done, 3791 // Label 326: @6682 3792 GIM_Reject, 3793 // Label 246: @6683 3794 GIM_Try, /*On fail goto*//*Label 327*/ 6714, // Rule ID 3684 // 3795 GIM_CheckFeatures, GIFBS_HasAVX512, 3796 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s1, 3797 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s1, 3798 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VK16RegClassID, 3799 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VK16RegClassID, 3800 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VK16RegClassID, 3801 // (and:{ *:[v16i1] } VK16:{ *:[v16i1] }:$src1, VK16:{ *:[v16i1] }:$src2) => (KANDWrr:{ *:[v16i1] } VK16:{ *:[v16i1] }:$src1, VK16:{ *:[v16i1] }:$src2) 3802 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::KANDWrr, 3803 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3804 // GIR_Coverage, 3684, 3805 GIR_Done, 3806 // Label 327: @6714 3807 GIM_Reject, 3808 // Label 247: @6715 3809 GIM_Try, /*On fail goto*//*Label 328*/ 6795, 3810 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, 3811 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 3812 GIM_Try, /*On fail goto*//*Label 329*/ 6748, // Rule ID 13463 // 3813 GIM_CheckFeatures, GIFBS_HasAVX_NoVLX, 3814 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 3815 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 3816 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 3817 // (and:{ *:[v16i8] } VR128:{ *:[v16i8] }:$src1, VR128:{ *:[v16i8] }:$src2) => (VPANDrr:{ *:[v16i8] } VR128:{ *:[v16i8] }:$src1, VR128:{ *:[v16i8] }:$src2) 3818 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPANDrr, 3819 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3820 // GIR_Coverage, 13463, 3821 GIR_Done, 3822 // Label 329: @6748 3823 GIM_Try, /*On fail goto*//*Label 330*/ 6771, // Rule ID 13487 // 3824 GIM_CheckFeatures, GIFBS_UseSSE2, 3825 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 3826 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 3827 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 3828 // (and:{ *:[v16i8] } VR128:{ *:[v16i8] }:$src1, VR128:{ *:[v16i8] }:$src2) => (PANDrr:{ *:[v16i8] } VR128:{ *:[v16i8] }:$src1, VR128:{ *:[v16i8] }:$src2) 3829 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::PANDrr, 3830 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3831 // GIR_Coverage, 13487, 3832 GIR_Done, 3833 // Label 330: @6771 3834 GIM_Try, /*On fail goto*//*Label 331*/ 6794, // Rule ID 15055 // 3835 GIM_CheckFeatures, GIFBS_HasVLX, 3836 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 3837 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 3838 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128XRegClassID, 3839 // (and:{ *:[v16i8] } VR128X:{ *:[v16i8] }:$src1, VR128X:{ *:[v16i8] }:$src2) => (VPANDQZ128rr:{ *:[v16i8] } VR128X:{ *:[v16i8] }:$src1, VR128X:{ *:[v16i8] }:$src2) 3840 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPANDQZ128rr, 3841 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3842 // GIR_Coverage, 15055, 3843 GIR_Done, 3844 // Label 331: @6794 3845 GIM_Reject, 3846 // Label 328: @6795 3847 GIM_Reject, 3848 // Label 248: @6796 3849 GIM_Try, /*On fail goto*//*Label 332*/ 6876, 3850 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s16, 3851 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s16, 3852 GIM_Try, /*On fail goto*//*Label 333*/ 6829, // Rule ID 13408 // 3853 GIM_CheckFeatures, GIFBS_HasAVX2_NoVLX, 3854 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID, 3855 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256RegClassID, 3856 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID, 3857 // (and:{ *:[v16i16] } VR256:{ *:[v16i16] }:$src1, VR256:{ *:[v16i16] }:$src2) => (VPANDYrr:{ *:[v16i16] } VR256:{ *:[v16i16] }:$src1, VR256:{ *:[v16i16] }:$src2) 3858 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPANDYrr, 3859 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3860 // GIR_Coverage, 13408, 3861 GIR_Done, 3862 // Label 333: @6829 3863 GIM_Try, /*On fail goto*//*Label 334*/ 6852, // Rule ID 13432 // 3864 GIM_CheckFeatures, GIFBS_HasAVX1Only, 3865 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID, 3866 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256RegClassID, 3867 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID, 3868 // (and:{ *:[v16i16] } VR256:{ *:[v16i16] }:$src1, VR256:{ *:[v16i16] }:$src2) => (VANDPSYrr:{ *:[v16i16] } VR256:{ *:[v16i16] }:$src1, VR256:{ *:[v16i16] }:$src2) 3869 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VANDPSYrr, 3870 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3871 // GIR_Coverage, 13432, 3872 GIR_Done, 3873 // Label 334: @6852 3874 GIM_Try, /*On fail goto*//*Label 335*/ 6875, // Rule ID 15072 // 3875 GIM_CheckFeatures, GIFBS_HasVLX, 3876 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 3877 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 3878 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256XRegClassID, 3879 // (and:{ *:[v16i16] } VR256X:{ *:[v16i16] }:$src1, VR256X:{ *:[v16i16] }:$src2) => (VPANDQZ256rr:{ *:[v16i16] } VR256X:{ *:[v16i16] }:$src1, VR256X:{ *:[v16i16] }:$src2) 3880 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPANDQZ256rr, 3881 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3882 // GIR_Coverage, 15072, 3883 GIR_Done, 3884 // Label 335: @6875 3885 GIM_Reject, 3886 // Label 332: @6876 3887 GIM_Reject, 3888 // Label 249: @6877 3889 GIM_Try, /*On fail goto*//*Label 336*/ 6908, // Rule ID 4975 // 3890 GIM_CheckFeatures, GIFBS_HasAVX512, 3891 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s32, 3892 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s32, 3893 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 3894 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID, 3895 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR512RegClassID, 3896 // (and:{ *:[v16i32] } VR512:{ *:[v16i32] }:$src1, VR512:{ *:[v16i32] }:$src2) => (VPANDDZrr:{ *:[v16i32] } VR512:{ *:[v16i32] }:$src1, VR512:{ *:[v16i32] }:$src2) 3897 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPANDDZrr, 3898 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3899 // GIR_Coverage, 4975, 3900 GIR_Done, 3901 // Label 336: @6908 3902 GIM_Reject, 3903 // Label 250: @6909 3904 GIM_Try, /*On fail goto*//*Label 337*/ 6940, // Rule ID 3685 // 3905 GIM_CheckFeatures, GIFBS_HasBWI, 3906 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v32s1, 3907 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v32s1, 3908 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VK32RegClassID, 3909 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VK32RegClassID, 3910 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VK32RegClassID, 3911 // (and:{ *:[v32i1] } VK32:{ *:[v32i1] }:$src1, VK32:{ *:[v32i1] }:$src2) => (KANDDrr:{ *:[v32i1] } VK32:{ *:[v32i1] }:$src1, VK32:{ *:[v32i1] }:$src2) 3912 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::KANDDrr, 3913 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3914 // GIR_Coverage, 3685, 3915 GIR_Done, 3916 // Label 337: @6940 3917 GIM_Reject, 3918 // Label 251: @6941 3919 GIM_Try, /*On fail goto*//*Label 338*/ 7021, 3920 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v32s8, 3921 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v32s8, 3922 GIM_Try, /*On fail goto*//*Label 339*/ 6974, // Rule ID 13407 // 3923 GIM_CheckFeatures, GIFBS_HasAVX2_NoVLX, 3924 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID, 3925 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256RegClassID, 3926 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID, 3927 // (and:{ *:[v32i8] } VR256:{ *:[v32i8] }:$src1, VR256:{ *:[v32i8] }:$src2) => (VPANDYrr:{ *:[v32i8] } VR256:{ *:[v32i8] }:$src1, VR256:{ *:[v32i8] }:$src2) 3928 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPANDYrr, 3929 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3930 // GIR_Coverage, 13407, 3931 GIR_Done, 3932 // Label 339: @6974 3933 GIM_Try, /*On fail goto*//*Label 340*/ 6997, // Rule ID 13431 // 3934 GIM_CheckFeatures, GIFBS_HasAVX1Only, 3935 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID, 3936 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256RegClassID, 3937 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID, 3938 // (and:{ *:[v32i8] } VR256:{ *:[v32i8] }:$src1, VR256:{ *:[v32i8] }:$src2) => (VANDPSYrr:{ *:[v32i8] } VR256:{ *:[v32i8] }:$src1, VR256:{ *:[v32i8] }:$src2) 3939 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VANDPSYrr, 3940 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3941 // GIR_Coverage, 13431, 3942 GIR_Done, 3943 // Label 340: @6997 3944 GIM_Try, /*On fail goto*//*Label 341*/ 7020, // Rule ID 15071 // 3945 GIM_CheckFeatures, GIFBS_HasVLX, 3946 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 3947 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 3948 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256XRegClassID, 3949 // (and:{ *:[v32i8] } VR256X:{ *:[v32i8] }:$src1, VR256X:{ *:[v32i8] }:$src2) => (VPANDQZ256rr:{ *:[v32i8] } VR256X:{ *:[v32i8] }:$src1, VR256X:{ *:[v32i8] }:$src2) 3950 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPANDQZ256rr, 3951 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3952 // GIR_Coverage, 15071, 3953 GIR_Done, 3954 // Label 341: @7020 3955 GIM_Reject, 3956 // Label 338: @7021 3957 GIM_Reject, 3958 // Label 252: @7022 3959 GIM_Try, /*On fail goto*//*Label 342*/ 7053, // Rule ID 15088 // 3960 GIM_CheckFeatures, GIFBS_HasAVX512, 3961 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v32s16, 3962 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v32s16, 3963 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 3964 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID, 3965 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR512RegClassID, 3966 // (and:{ *:[v32i16] } VR512:{ *:[v32i16] }:$src1, VR512:{ *:[v32i16] }:$src2) => (VPANDQZrr:{ *:[v32i16] } VR512:{ *:[v32i16] }:$src1, VR512:{ *:[v32i16] }:$src2) 3967 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPANDQZrr, 3968 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3969 // GIR_Coverage, 15088, 3970 GIR_Done, 3971 // Label 342: @7053 3972 GIM_Reject, 3973 // Label 253: @7054 3974 GIM_Try, /*On fail goto*//*Label 343*/ 7085, // Rule ID 3686 // 3975 GIM_CheckFeatures, GIFBS_HasBWI, 3976 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v64s1, 3977 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v64s1, 3978 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VK64RegClassID, 3979 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VK64RegClassID, 3980 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VK64RegClassID, 3981 // (and:{ *:[v64i1] } VK64:{ *:[v64i1] }:$src1, VK64:{ *:[v64i1] }:$src2) => (KANDQrr:{ *:[v64i1] } VK64:{ *:[v64i1] }:$src1, VK64:{ *:[v64i1] }:$src2) 3982 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::KANDQrr, 3983 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3984 // GIR_Coverage, 3686, 3985 GIR_Done, 3986 // Label 343: @7085 3987 GIM_Reject, 3988 // Label 254: @7086 3989 GIM_Try, /*On fail goto*//*Label 344*/ 7117, // Rule ID 15087 // 3990 GIM_CheckFeatures, GIFBS_HasAVX512, 3991 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v64s8, 3992 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v64s8, 3993 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 3994 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID, 3995 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR512RegClassID, 3996 // (and:{ *:[v64i8] } VR512:{ *:[v64i8] }:$src1, VR512:{ *:[v64i8] }:$src2) => (VPANDQZrr:{ *:[v64i8] } VR512:{ *:[v64i8] }:$src1, VR512:{ *:[v64i8] }:$src2) 3997 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPANDQZrr, 3998 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3999 // GIR_Coverage, 15087, 4000 GIR_Done, 4001 // Label 344: @7117 4002 GIM_Reject, 4003 // Label 255: @7118 4004 GIM_Reject, 4005 // Label 4: @7119 4006 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 25, /*)*//*default:*//*Label 368*/ 10988, 4007 /*GILLT_s1*//*Label 345*/ 7150, 4008 /*GILLT_s8*//*Label 346*/ 7243, 4009 /*GILLT_s16*//*Label 347*/ 7309, 4010 /*GILLT_s32*//*Label 348*/ 7608, 4011 /*GILLT_s64*//*Label 349*/ 8713, 0, 0, 4012 /*GILLT_v2s1*//*Label 350*/ 9821, 4013 /*GILLT_v2s64*//*Label 351*/ 9914, 4014 /*GILLT_v4s1*//*Label 352*/ 9995, 4015 /*GILLT_v4s32*//*Label 353*/ 10088, 4016 /*GILLT_v4s64*//*Label 354*/ 10169, 4017 /*GILLT_v8s1*//*Label 355*/ 10250, 4018 /*GILLT_v8s16*//*Label 356*/ 10359, 4019 /*GILLT_v8s32*//*Label 357*/ 10440, 4020 /*GILLT_v8s64*//*Label 358*/ 10521, 4021 /*GILLT_v16s1*//*Label 359*/ 10553, 4022 /*GILLT_v16s8*//*Label 360*/ 10585, 4023 /*GILLT_v16s16*//*Label 361*/ 10666, 4024 /*GILLT_v16s32*//*Label 362*/ 10747, 4025 /*GILLT_v32s1*//*Label 363*/ 10779, 4026 /*GILLT_v32s8*//*Label 364*/ 10811, 4027 /*GILLT_v32s16*//*Label 365*/ 10892, 4028 /*GILLT_v64s1*//*Label 366*/ 10924, 4029 /*GILLT_v64s8*//*Label 367*/ 10956, 4030 // Label 345: @7150 4031 GIM_Try, /*On fail goto*//*Label 369*/ 7242, // Rule ID 14594 // 4032 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s1, 4033 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s1, 4034 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VK1RegClassID, 4035 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VK1RegClassID, 4036 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VK1RegClassID, 4037 // (or:{ *:[v1i1] } VK1:{ *:[v1i1] }:$src1, VK1:{ *:[v1i1] }:$src2) => (COPY_TO_REGCLASS:{ *:[v1i1] } (KORWrr:{ *:[v16i1] } (COPY_TO_REGCLASS:{ *:[v16i1] } VK1:{ *:[v1i1] }:$src1, VK16:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v16i1] } VK1:{ *:[v1i1] }:$src2, VK16:{ *:[i32] })), VK1:{ *:[i32] }) 4038 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s1, 4039 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s1, 4040 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s1, 4041 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY, 4042 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, 4043 GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // src2 4044 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, 4045 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY, 4046 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 4047 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src1 4048 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 4049 GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::KORWrr, 4050 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 4051 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 4052 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0, 4053 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 4054 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 4055 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 4056 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 4057 GIR_EraseFromParent, /*InsnID*/0, 4058 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VK1*/8, 4059 // GIR_Coverage, 14594, 4060 GIR_Done, 4061 // Label 369: @7242 4062 GIM_Reject, 4063 // Label 346: @7243 4064 GIM_Try, /*On fail goto*//*Label 370*/ 7308, 4065 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s8, 4066 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s8, 4067 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR8RegClassID, 4068 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR8RegClassID, 4069 GIM_Try, /*On fail goto*//*Label 371*/ 7291, // Rule ID 17359 // 4070 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 4071 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 4072 // MIs[1] Operand 1 4073 // No operand predicates 4074 GIM_CheckIsSafeToFold, /*InsnID*/1, 4075 // (or:{ *:[i8] } GR8:{ *:[i8] }:$src1, (imm:{ *:[i8] }):$src2) => (OR8ri:{ *:[i8] }:{ *:[i32] } GR8:{ *:[i8] }:$src1, (imm:{ *:[i8] }):$src2) 4076 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::OR8ri, 4077 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 4078 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 4079 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2 4080 GIR_EraseFromParent, /*InsnID*/0, 4081 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4082 // GIR_Coverage, 17359, 4083 GIR_Done, 4084 // Label 371: @7291 4085 GIM_Try, /*On fail goto*//*Label 372*/ 7307, // Rule ID 17351 // 4086 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR8RegClassID, 4087 // (or:{ *:[i8] } GR8:{ *:[i8] }:$src1, GR8:{ *:[i8] }:$src2) => (OR8rr:{ *:[i8] }:{ *:[i32] } GR8:{ *:[i8] }:$src1, GR8:{ *:[i8] }:$src2) 4088 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::OR8rr, 4089 GIR_AddImplicitDef, /*InsnID*/0, X86::EFLAGS, 4090 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4091 // GIR_Coverage, 17351, 4092 GIR_Done, 4093 // Label 372: @7307 4094 GIM_Reject, 4095 // Label 370: @7308 4096 GIM_Reject, 4097 // Label 347: @7309 4098 GIM_Try, /*On fail goto*//*Label 373*/ 7607, 4099 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, 4100 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16, 4101 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR16RegClassID, 4102 GIM_Try, /*On fail goto*//*Label 374*/ 7419, // Rule ID 20033 // 4103 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 4104 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SHL, 4105 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, 4106 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s8, 4107 GIM_CheckConstantInt, /*MI*/1, /*Op*/1, 1, 4108 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/X86::GR8RegClassID, 4109 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR16RegClassID, 4110 GIM_CheckIsSafeToFold, /*InsnID*/1, 4111 // (or:{ *:[i16] } (shl:{ *:[i16] } 1:{ *:[i16] }, GR8:{ *:[i8] }:$src2), GR16:{ *:[i16] }:$src1) => (BTS16rr:{ *:[i16] }:{ *:[i32] } GR16:{ *:[i16] }:$src1, (INSERT_SUBREG:{ *:[i16] } (IMPLICIT_DEF:{ *:[i16] }), GR8:{ *:[i8] }:$src2, sub_8bit:{ *:[i32] })) 4112 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, 4113 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16, 4114 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, 4115 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 4116 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 4117 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, 4118 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 4119 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 4120 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // src2 4121 GIR_AddImm, /*InsnID*/1, /*Imm*/1, 4122 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, /*RC GR16*/6, 4123 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, /*RC GR16*/6, 4124 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, /*RC GR8*/0, 4125 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BTS16rr, 4126 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 4127 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 4128 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 4129 GIR_EraseFromParent, /*InsnID*/0, 4130 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4131 // GIR_Coverage, 20033, 4132 GIR_Done, 4133 // Label 374: @7419 4134 GIM_Try, /*On fail goto*//*Label 375*/ 7515, // Rule ID 17262 // 4135 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR16RegClassID, 4136 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 4137 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SHL, 4138 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, 4139 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s8, 4140 GIM_CheckConstantInt, /*MI*/1, /*Op*/1, 1, 4141 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/X86::GR8RegClassID, 4142 GIM_CheckIsSafeToFold, /*InsnID*/1, 4143 // (or:{ *:[i16] } GR16:{ *:[i16] }:$src1, (shl:{ *:[i16] } 1:{ *:[i16] }, GR8:{ *:[i8] }:$src2)) => (BTS16rr:{ *:[i16] }:{ *:[i32] } GR16:{ *:[i16] }:$src1, (INSERT_SUBREG:{ *:[i16] } (IMPLICIT_DEF:{ *:[i16] }), GR8:{ *:[i8] }:$src2, sub_8bit:{ *:[i32] })) 4144 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, 4145 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16, 4146 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, 4147 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 4148 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 4149 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, 4150 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 4151 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 4152 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // src2 4153 GIR_AddImm, /*InsnID*/1, /*Imm*/1, 4154 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, /*RC GR16*/6, 4155 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, /*RC GR16*/6, 4156 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, /*RC GR8*/0, 4157 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BTS16rr, 4158 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 4159 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 4160 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 4161 GIR_EraseFromParent, /*InsnID*/0, 4162 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4163 // GIR_Coverage, 17262, 4164 GIR_Done, 4165 // Label 375: @7515 4166 GIM_Try, /*On fail goto*//*Label 376*/ 7552, // Rule ID 17362 // 4167 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR16RegClassID, 4168 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 4169 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 4170 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_i16immSExt8, 4171 // MIs[1] Operand 1 4172 // No operand predicates 4173 GIM_CheckIsSafeToFold, /*InsnID*/1, 4174 // (or:{ *:[i16] } GR16:{ *:[i16] }:$src1, (imm:{ *:[i16] })<<P:Predicate_i16immSExt8>>:$src2) => (OR16ri8:{ *:[i16] }:{ *:[i32] } GR16:{ *:[i16] }:$src1, (imm:{ *:[i16] })<<P:Predicate_i16immSExt8>>:$src2) 4175 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::OR16ri8, 4176 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 4177 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 4178 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2 4179 GIR_EraseFromParent, /*InsnID*/0, 4180 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4181 // GIR_Coverage, 17362, 4182 GIR_Done, 4183 // Label 376: @7552 4184 GIM_Try, /*On fail goto*//*Label 377*/ 7586, // Rule ID 17360 // 4185 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR16RegClassID, 4186 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 4187 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 4188 // MIs[1] Operand 1 4189 // No operand predicates 4190 GIM_CheckIsSafeToFold, /*InsnID*/1, 4191 // (or:{ *:[i16] } GR16:{ *:[i16] }:$src1, (imm:{ *:[i16] }):$src2) => (OR16ri:{ *:[i16] }:{ *:[i32] } GR16:{ *:[i16] }:$src1, (imm:{ *:[i16] }):$src2) 4192 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::OR16ri, 4193 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 4194 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 4195 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2 4196 GIR_EraseFromParent, /*InsnID*/0, 4197 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4198 // GIR_Coverage, 17360, 4199 GIR_Done, 4200 // Label 377: @7586 4201 GIM_Try, /*On fail goto*//*Label 378*/ 7606, // Rule ID 17352 // 4202 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR16RegClassID, 4203 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR16RegClassID, 4204 // (or:{ *:[i16] } GR16:{ *:[i16] }:$src1, GR16:{ *:[i16] }:$src2) => (OR16rr:{ *:[i16] }:{ *:[i32] } GR16:{ *:[i16] }:$src1, GR16:{ *:[i16] }:$src2) 4205 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::OR16rr, 4206 GIR_AddImplicitDef, /*InsnID*/0, X86::EFLAGS, 4207 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4208 // GIR_Coverage, 17352, 4209 GIR_Done, 4210 // Label 378: @7606 4211 GIM_Reject, 4212 // Label 373: @7607 4213 GIM_Reject, 4214 // Label 348: @7608 4215 GIM_Try, /*On fail goto*//*Label 379*/ 8712, 4216 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 4217 GIM_Try, /*On fail goto*//*Label 380*/ 7689, // Rule ID 19196 // 4218 GIM_CheckFeatures, GIFBS_HasTBM, 4219 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 4220 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 4221 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 4222 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD, 4223 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, 4224 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, 4225 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::GR32RegClassID, 4226 GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, 4227 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] 4228 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_XOR, 4229 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, 4230 // MIs[2] src 4231 GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, 4232 GIM_CheckConstantInt, /*MI*/2, /*Op*/2, -1, 4233 GIM_CheckIsSafeToFold, /*InsnID*/1, 4234 GIM_CheckIsSafeToFold, /*InsnID*/2, 4235 // (or:{ *:[i32] } (add:{ *:[i32] } GR32:{ *:[i32] }:$src, -1:{ *:[i32] }), (xor:{ *:[i32] } GR32:{ *:[i32] }:$src, -1:{ *:[i32] })) => (BLSIC32rr:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src) 4236 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLSIC32rr, 4237 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 4238 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src 4239 GIR_EraseFromParent, /*InsnID*/0, 4240 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4241 // GIR_Coverage, 19196, 4242 GIR_Done, 4243 // Label 380: @7689 4244 GIM_Try, /*On fail goto*//*Label 381*/ 7764, // Rule ID 19198 // 4245 GIM_CheckFeatures, GIFBS_HasTBM, 4246 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 4247 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 4248 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 4249 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD, 4250 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, 4251 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, 4252 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::GR32RegClassID, 4253 GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 1, 4254 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] 4255 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_XOR, 4256 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, 4257 // MIs[2] src 4258 GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, 4259 GIM_CheckConstantInt, /*MI*/2, /*Op*/2, -1, 4260 GIM_CheckIsSafeToFold, /*InsnID*/1, 4261 GIM_CheckIsSafeToFold, /*InsnID*/2, 4262 // (or:{ *:[i32] } (add:{ *:[i32] } GR32:{ *:[i32] }:$src, 1:{ *:[i32] }), (xor:{ *:[i32] } GR32:{ *:[i32] }:$src, -1:{ *:[i32] })) => (T1MSKC32rr:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src) 4263 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::T1MSKC32rr, 4264 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 4265 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src 4266 GIR_EraseFromParent, /*InsnID*/0, 4267 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4268 // GIR_Coverage, 19198, 4269 GIR_Done, 4270 // Label 381: @7764 4271 GIM_Try, /*On fail goto*//*Label 382*/ 7839, // Rule ID 19184 // 4272 GIM_CheckFeatures, GIFBS_HasTBM, 4273 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 4274 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 4275 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, 4276 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, 4277 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, 4278 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] 4279 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ADD, 4280 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, 4281 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, 4282 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/X86::GR32RegClassID, 4283 GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 1, 4284 GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, 4285 // MIs[0] src 4286 GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, 4287 GIM_CheckIsSafeToFold, /*InsnID*/1, 4288 GIM_CheckIsSafeToFold, /*InsnID*/2, 4289 // (or:{ *:[i32] } (xor:{ *:[i32] } (add:{ *:[i32] } GR32:{ *:[i32] }:$src, 1:{ *:[i32] }), -1:{ *:[i32] }), GR32:{ *:[i32] }:$src) => (BLCI32rr:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src) 4290 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLCI32rr, 4291 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 4292 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src 4293 GIR_EraseFromParent, /*InsnID*/0, 4294 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4295 // GIR_Coverage, 19184, 4296 GIR_Done, 4297 // Label 382: @7839 4298 GIM_Try, /*On fail goto*//*Label 383*/ 7914, // Rule ID 13017 // 4299 GIM_CheckFeatures, GIFBS_HasTBM, 4300 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 4301 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 4302 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 4303 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, 4304 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, 4305 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, 4306 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::GR32RegClassID, 4307 GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, 4308 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] 4309 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ADD, 4310 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, 4311 // MIs[2] src 4312 GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, 4313 GIM_CheckConstantInt, /*MI*/2, /*Op*/2, -1, 4314 GIM_CheckIsSafeToFold, /*InsnID*/1, 4315 GIM_CheckIsSafeToFold, /*InsnID*/2, 4316 // (or:{ *:[i32] } (xor:{ *:[i32] } GR32:{ *:[i32] }:$src, -1:{ *:[i32] }), (add:{ *:[i32] } GR32:{ *:[i32] }:$src, -1:{ *:[i32] })) => (BLSIC32rr:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src) 4317 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLSIC32rr, 4318 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 4319 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src 4320 GIR_EraseFromParent, /*InsnID*/0, 4321 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4322 // GIR_Coverage, 13017, 4323 GIR_Done, 4324 // Label 383: @7914 4325 GIM_Try, /*On fail goto*//*Label 384*/ 7989, // Rule ID 13019 // 4326 GIM_CheckFeatures, GIFBS_HasTBM, 4327 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 4328 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 4329 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 4330 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, 4331 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, 4332 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, 4333 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::GR32RegClassID, 4334 GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, 4335 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] 4336 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ADD, 4337 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, 4338 // MIs[2] src 4339 GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, 4340 GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 1, 4341 GIM_CheckIsSafeToFold, /*InsnID*/1, 4342 GIM_CheckIsSafeToFold, /*InsnID*/2, 4343 // (or:{ *:[i32] } (xor:{ *:[i32] } GR32:{ *:[i32] }:$src, -1:{ *:[i32] }), (add:{ *:[i32] } GR32:{ *:[i32] }:$src, 1:{ *:[i32] })) => (T1MSKC32rr:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src) 4344 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::T1MSKC32rr, 4345 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 4346 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src 4347 GIR_EraseFromParent, /*InsnID*/0, 4348 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4349 // GIR_Coverage, 13019, 4350 GIR_Done, 4351 // Label 384: @7989 4352 GIM_Try, /*On fail goto*//*Label 385*/ 8064, // Rule ID 13005 // 4353 GIM_CheckFeatures, GIFBS_HasTBM, 4354 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 4355 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 4356 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR32RegClassID, 4357 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 4358 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, 4359 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, 4360 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, 4361 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] 4362 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ADD, 4363 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, 4364 // MIs[2] src 4365 GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/0, /*OtherOpIdx*/1, 4366 GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 1, 4367 GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, 4368 GIM_CheckIsSafeToFold, /*InsnID*/1, 4369 GIM_CheckIsSafeToFold, /*InsnID*/2, 4370 // (or:{ *:[i32] } GR32:{ *:[i32] }:$src, (xor:{ *:[i32] } (add:{ *:[i32] } GR32:{ *:[i32] }:$src, 1:{ *:[i32] }), -1:{ *:[i32] })) => (BLCI32rr:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src) 4371 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLCI32rr, 4372 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 4373 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 4374 GIR_EraseFromParent, /*InsnID*/0, 4375 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4376 // GIR_Coverage, 13005, 4377 GIR_Done, 4378 // Label 385: @8064 4379 GIM_Try, /*On fail goto*//*Label 386*/ 8118, // Rule ID 19192 // 4380 GIM_CheckFeatures, GIFBS_HasTBM, 4381 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 4382 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 4383 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD, 4384 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, 4385 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, 4386 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::GR32RegClassID, 4387 GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 1, 4388 // MIs[0] src 4389 GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, 4390 GIM_CheckIsSafeToFold, /*InsnID*/1, 4391 // (or:{ *:[i32] } (add:{ *:[i32] } GR32:{ *:[i32] }:$src, 1:{ *:[i32] }), GR32:{ *:[i32] }:$src) => (BLCS32rr:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src) 4392 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLCS32rr, 4393 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 4394 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src 4395 GIR_EraseFromParent, /*InsnID*/0, 4396 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4397 // GIR_Coverage, 19192, 4398 GIR_Done, 4399 // Label 386: @8118 4400 GIM_Try, /*On fail goto*//*Label 387*/ 8172, // Rule ID 19194 // 4401 GIM_CheckFeatures, GIFBS_HasTBM, 4402 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 4403 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 4404 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD, 4405 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, 4406 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, 4407 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::GR32RegClassID, 4408 GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, 4409 // MIs[0] src 4410 GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, 4411 GIM_CheckIsSafeToFold, /*InsnID*/1, 4412 // (or:{ *:[i32] } (add:{ *:[i32] } GR32:{ *:[i32] }:$src, -1:{ *:[i32] }), GR32:{ *:[i32] }:$src) => (BLSFILL32rr:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src) 4413 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLSFILL32rr, 4414 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 4415 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src 4416 GIR_EraseFromParent, /*InsnID*/0, 4417 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4418 // GIR_Coverage, 19194, 4419 GIR_Done, 4420 // Label 387: @8172 4421 GIM_Try, /*On fail goto*//*Label 388*/ 8276, // Rule ID 20039 // 4422 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 4423 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 4424 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 4425 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SHL, 4426 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, 4427 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s8, 4428 GIM_CheckConstantInt, /*MI*/1, /*Op*/1, 1, 4429 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/X86::GR8RegClassID, 4430 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR32RegClassID, 4431 GIM_CheckIsSafeToFold, /*InsnID*/1, 4432 // (or:{ *:[i32] } (shl:{ *:[i32] } 1:{ *:[i32] }, GR8:{ *:[i8] }:$src2), GR32:{ *:[i32] }:$src1) => (BTS32rr:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src1, (INSERT_SUBREG:{ *:[i32] } (IMPLICIT_DEF:{ *:[i32] }), GR8:{ *:[i8] }:$src2, sub_8bit:{ *:[i32] })) 4433 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, 4434 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, 4435 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, 4436 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 4437 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 4438 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, 4439 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 4440 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 4441 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // src2 4442 GIR_AddImm, /*InsnID*/1, /*Imm*/1, 4443 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, /*RC LOW32_ADDR_ACCESS_RBP_with_sub_8bit*/30, 4444 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, /*RC LOW32_ADDR_ACCESS_RBP_with_sub_8bit*/30, 4445 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, /*RC GR8*/0, 4446 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BTS32rr, 4447 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 4448 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 4449 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 4450 GIR_EraseFromParent, /*InsnID*/0, 4451 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4452 // GIR_Coverage, 20039, 4453 GIR_Done, 4454 // Label 388: @8276 4455 GIM_Try, /*On fail goto*//*Label 389*/ 8330, // Rule ID 19186 // 4456 GIM_CheckFeatures, GIFBS_HasTBM, 4457 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 4458 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 4459 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SUB, 4460 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, 4461 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, 4462 GIM_CheckConstantInt, /*MI*/1, /*Op*/1, -2, 4463 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/X86::GR32RegClassID, 4464 // MIs[0] src 4465 GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, 4466 GIM_CheckIsSafeToFold, /*InsnID*/1, 4467 // (or:{ *:[i32] } (sub:{ *:[i32] } -2:{ *:[i32] }, GR32:{ *:[i32] }:$src), GR32:{ *:[i32] }:$src) => (BLCI32rr:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src) 4468 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLCI32rr, 4469 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 4470 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src 4471 GIR_EraseFromParent, /*InsnID*/0, 4472 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4473 // GIR_Coverage, 19186, 4474 GIR_Done, 4475 // Label 389: @8330 4476 GIM_Try, /*On fail goto*//*Label 390*/ 8384, // Rule ID 13013 // 4477 GIM_CheckFeatures, GIFBS_HasTBM, 4478 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 4479 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 4480 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR32RegClassID, 4481 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 4482 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD, 4483 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, 4484 // MIs[1] src 4485 GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/1, /*OtherMI*/0, /*OtherOpIdx*/1, 4486 GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 1, 4487 GIM_CheckIsSafeToFold, /*InsnID*/1, 4488 // (or:{ *:[i32] } GR32:{ *:[i32] }:$src, (add:{ *:[i32] } GR32:{ *:[i32] }:$src, 1:{ *:[i32] })) => (BLCS32rr:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src) 4489 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLCS32rr, 4490 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 4491 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 4492 GIR_EraseFromParent, /*InsnID*/0, 4493 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4494 // GIR_Coverage, 13013, 4495 GIR_Done, 4496 // Label 390: @8384 4497 GIM_Try, /*On fail goto*//*Label 391*/ 8438, // Rule ID 13015 // 4498 GIM_CheckFeatures, GIFBS_HasTBM, 4499 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 4500 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 4501 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR32RegClassID, 4502 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 4503 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD, 4504 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, 4505 // MIs[1] src 4506 GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/1, /*OtherMI*/0, /*OtherOpIdx*/1, 4507 GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, 4508 GIM_CheckIsSafeToFold, /*InsnID*/1, 4509 // (or:{ *:[i32] } GR32:{ *:[i32] }:$src, (add:{ *:[i32] } GR32:{ *:[i32] }:$src, -1:{ *:[i32] })) => (BLSFILL32rr:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src) 4510 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLSFILL32rr, 4511 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 4512 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 4513 GIR_EraseFromParent, /*InsnID*/0, 4514 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4515 // GIR_Coverage, 13015, 4516 GIR_Done, 4517 // Label 391: @8438 4518 GIM_Try, /*On fail goto*//*Label 392*/ 8542, // Rule ID 17268 // 4519 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 4520 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 4521 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR32RegClassID, 4522 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 4523 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SHL, 4524 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, 4525 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s8, 4526 GIM_CheckConstantInt, /*MI*/1, /*Op*/1, 1, 4527 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/X86::GR8RegClassID, 4528 GIM_CheckIsSafeToFold, /*InsnID*/1, 4529 // (or:{ *:[i32] } GR32:{ *:[i32] }:$src1, (shl:{ *:[i32] } 1:{ *:[i32] }, GR8:{ *:[i8] }:$src2)) => (BTS32rr:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src1, (INSERT_SUBREG:{ *:[i32] } (IMPLICIT_DEF:{ *:[i32] }), GR8:{ *:[i8] }:$src2, sub_8bit:{ *:[i32] })) 4530 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, 4531 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, 4532 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, 4533 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 4534 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 4535 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, 4536 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 4537 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 4538 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // src2 4539 GIR_AddImm, /*InsnID*/1, /*Imm*/1, 4540 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, /*RC LOW32_ADDR_ACCESS_RBP_with_sub_8bit*/30, 4541 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, /*RC LOW32_ADDR_ACCESS_RBP_with_sub_8bit*/30, 4542 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, /*RC GR8*/0, 4543 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BTS32rr, 4544 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 4545 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 4546 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 4547 GIR_EraseFromParent, /*InsnID*/0, 4548 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4549 // GIR_Coverage, 17268, 4550 GIR_Done, 4551 // Label 392: @8542 4552 GIM_Try, /*On fail goto*//*Label 393*/ 8596, // Rule ID 13007 // 4553 GIM_CheckFeatures, GIFBS_HasTBM, 4554 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 4555 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 4556 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR32RegClassID, 4557 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 4558 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SUB, 4559 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, 4560 GIM_CheckConstantInt, /*MI*/1, /*Op*/1, -2, 4561 // MIs[1] src 4562 GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/2, /*OtherMI*/0, /*OtherOpIdx*/1, 4563 GIM_CheckIsSafeToFold, /*InsnID*/1, 4564 // (or:{ *:[i32] } GR32:{ *:[i32] }:$src, (sub:{ *:[i32] } -2:{ *:[i32] }, GR32:{ *:[i32] }:$src)) => (BLCI32rr:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src) 4565 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLCI32rr, 4566 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 4567 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 4568 GIR_EraseFromParent, /*InsnID*/0, 4569 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4570 // GIR_Coverage, 13007, 4571 GIR_Done, 4572 // Label 393: @8596 4573 GIM_Try, /*On fail goto*//*Label 394*/ 8641, // Rule ID 17363 // 4574 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 4575 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 4576 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR32RegClassID, 4577 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 4578 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 4579 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_i32immSExt8, 4580 // MIs[1] Operand 1 4581 // No operand predicates 4582 GIM_CheckIsSafeToFold, /*InsnID*/1, 4583 // (or:{ *:[i32] } GR32:{ *:[i32] }:$src1, (imm:{ *:[i32] })<<P:Predicate_i32immSExt8>>:$src2) => (OR32ri8:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src1, (imm:{ *:[i32] })<<P:Predicate_i32immSExt8>>:$src2) 4584 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::OR32ri8, 4585 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 4586 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 4587 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2 4588 GIR_EraseFromParent, /*InsnID*/0, 4589 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4590 // GIR_Coverage, 17363, 4591 GIR_Done, 4592 // Label 394: @8641 4593 GIM_Try, /*On fail goto*//*Label 395*/ 8683, // Rule ID 17361 // 4594 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 4595 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 4596 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR32RegClassID, 4597 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 4598 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 4599 // MIs[1] Operand 1 4600 // No operand predicates 4601 GIM_CheckIsSafeToFold, /*InsnID*/1, 4602 // (or:{ *:[i32] } GR32:{ *:[i32] }:$src1, (imm:{ *:[i32] }):$src2) => (OR32ri:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src1, (imm:{ *:[i32] }):$src2) 4603 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::OR32ri, 4604 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 4605 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 4606 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2 4607 GIR_EraseFromParent, /*InsnID*/0, 4608 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4609 // GIR_Coverage, 17361, 4610 GIR_Done, 4611 // Label 395: @8683 4612 GIM_Try, /*On fail goto*//*Label 396*/ 8711, // Rule ID 17353 // 4613 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 4614 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 4615 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR32RegClassID, 4616 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR32RegClassID, 4617 // (or:{ *:[i32] } GR32:{ *:[i32] }:$src1, GR32:{ *:[i32] }:$src2) => (OR32rr:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src1, GR32:{ *:[i32] }:$src2) 4618 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::OR32rr, 4619 GIR_AddImplicitDef, /*InsnID*/0, X86::EFLAGS, 4620 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4621 // GIR_Coverage, 17353, 4622 GIR_Done, 4623 // Label 396: @8711 4624 GIM_Reject, 4625 // Label 379: @8712 4626 GIM_Reject, 4627 // Label 349: @8713 4628 GIM_Try, /*On fail goto*//*Label 397*/ 9820, 4629 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 4630 GIM_Try, /*On fail goto*//*Label 398*/ 8794, // Rule ID 19197 // 4631 GIM_CheckFeatures, GIFBS_HasTBM, 4632 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 4633 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID, 4634 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 4635 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD, 4636 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, 4637 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, 4638 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::GR64RegClassID, 4639 GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, 4640 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] 4641 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_XOR, 4642 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, 4643 // MIs[2] src 4644 GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, 4645 GIM_CheckConstantInt, /*MI*/2, /*Op*/2, -1, 4646 GIM_CheckIsSafeToFold, /*InsnID*/1, 4647 GIM_CheckIsSafeToFold, /*InsnID*/2, 4648 // (or:{ *:[i64] } (add:{ *:[i64] } GR64:{ *:[i64] }:$src, -1:{ *:[i64] }), (xor:{ *:[i64] } GR64:{ *:[i64] }:$src, -1:{ *:[i64] })) => (BLSIC64rr:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src) 4649 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLSIC64rr, 4650 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 4651 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src 4652 GIR_EraseFromParent, /*InsnID*/0, 4653 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4654 // GIR_Coverage, 19197, 4655 GIR_Done, 4656 // Label 398: @8794 4657 GIM_Try, /*On fail goto*//*Label 399*/ 8869, // Rule ID 19199 // 4658 GIM_CheckFeatures, GIFBS_HasTBM, 4659 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 4660 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID, 4661 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 4662 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD, 4663 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, 4664 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, 4665 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::GR64RegClassID, 4666 GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 1, 4667 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] 4668 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_XOR, 4669 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, 4670 // MIs[2] src 4671 GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, 4672 GIM_CheckConstantInt, /*MI*/2, /*Op*/2, -1, 4673 GIM_CheckIsSafeToFold, /*InsnID*/1, 4674 GIM_CheckIsSafeToFold, /*InsnID*/2, 4675 // (or:{ *:[i64] } (add:{ *:[i64] } GR64:{ *:[i64] }:$src, 1:{ *:[i64] }), (xor:{ *:[i64] } GR64:{ *:[i64] }:$src, -1:{ *:[i64] })) => (T1MSKC64rr:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src) 4676 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::T1MSKC64rr, 4677 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 4678 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src 4679 GIR_EraseFromParent, /*InsnID*/0, 4680 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4681 // GIR_Coverage, 19199, 4682 GIR_Done, 4683 // Label 399: @8869 4684 GIM_Try, /*On fail goto*//*Label 400*/ 8944, // Rule ID 19185 // 4685 GIM_CheckFeatures, GIFBS_HasTBM, 4686 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID, 4687 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 4688 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, 4689 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, 4690 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, 4691 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] 4692 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ADD, 4693 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, 4694 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, 4695 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/X86::GR64RegClassID, 4696 GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 1, 4697 GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, 4698 // MIs[0] src 4699 GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, 4700 GIM_CheckIsSafeToFold, /*InsnID*/1, 4701 GIM_CheckIsSafeToFold, /*InsnID*/2, 4702 // (or:{ *:[i64] } (xor:{ *:[i64] } (add:{ *:[i64] } GR64:{ *:[i64] }:$src, 1:{ *:[i64] }), -1:{ *:[i64] }), GR64:{ *:[i64] }:$src) => (BLCI64rr:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src) 4703 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLCI64rr, 4704 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 4705 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src 4706 GIR_EraseFromParent, /*InsnID*/0, 4707 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4708 // GIR_Coverage, 19185, 4709 GIR_Done, 4710 // Label 400: @8944 4711 GIM_Try, /*On fail goto*//*Label 401*/ 9019, // Rule ID 13018 // 4712 GIM_CheckFeatures, GIFBS_HasTBM, 4713 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 4714 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID, 4715 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 4716 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, 4717 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, 4718 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, 4719 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::GR64RegClassID, 4720 GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, 4721 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] 4722 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ADD, 4723 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, 4724 // MIs[2] src 4725 GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, 4726 GIM_CheckConstantInt, /*MI*/2, /*Op*/2, -1, 4727 GIM_CheckIsSafeToFold, /*InsnID*/1, 4728 GIM_CheckIsSafeToFold, /*InsnID*/2, 4729 // (or:{ *:[i64] } (xor:{ *:[i64] } GR64:{ *:[i64] }:$src, -1:{ *:[i64] }), (add:{ *:[i64] } GR64:{ *:[i64] }:$src, -1:{ *:[i64] })) => (BLSIC64rr:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src) 4730 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLSIC64rr, 4731 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 4732 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src 4733 GIR_EraseFromParent, /*InsnID*/0, 4734 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4735 // GIR_Coverage, 13018, 4736 GIR_Done, 4737 // Label 401: @9019 4738 GIM_Try, /*On fail goto*//*Label 402*/ 9094, // Rule ID 13020 // 4739 GIM_CheckFeatures, GIFBS_HasTBM, 4740 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 4741 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID, 4742 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 4743 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, 4744 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, 4745 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, 4746 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::GR64RegClassID, 4747 GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, 4748 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] 4749 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ADD, 4750 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, 4751 // MIs[2] src 4752 GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, 4753 GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 1, 4754 GIM_CheckIsSafeToFold, /*InsnID*/1, 4755 GIM_CheckIsSafeToFold, /*InsnID*/2, 4756 // (or:{ *:[i64] } (xor:{ *:[i64] } GR64:{ *:[i64] }:$src, -1:{ *:[i64] }), (add:{ *:[i64] } GR64:{ *:[i64] }:$src, 1:{ *:[i64] })) => (T1MSKC64rr:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src) 4757 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::T1MSKC64rr, 4758 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 4759 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src 4760 GIR_EraseFromParent, /*InsnID*/0, 4761 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4762 // GIR_Coverage, 13020, 4763 GIR_Done, 4764 // Label 402: @9094 4765 GIM_Try, /*On fail goto*//*Label 403*/ 9169, // Rule ID 13006 // 4766 GIM_CheckFeatures, GIFBS_HasTBM, 4767 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 4768 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID, 4769 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR64RegClassID, 4770 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 4771 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, 4772 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, 4773 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, 4774 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] 4775 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ADD, 4776 GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, 4777 // MIs[2] src 4778 GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/0, /*OtherOpIdx*/1, 4779 GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 1, 4780 GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, 4781 GIM_CheckIsSafeToFold, /*InsnID*/1, 4782 GIM_CheckIsSafeToFold, /*InsnID*/2, 4783 // (or:{ *:[i64] } GR64:{ *:[i64] }:$src, (xor:{ *:[i64] } (add:{ *:[i64] } GR64:{ *:[i64] }:$src, 1:{ *:[i64] }), -1:{ *:[i64] })) => (BLCI64rr:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src) 4784 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLCI64rr, 4785 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 4786 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 4787 GIR_EraseFromParent, /*InsnID*/0, 4788 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4789 // GIR_Coverage, 13006, 4790 GIR_Done, 4791 // Label 403: @9169 4792 GIM_Try, /*On fail goto*//*Label 404*/ 9223, // Rule ID 19193 // 4793 GIM_CheckFeatures, GIFBS_HasTBM, 4794 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID, 4795 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 4796 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD, 4797 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, 4798 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, 4799 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::GR64RegClassID, 4800 GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 1, 4801 // MIs[0] src 4802 GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, 4803 GIM_CheckIsSafeToFold, /*InsnID*/1, 4804 // (or:{ *:[i64] } (add:{ *:[i64] } GR64:{ *:[i64] }:$src, 1:{ *:[i64] }), GR64:{ *:[i64] }:$src) => (BLCS64rr:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src) 4805 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLCS64rr, 4806 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 4807 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src 4808 GIR_EraseFromParent, /*InsnID*/0, 4809 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4810 // GIR_Coverage, 19193, 4811 GIR_Done, 4812 // Label 404: @9223 4813 GIM_Try, /*On fail goto*//*Label 405*/ 9277, // Rule ID 19195 // 4814 GIM_CheckFeatures, GIFBS_HasTBM, 4815 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID, 4816 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 4817 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD, 4818 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, 4819 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, 4820 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::GR64RegClassID, 4821 GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, 4822 // MIs[0] src 4823 GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, 4824 GIM_CheckIsSafeToFold, /*InsnID*/1, 4825 // (or:{ *:[i64] } (add:{ *:[i64] } GR64:{ *:[i64] }:$src, -1:{ *:[i64] }), GR64:{ *:[i64] }:$src) => (BLSFILL64rr:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src) 4826 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLSFILL64rr, 4827 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 4828 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src 4829 GIR_EraseFromParent, /*InsnID*/0, 4830 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4831 // GIR_Coverage, 19195, 4832 GIR_Done, 4833 // Label 405: @9277 4834 GIM_Try, /*On fail goto*//*Label 406*/ 9381, // Rule ID 20045 // 4835 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 4836 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID, 4837 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 4838 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SHL, 4839 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, 4840 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s8, 4841 GIM_CheckConstantInt, /*MI*/1, /*Op*/1, 1, 4842 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/X86::GR8RegClassID, 4843 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR64RegClassID, 4844 GIM_CheckIsSafeToFold, /*InsnID*/1, 4845 // (or:{ *:[i64] } (shl:{ *:[i64] } 1:{ *:[i64] }, GR8:{ *:[i8] }:$src2), GR64:{ *:[i64] }:$src1) => (BTS64rr:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src1, (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), GR8:{ *:[i8] }:$src2, sub_8bit:{ *:[i32] })) 4846 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, 4847 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, 4848 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, 4849 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 4850 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 4851 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, 4852 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 4853 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 4854 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // src2 4855 GIR_AddImm, /*InsnID*/1, /*Imm*/1, 4856 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, /*RC GR64_with_sub_8bit*/68, 4857 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, /*RC GR64_with_sub_8bit*/68, 4858 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, /*RC GR8*/0, 4859 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BTS64rr, 4860 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 4861 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 4862 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 4863 GIR_EraseFromParent, /*InsnID*/0, 4864 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4865 // GIR_Coverage, 20045, 4866 GIR_Done, 4867 // Label 406: @9381 4868 GIM_Try, /*On fail goto*//*Label 407*/ 9435, // Rule ID 19187 // 4869 GIM_CheckFeatures, GIFBS_HasTBM, 4870 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID, 4871 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 4872 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SUB, 4873 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, 4874 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, 4875 GIM_CheckConstantInt, /*MI*/1, /*Op*/1, -2, 4876 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/X86::GR64RegClassID, 4877 // MIs[0] src 4878 GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, 4879 GIM_CheckIsSafeToFold, /*InsnID*/1, 4880 // (or:{ *:[i64] } (sub:{ *:[i64] } -2:{ *:[i64] }, GR64:{ *:[i64] }:$src), GR64:{ *:[i64] }:$src) => (BLCI64rr:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src) 4881 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLCI64rr, 4882 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 4883 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src 4884 GIR_EraseFromParent, /*InsnID*/0, 4885 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4886 // GIR_Coverage, 19187, 4887 GIR_Done, 4888 // Label 407: @9435 4889 GIM_Try, /*On fail goto*//*Label 408*/ 9489, // Rule ID 13014 // 4890 GIM_CheckFeatures, GIFBS_HasTBM, 4891 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 4892 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID, 4893 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR64RegClassID, 4894 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 4895 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD, 4896 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, 4897 // MIs[1] src 4898 GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/1, /*OtherMI*/0, /*OtherOpIdx*/1, 4899 GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 1, 4900 GIM_CheckIsSafeToFold, /*InsnID*/1, 4901 // (or:{ *:[i64] } GR64:{ *:[i64] }:$src, (add:{ *:[i64] } GR64:{ *:[i64] }:$src, 1:{ *:[i64] })) => (BLCS64rr:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src) 4902 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLCS64rr, 4903 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 4904 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 4905 GIR_EraseFromParent, /*InsnID*/0, 4906 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4907 // GIR_Coverage, 13014, 4908 GIR_Done, 4909 // Label 408: @9489 4910 GIM_Try, /*On fail goto*//*Label 409*/ 9543, // Rule ID 13016 // 4911 GIM_CheckFeatures, GIFBS_HasTBM, 4912 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 4913 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID, 4914 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR64RegClassID, 4915 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 4916 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD, 4917 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, 4918 // MIs[1] src 4919 GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/1, /*OtherMI*/0, /*OtherOpIdx*/1, 4920 GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, 4921 GIM_CheckIsSafeToFold, /*InsnID*/1, 4922 // (or:{ *:[i64] } GR64:{ *:[i64] }:$src, (add:{ *:[i64] } GR64:{ *:[i64] }:$src, -1:{ *:[i64] })) => (BLSFILL64rr:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src) 4923 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLSFILL64rr, 4924 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 4925 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 4926 GIR_EraseFromParent, /*InsnID*/0, 4927 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4928 // GIR_Coverage, 13016, 4929 GIR_Done, 4930 // Label 409: @9543 4931 GIM_Try, /*On fail goto*//*Label 410*/ 9647, // Rule ID 17274 // 4932 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 4933 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID, 4934 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR64RegClassID, 4935 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 4936 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SHL, 4937 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, 4938 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s8, 4939 GIM_CheckConstantInt, /*MI*/1, /*Op*/1, 1, 4940 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/X86::GR8RegClassID, 4941 GIM_CheckIsSafeToFold, /*InsnID*/1, 4942 // (or:{ *:[i64] } GR64:{ *:[i64] }:$src1, (shl:{ *:[i64] } 1:{ *:[i64] }, GR8:{ *:[i8] }:$src2)) => (BTS64rr:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src1, (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), GR8:{ *:[i8] }:$src2, sub_8bit:{ *:[i32] })) 4943 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, 4944 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, 4945 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, 4946 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 4947 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 4948 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, 4949 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 4950 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 4951 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // src2 4952 GIR_AddImm, /*InsnID*/1, /*Imm*/1, 4953 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, /*RC GR64_with_sub_8bit*/68, 4954 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, /*RC GR64_with_sub_8bit*/68, 4955 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, /*RC GR8*/0, 4956 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BTS64rr, 4957 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 4958 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 4959 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 4960 GIR_EraseFromParent, /*InsnID*/0, 4961 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4962 // GIR_Coverage, 17274, 4963 GIR_Done, 4964 // Label 410: @9647 4965 GIM_Try, /*On fail goto*//*Label 411*/ 9701, // Rule ID 13008 // 4966 GIM_CheckFeatures, GIFBS_HasTBM, 4967 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 4968 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID, 4969 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR64RegClassID, 4970 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 4971 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SUB, 4972 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, 4973 GIM_CheckConstantInt, /*MI*/1, /*Op*/1, -2, 4974 // MIs[1] src 4975 GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/2, /*OtherMI*/0, /*OtherOpIdx*/1, 4976 GIM_CheckIsSafeToFold, /*InsnID*/1, 4977 // (or:{ *:[i64] } GR64:{ *:[i64] }:$src, (sub:{ *:[i64] } -2:{ *:[i64] }, GR64:{ *:[i64] }:$src)) => (BLCI64rr:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src) 4978 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLCI64rr, 4979 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 4980 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 4981 GIR_EraseFromParent, /*InsnID*/0, 4982 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4983 // GIR_Coverage, 13008, 4984 GIR_Done, 4985 // Label 411: @9701 4986 GIM_Try, /*On fail goto*//*Label 412*/ 9746, // Rule ID 17364 // 4987 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 4988 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID, 4989 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR64RegClassID, 4990 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 4991 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 4992 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_i64immSExt8, 4993 // MIs[1] Operand 1 4994 // No operand predicates 4995 GIM_CheckIsSafeToFold, /*InsnID*/1, 4996 // (or:{ *:[i64] } GR64:{ *:[i64] }:$src1, (imm:{ *:[i64] })<<P:Predicate_i64immSExt8>>:$src2) => (OR64ri8:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src1, (imm:{ *:[i64] })<<P:Predicate_i64immSExt8>>:$src2) 4997 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::OR64ri8, 4998 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 4999 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 5000 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2 5001 GIR_EraseFromParent, /*InsnID*/0, 5002 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5003 // GIR_Coverage, 17364, 5004 GIR_Done, 5005 // Label 412: @9746 5006 GIM_Try, /*On fail goto*//*Label 413*/ 9791, // Rule ID 17365 // 5007 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 5008 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID, 5009 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR64RegClassID, 5010 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 5011 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 5012 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_i64immSExt32, 5013 // MIs[1] Operand 1 5014 // No operand predicates 5015 GIM_CheckIsSafeToFold, /*InsnID*/1, 5016 // (or:{ *:[i64] } GR64:{ *:[i64] }:$src1, (imm:{ *:[i64] })<<P:Predicate_i64immSExt32>>:$src2) => (OR64ri32:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src1, (imm:{ *:[i64] })<<P:Predicate_i64immSExt32>>:$src2) 5017 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::OR64ri32, 5018 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 5019 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 5020 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2 5021 GIR_EraseFromParent, /*InsnID*/0, 5022 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5023 // GIR_Coverage, 17365, 5024 GIR_Done, 5025 // Label 413: @9791 5026 GIM_Try, /*On fail goto*//*Label 414*/ 9819, // Rule ID 17354 // 5027 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 5028 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID, 5029 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR64RegClassID, 5030 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR64RegClassID, 5031 // (or:{ *:[i64] } GR64:{ *:[i64] }:$src1, GR64:{ *:[i64] }:$src2) => (OR64rr:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src1, GR64:{ *:[i64] }:$src2) 5032 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::OR64rr, 5033 GIR_AddImplicitDef, /*InsnID*/0, X86::EFLAGS, 5034 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5035 // GIR_Coverage, 17354, 5036 GIR_Done, 5037 // Label 414: @9819 5038 GIM_Reject, 5039 // Label 397: @9820 5040 GIM_Reject, 5041 // Label 350: @9821 5042 GIM_Try, /*On fail goto*//*Label 415*/ 9913, // Rule ID 14595 // 5043 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s1, 5044 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s1, 5045 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VK1RegClassID, 5046 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VK2RegClassID, 5047 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VK2RegClassID, 5048 // (or:{ *:[v2i1] } VK2:{ *:[v2i1] }:$src1, VK2:{ *:[v2i1] }:$src2) => (COPY_TO_REGCLASS:{ *:[v2i1] } (KORWrr:{ *:[v16i1] } (COPY_TO_REGCLASS:{ *:[v16i1] } VK2:{ *:[v2i1] }:$src1, VK16:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v16i1] } VK2:{ *:[v2i1] }:$src2, VK16:{ *:[i32] })), VK1:{ *:[i32] }) 5049 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s1, 5050 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s1, 5051 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s1, 5052 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY, 5053 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, 5054 GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // src2 5055 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, 5056 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY, 5057 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 5058 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src1 5059 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 5060 GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::KORWrr, 5061 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 5062 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 5063 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0, 5064 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 5065 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 5066 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 5067 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 5068 GIR_EraseFromParent, /*InsnID*/0, 5069 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VK1*/8, 5070 // GIR_Coverage, 14595, 5071 GIR_Done, 5072 // Label 415: @9913 5073 GIM_Reject, 5074 // Label 351: @9914 5075 GIM_Try, /*On fail goto*//*Label 416*/ 9994, 5076 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, 5077 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 5078 GIM_Try, /*On fail goto*//*Label 417*/ 9947, // Rule ID 1631 // 5079 GIM_CheckFeatures, GIFBS_HasAVX_NoVLX, 5080 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 5081 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 5082 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 5083 // (or:{ *:[v2i64] } VR128:{ *:[v2i64] }:$src1, VR128:{ *:[v2i64] }:$src2) => (VPORrr:{ *:[v2i64] } VR128:{ *:[v2i64] }:$src1, VR128:{ *:[v2i64] }:$src2) 5084 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPORrr, 5085 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5086 // GIR_Coverage, 1631, 5087 GIR_Done, 5088 // Label 417: @9947 5089 GIM_Try, /*On fail goto*//*Label 418*/ 9970, // Rule ID 1633 // 5090 GIM_CheckFeatures, GIFBS_UseSSE2, 5091 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 5092 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 5093 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 5094 // (or:{ *:[v2i64] } VR128:{ *:[v2i64] }:$src1, VR128:{ *:[v2i64] }:$src2) => (PORrr:{ *:[v2i64] } VR128:{ *:[v2i64] }:$src1, VR128:{ *:[v2i64] }:$src2) 5095 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::PORrr, 5096 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5097 // GIR_Coverage, 1633, 5098 GIR_Done, 5099 // Label 418: @9970 5100 GIM_Try, /*On fail goto*//*Label 419*/ 9993, // Rule ID 5020 // 5101 GIM_CheckFeatures, GIFBS_HasAVX512_HasVLX, 5102 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 5103 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 5104 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128XRegClassID, 5105 // (or:{ *:[v2i64] } VR128X:{ *:[v2i64] }:$src1, VR128X:{ *:[v2i64] }:$src2) => (VPORQZ128rr:{ *:[v2i64] } VR128X:{ *:[v2i64] }:$src1, VR128X:{ *:[v2i64] }:$src2) 5106 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPORQZ128rr, 5107 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5108 // GIR_Coverage, 5020, 5109 GIR_Done, 5110 // Label 419: @9993 5111 GIM_Reject, 5112 // Label 416: @9994 5113 GIM_Reject, 5114 // Label 352: @9995 5115 GIM_Try, /*On fail goto*//*Label 420*/ 10087, // Rule ID 14596 // 5116 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s1, 5117 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s1, 5118 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VK1RegClassID, 5119 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VK4RegClassID, 5120 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VK4RegClassID, 5121 // (or:{ *:[v4i1] } VK4:{ *:[v4i1] }:$src1, VK4:{ *:[v4i1] }:$src2) => (COPY_TO_REGCLASS:{ *:[v4i1] } (KORWrr:{ *:[v16i1] } (COPY_TO_REGCLASS:{ *:[v16i1] } VK4:{ *:[v4i1] }:$src1, VK16:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v16i1] } VK4:{ *:[v4i1] }:$src2, VK16:{ *:[i32] })), VK1:{ *:[i32] }) 5122 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s1, 5123 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s1, 5124 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s1, 5125 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY, 5126 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, 5127 GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // src2 5128 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, 5129 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY, 5130 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 5131 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src1 5132 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 5133 GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::KORWrr, 5134 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 5135 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 5136 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0, 5137 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 5138 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 5139 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 5140 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 5141 GIR_EraseFromParent, /*InsnID*/0, 5142 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VK1*/8, 5143 // GIR_Coverage, 14596, 5144 GIR_Done, 5145 // Label 420: @10087 5146 GIM_Reject, 5147 // Label 353: @10088 5148 GIM_Try, /*On fail goto*//*Label 421*/ 10168, 5149 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 5150 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 5151 GIM_Try, /*On fail goto*//*Label 422*/ 10121, // Rule ID 5047 // 5152 GIM_CheckFeatures, GIFBS_HasAVX512_HasVLX, 5153 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 5154 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 5155 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128XRegClassID, 5156 // (or:{ *:[v4i32] } VR128X:{ *:[v4i32] }:$src1, VR128X:{ *:[v4i32] }:$src2) => (VPORDZ128rr:{ *:[v4i32] } VR128X:{ *:[v4i32] }:$src1, VR128X:{ *:[v4i32] }:$src2) 5157 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPORDZ128rr, 5158 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5159 // GIR_Coverage, 5047, 5160 GIR_Done, 5161 // Label 422: @10121 5162 GIM_Try, /*On fail goto*//*Label 423*/ 10144, // Rule ID 13468 // 5163 GIM_CheckFeatures, GIFBS_HasAVX_NoVLX, 5164 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 5165 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 5166 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 5167 // (or:{ *:[v4i32] } VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2) => (VPORrr:{ *:[v4i32] } VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2) 5168 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPORrr, 5169 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5170 // GIR_Coverage, 13468, 5171 GIR_Done, 5172 // Label 423: @10144 5173 GIM_Try, /*On fail goto*//*Label 424*/ 10167, // Rule ID 13492 // 5174 GIM_CheckFeatures, GIFBS_UseSSE2, 5175 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 5176 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 5177 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 5178 // (or:{ *:[v4i32] } VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2) => (PORrr:{ *:[v4i32] } VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2) 5179 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::PORrr, 5180 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5181 // GIR_Coverage, 13492, 5182 GIR_Done, 5183 // Label 424: @10167 5184 GIM_Reject, 5185 // Label 421: @10168 5186 GIM_Reject, 5187 // Label 354: @10169 5188 GIM_Try, /*On fail goto*//*Label 425*/ 10249, 5189 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s64, 5190 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s64, 5191 GIM_Try, /*On fail goto*//*Label 426*/ 10202, // Rule ID 1635 // 5192 GIM_CheckFeatures, GIFBS_HasAVX2_NoVLX, 5193 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID, 5194 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256RegClassID, 5195 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID, 5196 // (or:{ *:[v4i64] } VR256:{ *:[v4i64] }:$src1, VR256:{ *:[v4i64] }:$src2) => (VPORYrr:{ *:[v4i64] } VR256:{ *:[v4i64] }:$src1, VR256:{ *:[v4i64] }:$src2) 5197 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPORYrr, 5198 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5199 // GIR_Coverage, 1635, 5200 GIR_Done, 5201 // Label 426: @10202 5202 GIM_Try, /*On fail goto*//*Label 427*/ 10225, // Rule ID 5011 // 5203 GIM_CheckFeatures, GIFBS_HasAVX512_HasVLX, 5204 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 5205 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 5206 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256XRegClassID, 5207 // (or:{ *:[v4i64] } VR256X:{ *:[v4i64] }:$src1, VR256X:{ *:[v4i64] }:$src2) => (VPORQZ256rr:{ *:[v4i64] } VR256X:{ *:[v4i64] }:$src1, VR256X:{ *:[v4i64] }:$src2) 5208 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPORQZ256rr, 5209 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5210 // GIR_Coverage, 5011, 5211 GIR_Done, 5212 // Label 427: @10225 5213 GIM_Try, /*On fail goto*//*Label 428*/ 10248, // Rule ID 13438 // 5214 GIM_CheckFeatures, GIFBS_HasAVX1Only, 5215 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID, 5216 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256RegClassID, 5217 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID, 5218 // (or:{ *:[v4i64] } VR256:{ *:[v4i64] }:$src1, VR256:{ *:[v4i64] }:$src2) => (VORPSYrr:{ *:[v4i64] } VR256:{ *:[v4i64] }:$src1, VR256:{ *:[v4i64] }:$src2) 5219 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VORPSYrr, 5220 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5221 // GIR_Coverage, 13438, 5222 GIR_Done, 5223 // Label 428: @10248 5224 GIM_Reject, 5225 // Label 425: @10249 5226 GIM_Reject, 5227 // Label 355: @10250 5228 GIM_Try, /*On fail goto*//*Label 429*/ 10358, 5229 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s1, 5230 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s1, 5231 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VK8RegClassID, 5232 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VK8RegClassID, 5233 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VK8RegClassID, 5234 GIM_Try, /*On fail goto*//*Label 430*/ 10283, // Rule ID 3687 // 5235 GIM_CheckFeatures, GIFBS_HasDQI, 5236 // (or:{ *:[v8i1] } VK8:{ *:[v8i1] }:$src1, VK8:{ *:[v8i1] }:$src2) => (KORBrr:{ *:[v8i1] } VK8:{ *:[v8i1] }:$src1, VK8:{ *:[v8i1] }:$src2) 5237 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::KORBrr, 5238 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5239 // GIR_Coverage, 3687, 5240 GIR_Done, 5241 // Label 430: @10283 5242 GIM_Try, /*On fail goto*//*Label 431*/ 10357, // Rule ID 14593 // 5243 GIM_CheckFeatures, GIFBS_NoDQI, 5244 // (or:{ *:[v8i1] } VK8:{ *:[v8i1] }:$src1, VK8:{ *:[v8i1] }:$src2) => (COPY_TO_REGCLASS:{ *:[v8i1] } (KORWrr:{ *:[v16i1] } (COPY_TO_REGCLASS:{ *:[v16i1] } VK8:{ *:[v8i1] }:$src1, VK16:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v16i1] } VK8:{ *:[v8i1] }:$src2, VK16:{ *:[i32] })), VK8:{ *:[i32] }) 5245 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s1, 5246 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s1, 5247 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s1, 5248 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY, 5249 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, 5250 GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // src2 5251 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, 5252 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY, 5253 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 5254 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src1 5255 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 5256 GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::KORWrr, 5257 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 5258 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 5259 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0, 5260 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 5261 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 5262 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 5263 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 5264 GIR_EraseFromParent, /*InsnID*/0, 5265 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VK8*/12, 5266 // GIR_Coverage, 14593, 5267 GIR_Done, 5268 // Label 431: @10357 5269 GIM_Reject, 5270 // Label 429: @10358 5271 GIM_Reject, 5272 // Label 356: @10359 5273 GIM_Try, /*On fail goto*//*Label 432*/ 10439, 5274 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, 5275 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 5276 GIM_Try, /*On fail goto*//*Label 433*/ 10392, // Rule ID 13467 // 5277 GIM_CheckFeatures, GIFBS_HasAVX_NoVLX, 5278 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 5279 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 5280 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 5281 // (or:{ *:[v8i16] } VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2) => (VPORrr:{ *:[v8i16] } VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2) 5282 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPORrr, 5283 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5284 // GIR_Coverage, 13467, 5285 GIR_Done, 5286 // Label 433: @10392 5287 GIM_Try, /*On fail goto*//*Label 434*/ 10415, // Rule ID 13491 // 5288 GIM_CheckFeatures, GIFBS_UseSSE2, 5289 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 5290 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 5291 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 5292 // (or:{ *:[v8i16] } VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2) => (PORrr:{ *:[v8i16] } VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2) 5293 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::PORrr, 5294 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5295 // GIR_Coverage, 13491, 5296 GIR_Done, 5297 // Label 434: @10415 5298 GIM_Try, /*On fail goto*//*Label 435*/ 10438, // Rule ID 15058 // 5299 GIM_CheckFeatures, GIFBS_HasVLX, 5300 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 5301 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 5302 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128XRegClassID, 5303 // (or:{ *:[v8i16] } VR128X:{ *:[v8i16] }:$src1, VR128X:{ *:[v8i16] }:$src2) => (VPORQZ128rr:{ *:[v8i16] } VR128X:{ *:[v8i16] }:$src1, VR128X:{ *:[v8i16] }:$src2) 5304 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPORQZ128rr, 5305 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5306 // GIR_Coverage, 15058, 5307 GIR_Done, 5308 // Label 435: @10438 5309 GIM_Reject, 5310 // Label 432: @10439 5311 GIM_Reject, 5312 // Label 357: @10440 5313 GIM_Try, /*On fail goto*//*Label 436*/ 10520, 5314 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s32, 5315 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s32, 5316 GIM_Try, /*On fail goto*//*Label 437*/ 10473, // Rule ID 5038 // 5317 GIM_CheckFeatures, GIFBS_HasAVX512_HasVLX, 5318 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 5319 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 5320 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256XRegClassID, 5321 // (or:{ *:[v8i32] } VR256X:{ *:[v8i32] }:$src1, VR256X:{ *:[v8i32] }:$src2) => (VPORDZ256rr:{ *:[v8i32] } VR256X:{ *:[v8i32] }:$src1, VR256X:{ *:[v8i32] }:$src2) 5322 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPORDZ256rr, 5323 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5324 // GIR_Coverage, 5038, 5325 GIR_Done, 5326 // Label 437: @10473 5327 GIM_Try, /*On fail goto*//*Label 438*/ 10496, // Rule ID 13412 // 5328 GIM_CheckFeatures, GIFBS_HasAVX2_NoVLX, 5329 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID, 5330 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256RegClassID, 5331 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID, 5332 // (or:{ *:[v8i32] } VR256:{ *:[v8i32] }:$src1, VR256:{ *:[v8i32] }:$src2) => (VPORYrr:{ *:[v8i32] } VR256:{ *:[v8i32] }:$src1, VR256:{ *:[v8i32] }:$src2) 5333 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPORYrr, 5334 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5335 // GIR_Coverage, 13412, 5336 GIR_Done, 5337 // Label 438: @10496 5338 GIM_Try, /*On fail goto*//*Label 439*/ 10519, // Rule ID 13437 // 5339 GIM_CheckFeatures, GIFBS_HasAVX1Only, 5340 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID, 5341 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256RegClassID, 5342 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID, 5343 // (or:{ *:[v8i32] } VR256:{ *:[v8i32] }:$src1, VR256:{ *:[v8i32] }:$src2) => (VORPSYrr:{ *:[v8i32] } VR256:{ *:[v8i32] }:$src1, VR256:{ *:[v8i32] }:$src2) 5344 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VORPSYrr, 5345 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5346 // GIR_Coverage, 13437, 5347 GIR_Done, 5348 // Label 439: @10519 5349 GIM_Reject, 5350 // Label 436: @10520 5351 GIM_Reject, 5352 // Label 358: @10521 5353 GIM_Try, /*On fail goto*//*Label 440*/ 10552, // Rule ID 5002 // 5354 GIM_CheckFeatures, GIFBS_HasAVX512, 5355 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s64, 5356 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s64, 5357 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 5358 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID, 5359 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR512RegClassID, 5360 // (or:{ *:[v8i64] } VR512:{ *:[v8i64] }:$src1, VR512:{ *:[v8i64] }:$src2) => (VPORQZrr:{ *:[v8i64] } VR512:{ *:[v8i64] }:$src1, VR512:{ *:[v8i64] }:$src2) 5361 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPORQZrr, 5362 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5363 // GIR_Coverage, 5002, 5364 GIR_Done, 5365 // Label 440: @10552 5366 GIM_Reject, 5367 // Label 359: @10553 5368 GIM_Try, /*On fail goto*//*Label 441*/ 10584, // Rule ID 3688 // 5369 GIM_CheckFeatures, GIFBS_HasAVX512, 5370 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s1, 5371 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s1, 5372 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VK16RegClassID, 5373 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VK16RegClassID, 5374 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VK16RegClassID, 5375 // (or:{ *:[v16i1] } VK16:{ *:[v16i1] }:$src1, VK16:{ *:[v16i1] }:$src2) => (KORWrr:{ *:[v16i1] } VK16:{ *:[v16i1] }:$src1, VK16:{ *:[v16i1] }:$src2) 5376 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::KORWrr, 5377 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5378 // GIR_Coverage, 3688, 5379 GIR_Done, 5380 // Label 441: @10584 5381 GIM_Reject, 5382 // Label 360: @10585 5383 GIM_Try, /*On fail goto*//*Label 442*/ 10665, 5384 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, 5385 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 5386 GIM_Try, /*On fail goto*//*Label 443*/ 10618, // Rule ID 13466 // 5387 GIM_CheckFeatures, GIFBS_HasAVX_NoVLX, 5388 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 5389 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 5390 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 5391 // (or:{ *:[v16i8] } VR128:{ *:[v16i8] }:$src1, VR128:{ *:[v16i8] }:$src2) => (VPORrr:{ *:[v16i8] } VR128:{ *:[v16i8] }:$src1, VR128:{ *:[v16i8] }:$src2) 5392 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPORrr, 5393 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5394 // GIR_Coverage, 13466, 5395 GIR_Done, 5396 // Label 443: @10618 5397 GIM_Try, /*On fail goto*//*Label 444*/ 10641, // Rule ID 13490 // 5398 GIM_CheckFeatures, GIFBS_UseSSE2, 5399 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 5400 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 5401 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 5402 // (or:{ *:[v16i8] } VR128:{ *:[v16i8] }:$src1, VR128:{ *:[v16i8] }:$src2) => (PORrr:{ *:[v16i8] } VR128:{ *:[v16i8] }:$src1, VR128:{ *:[v16i8] }:$src2) 5403 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::PORrr, 5404 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5405 // GIR_Coverage, 13490, 5406 GIR_Done, 5407 // Label 444: @10641 5408 GIM_Try, /*On fail goto*//*Label 445*/ 10664, // Rule ID 15057 // 5409 GIM_CheckFeatures, GIFBS_HasVLX, 5410 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 5411 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 5412 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128XRegClassID, 5413 // (or:{ *:[v16i8] } VR128X:{ *:[v16i8] }:$src1, VR128X:{ *:[v16i8] }:$src2) => (VPORQZ128rr:{ *:[v16i8] } VR128X:{ *:[v16i8] }:$src1, VR128X:{ *:[v16i8] }:$src2) 5414 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPORQZ128rr, 5415 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5416 // GIR_Coverage, 15057, 5417 GIR_Done, 5418 // Label 445: @10664 5419 GIM_Reject, 5420 // Label 442: @10665 5421 GIM_Reject, 5422 // Label 361: @10666 5423 GIM_Try, /*On fail goto*//*Label 446*/ 10746, 5424 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s16, 5425 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s16, 5426 GIM_Try, /*On fail goto*//*Label 447*/ 10699, // Rule ID 13411 // 5427 GIM_CheckFeatures, GIFBS_HasAVX2_NoVLX, 5428 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID, 5429 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256RegClassID, 5430 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID, 5431 // (or:{ *:[v16i16] } VR256:{ *:[v16i16] }:$src1, VR256:{ *:[v16i16] }:$src2) => (VPORYrr:{ *:[v16i16] } VR256:{ *:[v16i16] }:$src1, VR256:{ *:[v16i16] }:$src2) 5432 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPORYrr, 5433 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5434 // GIR_Coverage, 13411, 5435 GIR_Done, 5436 // Label 447: @10699 5437 GIM_Try, /*On fail goto*//*Label 448*/ 10722, // Rule ID 13436 // 5438 GIM_CheckFeatures, GIFBS_HasAVX1Only, 5439 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID, 5440 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256RegClassID, 5441 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID, 5442 // (or:{ *:[v16i16] } VR256:{ *:[v16i16] }:$src1, VR256:{ *:[v16i16] }:$src2) => (VORPSYrr:{ *:[v16i16] } VR256:{ *:[v16i16] }:$src1, VR256:{ *:[v16i16] }:$src2) 5443 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VORPSYrr, 5444 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5445 // GIR_Coverage, 13436, 5446 GIR_Done, 5447 // Label 448: @10722 5448 GIM_Try, /*On fail goto*//*Label 449*/ 10745, // Rule ID 15074 // 5449 GIM_CheckFeatures, GIFBS_HasVLX, 5450 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 5451 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 5452 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256XRegClassID, 5453 // (or:{ *:[v16i16] } VR256X:{ *:[v16i16] }:$src1, VR256X:{ *:[v16i16] }:$src2) => (VPORQZ256rr:{ *:[v16i16] } VR256X:{ *:[v16i16] }:$src1, VR256X:{ *:[v16i16] }:$src2) 5454 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPORQZ256rr, 5455 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5456 // GIR_Coverage, 15074, 5457 GIR_Done, 5458 // Label 449: @10745 5459 GIM_Reject, 5460 // Label 446: @10746 5461 GIM_Reject, 5462 // Label 362: @10747 5463 GIM_Try, /*On fail goto*//*Label 450*/ 10778, // Rule ID 5029 // 5464 GIM_CheckFeatures, GIFBS_HasAVX512, 5465 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s32, 5466 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s32, 5467 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 5468 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID, 5469 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR512RegClassID, 5470 // (or:{ *:[v16i32] } VR512:{ *:[v16i32] }:$src1, VR512:{ *:[v16i32] }:$src2) => (VPORDZrr:{ *:[v16i32] } VR512:{ *:[v16i32] }:$src1, VR512:{ *:[v16i32] }:$src2) 5471 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPORDZrr, 5472 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5473 // GIR_Coverage, 5029, 5474 GIR_Done, 5475 // Label 450: @10778 5476 GIM_Reject, 5477 // Label 363: @10779 5478 GIM_Try, /*On fail goto*//*Label 451*/ 10810, // Rule ID 3689 // 5479 GIM_CheckFeatures, GIFBS_HasBWI, 5480 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v32s1, 5481 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v32s1, 5482 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VK32RegClassID, 5483 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VK32RegClassID, 5484 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VK32RegClassID, 5485 // (or:{ *:[v32i1] } VK32:{ *:[v32i1] }:$src1, VK32:{ *:[v32i1] }:$src2) => (KORDrr:{ *:[v32i1] } VK32:{ *:[v32i1] }:$src1, VK32:{ *:[v32i1] }:$src2) 5486 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::KORDrr, 5487 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5488 // GIR_Coverage, 3689, 5489 GIR_Done, 5490 // Label 451: @10810 5491 GIM_Reject, 5492 // Label 364: @10811 5493 GIM_Try, /*On fail goto*//*Label 452*/ 10891, 5494 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v32s8, 5495 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v32s8, 5496 GIM_Try, /*On fail goto*//*Label 453*/ 10844, // Rule ID 13410 // 5497 GIM_CheckFeatures, GIFBS_HasAVX2_NoVLX, 5498 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID, 5499 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256RegClassID, 5500 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID, 5501 // (or:{ *:[v32i8] } VR256:{ *:[v32i8] }:$src1, VR256:{ *:[v32i8] }:$src2) => (VPORYrr:{ *:[v32i8] } VR256:{ *:[v32i8] }:$src1, VR256:{ *:[v32i8] }:$src2) 5502 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPORYrr, 5503 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5504 // GIR_Coverage, 13410, 5505 GIR_Done, 5506 // Label 453: @10844 5507 GIM_Try, /*On fail goto*//*Label 454*/ 10867, // Rule ID 13435 // 5508 GIM_CheckFeatures, GIFBS_HasAVX1Only, 5509 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID, 5510 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256RegClassID, 5511 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID, 5512 // (or:{ *:[v32i8] } VR256:{ *:[v32i8] }:$src1, VR256:{ *:[v32i8] }:$src2) => (VORPSYrr:{ *:[v32i8] } VR256:{ *:[v32i8] }:$src1, VR256:{ *:[v32i8] }:$src2) 5513 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VORPSYrr, 5514 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5515 // GIR_Coverage, 13435, 5516 GIR_Done, 5517 // Label 454: @10867 5518 GIM_Try, /*On fail goto*//*Label 455*/ 10890, // Rule ID 15073 // 5519 GIM_CheckFeatures, GIFBS_HasVLX, 5520 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 5521 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 5522 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256XRegClassID, 5523 // (or:{ *:[v32i8] } VR256X:{ *:[v32i8] }:$src1, VR256X:{ *:[v32i8] }:$src2) => (VPORQZ256rr:{ *:[v32i8] } VR256X:{ *:[v32i8] }:$src1, VR256X:{ *:[v32i8] }:$src2) 5524 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPORQZ256rr, 5525 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5526 // GIR_Coverage, 15073, 5527 GIR_Done, 5528 // Label 455: @10890 5529 GIM_Reject, 5530 // Label 452: @10891 5531 GIM_Reject, 5532 // Label 365: @10892 5533 GIM_Try, /*On fail goto*//*Label 456*/ 10923, // Rule ID 15090 // 5534 GIM_CheckFeatures, GIFBS_HasAVX512, 5535 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v32s16, 5536 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v32s16, 5537 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 5538 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID, 5539 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR512RegClassID, 5540 // (or:{ *:[v32i16] } VR512:{ *:[v32i16] }:$src1, VR512:{ *:[v32i16] }:$src2) => (VPORQZrr:{ *:[v32i16] } VR512:{ *:[v32i16] }:$src1, VR512:{ *:[v32i16] }:$src2) 5541 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPORQZrr, 5542 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5543 // GIR_Coverage, 15090, 5544 GIR_Done, 5545 // Label 456: @10923 5546 GIM_Reject, 5547 // Label 366: @10924 5548 GIM_Try, /*On fail goto*//*Label 457*/ 10955, // Rule ID 3690 // 5549 GIM_CheckFeatures, GIFBS_HasBWI, 5550 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v64s1, 5551 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v64s1, 5552 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VK64RegClassID, 5553 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VK64RegClassID, 5554 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VK64RegClassID, 5555 // (or:{ *:[v64i1] } VK64:{ *:[v64i1] }:$src1, VK64:{ *:[v64i1] }:$src2) => (KORQrr:{ *:[v64i1] } VK64:{ *:[v64i1] }:$src1, VK64:{ *:[v64i1] }:$src2) 5556 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::KORQrr, 5557 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5558 // GIR_Coverage, 3690, 5559 GIR_Done, 5560 // Label 457: @10955 5561 GIM_Reject, 5562 // Label 367: @10956 5563 GIM_Try, /*On fail goto*//*Label 458*/ 10987, // Rule ID 15089 // 5564 GIM_CheckFeatures, GIFBS_HasAVX512, 5565 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v64s8, 5566 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v64s8, 5567 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 5568 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID, 5569 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR512RegClassID, 5570 // (or:{ *:[v64i8] } VR512:{ *:[v64i8] }:$src1, VR512:{ *:[v64i8] }:$src2) => (VPORQZrr:{ *:[v64i8] } VR512:{ *:[v64i8] }:$src1, VR512:{ *:[v64i8] }:$src2) 5571 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPORQZrr, 5572 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5573 // GIR_Coverage, 15089, 5574 GIR_Done, 5575 // Label 458: @10987 5576 GIM_Reject, 5577 // Label 368: @10988 5578 GIM_Reject, 5579 // Label 5: @10989 5580 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 25, /*)*//*default:*//*Label 482*/ 14164, 5581 /*GILLT_s1*//*Label 459*/ 11020, 5582 /*GILLT_s8*//*Label 460*/ 11419, 5583 /*GILLT_s16*//*Label 461*/ 11507, 5584 /*GILLT_s32*//*Label 462*/ 11832, 5585 /*GILLT_s64*//*Label 463*/ 12413, 0, 0, 5586 /*GILLT_v2s1*//*Label 464*/ 12997, 5587 /*GILLT_v2s64*//*Label 465*/ 13090, 5588 /*GILLT_v4s1*//*Label 466*/ 13171, 5589 /*GILLT_v4s32*//*Label 467*/ 13264, 5590 /*GILLT_v4s64*//*Label 468*/ 13345, 5591 /*GILLT_v8s1*//*Label 469*/ 13426, 5592 /*GILLT_v8s16*//*Label 470*/ 13535, 5593 /*GILLT_v8s32*//*Label 471*/ 13616, 5594 /*GILLT_v8s64*//*Label 472*/ 13697, 5595 /*GILLT_v16s1*//*Label 473*/ 13729, 5596 /*GILLT_v16s8*//*Label 474*/ 13761, 5597 /*GILLT_v16s16*//*Label 475*/ 13842, 5598 /*GILLT_v16s32*//*Label 476*/ 13923, 5599 /*GILLT_v32s1*//*Label 477*/ 13955, 5600 /*GILLT_v32s8*//*Label 478*/ 13987, 5601 /*GILLT_v32s16*//*Label 479*/ 14068, 5602 /*GILLT_v64s1*//*Label 480*/ 14100, 5603 /*GILLT_v64s8*//*Label 481*/ 14132, 5604 // Label 459: @11020 5605 GIM_Try, /*On fail goto*//*Label 483*/ 11418, 5606 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s1, 5607 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s1, 5608 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VK1RegClassID, 5609 GIM_Try, /*On fail goto*//*Label 484*/ 11135, // Rule ID 19455 // 5610 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 5611 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, 5612 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s1, 5613 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s1, 5614 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::VK1RegClassID, 5615 GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, 5616 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VK1RegClassID, 5617 GIM_CheckIsSafeToFold, /*InsnID*/1, 5618 // (xor:{ *:[v1i1] } (xor:{ *:[v1i1] } VK1:{ *:[v1i1] }:$src1, -1:{ *:[v1i1] }), VK1:{ *:[v1i1] }:$src2) => (COPY_TO_REGCLASS:{ *:[v1i1] } (KXNORWrr:{ *:[v16i1] } (COPY_TO_REGCLASS:{ *:[v16i1] } VK1:{ *:[v1i1] }:$src1, VK16:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v16i1] } VK1:{ *:[v1i1] }:$src2, VK16:{ *:[i32] })), VK1:{ *:[i32] }) 5619 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s1, 5620 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s1, 5621 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s1, 5622 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY, 5623 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, 5624 GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // src2 5625 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, 5626 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY, 5627 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 5628 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // src1 5629 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 5630 GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::KXNORWrr, 5631 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 5632 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 5633 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0, 5634 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 5635 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 5636 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 5637 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 5638 GIR_EraseFromParent, /*InsnID*/0, 5639 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VK1*/8, 5640 // GIR_Coverage, 19455, 5641 GIR_Done, 5642 // Label 484: @11135 5643 GIM_Try, /*On fail goto*//*Label 485*/ 11236, // Rule ID 14598 // 5644 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 5645 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, 5646 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s1, 5647 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s1, 5648 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::VK1RegClassID, 5649 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/X86::VK1RegClassID, 5650 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1, 5651 GIM_CheckIsSafeToFold, /*InsnID*/1, 5652 // (xor:{ *:[v1i1] } (xor:{ *:[v1i1] } VK1:{ *:[v1i1] }:$src1, VK1:{ *:[v1i1] }:$src2), -1:{ *:[v1i1] }) => (COPY_TO_REGCLASS:{ *:[v1i1] } (KXNORWrr:{ *:[v16i1] } (COPY_TO_REGCLASS:{ *:[v16i1] } VK1:{ *:[v1i1] }:$src1, VK16:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v16i1] } VK1:{ *:[v1i1] }:$src2, VK16:{ *:[i32] })), VK1:{ *:[i32] }) 5653 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s1, 5654 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s1, 5655 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s1, 5656 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY, 5657 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, 5658 GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/1, /*OpIdx*/2, // src2 5659 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, 5660 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY, 5661 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 5662 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // src1 5663 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 5664 GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::KXNORWrr, 5665 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 5666 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 5667 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0, 5668 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 5669 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 5670 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 5671 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 5672 GIR_EraseFromParent, /*InsnID*/0, 5673 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VK1*/8, 5674 // GIR_Coverage, 14598, 5675 GIR_Done, 5676 // Label 485: @11236 5677 GIM_Try, /*On fail goto*//*Label 486*/ 11337, // Rule ID 19456 // 5678 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VK1RegClassID, 5679 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 5680 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR, 5681 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s1, 5682 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s1, 5683 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::VK1RegClassID, 5684 GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, 5685 GIM_CheckIsSafeToFold, /*InsnID*/1, 5686 // (xor:{ *:[v1i1] } VK1:{ *:[v1i1] }:$src2, (xor:{ *:[v1i1] } VK1:{ *:[v1i1] }:$src1, -1:{ *:[v1i1] })) => (COPY_TO_REGCLASS:{ *:[v1i1] } (KXNORWrr:{ *:[v16i1] } (COPY_TO_REGCLASS:{ *:[v16i1] } VK1:{ *:[v1i1] }:$src1, VK16:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v16i1] } VK1:{ *:[v1i1] }:$src2, VK16:{ *:[i32] })), VK1:{ *:[i32] }) 5687 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s1, 5688 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s1, 5689 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s1, 5690 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY, 5691 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, 5692 GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // src2 5693 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, 5694 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY, 5695 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 5696 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // src1 5697 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 5698 GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::KXNORWrr, 5699 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 5700 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 5701 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0, 5702 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 5703 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 5704 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 5705 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 5706 GIR_EraseFromParent, /*InsnID*/0, 5707 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VK1*/8, 5708 // GIR_Coverage, 19456, 5709 GIR_Done, 5710 // Label 486: @11337 5711 GIM_Try, /*On fail goto*//*Label 487*/ 11417, // Rule ID 14602 // 5712 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VK1RegClassID, 5713 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VK1RegClassID, 5714 // (xor:{ *:[v1i1] } VK1:{ *:[v1i1] }:$src1, VK1:{ *:[v1i1] }:$src2) => (COPY_TO_REGCLASS:{ *:[v1i1] } (KXORWrr:{ *:[v16i1] } (COPY_TO_REGCLASS:{ *:[v16i1] } VK1:{ *:[v1i1] }:$src1, VK16:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v16i1] } VK1:{ *:[v1i1] }:$src2, VK16:{ *:[i32] })), VK1:{ *:[i32] }) 5715 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s1, 5716 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s1, 5717 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s1, 5718 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY, 5719 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, 5720 GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // src2 5721 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, 5722 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY, 5723 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 5724 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src1 5725 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 5726 GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::KXORWrr, 5727 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 5728 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 5729 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0, 5730 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 5731 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 5732 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 5733 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 5734 GIR_EraseFromParent, /*InsnID*/0, 5735 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VK1*/8, 5736 // GIR_Coverage, 14602, 5737 GIR_Done, 5738 // Label 487: @11417 5739 GIM_Reject, 5740 // Label 483: @11418 5741 GIM_Reject, 5742 // Label 460: @11419 5743 GIM_Try, /*On fail goto*//*Label 488*/ 11506, 5744 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s8, 5745 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s8, 5746 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR8RegClassID, 5747 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR8RegClassID, 5748 GIM_Try, /*On fail goto*//*Label 489*/ 11459, // Rule ID 156 // 5749 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1, 5750 // (xor:{ *:[i8] } GR8:{ *:[i8] }:$src1, -1:{ *:[i8] }) => (NOT8r:{ *:[i8] } GR8:{ *:[i8] }:$src1) 5751 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::NOT8r, 5752 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 5753 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 5754 GIR_EraseFromParent, /*InsnID*/0, 5755 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5756 // GIR_Coverage, 156, 5757 GIR_Done, 5758 // Label 489: @11459 5759 GIM_Try, /*On fail goto*//*Label 490*/ 11489, // Rule ID 17374 // 5760 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 5761 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 5762 // MIs[1] Operand 1 5763 // No operand predicates 5764 GIM_CheckIsSafeToFold, /*InsnID*/1, 5765 // (xor:{ *:[i8] } GR8:{ *:[i8] }:$src1, (imm:{ *:[i8] }):$src2) => (XOR8ri:{ *:[i8] }:{ *:[i32] } GR8:{ *:[i8] }:$src1, (imm:{ *:[i8] }):$src2) 5766 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::XOR8ri, 5767 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 5768 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 5769 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2 5770 GIR_EraseFromParent, /*InsnID*/0, 5771 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5772 // GIR_Coverage, 17374, 5773 GIR_Done, 5774 // Label 490: @11489 5775 GIM_Try, /*On fail goto*//*Label 491*/ 11505, // Rule ID 17366 // 5776 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR8RegClassID, 5777 // (xor:{ *:[i8] } GR8:{ *:[i8] }:$src1, GR8:{ *:[i8] }:$src2) => (XOR8rr:{ *:[i8] }:{ *:[i32] } GR8:{ *:[i8] }:$src1, GR8:{ *:[i8] }:$src2) 5778 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::XOR8rr, 5779 GIR_AddImplicitDef, /*InsnID*/0, X86::EFLAGS, 5780 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5781 // GIR_Coverage, 17366, 5782 GIR_Done, 5783 // Label 491: @11505 5784 GIM_Reject, 5785 // Label 488: @11506 5786 GIM_Reject, 5787 // Label 461: @11507 5788 GIM_Try, /*On fail goto*//*Label 492*/ 11831, 5789 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, 5790 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16, 5791 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR16RegClassID, 5792 GIM_Try, /*On fail goto*//*Label 493*/ 11617, // Rule ID 20034 // 5793 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 5794 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SHL, 5795 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, 5796 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s8, 5797 GIM_CheckConstantInt, /*MI*/1, /*Op*/1, 1, 5798 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/X86::GR8RegClassID, 5799 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR16RegClassID, 5800 GIM_CheckIsSafeToFold, /*InsnID*/1, 5801 // (xor:{ *:[i16] } (shl:{ *:[i16] } 1:{ *:[i16] }, GR8:{ *:[i8] }:$src2), GR16:{ *:[i16] }:$src1) => (BTC16rr:{ *:[i16] }:{ *:[i32] } GR16:{ *:[i16] }:$src1, (INSERT_SUBREG:{ *:[i16] } (IMPLICIT_DEF:{ *:[i16] }), GR8:{ *:[i8] }:$src2, sub_8bit:{ *:[i32] })) 5802 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, 5803 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16, 5804 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, 5805 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 5806 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 5807 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, 5808 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 5809 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 5810 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // src2 5811 GIR_AddImm, /*InsnID*/1, /*Imm*/1, 5812 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, /*RC GR16*/6, 5813 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, /*RC GR16*/6, 5814 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, /*RC GR8*/0, 5815 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BTC16rr, 5816 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 5817 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 5818 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 5819 GIR_EraseFromParent, /*InsnID*/0, 5820 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5821 // GIR_Coverage, 20034, 5822 GIR_Done, 5823 // Label 493: @11617 5824 GIM_Try, /*On fail goto*//*Label 494*/ 11713, // Rule ID 17263 // 5825 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR16RegClassID, 5826 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 5827 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SHL, 5828 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, 5829 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s8, 5830 GIM_CheckConstantInt, /*MI*/1, /*Op*/1, 1, 5831 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/X86::GR8RegClassID, 5832 GIM_CheckIsSafeToFold, /*InsnID*/1, 5833 // (xor:{ *:[i16] } GR16:{ *:[i16] }:$src1, (shl:{ *:[i16] } 1:{ *:[i16] }, GR8:{ *:[i8] }:$src2)) => (BTC16rr:{ *:[i16] }:{ *:[i32] } GR16:{ *:[i16] }:$src1, (INSERT_SUBREG:{ *:[i16] } (IMPLICIT_DEF:{ *:[i16] }), GR8:{ *:[i8] }:$src2, sub_8bit:{ *:[i32] })) 5834 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, 5835 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16, 5836 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, 5837 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 5838 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 5839 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, 5840 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 5841 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 5842 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // src2 5843 GIR_AddImm, /*InsnID*/1, /*Imm*/1, 5844 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, /*RC GR16*/6, 5845 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, /*RC GR16*/6, 5846 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, /*RC GR8*/0, 5847 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BTC16rr, 5848 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 5849 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 5850 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 5851 GIR_EraseFromParent, /*InsnID*/0, 5852 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5853 // GIR_Coverage, 17263, 5854 GIR_Done, 5855 // Label 494: @11713 5856 GIM_Try, /*On fail goto*//*Label 495*/ 11739, // Rule ID 157 // 5857 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR16RegClassID, 5858 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1, 5859 // (xor:{ *:[i16] } GR16:{ *:[i16] }:$src1, -1:{ *:[i16] }) => (NOT16r:{ *:[i16] } GR16:{ *:[i16] }:$src1) 5860 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::NOT16r, 5861 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 5862 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 5863 GIR_EraseFromParent, /*InsnID*/0, 5864 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5865 // GIR_Coverage, 157, 5866 GIR_Done, 5867 // Label 495: @11739 5868 GIM_Try, /*On fail goto*//*Label 496*/ 11776, // Rule ID 17377 // 5869 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR16RegClassID, 5870 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 5871 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 5872 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_i16immSExt8, 5873 // MIs[1] Operand 1 5874 // No operand predicates 5875 GIM_CheckIsSafeToFold, /*InsnID*/1, 5876 // (xor:{ *:[i16] } GR16:{ *:[i16] }:$src1, (imm:{ *:[i16] })<<P:Predicate_i16immSExt8>>:$src2) => (XOR16ri8:{ *:[i16] }:{ *:[i32] } GR16:{ *:[i16] }:$src1, (imm:{ *:[i16] })<<P:Predicate_i16immSExt8>>:$src2) 5877 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::XOR16ri8, 5878 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 5879 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 5880 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2 5881 GIR_EraseFromParent, /*InsnID*/0, 5882 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5883 // GIR_Coverage, 17377, 5884 GIR_Done, 5885 // Label 496: @11776 5886 GIM_Try, /*On fail goto*//*Label 497*/ 11810, // Rule ID 17375 // 5887 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR16RegClassID, 5888 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 5889 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 5890 // MIs[1] Operand 1 5891 // No operand predicates 5892 GIM_CheckIsSafeToFold, /*InsnID*/1, 5893 // (xor:{ *:[i16] } GR16:{ *:[i16] }:$src1, (imm:{ *:[i16] }):$src2) => (XOR16ri:{ *:[i16] }:{ *:[i32] } GR16:{ *:[i16] }:$src1, (imm:{ *:[i16] }):$src2) 5894 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::XOR16ri, 5895 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 5896 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 5897 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2 5898 GIR_EraseFromParent, /*InsnID*/0, 5899 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5900 // GIR_Coverage, 17375, 5901 GIR_Done, 5902 // Label 497: @11810 5903 GIM_Try, /*On fail goto*//*Label 498*/ 11830, // Rule ID 17367 // 5904 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR16RegClassID, 5905 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR16RegClassID, 5906 // (xor:{ *:[i16] } GR16:{ *:[i16] }:$src1, GR16:{ *:[i16] }:$src2) => (XOR16rr:{ *:[i16] }:{ *:[i32] } GR16:{ *:[i16] }:$src1, GR16:{ *:[i16] }:$src2) 5907 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::XOR16rr, 5908 GIR_AddImplicitDef, /*InsnID*/0, X86::EFLAGS, 5909 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5910 // GIR_Coverage, 17367, 5911 GIR_Done, 5912 // Label 498: @11830 5913 GIM_Reject, 5914 // Label 492: @11831 5915 GIM_Reject, 5916 // Label 462: @11832 5917 GIM_Try, /*On fail goto*//*Label 499*/ 12412, 5918 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 5919 GIM_Try, /*On fail goto*//*Label 500*/ 11892, // Rule ID 19172 // 5920 GIM_CheckFeatures, GIFBS_HasBMI, 5921 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 5922 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 5923 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD, 5924 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, 5925 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, 5926 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::GR32RegClassID, 5927 GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, 5928 // MIs[0] src 5929 GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, 5930 GIM_CheckIsSafeToFold, /*InsnID*/1, 5931 // (xor:{ *:[i32] } (add:{ *:[i32] } GR32:{ *:[i32] }:$src, -1:{ *:[i32] }), GR32:{ *:[i32] }:$src) => (BLSMSK32rr:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src) 5932 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLSMSK32rr, 5933 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 5934 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src 5935 GIR_EraseFromParent, /*InsnID*/0, 5936 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5937 // GIR_Coverage, 19172, 5938 GIR_Done, 5939 // Label 500: @11892 5940 GIM_Try, /*On fail goto*//*Label 501*/ 11946, // Rule ID 19190 // 5941 GIM_CheckFeatures, GIFBS_HasTBM, 5942 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 5943 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 5944 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD, 5945 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, 5946 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, 5947 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::GR32RegClassID, 5948 GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 1, 5949 // MIs[0] src 5950 GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, 5951 GIM_CheckIsSafeToFold, /*InsnID*/1, 5952 // (xor:{ *:[i32] } (add:{ *:[i32] } GR32:{ *:[i32] }:$src, 1:{ *:[i32] }), GR32:{ *:[i32] }:$src) => (BLCMSK32rr:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src) 5953 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLCMSK32rr, 5954 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 5955 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src 5956 GIR_EraseFromParent, /*InsnID*/0, 5957 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5958 // GIR_Coverage, 19190, 5959 GIR_Done, 5960 // Label 501: @11946 5961 GIM_Try, /*On fail goto*//*Label 502*/ 12050, // Rule ID 20040 // 5962 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 5963 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 5964 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 5965 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SHL, 5966 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, 5967 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s8, 5968 GIM_CheckConstantInt, /*MI*/1, /*Op*/1, 1, 5969 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/X86::GR8RegClassID, 5970 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR32RegClassID, 5971 GIM_CheckIsSafeToFold, /*InsnID*/1, 5972 // (xor:{ *:[i32] } (shl:{ *:[i32] } 1:{ *:[i32] }, GR8:{ *:[i8] }:$src2), GR32:{ *:[i32] }:$src1) => (BTC32rr:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src1, (INSERT_SUBREG:{ *:[i32] } (IMPLICIT_DEF:{ *:[i32] }), GR8:{ *:[i8] }:$src2, sub_8bit:{ *:[i32] })) 5973 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, 5974 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, 5975 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, 5976 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 5977 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 5978 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, 5979 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 5980 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 5981 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // src2 5982 GIR_AddImm, /*InsnID*/1, /*Imm*/1, 5983 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, /*RC LOW32_ADDR_ACCESS_RBP_with_sub_8bit*/30, 5984 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, /*RC LOW32_ADDR_ACCESS_RBP_with_sub_8bit*/30, 5985 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, /*RC GR8*/0, 5986 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BTC32rr, 5987 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 5988 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 5989 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 5990 GIR_EraseFromParent, /*InsnID*/0, 5991 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5992 // GIR_Coverage, 20040, 5993 GIR_Done, 5994 // Label 502: @12050 5995 GIM_Try, /*On fail goto*//*Label 503*/ 12104, // Rule ID 12987 // 5996 GIM_CheckFeatures, GIFBS_HasBMI, 5997 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 5998 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 5999 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR32RegClassID, 6000 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 6001 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD, 6002 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, 6003 // MIs[1] src 6004 GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/1, /*OtherMI*/0, /*OtherOpIdx*/1, 6005 GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, 6006 GIM_CheckIsSafeToFold, /*InsnID*/1, 6007 // (xor:{ *:[i32] } GR32:{ *:[i32] }:$src, (add:{ *:[i32] } GR32:{ *:[i32] }:$src, -1:{ *:[i32] })) => (BLSMSK32rr:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src) 6008 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLSMSK32rr, 6009 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 6010 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 6011 GIR_EraseFromParent, /*InsnID*/0, 6012 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6013 // GIR_Coverage, 12987, 6014 GIR_Done, 6015 // Label 503: @12104 6016 GIM_Try, /*On fail goto*//*Label 504*/ 12158, // Rule ID 13011 // 6017 GIM_CheckFeatures, GIFBS_HasTBM, 6018 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 6019 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 6020 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR32RegClassID, 6021 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 6022 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD, 6023 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, 6024 // MIs[1] src 6025 GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/1, /*OtherMI*/0, /*OtherOpIdx*/1, 6026 GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 1, 6027 GIM_CheckIsSafeToFold, /*InsnID*/1, 6028 // (xor:{ *:[i32] } GR32:{ *:[i32] }:$src, (add:{ *:[i32] } GR32:{ *:[i32] }:$src, 1:{ *:[i32] })) => (BLCMSK32rr:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src) 6029 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLCMSK32rr, 6030 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 6031 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 6032 GIR_EraseFromParent, /*InsnID*/0, 6033 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6034 // GIR_Coverage, 13011, 6035 GIR_Done, 6036 // Label 504: @12158 6037 GIM_Try, /*On fail goto*//*Label 505*/ 12262, // Rule ID 17269 // 6038 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 6039 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 6040 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR32RegClassID, 6041 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 6042 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SHL, 6043 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, 6044 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s8, 6045 GIM_CheckConstantInt, /*MI*/1, /*Op*/1, 1, 6046 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/X86::GR8RegClassID, 6047 GIM_CheckIsSafeToFold, /*InsnID*/1, 6048 // (xor:{ *:[i32] } GR32:{ *:[i32] }:$src1, (shl:{ *:[i32] } 1:{ *:[i32] }, GR8:{ *:[i8] }:$src2)) => (BTC32rr:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src1, (INSERT_SUBREG:{ *:[i32] } (IMPLICIT_DEF:{ *:[i32] }), GR8:{ *:[i8] }:$src2, sub_8bit:{ *:[i32] })) 6049 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, 6050 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, 6051 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, 6052 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 6053 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 6054 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, 6055 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 6056 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 6057 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // src2 6058 GIR_AddImm, /*InsnID*/1, /*Imm*/1, 6059 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, /*RC LOW32_ADDR_ACCESS_RBP_with_sub_8bit*/30, 6060 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, /*RC LOW32_ADDR_ACCESS_RBP_with_sub_8bit*/30, 6061 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, /*RC GR8*/0, 6062 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BTC32rr, 6063 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 6064 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 6065 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 6066 GIR_EraseFromParent, /*InsnID*/0, 6067 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6068 // GIR_Coverage, 17269, 6069 GIR_Done, 6070 // Label 505: @12262 6071 GIM_Try, /*On fail goto*//*Label 506*/ 12296, // Rule ID 158 // 6072 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 6073 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 6074 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR32RegClassID, 6075 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1, 6076 // (xor:{ *:[i32] } GR32:{ *:[i32] }:$src1, -1:{ *:[i32] }) => (NOT32r:{ *:[i32] } GR32:{ *:[i32] }:$src1) 6077 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::NOT32r, 6078 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 6079 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 6080 GIR_EraseFromParent, /*InsnID*/0, 6081 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6082 // GIR_Coverage, 158, 6083 GIR_Done, 6084 // Label 506: @12296 6085 GIM_Try, /*On fail goto*//*Label 507*/ 12341, // Rule ID 17378 // 6086 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 6087 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 6088 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR32RegClassID, 6089 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 6090 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 6091 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_i32immSExt8, 6092 // MIs[1] Operand 1 6093 // No operand predicates 6094 GIM_CheckIsSafeToFold, /*InsnID*/1, 6095 // (xor:{ *:[i32] } GR32:{ *:[i32] }:$src1, (imm:{ *:[i32] })<<P:Predicate_i32immSExt8>>:$src2) => (XOR32ri8:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src1, (imm:{ *:[i32] })<<P:Predicate_i32immSExt8>>:$src2) 6096 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::XOR32ri8, 6097 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 6098 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 6099 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2 6100 GIR_EraseFromParent, /*InsnID*/0, 6101 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6102 // GIR_Coverage, 17378, 6103 GIR_Done, 6104 // Label 507: @12341 6105 GIM_Try, /*On fail goto*//*Label 508*/ 12383, // Rule ID 17376 // 6106 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 6107 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 6108 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR32RegClassID, 6109 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 6110 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 6111 // MIs[1] Operand 1 6112 // No operand predicates 6113 GIM_CheckIsSafeToFold, /*InsnID*/1, 6114 // (xor:{ *:[i32] } GR32:{ *:[i32] }:$src1, (imm:{ *:[i32] }):$src2) => (XOR32ri:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src1, (imm:{ *:[i32] }):$src2) 6115 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::XOR32ri, 6116 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 6117 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 6118 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2 6119 GIR_EraseFromParent, /*InsnID*/0, 6120 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6121 // GIR_Coverage, 17376, 6122 GIR_Done, 6123 // Label 508: @12383 6124 GIM_Try, /*On fail goto*//*Label 509*/ 12411, // Rule ID 17368 // 6125 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 6126 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 6127 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR32RegClassID, 6128 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR32RegClassID, 6129 // (xor:{ *:[i32] } GR32:{ *:[i32] }:$src1, GR32:{ *:[i32] }:$src2) => (XOR32rr:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src1, GR32:{ *:[i32] }:$src2) 6130 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::XOR32rr, 6131 GIR_AddImplicitDef, /*InsnID*/0, X86::EFLAGS, 6132 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6133 // GIR_Coverage, 17368, 6134 GIR_Done, 6135 // Label 509: @12411 6136 GIM_Reject, 6137 // Label 499: @12412 6138 GIM_Reject, 6139 // Label 463: @12413 6140 GIM_Try, /*On fail goto*//*Label 510*/ 12996, 6141 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 6142 GIM_Try, /*On fail goto*//*Label 511*/ 12473, // Rule ID 19173 // 6143 GIM_CheckFeatures, GIFBS_HasBMI, 6144 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID, 6145 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 6146 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD, 6147 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, 6148 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, 6149 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::GR64RegClassID, 6150 GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, 6151 // MIs[0] src 6152 GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, 6153 GIM_CheckIsSafeToFold, /*InsnID*/1, 6154 // (xor:{ *:[i64] } (add:{ *:[i64] } GR64:{ *:[i64] }:$src, -1:{ *:[i64] }), GR64:{ *:[i64] }:$src) => (BLSMSK64rr:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src) 6155 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLSMSK64rr, 6156 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 6157 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src 6158 GIR_EraseFromParent, /*InsnID*/0, 6159 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6160 // GIR_Coverage, 19173, 6161 GIR_Done, 6162 // Label 511: @12473 6163 GIM_Try, /*On fail goto*//*Label 512*/ 12527, // Rule ID 19191 // 6164 GIM_CheckFeatures, GIFBS_HasTBM, 6165 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID, 6166 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 6167 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD, 6168 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, 6169 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, 6170 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::GR64RegClassID, 6171 GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 1, 6172 // MIs[0] src 6173 GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, 6174 GIM_CheckIsSafeToFold, /*InsnID*/1, 6175 // (xor:{ *:[i64] } (add:{ *:[i64] } GR64:{ *:[i64] }:$src, 1:{ *:[i64] }), GR64:{ *:[i64] }:$src) => (BLCMSK64rr:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src) 6176 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLCMSK64rr, 6177 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 6178 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src 6179 GIR_EraseFromParent, /*InsnID*/0, 6180 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6181 // GIR_Coverage, 19191, 6182 GIR_Done, 6183 // Label 512: @12527 6184 GIM_Try, /*On fail goto*//*Label 513*/ 12631, // Rule ID 20046 // 6185 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 6186 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID, 6187 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 6188 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SHL, 6189 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, 6190 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s8, 6191 GIM_CheckConstantInt, /*MI*/1, /*Op*/1, 1, 6192 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/X86::GR8RegClassID, 6193 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR64RegClassID, 6194 GIM_CheckIsSafeToFold, /*InsnID*/1, 6195 // (xor:{ *:[i64] } (shl:{ *:[i64] } 1:{ *:[i64] }, GR8:{ *:[i8] }:$src2), GR64:{ *:[i64] }:$src1) => (BTC64rr:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src1, (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), GR8:{ *:[i8] }:$src2, sub_8bit:{ *:[i32] })) 6196 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, 6197 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, 6198 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, 6199 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 6200 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 6201 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, 6202 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 6203 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 6204 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // src2 6205 GIR_AddImm, /*InsnID*/1, /*Imm*/1, 6206 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, /*RC GR64_with_sub_8bit*/68, 6207 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, /*RC GR64_with_sub_8bit*/68, 6208 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, /*RC GR8*/0, 6209 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BTC64rr, 6210 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 6211 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 6212 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 6213 GIR_EraseFromParent, /*InsnID*/0, 6214 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6215 // GIR_Coverage, 20046, 6216 GIR_Done, 6217 // Label 513: @12631 6218 GIM_Try, /*On fail goto*//*Label 514*/ 12685, // Rule ID 12988 // 6219 GIM_CheckFeatures, GIFBS_HasBMI, 6220 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 6221 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID, 6222 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR64RegClassID, 6223 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 6224 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD, 6225 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, 6226 // MIs[1] src 6227 GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/1, /*OtherMI*/0, /*OtherOpIdx*/1, 6228 GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1, 6229 GIM_CheckIsSafeToFold, /*InsnID*/1, 6230 // (xor:{ *:[i64] } GR64:{ *:[i64] }:$src, (add:{ *:[i64] } GR64:{ *:[i64] }:$src, -1:{ *:[i64] })) => (BLSMSK64rr:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src) 6231 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLSMSK64rr, 6232 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 6233 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 6234 GIR_EraseFromParent, /*InsnID*/0, 6235 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6236 // GIR_Coverage, 12988, 6237 GIR_Done, 6238 // Label 514: @12685 6239 GIM_Try, /*On fail goto*//*Label 515*/ 12739, // Rule ID 13012 // 6240 GIM_CheckFeatures, GIFBS_HasTBM, 6241 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 6242 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID, 6243 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR64RegClassID, 6244 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 6245 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD, 6246 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, 6247 // MIs[1] src 6248 GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/1, /*OtherMI*/0, /*OtherOpIdx*/1, 6249 GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 1, 6250 GIM_CheckIsSafeToFold, /*InsnID*/1, 6251 // (xor:{ *:[i64] } GR64:{ *:[i64] }:$src, (add:{ *:[i64] } GR64:{ *:[i64] }:$src, 1:{ *:[i64] })) => (BLCMSK64rr:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src) 6252 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BLCMSK64rr, 6253 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 6254 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 6255 GIR_EraseFromParent, /*InsnID*/0, 6256 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6257 // GIR_Coverage, 13012, 6258 GIR_Done, 6259 // Label 515: @12739 6260 GIM_Try, /*On fail goto*//*Label 516*/ 12843, // Rule ID 17275 // 6261 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 6262 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID, 6263 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR64RegClassID, 6264 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 6265 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SHL, 6266 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, 6267 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s8, 6268 GIM_CheckConstantInt, /*MI*/1, /*Op*/1, 1, 6269 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/X86::GR8RegClassID, 6270 GIM_CheckIsSafeToFold, /*InsnID*/1, 6271 // (xor:{ *:[i64] } GR64:{ *:[i64] }:$src1, (shl:{ *:[i64] } 1:{ *:[i64] }, GR8:{ *:[i8] }:$src2)) => (BTC64rr:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src1, (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), GR8:{ *:[i8] }:$src2, sub_8bit:{ *:[i32] })) 6272 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, 6273 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, 6274 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, 6275 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 6276 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 6277 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, 6278 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 6279 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 6280 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // src2 6281 GIR_AddImm, /*InsnID*/1, /*Imm*/1, 6282 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, /*RC GR64_with_sub_8bit*/68, 6283 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, /*RC GR64_with_sub_8bit*/68, 6284 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, /*RC GR8*/0, 6285 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::BTC64rr, 6286 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 6287 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 6288 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 6289 GIR_EraseFromParent, /*InsnID*/0, 6290 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6291 // GIR_Coverage, 17275, 6292 GIR_Done, 6293 // Label 516: @12843 6294 GIM_Try, /*On fail goto*//*Label 517*/ 12877, // Rule ID 159 // 6295 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 6296 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID, 6297 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR64RegClassID, 6298 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1, 6299 // (xor:{ *:[i64] } GR64:{ *:[i64] }:$src1, -1:{ *:[i64] }) => (NOT64r:{ *:[i64] } GR64:{ *:[i64] }:$src1) 6300 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::NOT64r, 6301 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 6302 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 6303 GIR_EraseFromParent, /*InsnID*/0, 6304 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6305 // GIR_Coverage, 159, 6306 GIR_Done, 6307 // Label 517: @12877 6308 GIM_Try, /*On fail goto*//*Label 518*/ 12922, // Rule ID 17379 // 6309 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 6310 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID, 6311 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR64RegClassID, 6312 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 6313 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 6314 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_i64immSExt8, 6315 // MIs[1] Operand 1 6316 // No operand predicates 6317 GIM_CheckIsSafeToFold, /*InsnID*/1, 6318 // (xor:{ *:[i64] } GR64:{ *:[i64] }:$src1, (imm:{ *:[i64] })<<P:Predicate_i64immSExt8>>:$src2) => (XOR64ri8:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src1, (imm:{ *:[i64] })<<P:Predicate_i64immSExt8>>:$src2) 6319 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::XOR64ri8, 6320 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 6321 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 6322 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2 6323 GIR_EraseFromParent, /*InsnID*/0, 6324 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6325 // GIR_Coverage, 17379, 6326 GIR_Done, 6327 // Label 518: @12922 6328 GIM_Try, /*On fail goto*//*Label 519*/ 12967, // Rule ID 17380 // 6329 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 6330 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID, 6331 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR64RegClassID, 6332 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 6333 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 6334 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_i64immSExt32, 6335 // MIs[1] Operand 1 6336 // No operand predicates 6337 GIM_CheckIsSafeToFold, /*InsnID*/1, 6338 // (xor:{ *:[i64] } GR64:{ *:[i64] }:$src1, (imm:{ *:[i64] })<<P:Predicate_i64immSExt32>>:$src2) => (XOR64ri32:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src1, (imm:{ *:[i64] })<<P:Predicate_i64immSExt32>>:$src2) 6339 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::XOR64ri32, 6340 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 6341 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 6342 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2 6343 GIR_EraseFromParent, /*InsnID*/0, 6344 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6345 // GIR_Coverage, 17380, 6346 GIR_Done, 6347 // Label 519: @12967 6348 GIM_Try, /*On fail goto*//*Label 520*/ 12995, // Rule ID 17369 // 6349 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 6350 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID, 6351 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR64RegClassID, 6352 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR64RegClassID, 6353 // (xor:{ *:[i64] } GR64:{ *:[i64] }:$src1, GR64:{ *:[i64] }:$src2) => (XOR64rr:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src1, GR64:{ *:[i64] }:$src2) 6354 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::XOR64rr, 6355 GIR_AddImplicitDef, /*InsnID*/0, X86::EFLAGS, 6356 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6357 // GIR_Coverage, 17369, 6358 GIR_Done, 6359 // Label 520: @12995 6360 GIM_Reject, 6361 // Label 510: @12996 6362 GIM_Reject, 6363 // Label 464: @12997 6364 GIM_Try, /*On fail goto*//*Label 521*/ 13089, // Rule ID 14603 // 6365 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s1, 6366 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s1, 6367 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VK1RegClassID, 6368 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VK2RegClassID, 6369 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VK2RegClassID, 6370 // (xor:{ *:[v2i1] } VK2:{ *:[v2i1] }:$src1, VK2:{ *:[v2i1] }:$src2) => (COPY_TO_REGCLASS:{ *:[v2i1] } (KXORWrr:{ *:[v16i1] } (COPY_TO_REGCLASS:{ *:[v16i1] } VK2:{ *:[v2i1] }:$src1, VK16:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v16i1] } VK2:{ *:[v2i1] }:$src2, VK16:{ *:[i32] })), VK1:{ *:[i32] }) 6371 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s1, 6372 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s1, 6373 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s1, 6374 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY, 6375 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, 6376 GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // src2 6377 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, 6378 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY, 6379 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 6380 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src1 6381 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 6382 GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::KXORWrr, 6383 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 6384 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 6385 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0, 6386 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 6387 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 6388 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 6389 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 6390 GIR_EraseFromParent, /*InsnID*/0, 6391 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VK1*/8, 6392 // GIR_Coverage, 14603, 6393 GIR_Done, 6394 // Label 521: @13089 6395 GIM_Reject, 6396 // Label 465: @13090 6397 GIM_Try, /*On fail goto*//*Label 522*/ 13170, 6398 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, 6399 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 6400 GIM_Try, /*On fail goto*//*Label 523*/ 13123, // Rule ID 1637 // 6401 GIM_CheckFeatures, GIFBS_HasAVX_NoVLX, 6402 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 6403 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 6404 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 6405 // (xor:{ *:[v2i64] } VR128:{ *:[v2i64] }:$src1, VR128:{ *:[v2i64] }:$src2) => (VPXORrr:{ *:[v2i64] } VR128:{ *:[v2i64] }:$src1, VR128:{ *:[v2i64] }:$src2) 6406 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPXORrr, 6407 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6408 // GIR_Coverage, 1637, 6409 GIR_Done, 6410 // Label 523: @13123 6411 GIM_Try, /*On fail goto*//*Label 524*/ 13146, // Rule ID 1639 // 6412 GIM_CheckFeatures, GIFBS_UseSSE2, 6413 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 6414 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 6415 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 6416 // (xor:{ *:[v2i64] } VR128:{ *:[v2i64] }:$src1, VR128:{ *:[v2i64] }:$src2) => (PXORrr:{ *:[v2i64] } VR128:{ *:[v2i64] }:$src1, VR128:{ *:[v2i64] }:$src2) 6417 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::PXORrr, 6418 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6419 // GIR_Coverage, 1639, 6420 GIR_Done, 6421 // Label 524: @13146 6422 GIM_Try, /*On fail goto*//*Label 525*/ 13169, // Rule ID 5074 // 6423 GIM_CheckFeatures, GIFBS_HasAVX512_HasVLX, 6424 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 6425 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 6426 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128XRegClassID, 6427 // (xor:{ *:[v2i64] } VR128X:{ *:[v2i64] }:$src1, VR128X:{ *:[v2i64] }:$src2) => (VPXORQZ128rr:{ *:[v2i64] } VR128X:{ *:[v2i64] }:$src1, VR128X:{ *:[v2i64] }:$src2) 6428 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPXORQZ128rr, 6429 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6430 // GIR_Coverage, 5074, 6431 GIR_Done, 6432 // Label 525: @13169 6433 GIM_Reject, 6434 // Label 522: @13170 6435 GIM_Reject, 6436 // Label 466: @13171 6437 GIM_Try, /*On fail goto*//*Label 526*/ 13263, // Rule ID 14604 // 6438 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s1, 6439 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s1, 6440 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VK1RegClassID, 6441 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VK4RegClassID, 6442 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VK4RegClassID, 6443 // (xor:{ *:[v4i1] } VK4:{ *:[v4i1] }:$src1, VK4:{ *:[v4i1] }:$src2) => (COPY_TO_REGCLASS:{ *:[v4i1] } (KXORWrr:{ *:[v16i1] } (COPY_TO_REGCLASS:{ *:[v16i1] } VK4:{ *:[v4i1] }:$src1, VK16:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v16i1] } VK4:{ *:[v4i1] }:$src2, VK16:{ *:[i32] })), VK1:{ *:[i32] }) 6444 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s1, 6445 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s1, 6446 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s1, 6447 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY, 6448 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, 6449 GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // src2 6450 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, 6451 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY, 6452 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 6453 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src1 6454 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 6455 GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::KXORWrr, 6456 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 6457 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 6458 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0, 6459 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 6460 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 6461 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 6462 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 6463 GIR_EraseFromParent, /*InsnID*/0, 6464 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VK1*/8, 6465 // GIR_Coverage, 14604, 6466 GIR_Done, 6467 // Label 526: @13263 6468 GIM_Reject, 6469 // Label 467: @13264 6470 GIM_Try, /*On fail goto*//*Label 527*/ 13344, 6471 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 6472 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 6473 GIM_Try, /*On fail goto*//*Label 528*/ 13297, // Rule ID 5101 // 6474 GIM_CheckFeatures, GIFBS_HasAVX512_HasVLX, 6475 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 6476 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 6477 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128XRegClassID, 6478 // (xor:{ *:[v4i32] } VR128X:{ *:[v4i32] }:$src1, VR128X:{ *:[v4i32] }:$src2) => (VPXORDZ128rr:{ *:[v4i32] } VR128X:{ *:[v4i32] }:$src1, VR128X:{ *:[v4i32] }:$src2) 6479 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPXORDZ128rr, 6480 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6481 // GIR_Coverage, 5101, 6482 GIR_Done, 6483 // Label 528: @13297 6484 GIM_Try, /*On fail goto*//*Label 529*/ 13320, // Rule ID 13471 // 6485 GIM_CheckFeatures, GIFBS_HasAVX_NoVLX, 6486 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 6487 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 6488 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 6489 // (xor:{ *:[v4i32] } VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2) => (VPXORrr:{ *:[v4i32] } VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2) 6490 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPXORrr, 6491 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6492 // GIR_Coverage, 13471, 6493 GIR_Done, 6494 // Label 529: @13320 6495 GIM_Try, /*On fail goto*//*Label 530*/ 13343, // Rule ID 13495 // 6496 GIM_CheckFeatures, GIFBS_UseSSE2, 6497 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 6498 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 6499 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 6500 // (xor:{ *:[v4i32] } VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2) => (PXORrr:{ *:[v4i32] } VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2) 6501 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::PXORrr, 6502 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6503 // GIR_Coverage, 13495, 6504 GIR_Done, 6505 // Label 530: @13343 6506 GIM_Reject, 6507 // Label 527: @13344 6508 GIM_Reject, 6509 // Label 468: @13345 6510 GIM_Try, /*On fail goto*//*Label 531*/ 13425, 6511 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s64, 6512 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s64, 6513 GIM_Try, /*On fail goto*//*Label 532*/ 13378, // Rule ID 1641 // 6514 GIM_CheckFeatures, GIFBS_HasAVX2_NoVLX, 6515 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID, 6516 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256RegClassID, 6517 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID, 6518 // (xor:{ *:[v4i64] } VR256:{ *:[v4i64] }:$src1, VR256:{ *:[v4i64] }:$src2) => (VPXORYrr:{ *:[v4i64] } VR256:{ *:[v4i64] }:$src1, VR256:{ *:[v4i64] }:$src2) 6519 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPXORYrr, 6520 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6521 // GIR_Coverage, 1641, 6522 GIR_Done, 6523 // Label 532: @13378 6524 GIM_Try, /*On fail goto*//*Label 533*/ 13401, // Rule ID 5065 // 6525 GIM_CheckFeatures, GIFBS_HasAVX512_HasVLX, 6526 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 6527 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 6528 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256XRegClassID, 6529 // (xor:{ *:[v4i64] } VR256X:{ *:[v4i64] }:$src1, VR256X:{ *:[v4i64] }:$src2) => (VPXORQZ256rr:{ *:[v4i64] } VR256X:{ *:[v4i64] }:$src1, VR256X:{ *:[v4i64] }:$src2) 6530 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPXORQZ256rr, 6531 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6532 // GIR_Coverage, 5065, 6533 GIR_Done, 6534 // Label 533: @13401 6535 GIM_Try, /*On fail goto*//*Label 534*/ 13424, // Rule ID 13442 // 6536 GIM_CheckFeatures, GIFBS_HasAVX1Only, 6537 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID, 6538 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256RegClassID, 6539 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID, 6540 // (xor:{ *:[v4i64] } VR256:{ *:[v4i64] }:$src1, VR256:{ *:[v4i64] }:$src2) => (VXORPSYrr:{ *:[v4i64] } VR256:{ *:[v4i64] }:$src1, VR256:{ *:[v4i64] }:$src2) 6541 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VXORPSYrr, 6542 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6543 // GIR_Coverage, 13442, 6544 GIR_Done, 6545 // Label 534: @13424 6546 GIM_Reject, 6547 // Label 531: @13425 6548 GIM_Reject, 6549 // Label 469: @13426 6550 GIM_Try, /*On fail goto*//*Label 535*/ 13534, 6551 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s1, 6552 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s1, 6553 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VK8RegClassID, 6554 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VK8RegClassID, 6555 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VK8RegClassID, 6556 GIM_Try, /*On fail goto*//*Label 536*/ 13459, // Rule ID 3695 // 6557 GIM_CheckFeatures, GIFBS_HasDQI, 6558 // (xor:{ *:[v8i1] } VK8:{ *:[v8i1] }:$src1, VK8:{ *:[v8i1] }:$src2) => (KXORBrr:{ *:[v8i1] } VK8:{ *:[v8i1] }:$src1, VK8:{ *:[v8i1] }:$src2) 6559 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::KXORBrr, 6560 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6561 // GIR_Coverage, 3695, 6562 GIR_Done, 6563 // Label 536: @13459 6564 GIM_Try, /*On fail goto*//*Label 537*/ 13533, // Rule ID 14601 // 6565 GIM_CheckFeatures, GIFBS_NoDQI, 6566 // (xor:{ *:[v8i1] } VK8:{ *:[v8i1] }:$src1, VK8:{ *:[v8i1] }:$src2) => (COPY_TO_REGCLASS:{ *:[v8i1] } (KXORWrr:{ *:[v16i1] } (COPY_TO_REGCLASS:{ *:[v16i1] } VK8:{ *:[v8i1] }:$src1, VK16:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[v16i1] } VK8:{ *:[v8i1] }:$src2, VK16:{ *:[i32] })), VK8:{ *:[i32] }) 6567 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s1, 6568 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s1, 6569 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s1, 6570 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY, 6571 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, 6572 GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // src2 6573 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, 6574 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY, 6575 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 6576 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src1 6577 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 6578 GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::KXORWrr, 6579 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 6580 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 6581 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0, 6582 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 6583 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 6584 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 6585 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 6586 GIR_EraseFromParent, /*InsnID*/0, 6587 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VK8*/12, 6588 // GIR_Coverage, 14601, 6589 GIR_Done, 6590 // Label 537: @13533 6591 GIM_Reject, 6592 // Label 535: @13534 6593 GIM_Reject, 6594 // Label 470: @13535 6595 GIM_Try, /*On fail goto*//*Label 538*/ 13615, 6596 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, 6597 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 6598 GIM_Try, /*On fail goto*//*Label 539*/ 13568, // Rule ID 13470 // 6599 GIM_CheckFeatures, GIFBS_HasAVX_NoVLX, 6600 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 6601 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 6602 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 6603 // (xor:{ *:[v8i16] } VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2) => (VPXORrr:{ *:[v8i16] } VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2) 6604 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPXORrr, 6605 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6606 // GIR_Coverage, 13470, 6607 GIR_Done, 6608 // Label 539: @13568 6609 GIM_Try, /*On fail goto*//*Label 540*/ 13591, // Rule ID 13494 // 6610 GIM_CheckFeatures, GIFBS_UseSSE2, 6611 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 6612 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 6613 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 6614 // (xor:{ *:[v8i16] } VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2) => (PXORrr:{ *:[v8i16] } VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2) 6615 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::PXORrr, 6616 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6617 // GIR_Coverage, 13494, 6618 GIR_Done, 6619 // Label 540: @13591 6620 GIM_Try, /*On fail goto*//*Label 541*/ 13614, // Rule ID 15060 // 6621 GIM_CheckFeatures, GIFBS_HasVLX, 6622 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 6623 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 6624 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128XRegClassID, 6625 // (xor:{ *:[v8i16] } VR128X:{ *:[v8i16] }:$src1, VR128X:{ *:[v8i16] }:$src2) => (VPXORQZ128rr:{ *:[v8i16] } VR128X:{ *:[v8i16] }:$src1, VR128X:{ *:[v8i16] }:$src2) 6626 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPXORQZ128rr, 6627 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6628 // GIR_Coverage, 15060, 6629 GIR_Done, 6630 // Label 541: @13614 6631 GIM_Reject, 6632 // Label 538: @13615 6633 GIM_Reject, 6634 // Label 471: @13616 6635 GIM_Try, /*On fail goto*//*Label 542*/ 13696, 6636 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s32, 6637 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s32, 6638 GIM_Try, /*On fail goto*//*Label 543*/ 13649, // Rule ID 5092 // 6639 GIM_CheckFeatures, GIFBS_HasAVX512_HasVLX, 6640 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 6641 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 6642 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256XRegClassID, 6643 // (xor:{ *:[v8i32] } VR256X:{ *:[v8i32] }:$src1, VR256X:{ *:[v8i32] }:$src2) => (VPXORDZ256rr:{ *:[v8i32] } VR256X:{ *:[v8i32] }:$src1, VR256X:{ *:[v8i32] }:$src2) 6644 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPXORDZ256rr, 6645 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6646 // GIR_Coverage, 5092, 6647 GIR_Done, 6648 // Label 543: @13649 6649 GIM_Try, /*On fail goto*//*Label 544*/ 13672, // Rule ID 13415 // 6650 GIM_CheckFeatures, GIFBS_HasAVX2_NoVLX, 6651 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID, 6652 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256RegClassID, 6653 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID, 6654 // (xor:{ *:[v8i32] } VR256:{ *:[v8i32] }:$src1, VR256:{ *:[v8i32] }:$src2) => (VPXORYrr:{ *:[v8i32] } VR256:{ *:[v8i32] }:$src1, VR256:{ *:[v8i32] }:$src2) 6655 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPXORYrr, 6656 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6657 // GIR_Coverage, 13415, 6658 GIR_Done, 6659 // Label 544: @13672 6660 GIM_Try, /*On fail goto*//*Label 545*/ 13695, // Rule ID 13441 // 6661 GIM_CheckFeatures, GIFBS_HasAVX1Only, 6662 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID, 6663 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256RegClassID, 6664 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID, 6665 // (xor:{ *:[v8i32] } VR256:{ *:[v8i32] }:$src1, VR256:{ *:[v8i32] }:$src2) => (VXORPSYrr:{ *:[v8i32] } VR256:{ *:[v8i32] }:$src1, VR256:{ *:[v8i32] }:$src2) 6666 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VXORPSYrr, 6667 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6668 // GIR_Coverage, 13441, 6669 GIR_Done, 6670 // Label 545: @13695 6671 GIM_Reject, 6672 // Label 542: @13696 6673 GIM_Reject, 6674 // Label 472: @13697 6675 GIM_Try, /*On fail goto*//*Label 546*/ 13728, // Rule ID 5056 // 6676 GIM_CheckFeatures, GIFBS_HasAVX512, 6677 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s64, 6678 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s64, 6679 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 6680 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID, 6681 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR512RegClassID, 6682 // (xor:{ *:[v8i64] } VR512:{ *:[v8i64] }:$src1, VR512:{ *:[v8i64] }:$src2) => (VPXORQZrr:{ *:[v8i64] } VR512:{ *:[v8i64] }:$src1, VR512:{ *:[v8i64] }:$src2) 6683 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPXORQZrr, 6684 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6685 // GIR_Coverage, 5056, 6686 GIR_Done, 6687 // Label 546: @13728 6688 GIM_Reject, 6689 // Label 473: @13729 6690 GIM_Try, /*On fail goto*//*Label 547*/ 13760, // Rule ID 3696 // 6691 GIM_CheckFeatures, GIFBS_HasAVX512, 6692 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s1, 6693 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s1, 6694 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VK16RegClassID, 6695 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VK16RegClassID, 6696 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VK16RegClassID, 6697 // (xor:{ *:[v16i1] } VK16:{ *:[v16i1] }:$src1, VK16:{ *:[v16i1] }:$src2) => (KXORWrr:{ *:[v16i1] } VK16:{ *:[v16i1] }:$src1, VK16:{ *:[v16i1] }:$src2) 6698 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::KXORWrr, 6699 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6700 // GIR_Coverage, 3696, 6701 GIR_Done, 6702 // Label 547: @13760 6703 GIM_Reject, 6704 // Label 474: @13761 6705 GIM_Try, /*On fail goto*//*Label 548*/ 13841, 6706 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, 6707 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 6708 GIM_Try, /*On fail goto*//*Label 549*/ 13794, // Rule ID 13469 // 6709 GIM_CheckFeatures, GIFBS_HasAVX_NoVLX, 6710 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 6711 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 6712 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 6713 // (xor:{ *:[v16i8] } VR128:{ *:[v16i8] }:$src1, VR128:{ *:[v16i8] }:$src2) => (VPXORrr:{ *:[v16i8] } VR128:{ *:[v16i8] }:$src1, VR128:{ *:[v16i8] }:$src2) 6714 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPXORrr, 6715 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6716 // GIR_Coverage, 13469, 6717 GIR_Done, 6718 // Label 549: @13794 6719 GIM_Try, /*On fail goto*//*Label 550*/ 13817, // Rule ID 13493 // 6720 GIM_CheckFeatures, GIFBS_UseSSE2, 6721 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 6722 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 6723 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 6724 // (xor:{ *:[v16i8] } VR128:{ *:[v16i8] }:$src1, VR128:{ *:[v16i8] }:$src2) => (PXORrr:{ *:[v16i8] } VR128:{ *:[v16i8] }:$src1, VR128:{ *:[v16i8] }:$src2) 6725 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::PXORrr, 6726 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6727 // GIR_Coverage, 13493, 6728 GIR_Done, 6729 // Label 550: @13817 6730 GIM_Try, /*On fail goto*//*Label 551*/ 13840, // Rule ID 15059 // 6731 GIM_CheckFeatures, GIFBS_HasVLX, 6732 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 6733 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 6734 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128XRegClassID, 6735 // (xor:{ *:[v16i8] } VR128X:{ *:[v16i8] }:$src1, VR128X:{ *:[v16i8] }:$src2) => (VPXORQZ128rr:{ *:[v16i8] } VR128X:{ *:[v16i8] }:$src1, VR128X:{ *:[v16i8] }:$src2) 6736 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPXORQZ128rr, 6737 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6738 // GIR_Coverage, 15059, 6739 GIR_Done, 6740 // Label 551: @13840 6741 GIM_Reject, 6742 // Label 548: @13841 6743 GIM_Reject, 6744 // Label 475: @13842 6745 GIM_Try, /*On fail goto*//*Label 552*/ 13922, 6746 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s16, 6747 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s16, 6748 GIM_Try, /*On fail goto*//*Label 553*/ 13875, // Rule ID 13414 // 6749 GIM_CheckFeatures, GIFBS_HasAVX2_NoVLX, 6750 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID, 6751 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256RegClassID, 6752 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID, 6753 // (xor:{ *:[v16i16] } VR256:{ *:[v16i16] }:$src1, VR256:{ *:[v16i16] }:$src2) => (VPXORYrr:{ *:[v16i16] } VR256:{ *:[v16i16] }:$src1, VR256:{ *:[v16i16] }:$src2) 6754 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPXORYrr, 6755 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6756 // GIR_Coverage, 13414, 6757 GIR_Done, 6758 // Label 553: @13875 6759 GIM_Try, /*On fail goto*//*Label 554*/ 13898, // Rule ID 13440 // 6760 GIM_CheckFeatures, GIFBS_HasAVX1Only, 6761 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID, 6762 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256RegClassID, 6763 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID, 6764 // (xor:{ *:[v16i16] } VR256:{ *:[v16i16] }:$src1, VR256:{ *:[v16i16] }:$src2) => (VXORPSYrr:{ *:[v16i16] } VR256:{ *:[v16i16] }:$src1, VR256:{ *:[v16i16] }:$src2) 6765 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VXORPSYrr, 6766 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6767 // GIR_Coverage, 13440, 6768 GIR_Done, 6769 // Label 554: @13898 6770 GIM_Try, /*On fail goto*//*Label 555*/ 13921, // Rule ID 15076 // 6771 GIM_CheckFeatures, GIFBS_HasVLX, 6772 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 6773 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 6774 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256XRegClassID, 6775 // (xor:{ *:[v16i16] } VR256X:{ *:[v16i16] }:$src1, VR256X:{ *:[v16i16] }:$src2) => (VPXORQZ256rr:{ *:[v16i16] } VR256X:{ *:[v16i16] }:$src1, VR256X:{ *:[v16i16] }:$src2) 6776 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPXORQZ256rr, 6777 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6778 // GIR_Coverage, 15076, 6779 GIR_Done, 6780 // Label 555: @13921 6781 GIM_Reject, 6782 // Label 552: @13922 6783 GIM_Reject, 6784 // Label 476: @13923 6785 GIM_Try, /*On fail goto*//*Label 556*/ 13954, // Rule ID 5083 // 6786 GIM_CheckFeatures, GIFBS_HasAVX512, 6787 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s32, 6788 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s32, 6789 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 6790 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID, 6791 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR512RegClassID, 6792 // (xor:{ *:[v16i32] } VR512:{ *:[v16i32] }:$src1, VR512:{ *:[v16i32] }:$src2) => (VPXORDZrr:{ *:[v16i32] } VR512:{ *:[v16i32] }:$src1, VR512:{ *:[v16i32] }:$src2) 6793 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPXORDZrr, 6794 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6795 // GIR_Coverage, 5083, 6796 GIR_Done, 6797 // Label 556: @13954 6798 GIM_Reject, 6799 // Label 477: @13955 6800 GIM_Try, /*On fail goto*//*Label 557*/ 13986, // Rule ID 3697 // 6801 GIM_CheckFeatures, GIFBS_HasBWI, 6802 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v32s1, 6803 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v32s1, 6804 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VK32RegClassID, 6805 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VK32RegClassID, 6806 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VK32RegClassID, 6807 // (xor:{ *:[v32i1] } VK32:{ *:[v32i1] }:$src1, VK32:{ *:[v32i1] }:$src2) => (KXORDrr:{ *:[v32i1] } VK32:{ *:[v32i1] }:$src1, VK32:{ *:[v32i1] }:$src2) 6808 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::KXORDrr, 6809 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6810 // GIR_Coverage, 3697, 6811 GIR_Done, 6812 // Label 557: @13986 6813 GIM_Reject, 6814 // Label 478: @13987 6815 GIM_Try, /*On fail goto*//*Label 558*/ 14067, 6816 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v32s8, 6817 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v32s8, 6818 GIM_Try, /*On fail goto*//*Label 559*/ 14020, // Rule ID 13413 // 6819 GIM_CheckFeatures, GIFBS_HasAVX2_NoVLX, 6820 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID, 6821 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256RegClassID, 6822 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID, 6823 // (xor:{ *:[v32i8] } VR256:{ *:[v32i8] }:$src1, VR256:{ *:[v32i8] }:$src2) => (VPXORYrr:{ *:[v32i8] } VR256:{ *:[v32i8] }:$src1, VR256:{ *:[v32i8] }:$src2) 6824 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPXORYrr, 6825 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6826 // GIR_Coverage, 13413, 6827 GIR_Done, 6828 // Label 559: @14020 6829 GIM_Try, /*On fail goto*//*Label 560*/ 14043, // Rule ID 13439 // 6830 GIM_CheckFeatures, GIFBS_HasAVX1Only, 6831 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID, 6832 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256RegClassID, 6833 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID, 6834 // (xor:{ *:[v32i8] } VR256:{ *:[v32i8] }:$src1, VR256:{ *:[v32i8] }:$src2) => (VXORPSYrr:{ *:[v32i8] } VR256:{ *:[v32i8] }:$src1, VR256:{ *:[v32i8] }:$src2) 6835 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VXORPSYrr, 6836 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6837 // GIR_Coverage, 13439, 6838 GIR_Done, 6839 // Label 560: @14043 6840 GIM_Try, /*On fail goto*//*Label 561*/ 14066, // Rule ID 15075 // 6841 GIM_CheckFeatures, GIFBS_HasVLX, 6842 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 6843 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 6844 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256XRegClassID, 6845 // (xor:{ *:[v32i8] } VR256X:{ *:[v32i8] }:$src1, VR256X:{ *:[v32i8] }:$src2) => (VPXORQZ256rr:{ *:[v32i8] } VR256X:{ *:[v32i8] }:$src1, VR256X:{ *:[v32i8] }:$src2) 6846 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPXORQZ256rr, 6847 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6848 // GIR_Coverage, 15075, 6849 GIR_Done, 6850 // Label 561: @14066 6851 GIM_Reject, 6852 // Label 558: @14067 6853 GIM_Reject, 6854 // Label 479: @14068 6855 GIM_Try, /*On fail goto*//*Label 562*/ 14099, // Rule ID 15092 // 6856 GIM_CheckFeatures, GIFBS_HasAVX512, 6857 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v32s16, 6858 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v32s16, 6859 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 6860 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID, 6861 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR512RegClassID, 6862 // (xor:{ *:[v32i16] } VR512:{ *:[v32i16] }:$src1, VR512:{ *:[v32i16] }:$src2) => (VPXORQZrr:{ *:[v32i16] } VR512:{ *:[v32i16] }:$src1, VR512:{ *:[v32i16] }:$src2) 6863 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPXORQZrr, 6864 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6865 // GIR_Coverage, 15092, 6866 GIR_Done, 6867 // Label 562: @14099 6868 GIM_Reject, 6869 // Label 480: @14100 6870 GIM_Try, /*On fail goto*//*Label 563*/ 14131, // Rule ID 3698 // 6871 GIM_CheckFeatures, GIFBS_HasBWI, 6872 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v64s1, 6873 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v64s1, 6874 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VK64RegClassID, 6875 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VK64RegClassID, 6876 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VK64RegClassID, 6877 // (xor:{ *:[v64i1] } VK64:{ *:[v64i1] }:$src1, VK64:{ *:[v64i1] }:$src2) => (KXORQrr:{ *:[v64i1] } VK64:{ *:[v64i1] }:$src1, VK64:{ *:[v64i1] }:$src2) 6878 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::KXORQrr, 6879 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6880 // GIR_Coverage, 3698, 6881 GIR_Done, 6882 // Label 563: @14131 6883 GIM_Reject, 6884 // Label 481: @14132 6885 GIM_Try, /*On fail goto*//*Label 564*/ 14163, // Rule ID 15091 // 6886 GIM_CheckFeatures, GIFBS_HasAVX512, 6887 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v64s8, 6888 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v64s8, 6889 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 6890 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID, 6891 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR512RegClassID, 6892 // (xor:{ *:[v64i8] } VR512:{ *:[v64i8] }:$src1, VR512:{ *:[v64i8] }:$src2) => (VPXORQZrr:{ *:[v64i8] } VR512:{ *:[v64i8] }:$src1, VR512:{ *:[v64i8] }:$src2) 6893 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPXORQZrr, 6894 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6895 // GIR_Coverage, 15091, 6896 GIR_Done, 6897 // Label 564: @14163 6898 GIM_Reject, 6899 // Label 482: @14164 6900 GIM_Reject, 6901 // Label 6: @14165 6902 GIM_Try, /*On fail goto*//*Label 565*/ 14320, 6903 GIM_CheckNumOperands, /*MI*/0, /*Expected*/3, 6904 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/16, 24, /*)*//*default:*//*Label 569*/ 14319, 6905 /*GILLT_v16s1*//*Label 566*/ 14184, 0, 0, 0, 6906 /*GILLT_v32s1*//*Label 567*/ 14229, 0, 0, 6907 /*GILLT_v64s1*//*Label 568*/ 14274, 6908 // Label 566: @14184 6909 GIM_Try, /*On fail goto*//*Label 570*/ 14228, // Rule ID 14605 // 6910 GIM_CheckFeatures, GIFBS_HasAVX512, 6911 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s1, 6912 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s1, 6913 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VK16RegClassID, 6914 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VK8RegClassID, 6915 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VK8RegClassID, 6916 // (concat_vectors:{ *:[v16i1] } VK8:{ *:[v8i1] }:$src1, VK8:{ *:[v8i1] }:$src2) => (KUNPCKBWrr:{ *:[v16i1] } VK8:{ *:[v8i1] }:$src2, VK8:{ *:[v8i1] }:$src1) 6917 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::KUNPCKBWrr, 6918 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 6919 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src2 6920 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 6921 GIR_EraseFromParent, /*InsnID*/0, 6922 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6923 // GIR_Coverage, 14605, 6924 GIR_Done, 6925 // Label 570: @14228 6926 GIM_Reject, 6927 // Label 567: @14229 6928 GIM_Try, /*On fail goto*//*Label 571*/ 14273, // Rule ID 14606 // 6929 GIM_CheckFeatures, GIFBS_HasBWI, 6930 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s1, 6931 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s1, 6932 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VK32RegClassID, 6933 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VK16RegClassID, 6934 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VK16RegClassID, 6935 // (concat_vectors:{ *:[v32i1] } VK16:{ *:[v16i1] }:$src1, VK16:{ *:[v16i1] }:$src2) => (KUNPCKWDrr:{ *:[v32i1] } VK16:{ *:[v16i1] }:$src2, VK16:{ *:[v16i1] }:$src1) 6936 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::KUNPCKWDrr, 6937 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 6938 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src2 6939 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 6940 GIR_EraseFromParent, /*InsnID*/0, 6941 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6942 // GIR_Coverage, 14606, 6943 GIR_Done, 6944 // Label 571: @14273 6945 GIM_Reject, 6946 // Label 568: @14274 6947 GIM_Try, /*On fail goto*//*Label 572*/ 14318, // Rule ID 14607 // 6948 GIM_CheckFeatures, GIFBS_HasBWI, 6949 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v32s1, 6950 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v32s1, 6951 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VK64RegClassID, 6952 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VK32RegClassID, 6953 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VK32RegClassID, 6954 // (concat_vectors:{ *:[v64i1] } VK32:{ *:[v32i1] }:$src1, VK32:{ *:[v32i1] }:$src2) => (KUNPCKDQrr:{ *:[v64i1] } VK32:{ *:[v32i1] }:$src2, VK32:{ *:[v32i1] }:$src1) 6955 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::KUNPCKDQrr, 6956 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 6957 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src2 6958 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 6959 GIR_EraseFromParent, /*InsnID*/0, 6960 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6961 // GIR_Coverage, 14607, 6962 GIR_Done, 6963 // Label 572: @14318 6964 GIM_Reject, 6965 // Label 569: @14319 6966 GIM_Reject, 6967 // Label 565: @14320 6968 GIM_Reject, 6969 // Label 7: @14321 6970 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/3, 24, /*)*//*default:*//*Label 579*/ 15050, 6971 /*GILLT_s32*//*Label 573*/ 14348, 6972 /*GILLT_s64*//*Label 574*/ 14556, 0, 0, 0, 0, 0, 0, 0, 6973 /*GILLT_v8s1*//*Label 575*/ 14764, 0, 0, 0, 6974 /*GILLT_v16s1*//*Label 576*/ 14842, 0, 0, 0, 6975 /*GILLT_v32s1*//*Label 577*/ 14920, 0, 0, 6976 /*GILLT_v64s1*//*Label 578*/ 14985, 6977 // Label 573: @14348 6978 GIM_Try, /*On fail goto*//*Label 580*/ 14371, // Rule ID 2374 // 6979 GIM_CheckFeatures, GIFBS_UseAVX, 6980 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 6981 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::FR32RegClassID, 6982 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR32RegClassID, 6983 // (bitconvert:{ *:[f32] } GR32:{ *:[i32] }:$src) => (VMOVDI2SSrr:{ *:[f32] } GR32:{ *:[i32] }:$src) 6984 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VMOVDI2SSrr, 6985 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6986 // GIR_Coverage, 2374, 6987 GIR_Done, 6988 // Label 580: @14371 6989 GIM_Try, /*On fail goto*//*Label 581*/ 14394, // Rule ID 2375 // 6990 GIM_CheckFeatures, GIFBS_UseSSE2, 6991 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 6992 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::FR32RegClassID, 6993 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR32RegClassID, 6994 // (bitconvert:{ *:[f32] } GR32:{ *:[i32] }:$src) => (MOVDI2SSrr:{ *:[f32] } GR32:{ *:[i32] }:$src) 6995 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::MOVDI2SSrr, 6996 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6997 // GIR_Coverage, 2375, 6998 GIR_Done, 6999 // Label 581: @14394 7000 GIM_Try, /*On fail goto*//*Label 582*/ 14417, // Rule ID 2384 // 7001 GIM_CheckFeatures, GIFBS_UseAVX, 7002 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 7003 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 7004 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR32RegClassID, 7005 // (bitconvert:{ *:[i32] } FR32:{ *:[f32] }:$src) => (VMOVSS2DIrr:{ *:[i32] } FR32:{ *:[f32] }:$src) 7006 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VMOVSS2DIrr, 7007 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7008 // GIR_Coverage, 2384, 7009 GIR_Done, 7010 // Label 582: @14417 7011 GIM_Try, /*On fail goto*//*Label 583*/ 14440, // Rule ID 2385 // 7012 GIM_CheckFeatures, GIFBS_UseSSE2, 7013 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 7014 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 7015 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR32RegClassID, 7016 // (bitconvert:{ *:[i32] } FR32:{ *:[f32] }:$src) => (MOVSS2DIrr:{ *:[i32] } FR32:{ *:[f32] }:$src) 7017 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::MOVSS2DIrr, 7018 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7019 // GIR_Coverage, 2385, 7020 GIR_Done, 7021 // Label 583: @14440 7022 GIM_Try, /*On fail goto*//*Label 584*/ 14463, // Rule ID 3866 // 7023 GIM_CheckFeatures, GIFBS_HasAVX512, 7024 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 7025 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::FR32XRegClassID, 7026 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR32RegClassID, 7027 // (bitconvert:{ *:[f32] } GR32:{ *:[i32] }:$src) => (VMOVDI2SSZrr:{ *:[f32] } GR32:{ *:[i32] }:$src) 7028 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VMOVDI2SSZrr, 7029 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7030 // GIR_Coverage, 3866, 7031 GIR_Done, 7032 // Label 584: @14463 7033 GIM_Try, /*On fail goto*//*Label 585*/ 14486, // Rule ID 3871 // 7034 GIM_CheckFeatures, GIFBS_HasAVX512, 7035 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 7036 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 7037 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR32XRegClassID, 7038 // (bitconvert:{ *:[i32] } FR32X:{ *:[f32] }:$src) => (VMOVSS2DIZrr:{ *:[i32] } FR32X:{ *:[f32] }:$src) 7039 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VMOVSS2DIZrr, 7040 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7041 // GIR_Coverage, 3871, 7042 GIR_Done, 7043 // Label 585: @14486 7044 GIM_Try, /*On fail goto*//*Label 586*/ 14509, // Rule ID 14544 // 7045 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v32s1, 7046 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 7047 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VK32RegClassID, 7048 // (bitconvert:{ *:[i32] } VK32:{ *:[v32i1] }:$src) => (COPY_TO_REGCLASS:{ *:[i32] } VK32:{ *:[v32i1] }:$src, GR32:{ *:[i32] }) 7049 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, 7050 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC GR32*/33, 7051 // GIR_Coverage, 14544, 7052 GIR_Done, 7053 // Label 586: @14509 7054 GIM_Try, /*On fail goto*//*Label 587*/ 14555, // Rule ID 14944 // 7055 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v32s1, 7056 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::FR32XRegClassID, 7057 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VK32RegClassID, 7058 // (bitconvert:{ *:[f32] } VK32:{ *:[v32i1] }:$src) => (VMOVDI2SSZrr:{ *:[f32] } (KMOVDrk:{ *:[i32] } VK32:{ *:[v32i1] }:$src)) 7059 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, 7060 GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::KMOVDrk, 7061 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 7062 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src 7063 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 7064 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VMOVDI2SSZrr, 7065 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 7066 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 7067 GIR_EraseFromParent, /*InsnID*/0, 7068 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7069 // GIR_Coverage, 14944, 7070 GIR_Done, 7071 // Label 587: @14555 7072 GIM_Reject, 7073 // Label 574: @14556 7074 GIM_Try, /*On fail goto*//*Label 588*/ 14579, // Rule ID 2369 // 7075 GIM_CheckFeatures, GIFBS_UseAVX, 7076 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 7077 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::FR64RegClassID, 7078 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR64RegClassID, 7079 // (bitconvert:{ *:[f64] } GR64:{ *:[i64] }:$src) => (VMOV64toSDrr:{ *:[f64] } GR64:{ *:[i64] }:$src) 7080 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VMOV64toSDrr, 7081 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7082 // GIR_Coverage, 2369, 7083 GIR_Done, 7084 // Label 588: @14579 7085 GIM_Try, /*On fail goto*//*Label 589*/ 14602, // Rule ID 2373 // 7086 GIM_CheckFeatures, GIFBS_UseSSE2, 7087 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 7088 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::FR64RegClassID, 7089 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR64RegClassID, 7090 // (bitconvert:{ *:[f64] } GR64:{ *:[i64] }:$src) => (MOV64toSDrr:{ *:[f64] } GR64:{ *:[i64] }:$src) 7091 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::MOV64toSDrr, 7092 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7093 // GIR_Coverage, 2373, 7094 GIR_Done, 7095 // Label 589: @14602 7096 GIM_Try, /*On fail goto*//*Label 590*/ 14625, // Rule ID 2382 // 7097 GIM_CheckFeatures, GIFBS_UseAVX, 7098 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 7099 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID, 7100 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR64RegClassID, 7101 // (bitconvert:{ *:[i64] } FR64:{ *:[f64] }:$src) => (VMOVSDto64rr:{ *:[i64] } FR64:{ *:[f64] }:$src) 7102 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VMOVSDto64rr, 7103 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7104 // GIR_Coverage, 2382, 7105 GIR_Done, 7106 // Label 590: @14625 7107 GIM_Try, /*On fail goto*//*Label 591*/ 14648, // Rule ID 2383 // 7108 GIM_CheckFeatures, GIFBS_UseSSE2, 7109 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 7110 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID, 7111 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR64RegClassID, 7112 // (bitconvert:{ *:[i64] } FR64:{ *:[f64] }:$src) => (MOVSDto64rr:{ *:[i64] } FR64:{ *:[f64] }:$src) 7113 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::MOVSDto64rr, 7114 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7115 // GIR_Coverage, 2383, 7116 GIR_Done, 7117 // Label 591: @14648 7118 GIM_Try, /*On fail goto*//*Label 592*/ 14671, // Rule ID 3864 // 7119 GIM_CheckFeatures, GIFBS_HasAVX512, 7120 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 7121 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::FR64XRegClassID, 7122 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR64RegClassID, 7123 // (bitconvert:{ *:[f64] } GR64:{ *:[i64] }:$src) => (VMOV64toSDZrr:{ *:[f64] } GR64:{ *:[i64] }:$src) 7124 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VMOV64toSDZrr, 7125 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7126 // GIR_Coverage, 3864, 7127 GIR_Done, 7128 // Label 592: @14671 7129 GIM_Try, /*On fail goto*//*Label 593*/ 14694, // Rule ID 3865 // 7130 GIM_CheckFeatures, GIFBS_HasAVX512, 7131 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 7132 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID, 7133 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR64XRegClassID, 7134 // (bitconvert:{ *:[i64] } FR64X:{ *:[f64] }:$src) => (VMOVSDto64Zrr:{ *:[i64] } FR64X:{ *:[f64] }:$src) 7135 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VMOVSDto64Zrr, 7136 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7137 // GIR_Coverage, 3865, 7138 GIR_Done, 7139 // Label 593: @14694 7140 GIM_Try, /*On fail goto*//*Label 594*/ 14717, // Rule ID 14546 // 7141 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v64s1, 7142 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID, 7143 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VK64RegClassID, 7144 // (bitconvert:{ *:[i64] } VK64:{ *:[v64i1] }:$src) => (COPY_TO_REGCLASS:{ *:[i64] } VK64:{ *:[v64i1] }:$src, GR64:{ *:[i32] }) 7145 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, 7146 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC GR64*/65, 7147 // GIR_Coverage, 14546, 7148 GIR_Done, 7149 // Label 594: @14717 7150 GIM_Try, /*On fail goto*//*Label 595*/ 14763, // Rule ID 14946 // 7151 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v64s1, 7152 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::FR64XRegClassID, 7153 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VK64RegClassID, 7154 // (bitconvert:{ *:[f64] } VK64:{ *:[v64i1] }:$src) => (VMOV64toSDZrr:{ *:[f64] } (KMOVQrk:{ *:[i64] } VK64:{ *:[v64i1] }:$src)) 7155 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, 7156 GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::KMOVQrk, 7157 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 7158 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src 7159 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 7160 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VMOV64toSDZrr, 7161 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 7162 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 7163 GIR_EraseFromParent, /*InsnID*/0, 7164 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7165 // GIR_Coverage, 14946, 7166 GIR_Done, 7167 // Label 595: @14763 7168 GIM_Reject, 7169 // Label 575: @14764 7170 GIM_Try, /*On fail goto*//*Label 596*/ 14841, // Rule ID 14535 // 7171 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s8, 7172 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VK8RegClassID, 7173 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR8RegClassID, 7174 // (bitconvert:{ *:[v8i1] } GR8:{ *:[i8] }:$src) => (COPY_TO_REGCLASS:{ *:[v8i1] } (INSERT_SUBREG:{ *:[i32] } (IMPLICIT_DEF:{ *:[i32] }), GR8:{ *:[i8] }:$src, sub_8bit:{ *:[i32] }), VK8:{ *:[i32] }) 7175 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, 7176 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, 7177 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, 7178 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 7179 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 7180 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, 7181 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 7182 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 7183 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src 7184 GIR_AddImm, /*InsnID*/1, /*Imm*/1, 7185 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, /*RC LOW32_ADDR_ACCESS_RBP_with_sub_8bit*/30, 7186 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, /*RC LOW32_ADDR_ACCESS_RBP_with_sub_8bit*/30, 7187 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, /*RC GR8*/0, 7188 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 7189 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 7190 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 7191 GIR_EraseFromParent, /*InsnID*/0, 7192 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VK8*/12, 7193 // GIR_Coverage, 14535, 7194 GIR_Done, 7195 // Label 596: @14841 7196 GIM_Reject, 7197 // Label 576: @14842 7198 GIM_Try, /*On fail goto*//*Label 597*/ 14919, // Rule ID 14533 // 7199 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, 7200 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VK16RegClassID, 7201 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR16RegClassID, 7202 // (bitconvert:{ *:[v16i1] } GR16:{ *:[i16] }:$src) => (COPY_TO_REGCLASS:{ *:[v16i1] } (INSERT_SUBREG:{ *:[i32] } (IMPLICIT_DEF:{ *:[i32] }), GR16:{ *:[i16] }:$src, sub_16bit:{ *:[i32] }), VK16:{ *:[i32] }) 7203 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, 7204 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, 7205 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, 7206 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 7207 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 7208 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, 7209 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 7210 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 7211 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src 7212 GIR_AddImm, /*InsnID*/1, /*Imm*/4, 7213 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, /*RC LOW32_ADDR_ACCESS_RBP*/28, 7214 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, /*RC LOW32_ADDR_ACCESS_RBP*/28, 7215 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, /*RC GR16*/6, 7216 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 7217 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 7218 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 7219 GIR_EraseFromParent, /*InsnID*/0, 7220 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VK16*/9, 7221 // GIR_Coverage, 14533, 7222 GIR_Done, 7223 // Label 597: @14919 7224 GIM_Reject, 7225 // Label 577: @14920 7226 GIM_Try, /*On fail goto*//*Label 598*/ 14984, 7227 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 7228 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VK32RegClassID, 7229 GIM_Try, /*On fail goto*//*Label 599*/ 14945, // Rule ID 14543 // 7230 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR32RegClassID, 7231 // (bitconvert:{ *:[v32i1] } GR32:{ *:[i32] }:$src) => (COPY_TO_REGCLASS:{ *:[v32i1] } GR32:{ *:[i32] }:$src, VK32:{ *:[i32] }) 7232 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, 7233 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VK32*/37, 7234 // GIR_Coverage, 14543, 7235 GIR_Done, 7236 // Label 599: @14945 7237 GIM_Try, /*On fail goto*//*Label 600*/ 14983, // Rule ID 14943 // 7238 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR32XRegClassID, 7239 // (bitconvert:{ *:[v32i1] } FR32X:{ *:[f32] }:$src) => (KMOVDkr:{ *:[v32i1] } (VMOVSS2DIZrr:{ *:[i32] } FR32X:{ *:[f32] }:$src)) 7240 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, 7241 GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::VMOVSS2DIZrr, 7242 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 7243 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src 7244 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 7245 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::KMOVDkr, 7246 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 7247 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 7248 GIR_EraseFromParent, /*InsnID*/0, 7249 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7250 // GIR_Coverage, 14943, 7251 GIR_Done, 7252 // Label 600: @14983 7253 GIM_Reject, 7254 // Label 598: @14984 7255 GIM_Reject, 7256 // Label 578: @14985 7257 GIM_Try, /*On fail goto*//*Label 601*/ 15049, 7258 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 7259 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VK64RegClassID, 7260 GIM_Try, /*On fail goto*//*Label 602*/ 15010, // Rule ID 14545 // 7261 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR64RegClassID, 7262 // (bitconvert:{ *:[v64i1] } GR64:{ *:[i64] }:$src) => (COPY_TO_REGCLASS:{ *:[v64i1] } GR64:{ *:[i64] }:$src, VK64:{ *:[i32] }) 7263 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, 7264 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC VK64*/78, 7265 // GIR_Coverage, 14545, 7266 GIR_Done, 7267 // Label 602: @15010 7268 GIM_Try, /*On fail goto*//*Label 603*/ 15048, // Rule ID 14945 // 7269 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR64XRegClassID, 7270 // (bitconvert:{ *:[v64i1] } FR64X:{ *:[f64] }:$src) => (KMOVQkr:{ *:[v64i1] } (VMOVSDto64Zrr:{ *:[i64] } FR64X:{ *:[f64] }:$src)) 7271 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, 7272 GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::VMOVSDto64Zrr, 7273 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 7274 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src 7275 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 7276 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::KMOVQkr, 7277 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 7278 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 7279 GIR_EraseFromParent, /*InsnID*/0, 7280 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7281 // GIR_Coverage, 14945, 7282 GIR_Done, 7283 // Label 603: @15048 7284 GIM_Reject, 7285 // Label 601: @15049 7286 GIM_Reject, 7287 // Label 579: @15050 7288 GIM_Reject, 7289 // Label 8: @15051 7290 GIM_Try, /*On fail goto*//*Label 604*/ 16153, 7291 GIM_CheckNumOperands, /*MI*/0, /*Expected*/3, 7292 GIM_Try, /*On fail goto*//*Label 605*/ 15096, // Rule ID 1123 // 7293 GIM_CheckFeatures, GIFBS_HasXOP, 7294 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_xop_vphsubwd, 7295 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 7296 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 7297 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 7298 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 7299 // (intrinsic_wo_chain:{ *:[v4i32] } 7458:{ *:[iPTR] }, VR128:{ *:[v8i16] }:$src) => (VPHSUBWDrr:{ *:[v4i32] } VR128:{ *:[v8i16] }:$src) 7300 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VPHSUBWDrr, 7301 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 7302 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src 7303 GIR_EraseFromParent, /*InsnID*/0, 7304 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7305 // GIR_Coverage, 1123, 7306 GIR_Done, 7307 // Label 605: @15096 7308 GIM_Try, /*On fail goto*//*Label 606*/ 15136, // Rule ID 1125 // 7309 GIM_CheckFeatures, GIFBS_HasXOP, 7310 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_xop_vphsubdq, 7311 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 7312 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 7313 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 7314 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 7315 // (intrinsic_wo_chain:{ *:[v2i64] } 7457:{ *:[iPTR] }, VR128:{ *:[v4i32] }:$src) => (VPHSUBDQrr:{ *:[v2i64] } VR128:{ *:[v4i32] }:$src) 7316 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VPHSUBDQrr, 7317 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 7318 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src 7319 GIR_EraseFromParent, /*InsnID*/0, 7320 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7321 // GIR_Coverage, 1125, 7322 GIR_Done, 7323 // Label 606: @15136 7324 GIM_Try, /*On fail goto*//*Label 607*/ 15176, // Rule ID 1127 // 7325 GIM_CheckFeatures, GIFBS_HasXOP, 7326 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_xop_vphsubbw, 7327 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, 7328 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 7329 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 7330 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 7331 // (intrinsic_wo_chain:{ *:[v8i16] } 7456:{ *:[iPTR] }, VR128:{ *:[v16i8] }:$src) => (VPHSUBBWrr:{ *:[v8i16] } VR128:{ *:[v16i8] }:$src) 7332 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VPHSUBBWrr, 7333 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 7334 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src 7335 GIR_EraseFromParent, /*InsnID*/0, 7336 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7337 // GIR_Coverage, 1127, 7338 GIR_Done, 7339 // Label 607: @15176 7340 GIM_Try, /*On fail goto*//*Label 608*/ 15216, // Rule ID 1129 // 7341 GIM_CheckFeatures, GIFBS_HasXOP, 7342 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_xop_vphaddwq, 7343 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 7344 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 7345 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 7346 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 7347 // (intrinsic_wo_chain:{ *:[v2i64] } 7455:{ *:[iPTR] }, VR128:{ *:[v8i16] }:$src) => (VPHADDWQrr:{ *:[v2i64] } VR128:{ *:[v8i16] }:$src) 7348 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VPHADDWQrr, 7349 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 7350 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src 7351 GIR_EraseFromParent, /*InsnID*/0, 7352 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7353 // GIR_Coverage, 1129, 7354 GIR_Done, 7355 // Label 608: @15216 7356 GIM_Try, /*On fail goto*//*Label 609*/ 15256, // Rule ID 1131 // 7357 GIM_CheckFeatures, GIFBS_HasXOP, 7358 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_xop_vphaddwd, 7359 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 7360 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 7361 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 7362 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 7363 // (intrinsic_wo_chain:{ *:[v4i32] } 7454:{ *:[iPTR] }, VR128:{ *:[v8i16] }:$src) => (VPHADDWDrr:{ *:[v4i32] } VR128:{ *:[v8i16] }:$src) 7364 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VPHADDWDrr, 7365 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 7366 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src 7367 GIR_EraseFromParent, /*InsnID*/0, 7368 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7369 // GIR_Coverage, 1131, 7370 GIR_Done, 7371 // Label 609: @15256 7372 GIM_Try, /*On fail goto*//*Label 610*/ 15296, // Rule ID 1133 // 7373 GIM_CheckFeatures, GIFBS_HasXOP, 7374 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_xop_vphadduwq, 7375 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 7376 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 7377 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 7378 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 7379 // (intrinsic_wo_chain:{ *:[v2i64] } 7453:{ *:[iPTR] }, VR128:{ *:[v8i16] }:$src) => (VPHADDUWQrr:{ *:[v2i64] } VR128:{ *:[v8i16] }:$src) 7380 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VPHADDUWQrr, 7381 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 7382 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src 7383 GIR_EraseFromParent, /*InsnID*/0, 7384 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7385 // GIR_Coverage, 1133, 7386 GIR_Done, 7387 // Label 610: @15296 7388 GIM_Try, /*On fail goto*//*Label 611*/ 15336, // Rule ID 1135 // 7389 GIM_CheckFeatures, GIFBS_HasXOP, 7390 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_xop_vphadduwd, 7391 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 7392 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 7393 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 7394 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 7395 // (intrinsic_wo_chain:{ *:[v4i32] } 7452:{ *:[iPTR] }, VR128:{ *:[v8i16] }:$src) => (VPHADDUWDrr:{ *:[v4i32] } VR128:{ *:[v8i16] }:$src) 7396 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VPHADDUWDrr, 7397 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 7398 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src 7399 GIR_EraseFromParent, /*InsnID*/0, 7400 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7401 // GIR_Coverage, 1135, 7402 GIR_Done, 7403 // Label 611: @15336 7404 GIM_Try, /*On fail goto*//*Label 612*/ 15376, // Rule ID 1137 // 7405 GIM_CheckFeatures, GIFBS_HasXOP, 7406 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_xop_vphaddudq, 7407 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 7408 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 7409 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 7410 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 7411 // (intrinsic_wo_chain:{ *:[v2i64] } 7451:{ *:[iPTR] }, VR128:{ *:[v4i32] }:$src) => (VPHADDUDQrr:{ *:[v2i64] } VR128:{ *:[v4i32] }:$src) 7412 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VPHADDUDQrr, 7413 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 7414 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src 7415 GIR_EraseFromParent, /*InsnID*/0, 7416 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7417 // GIR_Coverage, 1137, 7418 GIR_Done, 7419 // Label 612: @15376 7420 GIM_Try, /*On fail goto*//*Label 613*/ 15416, // Rule ID 1139 // 7421 GIM_CheckFeatures, GIFBS_HasXOP, 7422 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_xop_vphaddubw, 7423 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, 7424 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 7425 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 7426 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 7427 // (intrinsic_wo_chain:{ *:[v8i16] } 7450:{ *:[iPTR] }, VR128:{ *:[v16i8] }:$src) => (VPHADDUBWrr:{ *:[v8i16] } VR128:{ *:[v16i8] }:$src) 7428 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VPHADDUBWrr, 7429 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 7430 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src 7431 GIR_EraseFromParent, /*InsnID*/0, 7432 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7433 // GIR_Coverage, 1139, 7434 GIR_Done, 7435 // Label 613: @15416 7436 GIM_Try, /*On fail goto*//*Label 614*/ 15456, // Rule ID 1141 // 7437 GIM_CheckFeatures, GIFBS_HasXOP, 7438 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_xop_vphaddubq, 7439 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 7440 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 7441 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 7442 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 7443 // (intrinsic_wo_chain:{ *:[v2i64] } 7449:{ *:[iPTR] }, VR128:{ *:[v16i8] }:$src) => (VPHADDUBQrr:{ *:[v2i64] } VR128:{ *:[v16i8] }:$src) 7444 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VPHADDUBQrr, 7445 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 7446 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src 7447 GIR_EraseFromParent, /*InsnID*/0, 7448 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7449 // GIR_Coverage, 1141, 7450 GIR_Done, 7451 // Label 614: @15456 7452 GIM_Try, /*On fail goto*//*Label 615*/ 15496, // Rule ID 1143 // 7453 GIM_CheckFeatures, GIFBS_HasXOP, 7454 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_xop_vphaddubd, 7455 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 7456 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 7457 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 7458 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 7459 // (intrinsic_wo_chain:{ *:[v4i32] } 7448:{ *:[iPTR] }, VR128:{ *:[v16i8] }:$src) => (VPHADDUBDrr:{ *:[v4i32] } VR128:{ *:[v16i8] }:$src) 7460 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VPHADDUBDrr, 7461 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 7462 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src 7463 GIR_EraseFromParent, /*InsnID*/0, 7464 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7465 // GIR_Coverage, 1143, 7466 GIR_Done, 7467 // Label 615: @15496 7468 GIM_Try, /*On fail goto*//*Label 616*/ 15536, // Rule ID 1145 // 7469 GIM_CheckFeatures, GIFBS_HasXOP, 7470 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_xop_vphadddq, 7471 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 7472 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 7473 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 7474 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 7475 // (intrinsic_wo_chain:{ *:[v2i64] } 7447:{ *:[iPTR] }, VR128:{ *:[v4i32] }:$src) => (VPHADDDQrr:{ *:[v2i64] } VR128:{ *:[v4i32] }:$src) 7476 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VPHADDDQrr, 7477 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 7478 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src 7479 GIR_EraseFromParent, /*InsnID*/0, 7480 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7481 // GIR_Coverage, 1145, 7482 GIR_Done, 7483 // Label 616: @15536 7484 GIM_Try, /*On fail goto*//*Label 617*/ 15576, // Rule ID 1147 // 7485 GIM_CheckFeatures, GIFBS_HasXOP, 7486 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_xop_vphaddbw, 7487 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, 7488 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 7489 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 7490 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 7491 // (intrinsic_wo_chain:{ *:[v8i16] } 7446:{ *:[iPTR] }, VR128:{ *:[v16i8] }:$src) => (VPHADDBWrr:{ *:[v8i16] } VR128:{ *:[v16i8] }:$src) 7492 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VPHADDBWrr, 7493 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 7494 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src 7495 GIR_EraseFromParent, /*InsnID*/0, 7496 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7497 // GIR_Coverage, 1147, 7498 GIR_Done, 7499 // Label 617: @15576 7500 GIM_Try, /*On fail goto*//*Label 618*/ 15616, // Rule ID 1149 // 7501 GIM_CheckFeatures, GIFBS_HasXOP, 7502 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_xop_vphaddbq, 7503 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 7504 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 7505 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 7506 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 7507 // (intrinsic_wo_chain:{ *:[v2i64] } 7445:{ *:[iPTR] }, VR128:{ *:[v16i8] }:$src) => (VPHADDBQrr:{ *:[v2i64] } VR128:{ *:[v16i8] }:$src) 7508 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VPHADDBQrr, 7509 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 7510 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src 7511 GIR_EraseFromParent, /*InsnID*/0, 7512 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7513 // GIR_Coverage, 1149, 7514 GIR_Done, 7515 // Label 618: @15616 7516 GIM_Try, /*On fail goto*//*Label 619*/ 15656, // Rule ID 1151 // 7517 GIM_CheckFeatures, GIFBS_HasXOP, 7518 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_xop_vphaddbd, 7519 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 7520 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 7521 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 7522 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 7523 // (intrinsic_wo_chain:{ *:[v4i32] } 7444:{ *:[iPTR] }, VR128:{ *:[v16i8] }:$src) => (VPHADDBDrr:{ *:[v4i32] } VR128:{ *:[v16i8] }:$src) 7524 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VPHADDBDrr, 7525 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 7526 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src 7527 GIR_EraseFromParent, /*InsnID*/0, 7528 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7529 // GIR_Coverage, 1151, 7530 GIR_Done, 7531 // Label 619: @15656 7532 GIM_Try, /*On fail goto*//*Label 620*/ 15696, // Rule ID 1153 // 7533 GIM_CheckFeatures, GIFBS_HasXOP, 7534 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_xop_vfrcz_ss, 7535 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 7536 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 7537 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 7538 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 7539 // (intrinsic_wo_chain:{ *:[v4f32] } 7439:{ *:[iPTR] }, VR128:{ *:[v4f32] }:$src) => (VFRCZSSrr:{ *:[v4f32] } VR128:{ *:[v4f32] }:$src) 7540 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VFRCZSSrr, 7541 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 7542 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src 7543 GIR_EraseFromParent, /*InsnID*/0, 7544 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7545 // GIR_Coverage, 1153, 7546 GIR_Done, 7547 // Label 620: @15696 7548 GIM_Try, /*On fail goto*//*Label 621*/ 15736, // Rule ID 1155 // 7549 GIM_CheckFeatures, GIFBS_HasXOP, 7550 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_xop_vfrcz_ps, 7551 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 7552 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 7553 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 7554 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 7555 // (intrinsic_wo_chain:{ *:[v4f32] } 7436:{ *:[iPTR] }, VR128:{ *:[v4f32] }:$src) => (VFRCZPSrr:{ *:[v4f32] } VR128:{ *:[v4f32] }:$src) 7556 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VFRCZPSrr, 7557 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 7558 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src 7559 GIR_EraseFromParent, /*InsnID*/0, 7560 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7561 // GIR_Coverage, 1155, 7562 GIR_Done, 7563 // Label 621: @15736 7564 GIM_Try, /*On fail goto*//*Label 622*/ 15776, // Rule ID 1157 // 7565 GIM_CheckFeatures, GIFBS_HasXOP, 7566 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_xop_vfrcz_ps_256, 7567 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s32, 7568 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s32, 7569 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID, 7570 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID, 7571 // (intrinsic_wo_chain:{ *:[v8f32] } 7437:{ *:[iPTR] }, VR256:{ *:[v8f32] }:$src) => (VFRCZPSYrr:{ *:[v8f32] } VR256:{ *:[v8f32] }:$src) 7572 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VFRCZPSYrr, 7573 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 7574 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src 7575 GIR_EraseFromParent, /*InsnID*/0, 7576 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7577 // GIR_Coverage, 1157, 7578 GIR_Done, 7579 // Label 622: @15776 7580 GIM_Try, /*On fail goto*//*Label 623*/ 15816, // Rule ID 1159 // 7581 GIM_CheckFeatures, GIFBS_HasXOP, 7582 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_xop_vfrcz_sd, 7583 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 7584 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 7585 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 7586 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 7587 // (intrinsic_wo_chain:{ *:[v2f64] } 7438:{ *:[iPTR] }, VR128:{ *:[v2f64] }:$src) => (VFRCZSDrr:{ *:[v2f64] } VR128:{ *:[v2f64] }:$src) 7588 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VFRCZSDrr, 7589 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 7590 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src 7591 GIR_EraseFromParent, /*InsnID*/0, 7592 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7593 // GIR_Coverage, 1159, 7594 GIR_Done, 7595 // Label 623: @15816 7596 GIM_Try, /*On fail goto*//*Label 624*/ 15856, // Rule ID 1161 // 7597 GIM_CheckFeatures, GIFBS_HasXOP, 7598 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_xop_vfrcz_pd, 7599 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 7600 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 7601 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 7602 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 7603 // (intrinsic_wo_chain:{ *:[v2f64] } 7434:{ *:[iPTR] }, VR128:{ *:[v2f64] }:$src) => (VFRCZPDrr:{ *:[v2f64] } VR128:{ *:[v2f64] }:$src) 7604 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VFRCZPDrr, 7605 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 7606 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src 7607 GIR_EraseFromParent, /*InsnID*/0, 7608 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7609 // GIR_Coverage, 1161, 7610 GIR_Done, 7611 // Label 624: @15856 7612 GIM_Try, /*On fail goto*//*Label 625*/ 15896, // Rule ID 1163 // 7613 GIM_CheckFeatures, GIFBS_HasXOP, 7614 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_xop_vfrcz_pd_256, 7615 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s64, 7616 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s64, 7617 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID, 7618 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID, 7619 // (intrinsic_wo_chain:{ *:[v4f64] } 7435:{ *:[iPTR] }, VR256:{ *:[v4f64] }:$src) => (VFRCZPDYrr:{ *:[v4f64] } VR256:{ *:[v4f64] }:$src) 7620 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VFRCZPDYrr, 7621 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 7622 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src 7623 GIR_EraseFromParent, /*InsnID*/0, 7624 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7625 // GIR_Coverage, 1163, 7626 GIR_Done, 7627 // Label 625: @15896 7628 GIM_Try, /*On fail goto*//*Label 626*/ 15936, // Rule ID 2806 // 7629 GIM_CheckFeatures, GIFBS_HasAES_HasAVX, 7630 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_aesni_aesimc, 7631 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 7632 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 7633 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 7634 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 7635 // (intrinsic_wo_chain:{ *:[v2i64] } 6360:{ *:[iPTR] }, VR128:{ *:[v2i64] }:$src1) => (VAESIMCrr:{ *:[v2i64] } VR128:{ *:[v2i64] }:$src1) 7636 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VAESIMCrr, 7637 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 7638 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 7639 GIR_EraseFromParent, /*InsnID*/0, 7640 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7641 // GIR_Coverage, 2806, 7642 GIR_Done, 7643 // Label 626: @15936 7644 GIM_Try, /*On fail goto*//*Label 627*/ 15976, // Rule ID 2808 // 7645 GIM_CheckFeatures, GIFBS_HasAES_NoAVX, 7646 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_aesni_aesimc, 7647 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 7648 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 7649 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 7650 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 7651 // (intrinsic_wo_chain:{ *:[v2i64] } 6360:{ *:[iPTR] }, VR128:{ *:[v2i64] }:$src1) => (AESIMCrr:{ *:[v2i64] } VR128:{ *:[v2i64] }:$src1) 7652 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::AESIMCrr, 7653 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 7654 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 7655 GIR_EraseFromParent, /*InsnID*/0, 7656 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7657 // GIR_Coverage, 2808, 7658 GIR_Done, 7659 // Label 627: @15976 7660 GIM_Try, /*On fail goto*//*Label 628*/ 16020, // Rule ID 13583 // 7661 GIM_CheckFeatures, GIFBS_UseSSE1, 7662 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_sse_rsqrt_ss, 7663 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 7664 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 7665 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 7666 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 7667 // (intrinsic_wo_chain:{ *:[v4f32] } 7256:{ *:[iPTR] }, VR128:{ *:[v4f32] }:$src) => (RSQRTSSr_Int:{ *:[v4f32] } VR128:{ *:[v4f32] }:$src, VR128:{ *:[v4f32] }:$src) 7668 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::RSQRTSSr_Int, 7669 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 7670 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src 7671 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src 7672 GIR_EraseFromParent, /*InsnID*/0, 7673 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7674 // GIR_Coverage, 13583, 7675 GIR_Done, 7676 // Label 628: @16020 7677 GIM_Try, /*On fail goto*//*Label 629*/ 16064, // Rule ID 13585 // 7678 GIM_CheckFeatures, GIFBS_HasAVX, 7679 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_sse_rsqrt_ss, 7680 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 7681 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 7682 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 7683 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 7684 // (intrinsic_wo_chain:{ *:[v4f32] } 7256:{ *:[iPTR] }, VR128:{ *:[v4f32] }:$src) => (VRSQRTSSr_Int:{ *:[v4f32] } VR128:{ *:[v4f32] }:$src, VR128:{ *:[v4f32] }:$src) 7685 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VRSQRTSSr_Int, 7686 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 7687 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src 7688 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src 7689 GIR_EraseFromParent, /*InsnID*/0, 7690 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7691 // GIR_Coverage, 13585, 7692 GIR_Done, 7693 // Label 629: @16064 7694 GIM_Try, /*On fail goto*//*Label 630*/ 16108, // Rule ID 13599 // 7695 GIM_CheckFeatures, GIFBS_UseSSE1, 7696 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_sse_rcp_ss, 7697 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 7698 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 7699 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 7700 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 7701 // (intrinsic_wo_chain:{ *:[v4f32] } 7254:{ *:[iPTR] }, VR128:{ *:[v4f32] }:$src) => (RCPSSr_Int:{ *:[v4f32] } VR128:{ *:[v4f32] }:$src, VR128:{ *:[v4f32] }:$src) 7702 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::RCPSSr_Int, 7703 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 7704 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src 7705 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src 7706 GIR_EraseFromParent, /*InsnID*/0, 7707 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7708 // GIR_Coverage, 13599, 7709 GIR_Done, 7710 // Label 630: @16108 7711 GIM_Try, /*On fail goto*//*Label 631*/ 16152, // Rule ID 13601 // 7712 GIM_CheckFeatures, GIFBS_HasAVX, 7713 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_sse_rcp_ss, 7714 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 7715 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 7716 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 7717 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 7718 // (intrinsic_wo_chain:{ *:[v4f32] } 7254:{ *:[iPTR] }, VR128:{ *:[v4f32] }:$src) => (VRCPSSr_Int:{ *:[v4f32] } VR128:{ *:[v4f32] }:$src, VR128:{ *:[v4f32] }:$src) 7719 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VRCPSSr_Int, 7720 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 7721 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src 7722 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src 7723 GIR_EraseFromParent, /*InsnID*/0, 7724 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7725 // GIR_Coverage, 13601, 7726 GIR_Done, 7727 // Label 631: @16152 7728 GIM_Reject, 7729 // Label 604: @16153 7730 GIM_Try, /*On fail goto*//*Label 632*/ 19061, 7731 GIM_CheckNumOperands, /*MI*/0, /*Expected*/4, 7732 GIM_Try, /*On fail goto*//*Label 633*/ 16205, // Rule ID 2810 // 7733 GIM_CheckFeatures, GIFBS_HasAES_HasAVX, 7734 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_aesni_aeskeygenassist, 7735 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 7736 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 7737 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 7738 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 7739 // MIs[0] src2 7740 GIM_CheckIsImm, /*MI*/0, /*Op*/3, 7741 // (intrinsic_wo_chain:{ *:[v2i64] } 6361:{ *:[iPTR] }, VR128:{ *:[v2i64] }:$src1, (timm:{ *:[i8] }):$src2) => (VAESKEYGENASSIST128rr:{ *:[v2i64] } VR128:{ *:[v2i64] }:$src1, (timm:{ *:[i8] }):$src2) 7742 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VAESKEYGENASSIST128rr, 7743 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 7744 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 7745 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src2 7746 GIR_EraseFromParent, /*InsnID*/0, 7747 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7748 // GIR_Coverage, 2810, 7749 GIR_Done, 7750 // Label 633: @16205 7751 GIM_Try, /*On fail goto*//*Label 634*/ 16252, // Rule ID 2812 // 7752 GIM_CheckFeatures, GIFBS_HasAES_NoAVX, 7753 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_aesni_aeskeygenassist, 7754 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 7755 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 7756 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 7757 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 7758 // MIs[0] src2 7759 GIM_CheckIsImm, /*MI*/0, /*Op*/3, 7760 // (intrinsic_wo_chain:{ *:[v2i64] } 6361:{ *:[iPTR] }, VR128:{ *:[v2i64] }:$src1, (timm:{ *:[i8] }):$src2) => (AESKEYGENASSIST128rr:{ *:[v2i64] } VR128:{ *:[v2i64] }:$src1, (timm:{ *:[i8] }):$src2) 7761 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::AESKEYGENASSIST128rr, 7762 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 7763 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 7764 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src2 7765 GIR_EraseFromParent, /*InsnID*/0, 7766 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7767 // GIR_Coverage, 2812, 7768 GIR_Done, 7769 // Label 634: @16252 7770 GIM_Try, /*On fail goto*//*Label 635*/ 16304, // Rule ID 82 // 7771 GIM_CheckFeatures, GIFBS_HasBMI2, 7772 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_bmi_pdep_32, 7773 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, 7774 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 7775 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 7776 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 7777 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR32RegClassID, 7778 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::GR32RegClassID, 7779 // (intrinsic_wo_chain:{ *:[i32] } 7088:{ *:[iPTR] }, GR32:{ *:[i32] }:$src1, GR32:{ *:[i32] }:$src2) => (PDEP32rr:{ *:[i32] } GR32:{ *:[i32] }:$src1, GR32:{ *:[i32] }:$src2) 7780 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::PDEP32rr, 7781 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 7782 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 7783 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src2 7784 GIR_EraseFromParent, /*InsnID*/0, 7785 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7786 // GIR_Coverage, 82, 7787 GIR_Done, 7788 // Label 635: @16304 7789 GIM_Try, /*On fail goto*//*Label 636*/ 16356, // Rule ID 84 // 7790 GIM_CheckFeatures, GIFBS_HasBMI2, 7791 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_bmi_pdep_64, 7792 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, 7793 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 7794 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, 7795 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID, 7796 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR64RegClassID, 7797 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::GR64RegClassID, 7798 // (intrinsic_wo_chain:{ *:[i64] } 7089:{ *:[iPTR] }, GR64:{ *:[i64] }:$src1, GR64:{ *:[i64] }:$src2) => (PDEP64rr:{ *:[i64] } GR64:{ *:[i64] }:$src1, GR64:{ *:[i64] }:$src2) 7799 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::PDEP64rr, 7800 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 7801 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 7802 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src2 7803 GIR_EraseFromParent, /*InsnID*/0, 7804 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7805 // GIR_Coverage, 84, 7806 GIR_Done, 7807 // Label 636: @16356 7808 GIM_Try, /*On fail goto*//*Label 637*/ 16408, // Rule ID 86 // 7809 GIM_CheckFeatures, GIFBS_HasBMI2, 7810 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_bmi_pext_32, 7811 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, 7812 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 7813 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 7814 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 7815 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR32RegClassID, 7816 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::GR32RegClassID, 7817 // (intrinsic_wo_chain:{ *:[i32] } 7090:{ *:[iPTR] }, GR32:{ *:[i32] }:$src1, GR32:{ *:[i32] }:$src2) => (PEXT32rr:{ *:[i32] } GR32:{ *:[i32] }:$src1, GR32:{ *:[i32] }:$src2) 7818 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::PEXT32rr, 7819 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 7820 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 7821 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src2 7822 GIR_EraseFromParent, /*InsnID*/0, 7823 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7824 // GIR_Coverage, 86, 7825 GIR_Done, 7826 // Label 637: @16408 7827 GIM_Try, /*On fail goto*//*Label 638*/ 16460, // Rule ID 88 // 7828 GIM_CheckFeatures, GIFBS_HasBMI2, 7829 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_bmi_pext_64, 7830 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, 7831 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 7832 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, 7833 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID, 7834 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR64RegClassID, 7835 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::GR64RegClassID, 7836 // (intrinsic_wo_chain:{ *:[i64] } 7091:{ *:[iPTR] }, GR64:{ *:[i64] }:$src1, GR64:{ *:[i64] }:$src2) => (PEXT64rr:{ *:[i64] } GR64:{ *:[i64] }:$src1, GR64:{ *:[i64] }:$src2) 7837 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::PEXT64rr, 7838 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 7839 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 7840 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src2 7841 GIR_EraseFromParent, /*InsnID*/0, 7842 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7843 // GIR_Coverage, 88, 7844 GIR_Done, 7845 // Label 638: @16460 7846 GIM_Try, /*On fail goto*//*Label 639*/ 16512, // Rule ID 2481 // 7847 GIM_CheckFeatures, GIFBS_HasAVX, 7848 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_ssse3_psign_b_128, 7849 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, 7850 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 7851 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, 7852 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 7853 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 7854 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR128RegClassID, 7855 // (intrinsic_wo_chain:{ *:[v16i8] } 7394:{ *:[iPTR] }, VR128:{ *:[v16i8] }:$src1, VR128:{ *:[v16i8] }:$src2) => (VPSIGNBrr:{ *:[v16i8] } VR128:{ *:[v16i8] }:$src1, VR128:{ *:[v16i8] }:$src2) 7856 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VPSIGNBrr, 7857 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 7858 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 7859 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src2 7860 GIR_EraseFromParent, /*InsnID*/0, 7861 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7862 // GIR_Coverage, 2481, 7863 GIR_Done, 7864 // Label 639: @16512 7865 GIM_Try, /*On fail goto*//*Label 640*/ 16564, // Rule ID 2483 // 7866 GIM_CheckFeatures, GIFBS_HasAVX, 7867 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_ssse3_psign_w_128, 7868 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, 7869 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 7870 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, 7871 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 7872 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 7873 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR128RegClassID, 7874 // (intrinsic_wo_chain:{ *:[v8i16] } 7398:{ *:[iPTR] }, VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2) => (VPSIGNWrr:{ *:[v8i16] } VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2) 7875 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VPSIGNWrr, 7876 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 7877 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 7878 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src2 7879 GIR_EraseFromParent, /*InsnID*/0, 7880 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7881 // GIR_Coverage, 2483, 7882 GIR_Done, 7883 // Label 640: @16564 7884 GIM_Try, /*On fail goto*//*Label 641*/ 16616, // Rule ID 2485 // 7885 GIM_CheckFeatures, GIFBS_HasAVX, 7886 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_ssse3_psign_d_128, 7887 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 7888 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 7889 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 7890 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 7891 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 7892 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR128RegClassID, 7893 // (intrinsic_wo_chain:{ *:[v4i32] } 7396:{ *:[iPTR] }, VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2) => (VPSIGNDrr:{ *:[v4i32] } VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2) 7894 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VPSIGNDrr, 7895 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 7896 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 7897 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src2 7898 GIR_EraseFromParent, /*InsnID*/0, 7899 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7900 // GIR_Coverage, 2485, 7901 GIR_Done, 7902 // Label 641: @16616 7903 GIM_Try, /*On fail goto*//*Label 642*/ 16668, // Rule ID 2487 // 7904 GIM_CheckFeatures, GIFBS_HasAVX, 7905 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_ssse3_phadd_sw_128, 7906 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, 7907 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 7908 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, 7909 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 7910 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 7911 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR128RegClassID, 7912 // (intrinsic_wo_chain:{ *:[v8i16] } 7378:{ *:[iPTR] }, VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2) => (VPHADDSWrr:{ *:[v8i16] } VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2) 7913 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VPHADDSWrr, 7914 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 7915 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 7916 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src2 7917 GIR_EraseFromParent, /*InsnID*/0, 7918 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7919 // GIR_Coverage, 2487, 7920 GIR_Done, 7921 // Label 642: @16668 7922 GIM_Try, /*On fail goto*//*Label 643*/ 16720, // Rule ID 2489 // 7923 GIM_CheckFeatures, GIFBS_HasAVX, 7924 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_ssse3_phsub_sw_128, 7925 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, 7926 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 7927 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, 7928 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 7929 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 7930 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR128RegClassID, 7931 // (intrinsic_wo_chain:{ *:[v8i16] } 7384:{ *:[iPTR] }, VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2) => (VPHSUBSWrr:{ *:[v8i16] } VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2) 7932 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VPHSUBSWrr, 7933 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 7934 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 7935 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src2 7936 GIR_EraseFromParent, /*InsnID*/0, 7937 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7938 // GIR_Coverage, 2489, 7939 GIR_Done, 7940 // Label 643: @16720 7941 GIM_Try, /*On fail goto*//*Label 644*/ 16772, // Rule ID 2505 // 7942 GIM_CheckFeatures, GIFBS_HasAVX2, 7943 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_avx2_psign_b, 7944 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v32s8, 7945 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v32s8, 7946 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v32s8, 7947 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID, 7948 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID, 7949 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR256RegClassID, 7950 // (intrinsic_wo_chain:{ *:[v32i8] } 6466:{ *:[iPTR] }, VR256:{ *:[v32i8] }:$src1, VR256:{ *:[v32i8] }:$src2) => (VPSIGNBYrr:{ *:[v32i8] } VR256:{ *:[v32i8] }:$src1, VR256:{ *:[v32i8] }:$src2) 7951 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VPSIGNBYrr, 7952 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 7953 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 7954 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src2 7955 GIR_EraseFromParent, /*InsnID*/0, 7956 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7957 // GIR_Coverage, 2505, 7958 GIR_Done, 7959 // Label 644: @16772 7960 GIM_Try, /*On fail goto*//*Label 645*/ 16824, // Rule ID 2507 // 7961 GIM_CheckFeatures, GIFBS_HasAVX2, 7962 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_avx2_psign_w, 7963 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s16, 7964 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s16, 7965 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s16, 7966 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID, 7967 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID, 7968 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR256RegClassID, 7969 // (intrinsic_wo_chain:{ *:[v16i16] } 6468:{ *:[iPTR] }, VR256:{ *:[v16i16] }:$src1, VR256:{ *:[v16i16] }:$src2) => (VPSIGNWYrr:{ *:[v16i16] } VR256:{ *:[v16i16] }:$src1, VR256:{ *:[v16i16] }:$src2) 7970 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VPSIGNWYrr, 7971 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 7972 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 7973 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src2 7974 GIR_EraseFromParent, /*InsnID*/0, 7975 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7976 // GIR_Coverage, 2507, 7977 GIR_Done, 7978 // Label 645: @16824 7979 GIM_Try, /*On fail goto*//*Label 646*/ 16876, // Rule ID 2509 // 7980 GIM_CheckFeatures, GIFBS_HasAVX2, 7981 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_avx2_psign_d, 7982 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s32, 7983 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s32, 7984 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s32, 7985 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID, 7986 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID, 7987 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR256RegClassID, 7988 // (intrinsic_wo_chain:{ *:[v8i32] } 6467:{ *:[iPTR] }, VR256:{ *:[v8i32] }:$src1, VR256:{ *:[v8i32] }:$src2) => (VPSIGNDYrr:{ *:[v8i32] } VR256:{ *:[v8i32] }:$src1, VR256:{ *:[v8i32] }:$src2) 7989 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VPSIGNDYrr, 7990 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 7991 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 7992 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src2 7993 GIR_EraseFromParent, /*InsnID*/0, 7994 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7995 // GIR_Coverage, 2509, 7996 GIR_Done, 7997 // Label 646: @16876 7998 GIM_Try, /*On fail goto*//*Label 647*/ 16928, // Rule ID 2511 // 7999 GIM_CheckFeatures, GIFBS_HasAVX2, 8000 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_avx2_phadd_sw, 8001 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s16, 8002 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s16, 8003 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s16, 8004 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID, 8005 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID, 8006 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR256RegClassID, 8007 // (intrinsic_wo_chain:{ *:[v16i16] } 6453:{ *:[iPTR] }, VR256:{ *:[v16i16] }:$src1, VR256:{ *:[v16i16] }:$src2) => (VPHADDSWYrr:{ *:[v16i16] } VR256:{ *:[v16i16] }:$src1, VR256:{ *:[v16i16] }:$src2) 8008 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VPHADDSWYrr, 8009 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 8010 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 8011 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src2 8012 GIR_EraseFromParent, /*InsnID*/0, 8013 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8014 // GIR_Coverage, 2511, 8015 GIR_Done, 8016 // Label 647: @16928 8017 GIM_Try, /*On fail goto*//*Label 648*/ 16980, // Rule ID 2513 // 8018 GIM_CheckFeatures, GIFBS_HasAVX2, 8019 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_avx2_phsub_sw, 8020 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s16, 8021 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s16, 8022 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s16, 8023 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID, 8024 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID, 8025 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR256RegClassID, 8026 // (intrinsic_wo_chain:{ *:[v16i16] } 6456:{ *:[iPTR] }, VR256:{ *:[v16i16] }:$src1, VR256:{ *:[v16i16] }:$src2) => (VPHSUBSWYrr:{ *:[v16i16] } VR256:{ *:[v16i16] }:$src1, VR256:{ *:[v16i16] }:$src2) 8027 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VPHSUBSWYrr, 8028 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 8029 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 8030 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src2 8031 GIR_EraseFromParent, /*InsnID*/0, 8032 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8033 // GIR_Coverage, 2513, 8034 GIR_Done, 8035 // Label 648: @16980 8036 GIM_Try, /*On fail goto*//*Label 649*/ 17032, // Rule ID 2523 // 8037 GIM_CheckFeatures, GIFBS_UseSSSE3, 8038 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_ssse3_psign_b_128, 8039 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8, 8040 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 8041 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, 8042 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 8043 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 8044 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR128RegClassID, 8045 // (intrinsic_wo_chain:{ *:[v16i8] } 7394:{ *:[iPTR] }, VR128:{ *:[v16i8] }:$src1, VR128:{ *:[v16i8] }:$src2) => (PSIGNBrr:{ *:[v16i8] } VR128:{ *:[v16i8] }:$src1, VR128:{ *:[v16i8] }:$src2) 8046 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::PSIGNBrr, 8047 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 8048 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 8049 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src2 8050 GIR_EraseFromParent, /*InsnID*/0, 8051 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8052 // GIR_Coverage, 2523, 8053 GIR_Done, 8054 // Label 649: @17032 8055 GIM_Try, /*On fail goto*//*Label 650*/ 17084, // Rule ID 2525 // 8056 GIM_CheckFeatures, GIFBS_UseSSSE3, 8057 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_ssse3_psign_w_128, 8058 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, 8059 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 8060 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, 8061 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 8062 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 8063 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR128RegClassID, 8064 // (intrinsic_wo_chain:{ *:[v8i16] } 7398:{ *:[iPTR] }, VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2) => (PSIGNWrr:{ *:[v8i16] } VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2) 8065 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::PSIGNWrr, 8066 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 8067 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 8068 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src2 8069 GIR_EraseFromParent, /*InsnID*/0, 8070 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8071 // GIR_Coverage, 2525, 8072 GIR_Done, 8073 // Label 650: @17084 8074 GIM_Try, /*On fail goto*//*Label 651*/ 17136, // Rule ID 2527 // 8075 GIM_CheckFeatures, GIFBS_UseSSSE3, 8076 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_ssse3_psign_d_128, 8077 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 8078 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 8079 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 8080 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 8081 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 8082 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR128RegClassID, 8083 // (intrinsic_wo_chain:{ *:[v4i32] } 7396:{ *:[iPTR] }, VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2) => (PSIGNDrr:{ *:[v4i32] } VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2) 8084 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::PSIGNDrr, 8085 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 8086 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 8087 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src2 8088 GIR_EraseFromParent, /*InsnID*/0, 8089 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8090 // GIR_Coverage, 2527, 8091 GIR_Done, 8092 // Label 651: @17136 8093 GIM_Try, /*On fail goto*//*Label 652*/ 17188, // Rule ID 2531 // 8094 GIM_CheckFeatures, GIFBS_UseSSSE3, 8095 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_ssse3_phadd_sw_128, 8096 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, 8097 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 8098 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, 8099 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 8100 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 8101 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR128RegClassID, 8102 // (intrinsic_wo_chain:{ *:[v8i16] } 7378:{ *:[iPTR] }, VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2) => (PHADDSWrr:{ *:[v8i16] } VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2) 8103 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::PHADDSWrr, 8104 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 8105 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 8106 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src2 8107 GIR_EraseFromParent, /*InsnID*/0, 8108 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8109 // GIR_Coverage, 2531, 8110 GIR_Done, 8111 // Label 652: @17188 8112 GIM_Try, /*On fail goto*//*Label 653*/ 17240, // Rule ID 2533 // 8113 GIM_CheckFeatures, GIFBS_UseSSSE3, 8114 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_ssse3_phsub_sw_128, 8115 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, 8116 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 8117 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, 8118 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 8119 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 8120 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR128RegClassID, 8121 // (intrinsic_wo_chain:{ *:[v8i16] } 7384:{ *:[iPTR] }, VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2) => (PHSUBSWrr:{ *:[v8i16] } VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2) 8122 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::PHSUBSWrr, 8123 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 8124 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 8125 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src2 8126 GIR_EraseFromParent, /*InsnID*/0, 8127 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8128 // GIR_Coverage, 2533, 8129 GIR_Done, 8130 // Label 653: @17240 8131 GIM_Try, /*On fail goto*//*Label 654*/ 17292, // Rule ID 2761 // 8132 GIM_CheckFeatures, GIFBS_HasSSE42, 8133 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_sse42_crc32_32_8, 8134 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, 8135 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 8136 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s8, 8137 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 8138 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR32RegClassID, 8139 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::GR8RegClassID, 8140 // (intrinsic_wo_chain:{ *:[i32] } 7352:{ *:[iPTR] }, GR32:{ *:[i32] }:$src1, GR8:{ *:[i8] }:$src2) => (CRC32r32r8:{ *:[i32] } GR32:{ *:[i32] }:$src1, GR8:{ *:[i8] }:$src2) 8141 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::CRC32r32r8, 8142 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 8143 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 8144 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src2 8145 GIR_EraseFromParent, /*InsnID*/0, 8146 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8147 // GIR_Coverage, 2761, 8148 GIR_Done, 8149 // Label 654: @17292 8150 GIM_Try, /*On fail goto*//*Label 655*/ 17344, // Rule ID 2763 // 8151 GIM_CheckFeatures, GIFBS_HasSSE42, 8152 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_sse42_crc32_32_16, 8153 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, 8154 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 8155 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s16, 8156 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 8157 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR32RegClassID, 8158 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::GR16RegClassID, 8159 // (intrinsic_wo_chain:{ *:[i32] } 7350:{ *:[iPTR] }, GR32:{ *:[i32] }:$src1, GR16:{ *:[i16] }:$src2) => (CRC32r32r16:{ *:[i32] } GR32:{ *:[i32] }:$src1, GR16:{ *:[i16] }:$src2) 8160 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::CRC32r32r16, 8161 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 8162 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 8163 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src2 8164 GIR_EraseFromParent, /*InsnID*/0, 8165 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8166 // GIR_Coverage, 2763, 8167 GIR_Done, 8168 // Label 655: @17344 8169 GIM_Try, /*On fail goto*//*Label 656*/ 17396, // Rule ID 2765 // 8170 GIM_CheckFeatures, GIFBS_HasSSE42, 8171 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_sse42_crc32_32_32, 8172 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, 8173 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 8174 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 8175 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 8176 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR32RegClassID, 8177 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::GR32RegClassID, 8178 // (intrinsic_wo_chain:{ *:[i32] } 7351:{ *:[iPTR] }, GR32:{ *:[i32] }:$src1, GR32:{ *:[i32] }:$src2) => (CRC32r32r32:{ *:[i32] } GR32:{ *:[i32] }:$src1, GR32:{ *:[i32] }:$src2) 8179 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::CRC32r32r32, 8180 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 8181 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 8182 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src2 8183 GIR_EraseFromParent, /*InsnID*/0, 8184 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8185 // GIR_Coverage, 2765, 8186 GIR_Done, 8187 // Label 656: @17396 8188 GIM_Try, /*On fail goto*//*Label 657*/ 17448, // Rule ID 2767 // 8189 GIM_CheckFeatures, GIFBS_HasSSE42, 8190 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_sse42_crc32_64_64, 8191 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, 8192 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 8193 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, 8194 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID, 8195 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR64RegClassID, 8196 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::GR64RegClassID, 8197 // (intrinsic_wo_chain:{ *:[i64] } 7353:{ *:[iPTR] }, GR64:{ *:[i64] }:$src1, GR64:{ *:[i64] }:$src2) => (CRC32r64r64:{ *:[i64] } GR64:{ *:[i64] }:$src1, GR64:{ *:[i64] }:$src2) 8198 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::CRC32r64r64, 8199 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 8200 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 8201 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src2 8202 GIR_EraseFromParent, /*InsnID*/0, 8203 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8204 // GIR_Coverage, 2767, 8205 GIR_Done, 8206 // Label 657: @17448 8207 GIM_Try, /*On fail goto*//*Label 658*/ 17500, // Rule ID 2770 // 8208 GIM_CheckFeatures, GIFBS_HasSHA, 8209 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_sha1nexte, 8210 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 8211 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 8212 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 8213 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 8214 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 8215 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR128RegClassID, 8216 // (intrinsic_wo_chain:{ *:[v4i32] } 7222:{ *:[iPTR] }, VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2) => (SHA1NEXTErr:{ *:[v4i32] } VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2) 8217 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SHA1NEXTErr, 8218 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 8219 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 8220 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src2 8221 GIR_EraseFromParent, /*InsnID*/0, 8222 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8223 // GIR_Coverage, 2770, 8224 GIR_Done, 8225 // Label 658: @17500 8226 GIM_Try, /*On fail goto*//*Label 659*/ 17552, // Rule ID 2772 // 8227 GIM_CheckFeatures, GIFBS_HasSHA, 8228 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_sha1msg1, 8229 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 8230 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 8231 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 8232 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 8233 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 8234 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR128RegClassID, 8235 // (intrinsic_wo_chain:{ *:[v4i32] } 7220:{ *:[iPTR] }, VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2) => (SHA1MSG1rr:{ *:[v4i32] } VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2) 8236 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SHA1MSG1rr, 8237 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 8238 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 8239 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src2 8240 GIR_EraseFromParent, /*InsnID*/0, 8241 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8242 // GIR_Coverage, 2772, 8243 GIR_Done, 8244 // Label 659: @17552 8245 GIM_Try, /*On fail goto*//*Label 660*/ 17604, // Rule ID 2774 // 8246 GIM_CheckFeatures, GIFBS_HasSHA, 8247 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_sha1msg2, 8248 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 8249 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 8250 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 8251 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 8252 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 8253 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR128RegClassID, 8254 // (intrinsic_wo_chain:{ *:[v4i32] } 7221:{ *:[iPTR] }, VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2) => (SHA1MSG2rr:{ *:[v4i32] } VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2) 8255 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SHA1MSG2rr, 8256 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 8257 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 8258 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src2 8259 GIR_EraseFromParent, /*InsnID*/0, 8260 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8261 // GIR_Coverage, 2774, 8262 GIR_Done, 8263 // Label 660: @17604 8264 GIM_Try, /*On fail goto*//*Label 661*/ 17656, // Rule ID 2778 // 8265 GIM_CheckFeatures, GIFBS_HasSHA, 8266 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_sha256msg1, 8267 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 8268 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 8269 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 8270 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 8271 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 8272 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR128RegClassID, 8273 // (intrinsic_wo_chain:{ *:[v4i32] } 7224:{ *:[iPTR] }, VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2) => (SHA256MSG1rr:{ *:[v4i32] } VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2) 8274 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SHA256MSG1rr, 8275 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 8276 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 8277 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src2 8278 GIR_EraseFromParent, /*InsnID*/0, 8279 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8280 // GIR_Coverage, 2778, 8281 GIR_Done, 8282 // Label 661: @17656 8283 GIM_Try, /*On fail goto*//*Label 662*/ 17708, // Rule ID 2780 // 8284 GIM_CheckFeatures, GIFBS_HasSHA, 8285 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_sha256msg2, 8286 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 8287 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 8288 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 8289 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 8290 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 8291 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR128RegClassID, 8292 // (intrinsic_wo_chain:{ *:[v4i32] } 7225:{ *:[iPTR] }, VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2) => (SHA256MSG2rr:{ *:[v4i32] } VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2) 8293 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SHA256MSG2rr, 8294 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 8295 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 8296 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src2 8297 GIR_EraseFromParent, /*InsnID*/0, 8298 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8299 // GIR_Coverage, 2780, 8300 GIR_Done, 8301 // Label 662: @17708 8302 GIM_Try, /*On fail goto*//*Label 663*/ 17760, // Rule ID 2782 // 8303 GIM_CheckFeatures, GIFBS_HasAES_HasAVX_NoVLX_Or_NoVAES, 8304 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_aesni_aesenc, 8305 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 8306 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 8307 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, 8308 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 8309 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 8310 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR128RegClassID, 8311 // (intrinsic_wo_chain:{ *:[v2i64] } 6354:{ *:[iPTR] }, VR128:{ *:[v2i64] }:$src1, VR128:{ *:[v2i64] }:$src2) => (VAESENCrr:{ *:[v2i64] } VR128:{ *:[v2i64] }:$src1, VR128:{ *:[v2i64] }:$src2) 8312 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VAESENCrr, 8313 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 8314 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 8315 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src2 8316 GIR_EraseFromParent, /*InsnID*/0, 8317 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8318 // GIR_Coverage, 2782, 8319 GIR_Done, 8320 // Label 663: @17760 8321 GIM_Try, /*On fail goto*//*Label 664*/ 17812, // Rule ID 2784 // 8322 GIM_CheckFeatures, GIFBS_HasAES_HasAVX_NoVLX_Or_NoVAES, 8323 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_aesni_aesenclast, 8324 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 8325 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 8326 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, 8327 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 8328 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 8329 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR128RegClassID, 8330 // (intrinsic_wo_chain:{ *:[v2i64] } 6357:{ *:[iPTR] }, VR128:{ *:[v2i64] }:$src1, VR128:{ *:[v2i64] }:$src2) => (VAESENCLASTrr:{ *:[v2i64] } VR128:{ *:[v2i64] }:$src1, VR128:{ *:[v2i64] }:$src2) 8331 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VAESENCLASTrr, 8332 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 8333 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 8334 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src2 8335 GIR_EraseFromParent, /*InsnID*/0, 8336 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8337 // GIR_Coverage, 2784, 8338 GIR_Done, 8339 // Label 664: @17812 8340 GIM_Try, /*On fail goto*//*Label 665*/ 17864, // Rule ID 2786 // 8341 GIM_CheckFeatures, GIFBS_HasAES_HasAVX_NoVLX_Or_NoVAES, 8342 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_aesni_aesdec, 8343 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 8344 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 8345 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, 8346 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 8347 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 8348 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR128RegClassID, 8349 // (intrinsic_wo_chain:{ *:[v2i64] } 6348:{ *:[iPTR] }, VR128:{ *:[v2i64] }:$src1, VR128:{ *:[v2i64] }:$src2) => (VAESDECrr:{ *:[v2i64] } VR128:{ *:[v2i64] }:$src1, VR128:{ *:[v2i64] }:$src2) 8350 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VAESDECrr, 8351 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 8352 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 8353 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src2 8354 GIR_EraseFromParent, /*InsnID*/0, 8355 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8356 // GIR_Coverage, 2786, 8357 GIR_Done, 8358 // Label 665: @17864 8359 GIM_Try, /*On fail goto*//*Label 666*/ 17916, // Rule ID 2788 // 8360 GIM_CheckFeatures, GIFBS_HasAES_HasAVX_NoVLX_Or_NoVAES, 8361 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_aesni_aesdeclast, 8362 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 8363 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 8364 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, 8365 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 8366 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 8367 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR128RegClassID, 8368 // (intrinsic_wo_chain:{ *:[v2i64] } 6351:{ *:[iPTR] }, VR128:{ *:[v2i64] }:$src1, VR128:{ *:[v2i64] }:$src2) => (VAESDECLASTrr:{ *:[v2i64] } VR128:{ *:[v2i64] }:$src1, VR128:{ *:[v2i64] }:$src2) 8369 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VAESDECLASTrr, 8370 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 8371 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 8372 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src2 8373 GIR_EraseFromParent, /*InsnID*/0, 8374 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8375 // GIR_Coverage, 2788, 8376 GIR_Done, 8377 // Label 666: @17916 8378 GIM_Try, /*On fail goto*//*Label 667*/ 17968, // Rule ID 2790 // 8379 GIM_CheckFeatures, GIFBS_HasVAES_NoVLX, 8380 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_aesni_aesenc_256, 8381 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s64, 8382 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s64, 8383 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s64, 8384 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID, 8385 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID, 8386 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR256RegClassID, 8387 // (intrinsic_wo_chain:{ *:[v4i64] } 6355:{ *:[iPTR] }, VR256:{ *:[v4i64] }:$src1, VR256:{ *:[v4i64] }:$src2) => (VAESENCYrr:{ *:[v4i64] } VR256:{ *:[v4i64] }:$src1, VR256:{ *:[v4i64] }:$src2) 8388 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VAESENCYrr, 8389 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 8390 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 8391 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src2 8392 GIR_EraseFromParent, /*InsnID*/0, 8393 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8394 // GIR_Coverage, 2790, 8395 GIR_Done, 8396 // Label 667: @17968 8397 GIM_Try, /*On fail goto*//*Label 668*/ 18020, // Rule ID 2792 // 8398 GIM_CheckFeatures, GIFBS_HasVAES_NoVLX, 8399 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_aesni_aesenclast_256, 8400 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s64, 8401 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s64, 8402 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s64, 8403 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID, 8404 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID, 8405 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR256RegClassID, 8406 // (intrinsic_wo_chain:{ *:[v4i64] } 6358:{ *:[iPTR] }, VR256:{ *:[v4i64] }:$src1, VR256:{ *:[v4i64] }:$src2) => (VAESENCLASTYrr:{ *:[v4i64] } VR256:{ *:[v4i64] }:$src1, VR256:{ *:[v4i64] }:$src2) 8407 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VAESENCLASTYrr, 8408 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 8409 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 8410 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src2 8411 GIR_EraseFromParent, /*InsnID*/0, 8412 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8413 // GIR_Coverage, 2792, 8414 GIR_Done, 8415 // Label 668: @18020 8416 GIM_Try, /*On fail goto*//*Label 669*/ 18072, // Rule ID 2794 // 8417 GIM_CheckFeatures, GIFBS_HasVAES_NoVLX, 8418 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_aesni_aesdec_256, 8419 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s64, 8420 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s64, 8421 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s64, 8422 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID, 8423 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID, 8424 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR256RegClassID, 8425 // (intrinsic_wo_chain:{ *:[v4i64] } 6349:{ *:[iPTR] }, VR256:{ *:[v4i64] }:$src1, VR256:{ *:[v4i64] }:$src2) => (VAESDECYrr:{ *:[v4i64] } VR256:{ *:[v4i64] }:$src1, VR256:{ *:[v4i64] }:$src2) 8426 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VAESDECYrr, 8427 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 8428 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 8429 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src2 8430 GIR_EraseFromParent, /*InsnID*/0, 8431 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8432 // GIR_Coverage, 2794, 8433 GIR_Done, 8434 // Label 669: @18072 8435 GIM_Try, /*On fail goto*//*Label 670*/ 18124, // Rule ID 2796 // 8436 GIM_CheckFeatures, GIFBS_HasVAES_NoVLX, 8437 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_aesni_aesdeclast_256, 8438 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s64, 8439 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s64, 8440 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s64, 8441 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID, 8442 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID, 8443 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR256RegClassID, 8444 // (intrinsic_wo_chain:{ *:[v4i64] } 6352:{ *:[iPTR] }, VR256:{ *:[v4i64] }:$src1, VR256:{ *:[v4i64] }:$src2) => (VAESDECLASTYrr:{ *:[v4i64] } VR256:{ *:[v4i64] }:$src1, VR256:{ *:[v4i64] }:$src2) 8445 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VAESDECLASTYrr, 8446 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 8447 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 8448 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src2 8449 GIR_EraseFromParent, /*InsnID*/0, 8450 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8451 // GIR_Coverage, 2796, 8452 GIR_Done, 8453 // Label 670: @18124 8454 GIM_Try, /*On fail goto*//*Label 671*/ 18176, // Rule ID 2798 // 8455 GIM_CheckFeatures, GIFBS_HasAES_NoAVX, 8456 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_aesni_aesenc, 8457 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 8458 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 8459 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, 8460 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 8461 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 8462 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR128RegClassID, 8463 // (intrinsic_wo_chain:{ *:[v2i64] } 6354:{ *:[iPTR] }, VR128:{ *:[v2i64] }:$src1, VR128:{ *:[v2i64] }:$src2) => (AESENCrr:{ *:[v2i64] } VR128:{ *:[v2i64] }:$src1, VR128:{ *:[v2i64] }:$src2) 8464 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::AESENCrr, 8465 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 8466 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 8467 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src2 8468 GIR_EraseFromParent, /*InsnID*/0, 8469 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8470 // GIR_Coverage, 2798, 8471 GIR_Done, 8472 // Label 671: @18176 8473 GIM_Try, /*On fail goto*//*Label 672*/ 18228, // Rule ID 2800 // 8474 GIM_CheckFeatures, GIFBS_HasAES_NoAVX, 8475 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_aesni_aesenclast, 8476 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 8477 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 8478 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, 8479 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 8480 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 8481 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR128RegClassID, 8482 // (intrinsic_wo_chain:{ *:[v2i64] } 6357:{ *:[iPTR] }, VR128:{ *:[v2i64] }:$src1, VR128:{ *:[v2i64] }:$src2) => (AESENCLASTrr:{ *:[v2i64] } VR128:{ *:[v2i64] }:$src1, VR128:{ *:[v2i64] }:$src2) 8483 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::AESENCLASTrr, 8484 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 8485 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 8486 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src2 8487 GIR_EraseFromParent, /*InsnID*/0, 8488 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8489 // GIR_Coverage, 2800, 8490 GIR_Done, 8491 // Label 672: @18228 8492 GIM_Try, /*On fail goto*//*Label 673*/ 18280, // Rule ID 2802 // 8493 GIM_CheckFeatures, GIFBS_HasAES_NoAVX, 8494 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_aesni_aesdec, 8495 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 8496 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 8497 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, 8498 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 8499 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 8500 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR128RegClassID, 8501 // (intrinsic_wo_chain:{ *:[v2i64] } 6348:{ *:[iPTR] }, VR128:{ *:[v2i64] }:$src1, VR128:{ *:[v2i64] }:$src2) => (AESDECrr:{ *:[v2i64] } VR128:{ *:[v2i64] }:$src1, VR128:{ *:[v2i64] }:$src2) 8502 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::AESDECrr, 8503 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 8504 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 8505 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src2 8506 GIR_EraseFromParent, /*InsnID*/0, 8507 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8508 // GIR_Coverage, 2802, 8509 GIR_Done, 8510 // Label 673: @18280 8511 GIM_Try, /*On fail goto*//*Label 674*/ 18332, // Rule ID 2804 // 8512 GIM_CheckFeatures, GIFBS_HasAES_NoAVX, 8513 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_aesni_aesdeclast, 8514 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 8515 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 8516 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, 8517 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 8518 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 8519 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR128RegClassID, 8520 // (intrinsic_wo_chain:{ *:[v2i64] } 6351:{ *:[iPTR] }, VR128:{ *:[v2i64] }:$src1, VR128:{ *:[v2i64] }:$src2) => (AESDECLASTrr:{ *:[v2i64] } VR128:{ *:[v2i64] }:$src1, VR128:{ *:[v2i64] }:$src2) 8521 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::AESDECLASTrr, 8522 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 8523 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 8524 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src2 8525 GIR_EraseFromParent, /*InsnID*/0, 8526 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8527 // GIR_Coverage, 2804, 8528 GIR_Done, 8529 // Label 674: @18332 8530 GIM_Try, /*On fail goto*//*Label 675*/ 18384, // Rule ID 2821 // 8531 GIM_CheckFeatures, GIFBS_HasSSE4A, 8532 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_sse4a_extrq, 8533 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 8534 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 8535 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, 8536 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 8537 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 8538 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR128RegClassID, 8539 // (intrinsic_wo_chain:{ *:[v2i64] } 7368:{ *:[iPTR] }, VR128:{ *:[v2i64] }:$src, VR128:{ *:[v16i8] }:$mask) => (EXTRQ:{ *:[v2i64] } VR128:{ *:[v2i64] }:$src, VR128:{ *:[v16i8] }:$mask) 8540 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::EXTRQ, 8541 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 8542 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src 8543 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // mask 8544 GIR_EraseFromParent, /*InsnID*/0, 8545 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8546 // GIR_Coverage, 2821, 8547 GIR_Done, 8548 // Label 675: @18384 8549 GIM_Try, /*On fail goto*//*Label 676*/ 18436, // Rule ID 2823 // 8550 GIM_CheckFeatures, GIFBS_HasSSE4A, 8551 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_sse4a_insertq, 8552 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 8553 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 8554 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, 8555 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 8556 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 8557 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR128RegClassID, 8558 // (intrinsic_wo_chain:{ *:[v2i64] } 7370:{ *:[iPTR] }, VR128:{ *:[v2i64] }:$src, VR128:{ *:[v2i64] }:$mask) => (INSERTQ:{ *:[v2i64] } VR128:{ *:[v2i64] }:$src, VR128:{ *:[v2i64] }:$mask) 8559 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::INSERTQ, 8560 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 8561 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src 8562 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // mask 8563 GIR_EraseFromParent, /*InsnID*/0, 8564 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8565 // GIR_Coverage, 2823, 8566 GIR_Done, 8567 // Label 676: @18436 8568 GIM_Try, /*On fail goto*//*Label 677*/ 18488, // Rule ID 11910 // 8569 GIM_CheckFeatures, GIFBS_HasVAES_HasVLX, 8570 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_aesni_aesenc, 8571 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 8572 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 8573 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, 8574 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 8575 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128XRegClassID, 8576 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR128XRegClassID, 8577 // (intrinsic_wo_chain:{ *:[v2i64] } 6354:{ *:[iPTR] }, VR128X:{ *:[v2i64] }:$src1, VR128X:{ *:[v2i64] }:$src2) => (VAESENCZ128rr:{ *:[v2i64] } VR128X:{ *:[v2i64] }:$src1, VR128X:{ *:[v2i64] }:$src2) 8578 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VAESENCZ128rr, 8579 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 8580 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 8581 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src2 8582 GIR_EraseFromParent, /*InsnID*/0, 8583 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8584 // GIR_Coverage, 11910, 8585 GIR_Done, 8586 // Label 677: @18488 8587 GIM_Try, /*On fail goto*//*Label 678*/ 18540, // Rule ID 11912 // 8588 GIM_CheckFeatures, GIFBS_HasVAES_HasVLX, 8589 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_aesni_aesenc_256, 8590 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s64, 8591 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s64, 8592 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s64, 8593 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 8594 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256XRegClassID, 8595 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR256XRegClassID, 8596 // (intrinsic_wo_chain:{ *:[v4i64] } 6355:{ *:[iPTR] }, VR256X:{ *:[v4i64] }:$src1, VR256X:{ *:[v4i64] }:$src2) => (VAESENCZ256rr:{ *:[v4i64] } VR256X:{ *:[v4i64] }:$src1, VR256X:{ *:[v4i64] }:$src2) 8597 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VAESENCZ256rr, 8598 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 8599 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 8600 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src2 8601 GIR_EraseFromParent, /*InsnID*/0, 8602 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8603 // GIR_Coverage, 11912, 8604 GIR_Done, 8605 // Label 678: @18540 8606 GIM_Try, /*On fail goto*//*Label 679*/ 18592, // Rule ID 11914 // 8607 GIM_CheckFeatures, GIFBS_HasAVX512_HasVAES, 8608 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_aesni_aesenc_512, 8609 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s64, 8610 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s64, 8611 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s64, 8612 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 8613 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR512RegClassID, 8614 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR512RegClassID, 8615 // (intrinsic_wo_chain:{ *:[v8i64] } 6356:{ *:[iPTR] }, VR512:{ *:[v8i64] }:$src1, VR512:{ *:[v8i64] }:$src2) => (VAESENCZrr:{ *:[v8i64] } VR512:{ *:[v8i64] }:$src1, VR512:{ *:[v8i64] }:$src2) 8616 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VAESENCZrr, 8617 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 8618 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 8619 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src2 8620 GIR_EraseFromParent, /*InsnID*/0, 8621 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8622 // GIR_Coverage, 11914, 8623 GIR_Done, 8624 // Label 679: @18592 8625 GIM_Try, /*On fail goto*//*Label 680*/ 18644, // Rule ID 11916 // 8626 GIM_CheckFeatures, GIFBS_HasVAES_HasVLX, 8627 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_aesni_aesenclast, 8628 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 8629 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 8630 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, 8631 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 8632 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128XRegClassID, 8633 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR128XRegClassID, 8634 // (intrinsic_wo_chain:{ *:[v2i64] } 6357:{ *:[iPTR] }, VR128X:{ *:[v2i64] }:$src1, VR128X:{ *:[v2i64] }:$src2) => (VAESENCLASTZ128rr:{ *:[v2i64] } VR128X:{ *:[v2i64] }:$src1, VR128X:{ *:[v2i64] }:$src2) 8635 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VAESENCLASTZ128rr, 8636 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 8637 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 8638 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src2 8639 GIR_EraseFromParent, /*InsnID*/0, 8640 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8641 // GIR_Coverage, 11916, 8642 GIR_Done, 8643 // Label 680: @18644 8644 GIM_Try, /*On fail goto*//*Label 681*/ 18696, // Rule ID 11918 // 8645 GIM_CheckFeatures, GIFBS_HasVAES_HasVLX, 8646 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_aesni_aesenclast_256, 8647 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s64, 8648 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s64, 8649 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s64, 8650 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 8651 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256XRegClassID, 8652 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR256XRegClassID, 8653 // (intrinsic_wo_chain:{ *:[v4i64] } 6358:{ *:[iPTR] }, VR256X:{ *:[v4i64] }:$src1, VR256X:{ *:[v4i64] }:$src2) => (VAESENCLASTZ256rr:{ *:[v4i64] } VR256X:{ *:[v4i64] }:$src1, VR256X:{ *:[v4i64] }:$src2) 8654 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VAESENCLASTZ256rr, 8655 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 8656 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 8657 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src2 8658 GIR_EraseFromParent, /*InsnID*/0, 8659 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8660 // GIR_Coverage, 11918, 8661 GIR_Done, 8662 // Label 681: @18696 8663 GIM_Try, /*On fail goto*//*Label 682*/ 18748, // Rule ID 11920 // 8664 GIM_CheckFeatures, GIFBS_HasAVX512_HasVAES, 8665 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_aesni_aesenclast_512, 8666 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s64, 8667 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s64, 8668 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s64, 8669 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 8670 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR512RegClassID, 8671 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR512RegClassID, 8672 // (intrinsic_wo_chain:{ *:[v8i64] } 6359:{ *:[iPTR] }, VR512:{ *:[v8i64] }:$src1, VR512:{ *:[v8i64] }:$src2) => (VAESENCLASTZrr:{ *:[v8i64] } VR512:{ *:[v8i64] }:$src1, VR512:{ *:[v8i64] }:$src2) 8673 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VAESENCLASTZrr, 8674 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 8675 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 8676 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src2 8677 GIR_EraseFromParent, /*InsnID*/0, 8678 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8679 // GIR_Coverage, 11920, 8680 GIR_Done, 8681 // Label 682: @18748 8682 GIM_Try, /*On fail goto*//*Label 683*/ 18800, // Rule ID 11922 // 8683 GIM_CheckFeatures, GIFBS_HasVAES_HasVLX, 8684 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_aesni_aesdec, 8685 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 8686 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 8687 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, 8688 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 8689 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128XRegClassID, 8690 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR128XRegClassID, 8691 // (intrinsic_wo_chain:{ *:[v2i64] } 6348:{ *:[iPTR] }, VR128X:{ *:[v2i64] }:$src1, VR128X:{ *:[v2i64] }:$src2) => (VAESDECZ128rr:{ *:[v2i64] } VR128X:{ *:[v2i64] }:$src1, VR128X:{ *:[v2i64] }:$src2) 8692 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VAESDECZ128rr, 8693 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 8694 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 8695 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src2 8696 GIR_EraseFromParent, /*InsnID*/0, 8697 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8698 // GIR_Coverage, 11922, 8699 GIR_Done, 8700 // Label 683: @18800 8701 GIM_Try, /*On fail goto*//*Label 684*/ 18852, // Rule ID 11924 // 8702 GIM_CheckFeatures, GIFBS_HasVAES_HasVLX, 8703 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_aesni_aesdec_256, 8704 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s64, 8705 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s64, 8706 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s64, 8707 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 8708 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256XRegClassID, 8709 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR256XRegClassID, 8710 // (intrinsic_wo_chain:{ *:[v4i64] } 6349:{ *:[iPTR] }, VR256X:{ *:[v4i64] }:$src1, VR256X:{ *:[v4i64] }:$src2) => (VAESDECZ256rr:{ *:[v4i64] } VR256X:{ *:[v4i64] }:$src1, VR256X:{ *:[v4i64] }:$src2) 8711 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VAESDECZ256rr, 8712 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 8713 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 8714 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src2 8715 GIR_EraseFromParent, /*InsnID*/0, 8716 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8717 // GIR_Coverage, 11924, 8718 GIR_Done, 8719 // Label 684: @18852 8720 GIM_Try, /*On fail goto*//*Label 685*/ 18904, // Rule ID 11926 // 8721 GIM_CheckFeatures, GIFBS_HasAVX512_HasVAES, 8722 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_aesni_aesdec_512, 8723 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s64, 8724 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s64, 8725 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s64, 8726 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 8727 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR512RegClassID, 8728 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR512RegClassID, 8729 // (intrinsic_wo_chain:{ *:[v8i64] } 6350:{ *:[iPTR] }, VR512:{ *:[v8i64] }:$src1, VR512:{ *:[v8i64] }:$src2) => (VAESDECZrr:{ *:[v8i64] } VR512:{ *:[v8i64] }:$src1, VR512:{ *:[v8i64] }:$src2) 8730 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VAESDECZrr, 8731 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 8732 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 8733 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src2 8734 GIR_EraseFromParent, /*InsnID*/0, 8735 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8736 // GIR_Coverage, 11926, 8737 GIR_Done, 8738 // Label 685: @18904 8739 GIM_Try, /*On fail goto*//*Label 686*/ 18956, // Rule ID 11928 // 8740 GIM_CheckFeatures, GIFBS_HasVAES_HasVLX, 8741 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_aesni_aesdeclast, 8742 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 8743 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 8744 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, 8745 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 8746 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128XRegClassID, 8747 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR128XRegClassID, 8748 // (intrinsic_wo_chain:{ *:[v2i64] } 6351:{ *:[iPTR] }, VR128X:{ *:[v2i64] }:$src1, VR128X:{ *:[v2i64] }:$src2) => (VAESDECLASTZ128rr:{ *:[v2i64] } VR128X:{ *:[v2i64] }:$src1, VR128X:{ *:[v2i64] }:$src2) 8749 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VAESDECLASTZ128rr, 8750 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 8751 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 8752 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src2 8753 GIR_EraseFromParent, /*InsnID*/0, 8754 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8755 // GIR_Coverage, 11928, 8756 GIR_Done, 8757 // Label 686: @18956 8758 GIM_Try, /*On fail goto*//*Label 687*/ 19008, // Rule ID 11930 // 8759 GIM_CheckFeatures, GIFBS_HasVAES_HasVLX, 8760 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_aesni_aesdeclast_256, 8761 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s64, 8762 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s64, 8763 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s64, 8764 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 8765 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256XRegClassID, 8766 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR256XRegClassID, 8767 // (intrinsic_wo_chain:{ *:[v4i64] } 6352:{ *:[iPTR] }, VR256X:{ *:[v4i64] }:$src1, VR256X:{ *:[v4i64] }:$src2) => (VAESDECLASTZ256rr:{ *:[v4i64] } VR256X:{ *:[v4i64] }:$src1, VR256X:{ *:[v4i64] }:$src2) 8768 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VAESDECLASTZ256rr, 8769 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 8770 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 8771 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src2 8772 GIR_EraseFromParent, /*InsnID*/0, 8773 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8774 // GIR_Coverage, 11930, 8775 GIR_Done, 8776 // Label 687: @19008 8777 GIM_Try, /*On fail goto*//*Label 688*/ 19060, // Rule ID 11932 // 8778 GIM_CheckFeatures, GIFBS_HasAVX512_HasVAES, 8779 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_aesni_aesdeclast_512, 8780 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s64, 8781 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s64, 8782 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s64, 8783 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 8784 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR512RegClassID, 8785 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR512RegClassID, 8786 // (intrinsic_wo_chain:{ *:[v8i64] } 6353:{ *:[iPTR] }, VR512:{ *:[v8i64] }:$src1, VR512:{ *:[v8i64] }:$src2) => (VAESDECLASTZrr:{ *:[v8i64] } VR512:{ *:[v8i64] }:$src1, VR512:{ *:[v8i64] }:$src2) 8787 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VAESDECLASTZrr, 8788 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 8789 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 8790 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src2 8791 GIR_EraseFromParent, /*InsnID*/0, 8792 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8793 // GIR_Coverage, 11932, 8794 GIR_Done, 8795 // Label 688: @19060 8796 GIM_Reject, 8797 // Label 632: @19061 8798 GIM_Try, /*On fail goto*//*Label 689*/ 21027, 8799 GIM_CheckNumOperands, /*MI*/0, /*Expected*/5, 8800 GIM_Try, /*On fail goto*//*Label 690*/ 19125, // Rule ID 1511 // 8801 GIM_CheckFeatures, GIFBS_HasAVX, 8802 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_sse_cmp_ss, 8803 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 8804 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 8805 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 8806 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 8807 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 8808 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR128RegClassID, 8809 // MIs[0] cc 8810 GIM_CheckIsImm, /*MI*/0, /*Op*/4, 8811 // (intrinsic_wo_chain:{ *:[v4f32] } 7229:{ *:[iPTR] }, VR128:{ *:[v4f32] }:$src1, VR128:{ *:[v4f32] }:$src, (timm:{ *:[i8] }):$cc) => (VCMPSSrr_Int:{ *:[v4f32] } VR128:{ *:[v4f32] }:$src1, VR128:{ *:[v4f32] }:$src, (timm:{ *:[i8] }):$cc) 8812 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VCMPSSrr_Int, 8813 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 8814 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 8815 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src 8816 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // cc 8817 GIR_EraseFromParent, /*InsnID*/0, 8818 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8819 // GIR_Coverage, 1511, 8820 GIR_Done, 8821 // Label 690: @19125 8822 GIM_Try, /*On fail goto*//*Label 691*/ 19184, // Rule ID 1513 // 8823 GIM_CheckFeatures, GIFBS_HasAVX, 8824 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_sse2_cmp_sd, 8825 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 8826 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 8827 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, 8828 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 8829 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 8830 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR128RegClassID, 8831 // MIs[0] cc 8832 GIM_CheckIsImm, /*MI*/0, /*Op*/4, 8833 // (intrinsic_wo_chain:{ *:[v2f64] } 7267:{ *:[iPTR] }, VR128:{ *:[v2f64] }:$src1, VR128:{ *:[v2f64] }:$src, (timm:{ *:[i8] }):$cc) => (VCMPSDrr_Int:{ *:[v2f64] } VR128:{ *:[v2f64] }:$src1, VR128:{ *:[v2f64] }:$src, (timm:{ *:[i8] }):$cc) 8834 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VCMPSDrr_Int, 8835 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 8836 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 8837 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src 8838 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // cc 8839 GIR_EraseFromParent, /*InsnID*/0, 8840 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8841 // GIR_Coverage, 1513, 8842 GIR_Done, 8843 // Label 691: @19184 8844 GIM_Try, /*On fail goto*//*Label 692*/ 19243, // Rule ID 1515 // 8845 GIM_CheckFeatures, GIFBS_UseSSE1, 8846 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_sse_cmp_ss, 8847 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 8848 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 8849 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 8850 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 8851 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 8852 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR128RegClassID, 8853 // MIs[0] cc 8854 GIM_CheckIsImm, /*MI*/0, /*Op*/4, 8855 // (intrinsic_wo_chain:{ *:[v4f32] } 7229:{ *:[iPTR] }, VR128:{ *:[v4f32] }:$src1, VR128:{ *:[v4f32] }:$src, (timm:{ *:[i8] }):$cc) => (CMPSSrr_Int:{ *:[v4f32] } VR128:{ *:[v4f32] }:$src1, VR128:{ *:[v4f32] }:$src, (timm:{ *:[i8] }):$cc) 8856 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::CMPSSrr_Int, 8857 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 8858 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 8859 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src 8860 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // cc 8861 GIR_EraseFromParent, /*InsnID*/0, 8862 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8863 // GIR_Coverage, 1515, 8864 GIR_Done, 8865 // Label 692: @19243 8866 GIM_Try, /*On fail goto*//*Label 693*/ 19302, // Rule ID 1517 // 8867 GIM_CheckFeatures, GIFBS_UseSSE2, 8868 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_sse2_cmp_sd, 8869 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 8870 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 8871 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, 8872 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 8873 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 8874 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR128RegClassID, 8875 // MIs[0] cc 8876 GIM_CheckIsImm, /*MI*/0, /*Op*/4, 8877 // (intrinsic_wo_chain:{ *:[v2f64] } 7267:{ *:[iPTR] }, VR128:{ *:[v2f64] }:$src1, VR128:{ *:[v2f64] }:$src, (timm:{ *:[i8] }):$cc) => (CMPSDrr_Int:{ *:[v2f64] } VR128:{ *:[v2f64] }:$src1, VR128:{ *:[v2f64] }:$src, (timm:{ *:[i8] }):$cc) 8878 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::CMPSDrr_Int, 8879 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 8880 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 8881 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src 8882 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // cc 8883 GIR_EraseFromParent, /*InsnID*/0, 8884 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8885 // GIR_Coverage, 1517, 8886 GIR_Done, 8887 // Label 693: @19302 8888 GIM_Try, /*On fail goto*//*Label 694*/ 19361, // Rule ID 2702 // 8889 GIM_CheckFeatures, GIFBS_HasAVX, 8890 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_sse41_mpsadbw, 8891 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, 8892 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 8893 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, 8894 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 8895 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 8896 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR128RegClassID, 8897 // MIs[0] src3 8898 GIM_CheckIsImm, /*MI*/0, /*Op*/4, 8899 // (intrinsic_wo_chain:{ *:[v8i16] } 7339:{ *:[iPTR] }, VR128:{ *:[v16i8] }:$src1, VR128:{ *:[v16i8] }:$src2, (timm:{ *:[i8] }):$src3) => (VMPSADBWrri:{ *:[v8i16] } VR128:{ *:[v16i8] }:$src1, VR128:{ *:[v16i8] }:$src2, (timm:{ *:[i8] }):$src3) 8900 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VMPSADBWrri, 8901 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 8902 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 8903 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src2 8904 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src3 8905 GIR_EraseFromParent, /*InsnID*/0, 8906 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8907 // GIR_Coverage, 2702, 8908 GIR_Done, 8909 // Label 694: @19361 8910 GIM_Try, /*On fail goto*//*Label 695*/ 19420, // Rule ID 2704 // 8911 GIM_CheckFeatures, GIFBS_HasAVX, 8912 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_sse41_dpps, 8913 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 8914 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 8915 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 8916 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 8917 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 8918 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR128RegClassID, 8919 // MIs[0] src3 8920 GIM_CheckIsImm, /*MI*/0, /*Op*/4, 8921 // (intrinsic_wo_chain:{ *:[v4f32] } 7337:{ *:[iPTR] }, VR128:{ *:[v4f32] }:$src1, VR128:{ *:[v4f32] }:$src2, (timm:{ *:[i8] }):$src3) => (VDPPSrri:{ *:[v4f32] } VR128:{ *:[v4f32] }:$src1, VR128:{ *:[v4f32] }:$src2, (timm:{ *:[i8] }):$src3) 8922 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VDPPSrri, 8923 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 8924 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 8925 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src2 8926 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src3 8927 GIR_EraseFromParent, /*InsnID*/0, 8928 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8929 // GIR_Coverage, 2704, 8930 GIR_Done, 8931 // Label 695: @19420 8932 GIM_Try, /*On fail goto*//*Label 696*/ 19479, // Rule ID 2706 // 8933 GIM_CheckFeatures, GIFBS_HasAVX, 8934 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_sse41_dppd, 8935 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 8936 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 8937 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, 8938 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 8939 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 8940 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR128RegClassID, 8941 // MIs[0] src3 8942 GIM_CheckIsImm, /*MI*/0, /*Op*/4, 8943 // (intrinsic_wo_chain:{ *:[v2f64] } 7336:{ *:[iPTR] }, VR128:{ *:[v2f64] }:$src1, VR128:{ *:[v2f64] }:$src2, (timm:{ *:[i8] }):$src3) => (VDPPDrri:{ *:[v2f64] } VR128:{ *:[v2f64] }:$src1, VR128:{ *:[v2f64] }:$src2, (timm:{ *:[i8] }):$src3) 8944 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VDPPDrri, 8945 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 8946 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 8947 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src2 8948 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src3 8949 GIR_EraseFromParent, /*InsnID*/0, 8950 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8951 // GIR_Coverage, 2706, 8952 GIR_Done, 8953 // Label 696: @19479 8954 GIM_Try, /*On fail goto*//*Label 697*/ 19538, // Rule ID 2708 // 8955 GIM_CheckFeatures, GIFBS_HasAVX, 8956 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_avx_dp_ps_256, 8957 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s32, 8958 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s32, 8959 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s32, 8960 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID, 8961 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID, 8962 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR256RegClassID, 8963 // MIs[0] src3 8964 GIM_CheckIsImm, /*MI*/0, /*Op*/4, 8965 // (intrinsic_wo_chain:{ *:[v8f32] } 6373:{ *:[iPTR] }, VR256:{ *:[v8f32] }:$src1, VR256:{ *:[v8f32] }:$src2, (timm:{ *:[i8] }):$src3) => (VDPPSYrri:{ *:[v8f32] } VR256:{ *:[v8f32] }:$src1, VR256:{ *:[v8f32] }:$src2, (timm:{ *:[i8] }):$src3) 8966 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VDPPSYrri, 8967 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 8968 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 8969 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src2 8970 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src3 8971 GIR_EraseFromParent, /*InsnID*/0, 8972 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8973 // GIR_Coverage, 2708, 8974 GIR_Done, 8975 // Label 697: @19538 8976 GIM_Try, /*On fail goto*//*Label 698*/ 19597, // Rule ID 2710 // 8977 GIM_CheckFeatures, GIFBS_HasAVX2, 8978 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_avx2_mpsadbw, 8979 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s16, 8980 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v32s8, 8981 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v32s8, 8982 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID, 8983 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID, 8984 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR256RegClassID, 8985 // MIs[0] src3 8986 GIM_CheckIsImm, /*MI*/0, /*Op*/4, 8987 // (intrinsic_wo_chain:{ *:[v16i16] } 6442:{ *:[iPTR] }, VR256:{ *:[v32i8] }:$src1, VR256:{ *:[v32i8] }:$src2, (timm:{ *:[i8] }):$src3) => (VMPSADBWYrri:{ *:[v16i16] } VR256:{ *:[v32i8] }:$src1, VR256:{ *:[v32i8] }:$src2, (timm:{ *:[i8] }):$src3) 8988 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VMPSADBWYrri, 8989 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 8990 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 8991 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src2 8992 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src3 8993 GIR_EraseFromParent, /*InsnID*/0, 8994 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8995 // GIR_Coverage, 2710, 8996 GIR_Done, 8997 // Label 698: @19597 8998 GIM_Try, /*On fail goto*//*Label 699*/ 19656, // Rule ID 2712 // 8999 GIM_CheckFeatures, GIFBS_UseSSE41, 9000 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_sse41_mpsadbw, 9001 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, 9002 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 9003 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8, 9004 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 9005 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 9006 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR128RegClassID, 9007 // MIs[0] src3 9008 GIM_CheckIsImm, /*MI*/0, /*Op*/4, 9009 // (intrinsic_wo_chain:{ *:[v8i16] } 7339:{ *:[iPTR] }, VR128:{ *:[v16i8] }:$src1, VR128:{ *:[v16i8] }:$src2, (timm:{ *:[i8] }):$src3) => (MPSADBWrri:{ *:[v8i16] } VR128:{ *:[v16i8] }:$src1, VR128:{ *:[v16i8] }:$src2, (timm:{ *:[i8] }):$src3) 9010 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::MPSADBWrri, 9011 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 9012 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 9013 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src2 9014 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src3 9015 GIR_EraseFromParent, /*InsnID*/0, 9016 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9017 // GIR_Coverage, 2712, 9018 GIR_Done, 9019 // Label 699: @19656 9020 GIM_Try, /*On fail goto*//*Label 700*/ 19715, // Rule ID 2714 // 9021 GIM_CheckFeatures, GIFBS_UseSSE41, 9022 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_sse41_dpps, 9023 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 9024 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 9025 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 9026 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 9027 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 9028 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR128RegClassID, 9029 // MIs[0] src3 9030 GIM_CheckIsImm, /*MI*/0, /*Op*/4, 9031 // (intrinsic_wo_chain:{ *:[v4f32] } 7337:{ *:[iPTR] }, VR128:{ *:[v4f32] }:$src1, VR128:{ *:[v4f32] }:$src2, (timm:{ *:[i8] }):$src3) => (DPPSrri:{ *:[v4f32] } VR128:{ *:[v4f32] }:$src1, VR128:{ *:[v4f32] }:$src2, (timm:{ *:[i8] }):$src3) 9032 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::DPPSrri, 9033 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 9034 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 9035 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src2 9036 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src3 9037 GIR_EraseFromParent, /*InsnID*/0, 9038 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9039 // GIR_Coverage, 2714, 9040 GIR_Done, 9041 // Label 700: @19715 9042 GIM_Try, /*On fail goto*//*Label 701*/ 19774, // Rule ID 2716 // 9043 GIM_CheckFeatures, GIFBS_UseSSE41, 9044 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_sse41_dppd, 9045 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 9046 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 9047 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, 9048 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 9049 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 9050 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR128RegClassID, 9051 // MIs[0] src3 9052 GIM_CheckIsImm, /*MI*/0, /*Op*/4, 9053 // (intrinsic_wo_chain:{ *:[v2f64] } 7336:{ *:[iPTR] }, VR128:{ *:[v2f64] }:$src1, VR128:{ *:[v2f64] }:$src2, (timm:{ *:[i8] }):$src3) => (DPPDrri:{ *:[v2f64] } VR128:{ *:[v2f64] }:$src1, VR128:{ *:[v2f64] }:$src2, (timm:{ *:[i8] }):$src3) 9054 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::DPPDrri, 9055 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 9056 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 9057 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src2 9058 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src3 9059 GIR_EraseFromParent, /*InsnID*/0, 9060 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9061 // GIR_Coverage, 2716, 9062 GIR_Done, 9063 // Label 701: @19774 9064 GIM_Try, /*On fail goto*//*Label 702*/ 19833, // Rule ID 2768 // 9065 GIM_CheckFeatures, GIFBS_HasSHA, 9066 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_sha1rnds4, 9067 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 9068 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 9069 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 9070 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 9071 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 9072 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR128RegClassID, 9073 // MIs[0] src3 9074 GIM_CheckIsImm, /*MI*/0, /*Op*/4, 9075 // (intrinsic_wo_chain:{ *:[v4i32] } 7223:{ *:[iPTR] }, VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2, (timm:{ *:[i8] }):$src3) => (SHA1RNDS4rri:{ *:[v4i32] } VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2, (timm:{ *:[i8] }):$src3) 9076 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SHA1RNDS4rri, 9077 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 9078 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 9079 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src2 9080 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src3 9081 GIR_EraseFromParent, /*InsnID*/0, 9082 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9083 // GIR_Coverage, 2768, 9084 GIR_Done, 9085 // Label 702: @19833 9086 GIM_Try, /*On fail goto*//*Label 703*/ 19892, // Rule ID 2814 // 9087 GIM_CheckFeatures, GIFBS_HasPCLMUL_NoAVX, 9088 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_pclmulqdq, 9089 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 9090 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 9091 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, 9092 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 9093 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 9094 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR128RegClassID, 9095 // MIs[0] src3 9096 GIM_CheckIsImm, /*MI*/0, /*Op*/4, 9097 // (intrinsic_wo_chain:{ *:[v2i64] } 7192:{ *:[iPTR] }, VR128:{ *:[v2i64] }:$src1, VR128:{ *:[v2i64] }:$src2, (timm:{ *:[i8] }):$src3) => (PCLMULQDQrr:{ *:[v2i64] } VR128:{ *:[v2i64] }:$src1, VR128:{ *:[v2i64] }:$src2, (timm:{ *:[i8] }):$src3) 9098 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::PCLMULQDQrr, 9099 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 9100 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 9101 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src2 9102 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src3 9103 GIR_EraseFromParent, /*InsnID*/0, 9104 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9105 // GIR_Coverage, 2814, 9106 GIR_Done, 9107 // Label 703: @19892 9108 GIM_Try, /*On fail goto*//*Label 704*/ 19951, // Rule ID 2816 // 9109 GIM_CheckFeatures, GIFBS_HasAVX_HasPCLMUL_NoVLX_Or_NoVPCLMULQDQ, 9110 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_pclmulqdq, 9111 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 9112 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 9113 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, 9114 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 9115 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 9116 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR128RegClassID, 9117 // MIs[0] src3 9118 GIM_CheckIsImm, /*MI*/0, /*Op*/4, 9119 // (intrinsic_wo_chain:{ *:[v2i64] } 7192:{ *:[iPTR] }, VR128:{ *:[v2i64] }:$src1, VR128:{ *:[v2i64] }:$src2, (timm:{ *:[i8] }):$src3) => (VPCLMULQDQrr:{ *:[v2i64] } VR128:{ *:[v2i64] }:$src1, VR128:{ *:[v2i64] }:$src2, (timm:{ *:[i8] }):$src3) 9120 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VPCLMULQDQrr, 9121 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 9122 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 9123 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src2 9124 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src3 9125 GIR_EraseFromParent, /*InsnID*/0, 9126 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9127 // GIR_Coverage, 2816, 9128 GIR_Done, 9129 // Label 704: @19951 9130 GIM_Try, /*On fail goto*//*Label 705*/ 20010, // Rule ID 2818 // 9131 GIM_CheckFeatures, GIFBS_HasVPCLMULQDQ_NoVLX, 9132 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_pclmulqdq_256, 9133 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s64, 9134 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s64, 9135 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s64, 9136 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID, 9137 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID, 9138 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR256RegClassID, 9139 // MIs[0] src3 9140 GIM_CheckIsImm, /*MI*/0, /*Op*/4, 9141 // (intrinsic_wo_chain:{ *:[v4i64] } 7193:{ *:[iPTR] }, VR256:{ *:[v4i64] }:$src1, VR256:{ *:[v4i64] }:$src2, (timm:{ *:[i8] }):$src3) => (VPCLMULQDQYrr:{ *:[v4i64] } VR256:{ *:[v4i64] }:$src1, VR256:{ *:[v4i64] }:$src2, (timm:{ *:[i8] }):$src3) 9142 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VPCLMULQDQYrr, 9143 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 9144 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 9145 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src2 9146 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src3 9147 GIR_EraseFromParent, /*InsnID*/0, 9148 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9149 // GIR_Coverage, 2818, 9150 GIR_Done, 9151 // Label 705: @20010 9152 GIM_Try, /*On fail goto*//*Label 706*/ 20069, // Rule ID 11934 // 9153 GIM_CheckFeatures, GIFBS_HasAVX512_HasVPCLMULQDQ, 9154 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_pclmulqdq_512, 9155 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s64, 9156 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s64, 9157 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s64, 9158 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 9159 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR512RegClassID, 9160 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR512RegClassID, 9161 // MIs[0] src3 9162 GIM_CheckIsImm, /*MI*/0, /*Op*/4, 9163 // (intrinsic_wo_chain:{ *:[v8i64] } 7194:{ *:[iPTR] }, VR512:{ *:[v8i64] }:$src1, VR512:{ *:[v8i64] }:$src2, (timm:{ *:[i8] }):$src3) => (VPCLMULQDQZrr:{ *:[v8i64] } VR512:{ *:[v8i64] }:$src1, VR512:{ *:[v8i64] }:$src2, (timm:{ *:[i8] }):$src3) 9164 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VPCLMULQDQZrr, 9165 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 9166 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 9167 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src2 9168 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src3 9169 GIR_EraseFromParent, /*InsnID*/0, 9170 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9171 // GIR_Coverage, 11934, 9172 GIR_Done, 9173 // Label 706: @20069 9174 GIM_Try, /*On fail goto*//*Label 707*/ 20128, // Rule ID 11936 // 9175 GIM_CheckFeatures, GIFBS_HasVLX_HasVPCLMULQDQ, 9176 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_pclmulqdq, 9177 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 9178 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 9179 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64, 9180 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 9181 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128XRegClassID, 9182 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR128XRegClassID, 9183 // MIs[0] src3 9184 GIM_CheckIsImm, /*MI*/0, /*Op*/4, 9185 // (intrinsic_wo_chain:{ *:[v2i64] } 7192:{ *:[iPTR] }, VR128X:{ *:[v2i64] }:$src1, VR128X:{ *:[v2i64] }:$src2, (timm:{ *:[i8] }):$src3) => (VPCLMULQDQZ128rr:{ *:[v2i64] } VR128X:{ *:[v2i64] }:$src1, VR128X:{ *:[v2i64] }:$src2, (timm:{ *:[i8] }):$src3) 9186 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VPCLMULQDQZ128rr, 9187 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 9188 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 9189 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src2 9190 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src3 9191 GIR_EraseFromParent, /*InsnID*/0, 9192 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9193 // GIR_Coverage, 11936, 9194 GIR_Done, 9195 // Label 707: @20128 9196 GIM_Try, /*On fail goto*//*Label 708*/ 20187, // Rule ID 11938 // 9197 GIM_CheckFeatures, GIFBS_HasVLX_HasVPCLMULQDQ, 9198 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_pclmulqdq_256, 9199 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s64, 9200 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s64, 9201 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s64, 9202 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 9203 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256XRegClassID, 9204 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR256XRegClassID, 9205 // MIs[0] src3 9206 GIM_CheckIsImm, /*MI*/0, /*Op*/4, 9207 // (intrinsic_wo_chain:{ *:[v4i64] } 7193:{ *:[iPTR] }, VR256X:{ *:[v4i64] }:$src1, VR256X:{ *:[v4i64] }:$src2, (timm:{ *:[i8] }):$src3) => (VPCLMULQDQZ256rr:{ *:[v4i64] } VR256X:{ *:[v4i64] }:$src1, VR256X:{ *:[v4i64] }:$src2, (timm:{ *:[i8] }):$src3) 9208 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VPCLMULQDQZ256rr, 9209 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 9210 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 9211 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src2 9212 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src3 9213 GIR_EraseFromParent, /*InsnID*/0, 9214 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9215 // GIR_Coverage, 11938, 9216 GIR_Done, 9217 // Label 708: @20187 9218 GIM_Try, /*On fail goto*//*Label 709*/ 20251, // Rule ID 1209 // 9219 GIM_CheckFeatures, GIFBS_HasXOP, 9220 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_xop_vpmadcswd, 9221 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 9222 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 9223 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, 9224 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32, 9225 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 9226 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 9227 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR128RegClassID, 9228 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/X86::VR128RegClassID, 9229 // (intrinsic_wo_chain:{ *:[v4i32] } 7470:{ *:[iPTR] }, VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2, VR128:{ *:[v4i32] }:$src3) => (VPMADCSWDrr:{ *:[v4i32] } VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2, VR128:{ *:[v4i32] }:$src3) 9230 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VPMADCSWDrr, 9231 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 9232 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 9233 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src2 9234 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src3 9235 GIR_EraseFromParent, /*InsnID*/0, 9236 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9237 // GIR_Coverage, 1209, 9238 GIR_Done, 9239 // Label 709: @20251 9240 GIM_Try, /*On fail goto*//*Label 710*/ 20315, // Rule ID 1211 // 9241 GIM_CheckFeatures, GIFBS_HasXOP, 9242 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_xop_vpmadcsswd, 9243 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 9244 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 9245 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, 9246 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32, 9247 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 9248 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 9249 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR128RegClassID, 9250 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/X86::VR128RegClassID, 9251 // (intrinsic_wo_chain:{ *:[v4i32] } 7469:{ *:[iPTR] }, VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2, VR128:{ *:[v4i32] }:$src3) => (VPMADCSSWDrr:{ *:[v4i32] } VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2, VR128:{ *:[v4i32] }:$src3) 9252 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VPMADCSSWDrr, 9253 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 9254 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 9255 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src2 9256 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src3 9257 GIR_EraseFromParent, /*InsnID*/0, 9258 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9259 // GIR_Coverage, 1211, 9260 GIR_Done, 9261 // Label 710: @20315 9262 GIM_Try, /*On fail goto*//*Label 711*/ 20379, // Rule ID 1213 // 9263 GIM_CheckFeatures, GIFBS_HasXOP, 9264 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_xop_vpmacsww, 9265 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, 9266 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 9267 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, 9268 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16, 9269 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 9270 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 9271 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR128RegClassID, 9272 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/X86::VR128RegClassID, 9273 // (intrinsic_wo_chain:{ *:[v8i16] } 7468:{ *:[iPTR] }, VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2, VR128:{ *:[v8i16] }:$src3) => (VPMACSWWrr:{ *:[v8i16] } VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2, VR128:{ *:[v8i16] }:$src3) 9274 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VPMACSWWrr, 9275 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 9276 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 9277 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src2 9278 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src3 9279 GIR_EraseFromParent, /*InsnID*/0, 9280 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9281 // GIR_Coverage, 1213, 9282 GIR_Done, 9283 // Label 711: @20379 9284 GIM_Try, /*On fail goto*//*Label 712*/ 20443, // Rule ID 1215 // 9285 GIM_CheckFeatures, GIFBS_HasXOP, 9286 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_xop_vpmacswd, 9287 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 9288 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 9289 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, 9290 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32, 9291 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 9292 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 9293 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR128RegClassID, 9294 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/X86::VR128RegClassID, 9295 // (intrinsic_wo_chain:{ *:[v4i32] } 7467:{ *:[iPTR] }, VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2, VR128:{ *:[v4i32] }:$src3) => (VPMACSWDrr:{ *:[v4i32] } VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2, VR128:{ *:[v4i32] }:$src3) 9296 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VPMACSWDrr, 9297 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 9298 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 9299 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src2 9300 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src3 9301 GIR_EraseFromParent, /*InsnID*/0, 9302 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9303 // GIR_Coverage, 1215, 9304 GIR_Done, 9305 // Label 712: @20443 9306 GIM_Try, /*On fail goto*//*Label 713*/ 20507, // Rule ID 1217 // 9307 GIM_CheckFeatures, GIFBS_HasXOP, 9308 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_xop_vpmacssww, 9309 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16, 9310 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 9311 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, 9312 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16, 9313 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 9314 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 9315 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR128RegClassID, 9316 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/X86::VR128RegClassID, 9317 // (intrinsic_wo_chain:{ *:[v8i16] } 7466:{ *:[iPTR] }, VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2, VR128:{ *:[v8i16] }:$src3) => (VPMACSSWWrr:{ *:[v8i16] } VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2, VR128:{ *:[v8i16] }:$src3) 9318 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VPMACSSWWrr, 9319 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 9320 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 9321 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src2 9322 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src3 9323 GIR_EraseFromParent, /*InsnID*/0, 9324 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9325 // GIR_Coverage, 1217, 9326 GIR_Done, 9327 // Label 713: @20507 9328 GIM_Try, /*On fail goto*//*Label 714*/ 20571, // Rule ID 1219 // 9329 GIM_CheckFeatures, GIFBS_HasXOP, 9330 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_xop_vpmacsswd, 9331 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 9332 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 9333 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16, 9334 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32, 9335 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 9336 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 9337 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR128RegClassID, 9338 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/X86::VR128RegClassID, 9339 // (intrinsic_wo_chain:{ *:[v4i32] } 7465:{ *:[iPTR] }, VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2, VR128:{ *:[v4i32] }:$src3) => (VPMACSSWDrr:{ *:[v4i32] } VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2, VR128:{ *:[v4i32] }:$src3) 9340 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VPMACSSWDrr, 9341 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 9342 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 9343 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src2 9344 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src3 9345 GIR_EraseFromParent, /*InsnID*/0, 9346 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9347 // GIR_Coverage, 1219, 9348 GIR_Done, 9349 // Label 714: @20571 9350 GIM_Try, /*On fail goto*//*Label 715*/ 20635, // Rule ID 1221 // 9351 GIM_CheckFeatures, GIFBS_HasXOP, 9352 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_xop_vpmacssdql, 9353 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 9354 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 9355 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 9356 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v2s64, 9357 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 9358 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 9359 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR128RegClassID, 9360 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/X86::VR128RegClassID, 9361 // (intrinsic_wo_chain:{ *:[v2i64] } 7464:{ *:[iPTR] }, VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2, VR128:{ *:[v2i64] }:$src3) => (VPMACSSDQLrr:{ *:[v2i64] } VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2, VR128:{ *:[v2i64] }:$src3) 9362 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VPMACSSDQLrr, 9363 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 9364 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 9365 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src2 9366 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src3 9367 GIR_EraseFromParent, /*InsnID*/0, 9368 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9369 // GIR_Coverage, 1221, 9370 GIR_Done, 9371 // Label 715: @20635 9372 GIM_Try, /*On fail goto*//*Label 716*/ 20699, // Rule ID 1223 // 9373 GIM_CheckFeatures, GIFBS_HasXOP, 9374 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_xop_vpmacssdqh, 9375 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 9376 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 9377 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 9378 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v2s64, 9379 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 9380 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 9381 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR128RegClassID, 9382 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/X86::VR128RegClassID, 9383 // (intrinsic_wo_chain:{ *:[v2i64] } 7463:{ *:[iPTR] }, VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2, VR128:{ *:[v2i64] }:$src3) => (VPMACSSDQHrr:{ *:[v2i64] } VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2, VR128:{ *:[v2i64] }:$src3) 9384 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VPMACSSDQHrr, 9385 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 9386 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 9387 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src2 9388 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src3 9389 GIR_EraseFromParent, /*InsnID*/0, 9390 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9391 // GIR_Coverage, 1223, 9392 GIR_Done, 9393 // Label 716: @20699 9394 GIM_Try, /*On fail goto*//*Label 717*/ 20763, // Rule ID 1225 // 9395 GIM_CheckFeatures, GIFBS_HasXOP, 9396 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_xop_vpmacssdd, 9397 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 9398 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 9399 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 9400 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32, 9401 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 9402 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 9403 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR128RegClassID, 9404 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/X86::VR128RegClassID, 9405 // (intrinsic_wo_chain:{ *:[v4i32] } 7462:{ *:[iPTR] }, VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2, VR128:{ *:[v4i32] }:$src3) => (VPMACSSDDrr:{ *:[v4i32] } VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2, VR128:{ *:[v4i32] }:$src3) 9406 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VPMACSSDDrr, 9407 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 9408 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 9409 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src2 9410 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src3 9411 GIR_EraseFromParent, /*InsnID*/0, 9412 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9413 // GIR_Coverage, 1225, 9414 GIR_Done, 9415 // Label 717: @20763 9416 GIM_Try, /*On fail goto*//*Label 718*/ 20827, // Rule ID 1227 // 9417 GIM_CheckFeatures, GIFBS_HasXOP, 9418 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_xop_vpmacsdql, 9419 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 9420 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 9421 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 9422 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v2s64, 9423 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 9424 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 9425 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR128RegClassID, 9426 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/X86::VR128RegClassID, 9427 // (intrinsic_wo_chain:{ *:[v2i64] } 7461:{ *:[iPTR] }, VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2, VR128:{ *:[v2i64] }:$src3) => (VPMACSDQLrr:{ *:[v2i64] } VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2, VR128:{ *:[v2i64] }:$src3) 9428 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VPMACSDQLrr, 9429 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 9430 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 9431 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src2 9432 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src3 9433 GIR_EraseFromParent, /*InsnID*/0, 9434 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9435 // GIR_Coverage, 1227, 9436 GIR_Done, 9437 // Label 718: @20827 9438 GIM_Try, /*On fail goto*//*Label 719*/ 20891, // Rule ID 1229 // 9439 GIM_CheckFeatures, GIFBS_HasXOP, 9440 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_xop_vpmacsdqh, 9441 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64, 9442 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 9443 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 9444 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v2s64, 9445 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 9446 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 9447 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR128RegClassID, 9448 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/X86::VR128RegClassID, 9449 // (intrinsic_wo_chain:{ *:[v2i64] } 7460:{ *:[iPTR] }, VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2, VR128:{ *:[v2i64] }:$src3) => (VPMACSDQHrr:{ *:[v2i64] } VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2, VR128:{ *:[v2i64] }:$src3) 9450 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VPMACSDQHrr, 9451 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 9452 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 9453 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src2 9454 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src3 9455 GIR_EraseFromParent, /*InsnID*/0, 9456 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9457 // GIR_Coverage, 1229, 9458 GIR_Done, 9459 // Label 719: @20891 9460 GIM_Try, /*On fail goto*//*Label 720*/ 20955, // Rule ID 1231 // 9461 GIM_CheckFeatures, GIFBS_HasXOP, 9462 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_xop_vpmacsdd, 9463 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 9464 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 9465 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 9466 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32, 9467 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 9468 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 9469 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR128RegClassID, 9470 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/X86::VR128RegClassID, 9471 // (intrinsic_wo_chain:{ *:[v4i32] } 7459:{ *:[iPTR] }, VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2, VR128:{ *:[v4i32] }:$src3) => (VPMACSDDrr:{ *:[v4i32] } VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2, VR128:{ *:[v4i32] }:$src3) 9472 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VPMACSDDrr, 9473 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 9474 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 9475 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src2 9476 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src3 9477 GIR_EraseFromParent, /*InsnID*/0, 9478 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9479 // GIR_Coverage, 1231, 9480 GIR_Done, 9481 // Label 720: @20955 9482 GIM_Try, /*On fail goto*//*Label 721*/ 21026, // Rule ID 2776 // 9483 GIM_CheckFeatures, GIFBS_HasSHA, 9484 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_sha256rnds2, 9485 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32, 9486 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 9487 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32, 9488 GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32, 9489 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 9490 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 9491 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::VR128RegClassID, 9492 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/X86::VR128RegClassID, 9493 // (intrinsic_wo_chain:{ *:[v4i32] } 7226:{ *:[iPTR] }, VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2, XMM0:{ *:[v4i32] }) => (SHA256RNDS2rr:{ *:[v4i32] } VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2) 9494 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, 9495 GIR_AddRegister, /*InsnID*/1, X86::XMM0, /*AddRegisterRegFlags*/RegState::Define, 9496 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // XMM0 9497 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SHA256RNDS2rr, 9498 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 9499 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 9500 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src2 9501 GIR_EraseFromParent, /*InsnID*/0, 9502 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9503 // GIR_Coverage, 2776, 9504 GIR_Done, 9505 // Label 721: @21026 9506 GIM_Reject, 9507 // Label 689: @21027 9508 GIM_Reject, 9509 // Label 9: @21028 9510 GIM_Try, /*On fail goto*//*Label 722*/ 21286, 9511 GIM_CheckNumOperands, /*MI*/0, /*Expected*/1, 9512 GIM_Try, /*On fail goto*//*Label 723*/ 21051, // Rule ID 1969 // 9513 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::x86_sse2_pause, 9514 // (intrinsic_void 7295:{ *:[iPTR] }) => (PAUSE) 9515 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::PAUSE, 9516 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 9517 GIR_EraseFromParent, /*InsnID*/0, 9518 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9519 // GIR_Coverage, 1969, 9520 GIR_Done, 9521 // Label 723: @21051 9522 GIM_Try, /*On fail goto*//*Label 724*/ 21071, // Rule ID 1970 // 9523 GIM_CheckFeatures, GIFBS_HasSSE1, 9524 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::x86_sse_sfence, 9525 // (intrinsic_void 7257:{ *:[iPTR] }) => (SFENCE) 9526 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SFENCE, 9527 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 9528 GIR_EraseFromParent, /*InsnID*/0, 9529 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9530 // GIR_Coverage, 1970, 9531 GIR_Done, 9532 // Label 724: @21071 9533 GIM_Try, /*On fail goto*//*Label 725*/ 21091, // Rule ID 1971 // 9534 GIM_CheckFeatures, GIFBS_HasSSE2, 9535 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::x86_sse2_lfence, 9536 // (intrinsic_void 7284:{ *:[iPTR] }) => (LFENCE) 9537 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::LFENCE, 9538 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 9539 GIR_EraseFromParent, /*InsnID*/0, 9540 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9541 // GIR_Coverage, 1971, 9542 GIR_Done, 9543 // Label 725: @21091 9544 GIM_Try, /*On fail goto*//*Label 726*/ 21111, // Rule ID 1972 // 9545 GIM_CheckFeatures, GIFBS_HasMFence, 9546 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::x86_sse2_mfence, 9547 // (intrinsic_void 7288:{ *:[iPTR] }) => (MFENCE) 9548 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::MFENCE, 9549 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 9550 GIR_EraseFromParent, /*InsnID*/0, 9551 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9552 // GIR_Coverage, 1972, 9553 GIR_Done, 9554 // Label 726: @21111 9555 GIM_Try, /*On fail goto*//*Label 727*/ 21131, // Rule ID 2856 // 9556 GIM_CheckFeatures, GIFBS_HasAVX, 9557 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::x86_avx_vzeroall, 9558 // (intrinsic_void 6416:{ *:[iPTR] }) => (VZEROALL) 9559 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VZEROALL, 9560 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 9561 GIR_EraseFromParent, /*InsnID*/0, 9562 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9563 // GIR_Coverage, 2856, 9564 GIR_Done, 9565 // Label 727: @21131 9566 GIM_Try, /*On fail goto*//*Label 728*/ 21151, // Rule ID 2857 // 9567 GIM_CheckFeatures, GIFBS_HasAVX, 9568 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::x86_avx_vzeroupper, 9569 // (intrinsic_void 6417:{ *:[iPTR] }) => (VZEROUPPER) 9570 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VZEROUPPER, 9571 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 9572 GIR_EraseFromParent, /*InsnID*/0, 9573 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9574 // GIR_Coverage, 2857, 9575 GIR_Done, 9576 // Label 728: @21151 9577 GIM_Try, /*On fail goto*//*Label 729*/ 21171, // Rule ID 12546 // 9578 GIM_CheckFeatures, GIFBS_HasMMX, 9579 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::x86_mmx_emms, 9580 // (intrinsic_void 7118:{ *:[iPTR] }) => (MMX_EMMS:{ *:[x86mmx] }) 9581 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::MMX_EMMS, 9582 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 9583 GIR_EraseFromParent, /*InsnID*/0, 9584 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9585 // GIR_Coverage, 12546, 9586 GIR_Done, 9587 // Label 729: @21171 9588 GIM_Try, /*On fail goto*//*Label 730*/ 21191, // Rule ID 12765 // 9589 GIM_CheckFeatures, GIFBS_Has3DNow, 9590 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::x86_mmx_femms, 9591 // (intrinsic_void 7119:{ *:[iPTR] }) => (FEMMS:{ *:[x86mmx] }) 9592 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::FEMMS, 9593 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 9594 GIR_EraseFromParent, /*InsnID*/0, 9595 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9596 // GIR_Coverage, 12765, 9597 GIR_Done, 9598 // Label 730: @21191 9599 GIM_Try, /*On fail goto*//*Label 731*/ 21211, // Rule ID 12780 // 9600 GIM_CheckFeatures, GIFBS_HasRTM, 9601 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::x86_xend, 9602 // (intrinsic_void 7432:{ *:[iPTR] }) => (XEND) 9603 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::XEND, 9604 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 9605 GIR_EraseFromParent, /*InsnID*/0, 9606 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9607 // GIR_Coverage, 12780, 9608 GIR_Done, 9609 // Label 731: @21211 9610 GIM_Try, /*On fail goto*//*Label 732*/ 21229, // Rule ID 12786 // 9611 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::x86_wbinvd, 9612 // (intrinsic_void 7419:{ *:[iPTR] }) => (WBINVD) 9613 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::WBINVD, 9614 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 9615 GIR_EraseFromParent, /*InsnID*/0, 9616 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9617 // GIR_Coverage, 12786, 9618 GIR_Done, 9619 // Label 732: @21229 9620 GIM_Try, /*On fail goto*//*Label 733*/ 21249, // Rule ID 12787 // 9621 GIM_CheckFeatures, GIFBS_HasWBNOINVD, 9622 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::x86_wbnoinvd, 9623 // (intrinsic_void 7420:{ *:[iPTR] }) => (WBNOINVD) 9624 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::WBNOINVD, 9625 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 9626 GIR_EraseFromParent, /*InsnID*/0, 9627 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9628 // GIR_Coverage, 12787, 9629 GIR_Done, 9630 // Label 733: @21249 9631 GIM_Try, /*On fail goto*//*Label 734*/ 21267, // Rule ID 12792 // 9632 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::x86_saveprevssp, 9633 // (intrinsic_void 7215:{ *:[iPTR] }) => (SAVEPREVSSP) 9634 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SAVEPREVSSP, 9635 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 9636 GIR_EraseFromParent, /*InsnID*/0, 9637 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9638 // GIR_Coverage, 12792, 9639 GIR_Done, 9640 // Label 734: @21267 9641 GIM_Try, /*On fail goto*//*Label 735*/ 21285, // Rule ID 12798 // 9642 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::x86_setssbsy, 9643 // (intrinsic_void 7219:{ *:[iPTR] }) => (SETSSBSY) 9644 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SETSSBSY, 9645 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 9646 GIR_EraseFromParent, /*InsnID*/0, 9647 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9648 // GIR_Coverage, 12798, 9649 GIR_Done, 9650 // Label 735: @21285 9651 GIM_Reject, 9652 // Label 722: @21286 9653 GIM_Try, /*On fail goto*//*Label 736*/ 22162, 9654 GIM_CheckNumOperands, /*MI*/0, /*Expected*/2, 9655 GIM_Try, /*On fail goto*//*Label 737*/ 21313, // Rule ID 12784 // 9656 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::x86_int, 9657 // MIs[0] Operand 1 9658 GIM_CheckLiteralInt, /*MI*/0, /*Op*/1, 3, 9659 // (intrinsic_void 7111:{ *:[iPTR] }, 3:{ *:[i8] }) => (INT3) 9660 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::INT3, 9661 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 9662 GIR_EraseFromParent, /*InsnID*/0, 9663 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9664 // GIR_Coverage, 12784, 9665 GIR_Done, 9666 // Label 737: @21313 9667 GIM_Try, /*On fail goto*//*Label 738*/ 21340, // Rule ID 12782 // 9668 GIM_CheckFeatures, GIFBS_HasRTM, 9669 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::x86_xabort, 9670 // MIs[0] imm 9671 GIM_CheckIsImm, /*MI*/0, /*Op*/1, 9672 // (intrinsic_void 7430:{ *:[iPTR] }, (timm:{ *:[i8] }):$imm) => (XABORT (timm:{ *:[i8] }):$imm) 9673 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::XABORT, 9674 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // imm 9675 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 9676 GIR_EraseFromParent, /*InsnID*/0, 9677 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9678 // GIR_Coverage, 12782, 9679 GIR_Done, 9680 // Label 738: @21340 9681 GIM_Try, /*On fail goto*//*Label 739*/ 21365, // Rule ID 12785 // 9682 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::x86_int, 9683 // MIs[0] trap 9684 GIM_CheckIsImm, /*MI*/0, /*Op*/1, 9685 // (intrinsic_void 7111:{ *:[iPTR] }, (timm:{ *:[i8] }):$trap) => (INT (timm:{ *:[i8] }):$trap) 9686 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::INT, 9687 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // trap 9688 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 9689 GIR_EraseFromParent, /*InsnID*/0, 9690 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9691 // GIR_Coverage, 12785, 9692 GIR_Done, 9693 // Label 739: @21365 9694 GIM_Try, /*On fail goto*//*Label 740*/ 21397, // Rule ID 1 // 9695 GIM_CheckFeatures, GIFBS_Not64BitMode, 9696 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_flags_read_u32, 9697 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, 9698 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 9699 // (intrinsic_w_chain:{ *:[i32] } 7101:{ *:[iPTR] }) => (RDFLAGS32:{ *:[i32] }:{ *:[i32] }) 9700 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::RDFLAGS32, 9701 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 9702 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 9703 GIR_EraseFromParent, /*InsnID*/0, 9704 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9705 // GIR_Coverage, 1, 9706 GIR_Done, 9707 // Label 740: @21397 9708 GIM_Try, /*On fail goto*//*Label 741*/ 21429, // Rule ID 2 // 9709 GIM_CheckFeatures, GIFBS_In64BitMode, 9710 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_flags_read_u64, 9711 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, 9712 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID, 9713 // (intrinsic_w_chain:{ *:[i64] } 7102:{ *:[iPTR] }) => (RDFLAGS64:{ *:[i64] }:{ *:[i32] }) 9714 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::RDFLAGS64, 9715 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 9716 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 9717 GIR_EraseFromParent, /*InsnID*/0, 9718 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9719 // GIR_Coverage, 2, 9720 GIR_Done, 9721 // Label 741: @21429 9722 GIM_Try, /*On fail goto*//*Label 742*/ 21461, // Rule ID 95 // 9723 GIM_CheckFeatures, GIFBS_HasLWP, 9724 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_slwpcb, 9725 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, 9726 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 9727 // (intrinsic_w_chain:{ *:[i32] } 7227:{ *:[iPTR] }) => (SLWPCB:{ *:[i32] }) 9728 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SLWPCB, 9729 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 9730 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 9731 GIR_EraseFromParent, /*InsnID*/0, 9732 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9733 // GIR_Coverage, 95, 9734 GIR_Done, 9735 // Label 742: @21461 9736 GIM_Try, /*On fail goto*//*Label 743*/ 21493, // Rule ID 97 // 9737 GIM_CheckFeatures, GIFBS_HasLWP, 9738 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_slwpcb, 9739 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, 9740 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID, 9741 // (intrinsic_w_chain:{ *:[i64] } 7227:{ *:[iPTR] }) => (SLWPCB64:{ *:[i64] }) 9742 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SLWPCB64, 9743 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 9744 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 9745 GIR_EraseFromParent, /*InsnID*/0, 9746 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9747 // GIR_Coverage, 97, 9748 GIR_Done, 9749 // Label 743: @21493 9750 GIM_Try, /*On fail goto*//*Label 744*/ 21525, // Rule ID 12779 // 9751 GIM_CheckFeatures, GIFBS_HasRTM, 9752 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_xbegin, 9753 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, 9754 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 9755 // (intrinsic_w_chain:{ *:[i32] } 7431:{ *:[iPTR] }) => (XBEGIN:{ *:[i32] }) 9756 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::XBEGIN, 9757 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 9758 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 9759 GIR_EraseFromParent, /*InsnID*/0, 9760 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9761 // GIR_Coverage, 12779, 9762 GIR_Done, 9763 // Label 744: @21525 9764 GIM_Try, /*On fail goto*//*Label 745*/ 21557, // Rule ID 12815 // 9765 GIM_CheckFeatures, GIFBS_HasFSGSBase_In64BitMode, 9766 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_rdfsbase_32, 9767 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, 9768 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 9769 // (intrinsic_w_chain:{ *:[i32] } 7197:{ *:[iPTR] }) => (RDFSBASE:{ *:[i32] }) 9770 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::RDFSBASE, 9771 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 9772 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 9773 GIR_EraseFromParent, /*InsnID*/0, 9774 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9775 // GIR_Coverage, 12815, 9776 GIR_Done, 9777 // Label 745: @21557 9778 GIM_Try, /*On fail goto*//*Label 746*/ 21589, // Rule ID 12816 // 9779 GIM_CheckFeatures, GIFBS_HasFSGSBase_In64BitMode, 9780 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_rdfsbase_64, 9781 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, 9782 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID, 9783 // (intrinsic_w_chain:{ *:[i64] } 7198:{ *:[iPTR] }) => (RDFSBASE64:{ *:[i64] }) 9784 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::RDFSBASE64, 9785 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 9786 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 9787 GIR_EraseFromParent, /*InsnID*/0, 9788 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9789 // GIR_Coverage, 12816, 9790 GIR_Done, 9791 // Label 746: @21589 9792 GIM_Try, /*On fail goto*//*Label 747*/ 21621, // Rule ID 12817 // 9793 GIM_CheckFeatures, GIFBS_HasFSGSBase_In64BitMode, 9794 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_rdgsbase_32, 9795 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, 9796 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 9797 // (intrinsic_w_chain:{ *:[i32] } 7199:{ *:[iPTR] }) => (RDGSBASE:{ *:[i32] }) 9798 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::RDGSBASE, 9799 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 9800 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 9801 GIR_EraseFromParent, /*InsnID*/0, 9802 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9803 // GIR_Coverage, 12817, 9804 GIR_Done, 9805 // Label 747: @21621 9806 GIM_Try, /*On fail goto*//*Label 748*/ 21653, // Rule ID 12818 // 9807 GIM_CheckFeatures, GIFBS_HasFSGSBase_In64BitMode, 9808 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_rdgsbase_64, 9809 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, 9810 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID, 9811 // (intrinsic_w_chain:{ *:[i64] } 7200:{ *:[iPTR] }) => (RDGSBASE64:{ *:[i64] }) 9812 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::RDGSBASE64, 9813 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 9814 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 9815 GIR_EraseFromParent, /*InsnID*/0, 9816 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9817 // GIR_Coverage, 12818, 9818 GIR_Done, 9819 // Label 748: @21653 9820 GIM_Try, /*On fail goto*//*Label 749*/ 21685, // Rule ID 12824 // 9821 GIM_CheckFeatures, GIFBS_HasRDPID_Not64BitMode, 9822 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_rdpid, 9823 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, 9824 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 9825 // (intrinsic_w_chain:{ *:[i32] } 7201:{ *:[iPTR] }) => (RDPID32:{ *:[i32] }) 9826 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::RDPID32, 9827 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 9828 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 9829 GIR_EraseFromParent, /*InsnID*/0, 9830 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9831 // GIR_Coverage, 12824, 9832 GIR_Done, 9833 // Label 749: @21685 9834 GIM_Try, /*On fail goto*//*Label 750*/ 21717, // Rule ID 3 // 9835 GIM_CheckFeatures, GIFBS_Not64BitMode, 9836 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::x86_flags_write_u32, 9837 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 9838 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR32RegClassID, 9839 // (intrinsic_void 7103:{ *:[iPTR] }, GR32:{ *:[i32] }:$src) => (WRFLAGS32:{ *:[i32] } GR32:{ *:[i32] }:$src) 9840 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::WRFLAGS32, 9841 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 9842 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 9843 GIR_EraseFromParent, /*InsnID*/0, 9844 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9845 // GIR_Coverage, 3, 9846 GIR_Done, 9847 // Label 750: @21717 9848 GIM_Try, /*On fail goto*//*Label 751*/ 21749, // Rule ID 4 // 9849 GIM_CheckFeatures, GIFBS_In64BitMode, 9850 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::x86_flags_write_u64, 9851 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 9852 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR64RegClassID, 9853 // (intrinsic_void 7104:{ *:[iPTR] }, GR64:{ *:[i64] }:$src) => (WRFLAGS64:{ *:[i64] } GR64:{ *:[i64] }:$src) 9854 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::WRFLAGS64, 9855 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 9856 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 9857 GIR_EraseFromParent, /*InsnID*/0, 9858 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9859 // GIR_Coverage, 4, 9860 GIR_Done, 9861 // Label 751: @21749 9862 GIM_Try, /*On fail goto*//*Label 752*/ 21779, // Rule ID 12788 // 9863 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::x86_incsspd, 9864 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 9865 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR32RegClassID, 9866 // (intrinsic_void 7109:{ *:[iPTR] }, GR32:{ *:[i32] }:$src) => (INCSSPD GR32:{ *:[i32] }:$src) 9867 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::INCSSPD, 9868 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 9869 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 9870 GIR_EraseFromParent, /*InsnID*/0, 9871 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9872 // GIR_Coverage, 12788, 9873 GIR_Done, 9874 // Label 752: @21779 9875 GIM_Try, /*On fail goto*//*Label 753*/ 21809, // Rule ID 12789 // 9876 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::x86_incsspq, 9877 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 9878 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR64RegClassID, 9879 // (intrinsic_void 7110:{ *:[iPTR] }, GR64:{ *:[i64] }:$src) => (INCSSPQ GR64:{ *:[i64] }:$src) 9880 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::INCSSPQ, 9881 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 9882 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 9883 GIR_EraseFromParent, /*InsnID*/0, 9884 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9885 // GIR_Coverage, 12789, 9886 GIR_Done, 9887 // Label 753: @21809 9888 GIM_Try, /*On fail goto*//*Label 754*/ 21841, // Rule ID 12819 // 9889 GIM_CheckFeatures, GIFBS_HasFSGSBase_In64BitMode, 9890 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::x86_wrfsbase_32, 9891 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 9892 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR32RegClassID, 9893 // (intrinsic_void 7421:{ *:[iPTR] }, GR32:{ *:[i32] }:$src) => (WRFSBASE GR32:{ *:[i32] }:$src) 9894 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::WRFSBASE, 9895 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 9896 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 9897 GIR_EraseFromParent, /*InsnID*/0, 9898 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9899 // GIR_Coverage, 12819, 9900 GIR_Done, 9901 // Label 754: @21841 9902 GIM_Try, /*On fail goto*//*Label 755*/ 21873, // Rule ID 12820 // 9903 GIM_CheckFeatures, GIFBS_HasFSGSBase_In64BitMode, 9904 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::x86_wrfsbase_64, 9905 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 9906 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR64RegClassID, 9907 // (intrinsic_void 7422:{ *:[iPTR] }, GR64:{ *:[i64] }:$src) => (WRFSBASE64 GR64:{ *:[i64] }:$src) 9908 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::WRFSBASE64, 9909 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 9910 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 9911 GIR_EraseFromParent, /*InsnID*/0, 9912 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9913 // GIR_Coverage, 12820, 9914 GIR_Done, 9915 // Label 755: @21873 9916 GIM_Try, /*On fail goto*//*Label 756*/ 21905, // Rule ID 12821 // 9917 GIM_CheckFeatures, GIFBS_HasFSGSBase_In64BitMode, 9918 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::x86_wrgsbase_32, 9919 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 9920 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR32RegClassID, 9921 // (intrinsic_void 7423:{ *:[iPTR] }, GR32:{ *:[i32] }:$src) => (WRGSBASE GR32:{ *:[i32] }:$src) 9922 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::WRGSBASE, 9923 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 9924 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 9925 GIR_EraseFromParent, /*InsnID*/0, 9926 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9927 // GIR_Coverage, 12821, 9928 GIR_Done, 9929 // Label 756: @21905 9930 GIM_Try, /*On fail goto*//*Label 757*/ 21937, // Rule ID 12822 // 9931 GIM_CheckFeatures, GIFBS_HasFSGSBase_In64BitMode, 9932 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::x86_wrgsbase_64, 9933 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 9934 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR64RegClassID, 9935 // (intrinsic_void 7424:{ *:[iPTR] }, GR64:{ *:[i64] }:$src) => (WRGSBASE64 GR64:{ *:[i64] }:$src) 9936 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::WRGSBASE64, 9937 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 9938 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 9939 GIR_EraseFromParent, /*InsnID*/0, 9940 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9941 // GIR_Coverage, 12822, 9942 GIR_Done, 9943 // Label 757: @21937 9944 GIM_Try, /*On fail goto*//*Label 758*/ 21969, // Rule ID 12827 // 9945 GIM_CheckFeatures, GIFBS_HasPTWRITE, 9946 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::x86_ptwrite32, 9947 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 9948 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR32RegClassID, 9949 // (intrinsic_void 7195:{ *:[iPTR] }, GR32:{ *:[i32] }:$dst) => (PTWRITEr GR32:{ *:[i32] }:$dst) 9950 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::PTWRITEr, 9951 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // dst 9952 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 9953 GIR_EraseFromParent, /*InsnID*/0, 9954 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9955 // GIR_Coverage, 12827, 9956 GIR_Done, 9957 // Label 758: @21969 9958 GIM_Try, /*On fail goto*//*Label 759*/ 22001, // Rule ID 12828 // 9959 GIM_CheckFeatures, GIFBS_HasPTWRITE_In64BitMode, 9960 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::x86_ptwrite64, 9961 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 9962 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR64RegClassID, 9963 // (intrinsic_void 7196:{ *:[iPTR] }, GR64:{ *:[i64] }:$dst) => (PTWRITE64r GR64:{ *:[i64] }:$dst) 9964 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::PTWRITE64r, 9965 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // dst 9966 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 9967 GIR_EraseFromParent, /*InsnID*/0, 9968 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9969 // GIR_Coverage, 12828, 9970 GIR_Done, 9971 // Label 759: @22001 9972 GIM_Try, /*On fail goto*//*Label 760*/ 22033, // Rule ID 94 // 9973 GIM_CheckFeatures, GIFBS_HasLWP, 9974 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::x86_llwpcb, 9975 // MIs[0] src 9976 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 9977 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR32RegClassID, 9978 // (intrinsic_void 7113:{ *:[iPTR] }, GR32:{ *:[i32] }:$src) => (LLWPCB GR32:{ *:[i32] }:$src) 9979 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::LLWPCB, 9980 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 9981 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 9982 GIR_EraseFromParent, /*InsnID*/0, 9983 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9984 // GIR_Coverage, 94, 9985 GIR_Done, 9986 // Label 760: @22033 9987 GIM_Try, /*On fail goto*//*Label 761*/ 22065, // Rule ID 96 // 9988 GIM_CheckFeatures, GIFBS_HasLWP, 9989 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::x86_llwpcb, 9990 // MIs[0] src 9991 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 9992 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR64RegClassID, 9993 // (intrinsic_void 7113:{ *:[iPTR] }, GR64:{ *:[i64] }:$src) => (LLWPCB64 GR64:{ *:[i64] }:$src) 9994 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::LLWPCB64, 9995 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 9996 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 9997 GIR_EraseFromParent, /*InsnID*/0, 9998 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9999 // GIR_Coverage, 96, 10000 GIR_Done, 10001 // Label 761: @22065 10002 GIM_Try, /*On fail goto*//*Label 762*/ 22097, // Rule ID 107 // 10003 GIM_CheckFeatures, GIFBS_HasWAITPKG_Not64BitMode, 10004 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::x86_umonitor, 10005 // MIs[0] src 10006 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/16, 10007 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR16RegClassID, 10008 // (intrinsic_void 7404:{ *:[iPTR] }, GR16:{ *:[i16] }:$src) => (UMONITOR16 GR16:{ *:[i16] }:$src) 10009 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::UMONITOR16, 10010 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 10011 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 10012 GIR_EraseFromParent, /*InsnID*/0, 10013 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10014 // GIR_Coverage, 107, 10015 GIR_Done, 10016 // Label 762: @22097 10017 GIM_Try, /*On fail goto*//*Label 763*/ 22129, // Rule ID 108 // 10018 GIM_CheckFeatures, GIFBS_HasWAITPKG, 10019 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::x86_umonitor, 10020 // MIs[0] src 10021 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 10022 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR32RegClassID, 10023 // (intrinsic_void 7404:{ *:[iPTR] }, GR32:{ *:[i32] }:$src) => (UMONITOR32 GR32:{ *:[i32] }:$src) 10024 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::UMONITOR32, 10025 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 10026 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 10027 GIR_EraseFromParent, /*InsnID*/0, 10028 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10029 // GIR_Coverage, 108, 10030 GIR_Done, 10031 // Label 763: @22129 10032 GIM_Try, /*On fail goto*//*Label 764*/ 22161, // Rule ID 109 // 10033 GIM_CheckFeatures, GIFBS_HasWAITPKG_In64BitMode, 10034 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::x86_umonitor, 10035 // MIs[0] src 10036 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 10037 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR64RegClassID, 10038 // (intrinsic_void 7404:{ *:[iPTR] }, GR64:{ *:[i64] }:$src) => (UMONITOR64 GR64:{ *:[i64] }:$src) 10039 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::UMONITOR64, 10040 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 10041 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 10042 GIR_EraseFromParent, /*InsnID*/0, 10043 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10044 // GIR_Coverage, 109, 10045 GIR_Done, 10046 // Label 764: @22161 10047 GIM_Reject, 10048 // Label 736: @22162 10049 GIM_Try, /*On fail goto*//*Label 765*/ 22310, 10050 GIM_CheckNumOperands, /*MI*/0, /*Expected*/3, 10051 GIM_Try, /*On fail goto*//*Label 766*/ 22209, // Rule ID 12790 // 10052 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_rdsspd, 10053 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, 10054 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 10055 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 10056 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR32RegClassID, 10057 // (intrinsic_w_chain:{ *:[i32] } 7210:{ *:[iPTR] }, GR32:{ *:[i32] }:$src) => (RDSSPD:{ *:[i32] } GR32:{ *:[i32] }:$src) 10058 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::RDSSPD, 10059 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 10060 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src 10061 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 10062 GIR_EraseFromParent, /*InsnID*/0, 10063 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10064 // GIR_Coverage, 12790, 10065 GIR_Done, 10066 // Label 766: @22209 10067 GIM_Try, /*On fail goto*//*Label 767*/ 22251, // Rule ID 12791 // 10068 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::x86_rdsspq, 10069 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, 10070 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 10071 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID, 10072 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR64RegClassID, 10073 // (intrinsic_w_chain:{ *:[i64] } 7211:{ *:[iPTR] }, GR64:{ *:[i64] }:$src) => (RDSSPQ:{ *:[i64] } GR64:{ *:[i64] }:$src) 10074 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::RDSSPQ, 10075 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 10076 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src 10077 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 10078 GIR_EraseFromParent, /*InsnID*/0, 10079 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10080 // GIR_Coverage, 12791, 10081 GIR_Done, 10082 // Label 767: @22251 10083 GIM_Try, /*On fail goto*//*Label 768*/ 22309, // Rule ID 2545 // 10084 GIM_CheckFeatures, GIFBS_HasSSE3, 10085 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::x86_sse3_mwait, 10086 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 10087 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 10088 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR32_CB_and_GR32_DCRegClassID, 10089 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR32_ADRegClassID, 10090 // (intrinsic_void 7333:{ *:[iPTR] }, ECX:{ *:[i32] }, EAX:{ *:[i32] }) => (MWAITrr) 10091 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY, 10092 GIR_AddRegister, /*InsnID*/2, X86::EAX, /*AddRegisterRegFlags*/RegState::Define, 10093 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // EAX 10094 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, 10095 GIR_AddRegister, /*InsnID*/1, X86::ECX, /*AddRegisterRegFlags*/RegState::Define, 10096 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // ECX 10097 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::MWAITrr, 10098 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 10099 GIR_EraseFromParent, /*InsnID*/0, 10100 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10101 // GIR_Coverage, 2545, 10102 GIR_Done, 10103 // Label 768: @22309 10104 GIM_Reject, 10105 // Label 765: @22310 10106 GIM_Try, /*On fail goto*//*Label 769*/ 22824, 10107 GIM_CheckNumOperands, /*MI*/0, /*Expected*/4, 10108 GIM_Try, /*On fail goto*//*Label 770*/ 22366, // Rule ID 102 // 10109 GIM_CheckFeatures, GIFBS_HasLWP, 10110 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::x86_lwpval32, 10111 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 10112 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 10113 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR32RegClassID, 10114 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR32RegClassID, 10115 // MIs[0] cntl 10116 GIM_CheckIsImm, /*MI*/0, /*Op*/3, 10117 // (intrinsic_void 7116:{ *:[iPTR] }, GR32:{ *:[i32] }:$src0, GR32:{ *:[i32] }:$src1, (timm:{ *:[i32] }):$cntl) => (LWPVAL32rri GR32:{ *:[i32] }:$src0, GR32:{ *:[i32] }:$src1, (timm:{ *:[i32] }):$cntl) 10118 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::LWPVAL32rri, 10119 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0 10120 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 10121 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // cntl 10122 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 10123 GIR_EraseFromParent, /*InsnID*/0, 10124 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10125 // GIR_Coverage, 102, 10126 GIR_Done, 10127 // Label 770: @22366 10128 GIM_Try, /*On fail goto*//*Label 771*/ 22417, // Rule ID 104 // 10129 GIM_CheckFeatures, GIFBS_HasLWP, 10130 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::x86_lwpval64, 10131 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 10132 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 10133 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR64RegClassID, 10134 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR32RegClassID, 10135 // MIs[0] cntl 10136 GIM_CheckIsImm, /*MI*/0, /*Op*/3, 10137 // (intrinsic_void 7117:{ *:[iPTR] }, GR64:{ *:[i64] }:$src0, GR32:{ *:[i32] }:$src1, (timm:{ *:[i32] }):$cntl) => (LWPVAL64rri GR64:{ *:[i64] }:$src0, GR32:{ *:[i32] }:$src1, (timm:{ *:[i32] }):$cntl) 10138 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::LWPVAL64rri, 10139 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0 10140 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 10141 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // cntl 10142 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 10143 GIR_EraseFromParent, /*InsnID*/0, 10144 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10145 // GIR_Coverage, 104, 10146 GIR_Done, 10147 // Label 771: @22417 10148 GIM_Try, /*On fail goto*//*Label 772*/ 22494, // Rule ID 106 // 10149 GIM_CheckFeatures, GIFBS_HasMWAITX, 10150 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::x86_mwaitx, 10151 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 10152 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 10153 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 10154 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR32_CB_and_GR32_DCRegClassID, 10155 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR32_ADRegClassID, 10156 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::GR32_ABCD_and_GR32_BSIRegClassID, 10157 // (intrinsic_void 7191:{ *:[iPTR] }, ECX:{ *:[i32] }, EAX:{ *:[i32] }, EBX:{ *:[i32] }) => (MWAITXrrr) 10158 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY, 10159 GIR_AddRegister, /*InsnID*/3, X86::EBX, /*AddRegisterRegFlags*/RegState::Define, 10160 GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/3, // EBX 10161 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY, 10162 GIR_AddRegister, /*InsnID*/2, X86::EAX, /*AddRegisterRegFlags*/RegState::Define, 10163 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // EAX 10164 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, 10165 GIR_AddRegister, /*InsnID*/1, X86::ECX, /*AddRegisterRegFlags*/RegState::Define, 10166 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // ECX 10167 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::MWAITXrrr, 10168 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 10169 GIR_EraseFromParent, /*InsnID*/0, 10170 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10171 // GIR_Coverage, 106, 10172 GIR_Done, 10173 // Label 772: @22494 10174 GIM_Try, /*On fail goto*//*Label 773*/ 22571, // Rule ID 12800 // 10175 GIM_CheckFeatures, GIFBS_HasXSAVE, 10176 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::x86_xsetbv, 10177 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 10178 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 10179 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 10180 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR32_CB_and_GR32_DCRegClassID, 10181 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR32_AD_and_GR32_DCRegClassID, 10182 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::GR32_ADRegClassID, 10183 // (intrinsic_void 7492:{ *:[iPTR] }, ECX:{ *:[i32] }, EDX:{ *:[i32] }, EAX:{ *:[i32] }) => (XSETBV) 10184 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY, 10185 GIR_AddRegister, /*InsnID*/3, X86::EAX, /*AddRegisterRegFlags*/RegState::Define, 10186 GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/3, // EAX 10187 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY, 10188 GIR_AddRegister, /*InsnID*/2, X86::EDX, /*AddRegisterRegFlags*/RegState::Define, 10189 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // EDX 10190 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, 10191 GIR_AddRegister, /*InsnID*/1, X86::ECX, /*AddRegisterRegFlags*/RegState::Define, 10192 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // ECX 10193 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::XSETBV, 10194 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 10195 GIR_EraseFromParent, /*InsnID*/0, 10196 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10197 // GIR_Coverage, 12800, 10198 GIR_Done, 10199 // Label 773: @22571 10200 GIM_Try, /*On fail goto*//*Label 774*/ 22634, // Rule ID 2362 // 10201 GIM_CheckFeatures, GIFBS_HasAVX_Not64BitMode, 10202 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::x86_sse2_maskmov_dqu, 10203 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, 10204 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 10205 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 10206 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 10207 // MIs[0] Operand 3 10208 GIM_CheckPointerToAny, /*MI*/0, /*Op*/3, /*SizeInBits*/32, 10209 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::GR32_DIBP_and_GR32_SIDIRegClassID, 10210 // (intrinsic_void 7285:{ *:[iPTR] }, VR128:{ *:[v16i8] }:$src, VR128:{ *:[v16i8] }:$mask, EDI:{ *:[i32] }) => (VMASKMOVDQU VR128:{ *:[v16i8] }:$src, VR128:{ *:[v16i8] }:$mask) 10211 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, 10212 GIR_AddRegister, /*InsnID*/1, X86::EDI, /*AddRegisterRegFlags*/RegState::Define, 10213 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // EDI 10214 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VMASKMOVDQU, 10215 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 10216 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // mask 10217 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 10218 GIR_EraseFromParent, /*InsnID*/0, 10219 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10220 // GIR_Coverage, 2362, 10221 GIR_Done, 10222 // Label 774: @22634 10223 GIM_Try, /*On fail goto*//*Label 775*/ 22697, // Rule ID 2363 // 10224 GIM_CheckFeatures, GIFBS_HasAVX_In64BitMode, 10225 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::x86_sse2_maskmov_dqu, 10226 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, 10227 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 10228 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 10229 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 10230 // MIs[0] Operand 3 10231 GIM_CheckPointerToAny, /*MI*/0, /*Op*/3, /*SizeInBits*/64, 10232 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDIRegClassID, 10233 // (intrinsic_void 7285:{ *:[iPTR] }, VR128:{ *:[v16i8] }:$src, VR128:{ *:[v16i8] }:$mask, RDI:{ *:[i64] }) => (VMASKMOVDQU64 VR128:{ *:[v16i8] }:$src, VR128:{ *:[v16i8] }:$mask) 10234 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, 10235 GIR_AddRegister, /*InsnID*/1, X86::RDI, /*AddRegisterRegFlags*/RegState::Define, 10236 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // RDI 10237 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VMASKMOVDQU64, 10238 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 10239 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // mask 10240 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 10241 GIR_EraseFromParent, /*InsnID*/0, 10242 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10243 // GIR_Coverage, 2363, 10244 GIR_Done, 10245 // Label 775: @22697 10246 GIM_Try, /*On fail goto*//*Label 776*/ 22760, // Rule ID 2364 // 10247 GIM_CheckFeatures, GIFBS_Not64BitMode_UseSSE2, 10248 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::x86_sse2_maskmov_dqu, 10249 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, 10250 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 10251 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 10252 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 10253 // MIs[0] Operand 3 10254 GIM_CheckPointerToAny, /*MI*/0, /*Op*/3, /*SizeInBits*/32, 10255 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::GR32_DIBP_and_GR32_SIDIRegClassID, 10256 // (intrinsic_void 7285:{ *:[iPTR] }, VR128:{ *:[v16i8] }:$src, VR128:{ *:[v16i8] }:$mask, EDI:{ *:[i32] }) => (MASKMOVDQU VR128:{ *:[v16i8] }:$src, VR128:{ *:[v16i8] }:$mask) 10257 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, 10258 GIR_AddRegister, /*InsnID*/1, X86::EDI, /*AddRegisterRegFlags*/RegState::Define, 10259 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // EDI 10260 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::MASKMOVDQU, 10261 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 10262 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // mask 10263 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 10264 GIR_EraseFromParent, /*InsnID*/0, 10265 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10266 // GIR_Coverage, 2364, 10267 GIR_Done, 10268 // Label 776: @22760 10269 GIM_Try, /*On fail goto*//*Label 777*/ 22823, // Rule ID 2365 // 10270 GIM_CheckFeatures, GIFBS_In64BitMode_UseSSE2, 10271 GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::x86_sse2_maskmov_dqu, 10272 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, 10273 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 10274 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 10275 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 10276 // MIs[0] Operand 3 10277 GIM_CheckPointerToAny, /*MI*/0, /*Op*/3, /*SizeInBits*/64, 10278 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/X86::GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDIRegClassID, 10279 // (intrinsic_void 7285:{ *:[iPTR] }, VR128:{ *:[v16i8] }:$src, VR128:{ *:[v16i8] }:$mask, RDI:{ *:[i64] }) => (MASKMOVDQU64 VR128:{ *:[v16i8] }:$src, VR128:{ *:[v16i8] }:$mask) 10280 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, 10281 GIR_AddRegister, /*InsnID*/1, X86::RDI, /*AddRegisterRegFlags*/RegState::Define, 10282 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // RDI 10283 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::MASKMOVDQU64, 10284 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 10285 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // mask 10286 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 10287 GIR_EraseFromParent, /*InsnID*/0, 10288 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10289 // GIR_Coverage, 2365, 10290 GIR_Done, 10291 // Label 777: @22823 10292 GIM_Reject, 10293 // Label 769: @22824 10294 GIM_Reject, 10295 // Label 10: @22825 10296 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/3, 25, /*)*//*default:*//*Label 792*/ 23605, 10297 /*GILLT_s32*//*Label 778*/ 22853, 10298 /*GILLT_s64*//*Label 779*/ 23024, 0, 0, 0, 10299 /*GILLT_v2s64*//*Label 780*/ 23200, 0, 10300 /*GILLT_v4s32*//*Label 781*/ 23224, 10301 /*GILLT_v4s64*//*Label 782*/ 23248, 0, 10302 /*GILLT_v8s16*//*Label 783*/ 23272, 10303 /*GILLT_v8s32*//*Label 784*/ 23335, 10304 /*GILLT_v8s64*//*Label 785*/ 23359, 0, 10305 /*GILLT_v16s8*//*Label 786*/ 23383, 10306 /*GILLT_v16s16*//*Label 787*/ 23446, 10307 /*GILLT_v16s32*//*Label 788*/ 23509, 0, 10308 /*GILLT_v32s8*//*Label 789*/ 23533, 10309 /*GILLT_v32s16*//*Label 790*/ 23557, 0, 10310 /*GILLT_v64s8*//*Label 791*/ 23581, 10311 // Label 778: @22853 10312 GIM_Try, /*On fail goto*//*Label 793*/ 22898, // Rule ID 14539 // 10313 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, 10314 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 10315 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 10316 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_BITCAST, 10317 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s1, 10318 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::VK16RegClassID, 10319 GIM_CheckIsSafeToFold, /*InsnID*/1, 10320 // (anyext:{ *:[i32] } (bitconvert:{ *:[i16] } VK16:{ *:[v16i1] }:$src)) => (COPY_TO_REGCLASS:{ *:[i32] } VK16:{ *:[v16i1] }:$src, GR32:{ *:[i32] }) 10321 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 10322 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 10323 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src 10324 GIR_EraseFromParent, /*InsnID*/0, 10325 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC GR32*/33, 10326 // GIR_Coverage, 14539, 10327 GIR_Done, 10328 // Label 793: @22898 10329 GIM_Try, /*On fail goto*//*Label 794*/ 22943, // Rule ID 14542 // 10330 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s8, 10331 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 10332 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 10333 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_BITCAST, 10334 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s1, 10335 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::VK8RegClassID, 10336 GIM_CheckIsSafeToFold, /*InsnID*/1, 10337 // (anyext:{ *:[i32] } (bitconvert:{ *:[i8] } VK8:{ *:[v8i1] }:$src)) => (COPY_TO_REGCLASS:{ *:[i32] } VK8:{ *:[v8i1] }:$src, GR32:{ *:[i32] }) 10338 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 10339 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 10340 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src 10341 GIR_EraseFromParent, /*InsnID*/0, 10342 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC GR32*/33, 10343 // GIR_Coverage, 14542, 10344 GIR_Done, 10345 // Label 794: @22943 10346 GIM_Try, /*On fail goto*//*Label 795*/ 22964, // Rule ID 17129 // 10347 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s8, 10348 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 10349 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR8RegClassID, 10350 // (anyext:{ *:[i32] } GR8:{ *:[i8] }:$src) => (MOVZX32rr8:{ *:[i32] } GR8:{ *:[i8] }:$src) 10351 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::MOVZX32rr8, 10352 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10353 // GIR_Coverage, 17129, 10354 GIR_Done, 10355 // Label 795: @22964 10356 GIM_Try, /*On fail goto*//*Label 796*/ 23023, // Rule ID 17130 // 10357 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, 10358 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::LOW32_ADDR_ACCESS_RBPRegClassID, 10359 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR16RegClassID, 10360 // (anyext:{ *:[i32] } GR16:{ *:[i16] }:$src) => (INSERT_SUBREG:{ *:[i32] } (IMPLICIT_DEF:{ *:[i32] }), GR16:{ *:[i16] }:$src, sub_16bit:{ *:[i32] }) 10361 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, 10362 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, 10363 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 10364 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 10365 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::INSERT_SUBREG, 10366 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 10367 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 10368 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 10369 GIR_AddImm, /*InsnID*/0, /*Imm*/4, 10370 GIR_EraseFromParent, /*InsnID*/0, 10371 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC LOW32_ADDR_ACCESS_RBP*/28, 10372 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, /*RC LOW32_ADDR_ACCESS_RBP*/28, 10373 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, /*RC GR16*/6, 10374 // GIR_Coverage, 17130, 10375 GIR_Done, 10376 // Label 796: @23023 10377 GIM_Reject, 10378 // Label 779: @23024 10379 GIM_Try, /*On fail goto*//*Label 797*/ 23082, // Rule ID 17131 // 10380 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s8, 10381 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID, 10382 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR8RegClassID, 10383 // (anyext:{ *:[i64] } GR8:{ *:[i8] }:$src) => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (MOVZX32rr8:{ *:[i32] } GR8:{ *:[i8] }:$src), sub_32bit:{ *:[i32] }) 10384 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, 10385 GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::MOVZX32rr8, 10386 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 10387 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src 10388 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 10389 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG, 10390 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 10391 GIR_AddImm, /*InsnID*/0, /*Imm*/0, 10392 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 10393 GIR_AddImm, /*InsnID*/0, /*Imm*/6, 10394 GIR_EraseFromParent, /*InsnID*/0, 10395 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC GR64*/65, 10396 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, /*RC GR32*/33, 10397 // GIR_Coverage, 17131, 10398 GIR_Done, 10399 // Label 797: @23082 10400 GIM_Try, /*On fail goto*//*Label 798*/ 23140, // Rule ID 17132 // 10401 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, 10402 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID, 10403 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR16RegClassID, 10404 // (anyext:{ *:[i64] } GR16:{ *:[i16] }:$src) => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (MOVZX32rr16:{ *:[i32] } GR16:{ *:[i16] }:$src), sub_32bit:{ *:[i32] }) 10405 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, 10406 GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::MOVZX32rr16, 10407 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 10408 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src 10409 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 10410 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG, 10411 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 10412 GIR_AddImm, /*InsnID*/0, /*Imm*/0, 10413 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 10414 GIR_AddImm, /*InsnID*/0, /*Imm*/6, 10415 GIR_EraseFromParent, /*InsnID*/0, 10416 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC GR64*/65, 10417 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, /*RC GR32*/33, 10418 // GIR_Coverage, 17132, 10419 GIR_Done, 10420 // Label 798: @23140 10421 GIM_Try, /*On fail goto*//*Label 799*/ 23199, // Rule ID 17133 // 10422 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 10423 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID, 10424 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR32RegClassID, 10425 // (anyext:{ *:[i64] } GR32:{ *:[i32] }:$src) => (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), GR32:{ *:[i32] }:$src, sub_32bit:{ *:[i32] }) 10426 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, 10427 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, 10428 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 10429 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 10430 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::INSERT_SUBREG, 10431 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 10432 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 10433 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 10434 GIR_AddImm, /*InsnID*/0, /*Imm*/6, 10435 GIR_EraseFromParent, /*InsnID*/0, 10436 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC GR64*/65, 10437 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, /*RC GR64*/65, 10438 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, /*RC GR32*/33, 10439 // GIR_Coverage, 17133, 10440 GIR_Done, 10441 // Label 799: @23199 10442 GIM_Reject, 10443 // Label 780: @23200 10444 GIM_Try, /*On fail goto*//*Label 800*/ 23223, // Rule ID 16466 // 10445 GIM_CheckFeatures, GIFBS_HasDQI_HasVLX, 10446 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s1, 10447 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 10448 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VK2RegClassID, 10449 // (anyext:{ *:[v2i64] } VK2:{ *:[v2i1] }:$src) => (VPMOVM2QZ128rr:{ *:[v2i64] } VK2:{ *:[v2i1] }:$src) 10450 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMOVM2QZ128rr, 10451 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10452 // GIR_Coverage, 16466, 10453 GIR_Done, 10454 // Label 800: @23223 10455 GIM_Reject, 10456 // Label 781: @23224 10457 GIM_Try, /*On fail goto*//*Label 801*/ 23247, // Rule ID 16463 // 10458 GIM_CheckFeatures, GIFBS_HasDQI_HasVLX, 10459 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s1, 10460 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 10461 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VK4RegClassID, 10462 // (anyext:{ *:[v4i32] } VK4:{ *:[v4i1] }:$src) => (VPMOVM2DZ128rr:{ *:[v4i32] } VK4:{ *:[v4i1] }:$src) 10463 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMOVM2DZ128rr, 10464 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10465 // GIR_Coverage, 16463, 10466 GIR_Done, 10467 // Label 801: @23247 10468 GIM_Reject, 10469 // Label 782: @23248 10470 GIM_Try, /*On fail goto*//*Label 802*/ 23271, // Rule ID 16465 // 10471 GIM_CheckFeatures, GIFBS_HasDQI_HasVLX, 10472 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s1, 10473 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 10474 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VK4RegClassID, 10475 // (anyext:{ *:[v4i64] } VK4:{ *:[v4i1] }:$src) => (VPMOVM2QZ256rr:{ *:[v4i64] } VK4:{ *:[v4i1] }:$src) 10476 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMOVM2QZ256rr, 10477 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10478 // GIR_Coverage, 16465, 10479 GIR_Done, 10480 // Label 802: @23271 10481 GIM_Reject, 10482 // Label 783: @23272 10483 GIM_Try, /*On fail goto*//*Label 803*/ 23334, 10484 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s1, 10485 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 10486 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VK8RegClassID, 10487 GIM_Try, /*On fail goto*//*Label 804*/ 23297, // Rule ID 16460 // 10488 GIM_CheckFeatures, GIFBS_HasBWI_HasVLX, 10489 // (anyext:{ *:[v8i16] } VK8:{ *:[v8i1] }:$src) => (VPMOVM2WZ128rr:{ *:[v8i16] } VK8:{ *:[v8i1] }:$src) 10490 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMOVM2WZ128rr, 10491 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10492 // GIR_Coverage, 16460, 10493 GIR_Done, 10494 // Label 804: @23297 10495 GIM_Try, /*On fail goto*//*Label 805*/ 23333, // Rule ID 16480 // 10496 GIM_CheckFeatures, GIFBS_HasDQI_HasVLX_NoBWI, 10497 // (anyext:{ *:[v8i16] } VK8:{ *:[v8i1] }:$src) => (VPMOVDWZ256rr:{ *:[v8i16] } (VPMOVM2DZ256rr:{ *:[v8i32] } VK8:{ *:[v8i1] }:$src)) 10498 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s32, 10499 GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::VPMOVM2DZ256rr, 10500 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 10501 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src 10502 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 10503 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VPMOVDWZ256rr, 10504 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 10505 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 10506 GIR_EraseFromParent, /*InsnID*/0, 10507 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10508 // GIR_Coverage, 16480, 10509 GIR_Done, 10510 // Label 805: @23333 10511 GIM_Reject, 10512 // Label 803: @23334 10513 GIM_Reject, 10514 // Label 784: @23335 10515 GIM_Try, /*On fail goto*//*Label 806*/ 23358, // Rule ID 16462 // 10516 GIM_CheckFeatures, GIFBS_HasDQI_HasVLX, 10517 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s1, 10518 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 10519 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VK8RegClassID, 10520 // (anyext:{ *:[v8i32] } VK8:{ *:[v8i1] }:$src) => (VPMOVM2DZ256rr:{ *:[v8i32] } VK8:{ *:[v8i1] }:$src) 10521 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMOVM2DZ256rr, 10522 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10523 // GIR_Coverage, 16462, 10524 GIR_Done, 10525 // Label 806: @23358 10526 GIM_Reject, 10527 // Label 785: @23359 10528 GIM_Try, /*On fail goto*//*Label 807*/ 23382, // Rule ID 16464 // 10529 GIM_CheckFeatures, GIFBS_HasDQI, 10530 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s1, 10531 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 10532 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VK8RegClassID, 10533 // (anyext:{ *:[v8i64] } VK8:{ *:[v8i1] }:$src) => (VPMOVM2QZrr:{ *:[v8i64] } VK8:{ *:[v8i1] }:$src) 10534 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMOVM2QZrr, 10535 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10536 // GIR_Coverage, 16464, 10537 GIR_Done, 10538 // Label 807: @23382 10539 GIM_Reject, 10540 // Label 786: @23383 10541 GIM_Try, /*On fail goto*//*Label 808*/ 23445, 10542 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s1, 10543 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 10544 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VK16RegClassID, 10545 GIM_Try, /*On fail goto*//*Label 809*/ 23408, // Rule ID 16457 // 10546 GIM_CheckFeatures, GIFBS_HasBWI_HasVLX, 10547 // (anyext:{ *:[v16i8] } VK16:{ *:[v16i1] }:$src) => (VPMOVM2BZ128rr:{ *:[v16i8] } VK16:{ *:[v16i1] }:$src) 10548 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMOVM2BZ128rr, 10549 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10550 // GIR_Coverage, 16457, 10551 GIR_Done, 10552 // Label 809: @23408 10553 GIM_Try, /*On fail goto*//*Label 810*/ 23444, // Rule ID 16477 // 10554 GIM_CheckFeatures, GIFBS_HasDQI_NoBWI, 10555 // (anyext:{ *:[v16i8] } VK16:{ *:[v16i1] }:$src) => (VPMOVDBZrr:{ *:[v16i8] } (VPMOVM2DZrr:{ *:[v16i32] } VK16:{ *:[v16i1] }:$src)) 10556 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s32, 10557 GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::VPMOVM2DZrr, 10558 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 10559 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src 10560 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 10561 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VPMOVDBZrr, 10562 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 10563 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 10564 GIR_EraseFromParent, /*InsnID*/0, 10565 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10566 // GIR_Coverage, 16477, 10567 GIR_Done, 10568 // Label 810: @23444 10569 GIM_Reject, 10570 // Label 808: @23445 10571 GIM_Reject, 10572 // Label 787: @23446 10573 GIM_Try, /*On fail goto*//*Label 811*/ 23508, 10574 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s1, 10575 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 10576 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VK16RegClassID, 10577 GIM_Try, /*On fail goto*//*Label 812*/ 23471, // Rule ID 16459 // 10578 GIM_CheckFeatures, GIFBS_HasBWI_HasVLX, 10579 // (anyext:{ *:[v16i16] } VK16:{ *:[v16i1] }:$src) => (VPMOVM2WZ256rr:{ *:[v16i16] } VK16:{ *:[v16i1] }:$src) 10580 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMOVM2WZ256rr, 10581 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10582 // GIR_Coverage, 16459, 10583 GIR_Done, 10584 // Label 812: @23471 10585 GIM_Try, /*On fail goto*//*Label 813*/ 23507, // Rule ID 16478 // 10586 GIM_CheckFeatures, GIFBS_HasDQI_NoBWI, 10587 // (anyext:{ *:[v16i16] } VK16:{ *:[v16i1] }:$src) => (VPMOVDWZrr:{ *:[v16i16] } (VPMOVM2DZrr:{ *:[v16i32] } VK16:{ *:[v16i1] }:$src)) 10588 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s32, 10589 GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::VPMOVM2DZrr, 10590 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 10591 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src 10592 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 10593 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VPMOVDWZrr, 10594 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 10595 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 10596 GIR_EraseFromParent, /*InsnID*/0, 10597 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10598 // GIR_Coverage, 16478, 10599 GIR_Done, 10600 // Label 813: @23507 10601 GIM_Reject, 10602 // Label 811: @23508 10603 GIM_Reject, 10604 // Label 788: @23509 10605 GIM_Try, /*On fail goto*//*Label 814*/ 23532, // Rule ID 16461 // 10606 GIM_CheckFeatures, GIFBS_HasDQI, 10607 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s1, 10608 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 10609 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VK16RegClassID, 10610 // (anyext:{ *:[v16i32] } VK16:{ *:[v16i1] }:$src) => (VPMOVM2DZrr:{ *:[v16i32] } VK16:{ *:[v16i1] }:$src) 10611 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMOVM2DZrr, 10612 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10613 // GIR_Coverage, 16461, 10614 GIR_Done, 10615 // Label 814: @23532 10616 GIM_Reject, 10617 // Label 789: @23533 10618 GIM_Try, /*On fail goto*//*Label 815*/ 23556, // Rule ID 16456 // 10619 GIM_CheckFeatures, GIFBS_HasBWI_HasVLX, 10620 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v32s1, 10621 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 10622 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VK32RegClassID, 10623 // (anyext:{ *:[v32i8] } VK32:{ *:[v32i1] }:$src) => (VPMOVM2BZ256rr:{ *:[v32i8] } VK32:{ *:[v32i1] }:$src) 10624 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMOVM2BZ256rr, 10625 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10626 // GIR_Coverage, 16456, 10627 GIR_Done, 10628 // Label 815: @23556 10629 GIM_Reject, 10630 // Label 790: @23557 10631 GIM_Try, /*On fail goto*//*Label 816*/ 23580, // Rule ID 16458 // 10632 GIM_CheckFeatures, GIFBS_HasBWI, 10633 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v32s1, 10634 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 10635 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VK32RegClassID, 10636 // (anyext:{ *:[v32i16] } VK32:{ *:[v32i1] }:$src) => (VPMOVM2WZrr:{ *:[v32i16] } VK32:{ *:[v32i1] }:$src) 10637 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMOVM2WZrr, 10638 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10639 // GIR_Coverage, 16458, 10640 GIR_Done, 10641 // Label 816: @23580 10642 GIM_Reject, 10643 // Label 791: @23581 10644 GIM_Try, /*On fail goto*//*Label 817*/ 23604, // Rule ID 16455 // 10645 GIM_CheckFeatures, GIFBS_HasBWI, 10646 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v64s1, 10647 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 10648 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VK64RegClassID, 10649 // (anyext:{ *:[v64i8] } VK64:{ *:[v64i1] }:$src) => (VPMOVM2BZrr:{ *:[v64i8] } VK64:{ *:[v64i1] }:$src) 10650 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMOVM2BZrr, 10651 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10652 // GIR_Coverage, 16455, 10653 GIR_Done, 10654 // Label 817: @23604 10655 GIM_Reject, 10656 // Label 792: @23605 10657 GIM_Reject, 10658 // Label 11: @23606 10659 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 22, /*)*//*default:*//*Label 826*/ 23988, 10660 /*GILLT_s8*//*Label 818*/ 23633, 10661 /*GILLT_s16*//*Label 819*/ 23712, 0, 0, 0, 0, 0, 0, 0, 10662 /*GILLT_v4s32*//*Label 820*/ 23750, 0, 0, 10663 /*GILLT_v8s16*//*Label 821*/ 23774, 10664 /*GILLT_v8s32*//*Label 822*/ 23821, 0, 0, 10665 /*GILLT_v16s8*//*Label 823*/ 23845, 10666 /*GILLT_v16s16*//*Label 824*/ 23940, 0, 0, 10667 /*GILLT_v32s8*//*Label 825*/ 23964, 10668 // Label 818: @23633 10669 GIM_Try, /*On fail goto*//*Label 827*/ 23672, // Rule ID 17183 // 10670 GIM_CheckFeatures, GIFBS_In64BitMode, 10671 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 10672 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 10673 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR32RegClassID, 10674 // (trunc:{ *:[i8] } GR32:{ *:[i32] }:$src) => (EXTRACT_SUBREG:{ *:[i8] } GR32:{ *:[i32] }:$src, sub_8bit:{ *:[i32] }) 10675 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 10676 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 10677 GIR_CopySubReg, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/1, // src 10678 GIR_EraseFromParent, /*InsnID*/0, 10679 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC GR8*/0, 10680 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, /*RC GR32*/33, 10681 // GIR_Coverage, 17183, 10682 GIR_Done, 10683 // Label 827: @23672 10684 GIM_Try, /*On fail goto*//*Label 828*/ 23711, // Rule ID 17184 // 10685 GIM_CheckFeatures, GIFBS_In64BitMode, 10686 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, 10687 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR16RegClassID, 10688 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR16RegClassID, 10689 // (trunc:{ *:[i8] } GR16:{ *:[i16] }:$src) => (EXTRACT_SUBREG:{ *:[i8] } GR16:{ *:[i16] }:$src, sub_8bit:{ *:[i32] }) 10690 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 10691 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 10692 GIR_CopySubReg, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/1, // src 10693 GIR_EraseFromParent, /*InsnID*/0, 10694 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC GR8*/0, 10695 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, /*RC GR16*/6, 10696 // GIR_Coverage, 17184, 10697 GIR_Done, 10698 // Label 828: @23711 10699 GIM_Reject, 10700 // Label 819: @23712 10701 GIM_Try, /*On fail goto*//*Label 829*/ 23749, // Rule ID 17177 // 10702 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 10703 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 10704 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR32RegClassID, 10705 // (trunc:{ *:[i16] } GR32:{ *:[i32] }:$src) => (EXTRACT_SUBREG:{ *:[i16] } GR32:{ *:[i32] }:$src, sub_16bit:{ *:[i32] }) 10706 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY, 10707 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 10708 GIR_CopySubReg, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/4, // src 10709 GIR_EraseFromParent, /*InsnID*/0, 10710 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC GR16*/6, 10711 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, /*RC GR32*/33, 10712 // GIR_Coverage, 17177, 10713 GIR_Done, 10714 // Label 829: @23749 10715 GIM_Reject, 10716 // Label 820: @23750 10717 GIM_Try, /*On fail goto*//*Label 830*/ 23773, // Rule ID 10193 // 10718 GIM_CheckFeatures, GIFBS_HasAVX512_HasVLX, 10719 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s64, 10720 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 10721 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 10722 // (trunc:{ *:[v4i32] } VR256X:{ *:[v4i64] }:$src) => (VPMOVQDZ256rr:{ *:[v4i32] } VR256X:{ *:[v4i64] }:$src) 10723 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMOVQDZ256rr, 10724 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10725 // GIR_Coverage, 10193, 10726 GIR_Done, 10727 // Label 830: @23773 10728 GIM_Reject, 10729 // Label 821: @23774 10730 GIM_Try, /*On fail goto*//*Label 831*/ 23797, // Rule ID 10169 // 10731 GIM_CheckFeatures, GIFBS_HasAVX512, 10732 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s64, 10733 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 10734 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID, 10735 // (trunc:{ *:[v8i16] } VR512:{ *:[v8i64] }:$src) => (VPMOVQWZrr:{ *:[v8i16] } VR512:{ *:[v8i64] }:$src) 10736 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMOVQWZrr, 10737 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10738 // GIR_Coverage, 10169, 10739 GIR_Done, 10740 // Label 831: @23797 10741 GIM_Try, /*On fail goto*//*Label 832*/ 23820, // Rule ID 10247 // 10742 GIM_CheckFeatures, GIFBS_HasAVX512_HasVLX, 10743 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s32, 10744 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 10745 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 10746 // (trunc:{ *:[v8i16] } VR256X:{ *:[v8i32] }:$src) => (VPMOVDWZ256rr:{ *:[v8i16] } VR256X:{ *:[v8i32] }:$src) 10747 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMOVDWZ256rr, 10748 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10749 // GIR_Coverage, 10247, 10750 GIR_Done, 10751 // Label 832: @23820 10752 GIM_Reject, 10753 // Label 822: @23821 10754 GIM_Try, /*On fail goto*//*Label 833*/ 23844, // Rule ID 10196 // 10755 GIM_CheckFeatures, GIFBS_HasAVX512, 10756 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s64, 10757 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 10758 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID, 10759 // (trunc:{ *:[v8i32] } VR512:{ *:[v8i64] }:$src) => (VPMOVQDZrr:{ *:[v8i32] } VR512:{ *:[v8i64] }:$src) 10760 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMOVQDZrr, 10761 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10762 // GIR_Coverage, 10196, 10763 GIR_Done, 10764 // Label 833: @23844 10765 GIM_Reject, 10766 // Label 823: @23845 10767 GIM_Try, /*On fail goto*//*Label 834*/ 23868, // Rule ID 10223 // 10768 GIM_CheckFeatures, GIFBS_HasAVX512, 10769 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s32, 10770 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 10771 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID, 10772 // (trunc:{ *:[v16i8] } VR512:{ *:[v16i32] }:$src) => (VPMOVDBZrr:{ *:[v16i8] } VR512:{ *:[v16i32] }:$src) 10773 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMOVDBZrr, 10774 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10775 // GIR_Coverage, 10223, 10776 GIR_Done, 10777 // Label 834: @23868 10778 GIM_Try, /*On fail goto*//*Label 835*/ 23891, // Rule ID 10274 // 10779 GIM_CheckFeatures, GIFBS_HasBWI_HasVLX, 10780 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s16, 10781 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 10782 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 10783 // (trunc:{ *:[v16i8] } VR256X:{ *:[v16i16] }:$src) => (VPMOVWBZ256rr:{ *:[v16i8] } VR256X:{ *:[v16i16] }:$src) 10784 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMOVWBZ256rr, 10785 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10786 // GIR_Coverage, 10274, 10787 GIR_Done, 10788 // Label 835: @23891 10789 GIM_Try, /*On fail goto*//*Label 836*/ 23939, // Rule ID 16453 // 10790 GIM_CheckFeatures, GIFBS_HasAVX512_NoBWI, 10791 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s16, 10792 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 10793 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 10794 // (trunc:{ *:[v16i8] } VR256X:{ *:[v16i16] }:$src) => (VPMOVDBZrr:{ *:[v16i8] } (VPMOVZXWDZrr:{ *:[v16i32] } VR256X:{ *:[v16i16] }:$src)) 10795 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s32, 10796 GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::VPMOVZXWDZrr, 10797 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 10798 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src 10799 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 10800 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VPMOVDBZrr, 10801 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 10802 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 10803 GIR_EraseFromParent, /*InsnID*/0, 10804 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10805 // GIR_Coverage, 16453, 10806 GIR_Done, 10807 // Label 836: @23939 10808 GIM_Reject, 10809 // Label 824: @23940 10810 GIM_Try, /*On fail goto*//*Label 837*/ 23963, // Rule ID 10250 // 10811 GIM_CheckFeatures, GIFBS_HasAVX512, 10812 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s32, 10813 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 10814 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID, 10815 // (trunc:{ *:[v16i16] } VR512:{ *:[v16i32] }:$src) => (VPMOVDWZrr:{ *:[v16i16] } VR512:{ *:[v16i32] }:$src) 10816 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMOVDWZrr, 10817 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10818 // GIR_Coverage, 10250, 10819 GIR_Done, 10820 // Label 837: @23963 10821 GIM_Reject, 10822 // Label 825: @23964 10823 GIM_Try, /*On fail goto*//*Label 838*/ 23987, // Rule ID 10277 // 10824 GIM_CheckFeatures, GIFBS_HasBWI, 10825 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v32s16, 10826 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 10827 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID, 10828 // (trunc:{ *:[v32i8] } VR512:{ *:[v32i16] }:$src) => (VPMOVWBZrr:{ *:[v32i8] } VR512:{ *:[v32i16] }:$src) 10829 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMOVWBZrr, 10830 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10831 // GIR_Coverage, 10277, 10832 GIR_Done, 10833 // Label 838: @23987 10834 GIM_Reject, 10835 // Label 826: @23988 10836 GIM_Reject, 10837 // Label 12: @23989 10838 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 5, /*)*//*default:*//*Label 843*/ 24191, 10839 /*GILLT_s8*//*Label 839*/ 23999, 10840 /*GILLT_s16*//*Label 840*/ 24021, 10841 /*GILLT_s32*//*Label 841*/ 24043, 10842 /*GILLT_s64*//*Label 842*/ 24140, 10843 // Label 839: @23999 10844 GIM_Try, /*On fail goto*//*Label 844*/ 24020, // Rule ID 19 // 10845 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR8RegClassID, 10846 // MIs[0] Operand 1 10847 // No operand predicates 10848 // (imm:{ *:[i8] }):$src => (MOV8ri:{ *:[i8] } (imm:{ *:[i8] }):$src) 10849 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::MOV8ri, 10850 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 10851 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // src 10852 GIR_EraseFromParent, /*InsnID*/0, 10853 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10854 // GIR_Coverage, 19, 10855 GIR_Done, 10856 // Label 844: @24020 10857 GIM_Reject, 10858 // Label 840: @24021 10859 GIM_Try, /*On fail goto*//*Label 845*/ 24042, // Rule ID 20 // 10860 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR16RegClassID, 10861 // MIs[0] Operand 1 10862 // No operand predicates 10863 // (imm:{ *:[i16] }):$src => (MOV16ri:{ *:[i16] } (imm:{ *:[i16] }):$src) 10864 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::MOV16ri, 10865 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 10866 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // src 10867 GIR_EraseFromParent, /*InsnID*/0, 10868 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10869 // GIR_Coverage, 20, 10870 GIR_Done, 10871 // Label 845: @24042 10872 GIM_Reject, 10873 // Label 841: @24043 10874 GIM_Try, /*On fail goto*//*Label 846*/ 24065, // Rule ID 12846 // 10875 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 10876 // MIs[0] Operand 1 10877 GIM_CheckLiteralInt, /*MI*/0, /*Op*/1, 0, 10878 // 0:{ *:[i32] } => (MOV32r0:{ *:[i32] }:{ *:[i32] }) 10879 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::MOV32r0, 10880 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 10881 GIR_EraseFromParent, /*InsnID*/0, 10882 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10883 // GIR_Coverage, 12846, 10884 GIR_Done, 10885 // Label 846: @24065 10886 GIM_Try, /*On fail goto*//*Label 847*/ 24089, // Rule ID 12847 // 10887 GIM_CheckFeatures, GIFBS_Not64BitMode_OptForSize, 10888 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 10889 // MIs[0] Operand 1 10890 GIM_CheckLiteralInt, /*MI*/0, /*Op*/1, 1, 10891 // 1:{ *:[i32] } => (MOV32r1:{ *:[i32] }:{ *:[i32] }) 10892 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::MOV32r1, 10893 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 10894 GIR_EraseFromParent, /*InsnID*/0, 10895 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10896 // GIR_Coverage, 12847, 10897 GIR_Done, 10898 // Label 847: @24089 10899 GIM_Try, /*On fail goto*//*Label 848*/ 24113, // Rule ID 12848 // 10900 GIM_CheckFeatures, GIFBS_Not64BitMode_OptForSize, 10901 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 10902 // MIs[0] Operand 1 10903 GIM_CheckLiteralInt, /*MI*/0, /*Op*/1, -1, 10904 // -1:{ *:[i32] } => (MOV32r_1:{ *:[i32] }:{ *:[i32] }) 10905 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::MOV32r_1, 10906 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 10907 GIR_EraseFromParent, /*InsnID*/0, 10908 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10909 // GIR_Coverage, 12848, 10910 GIR_Done, 10911 // Label 848: @24113 10912 GIM_Try, /*On fail goto*//*Label 849*/ 24139, // Rule ID 12849 // 10913 GIM_CheckFeatures, GIFBS_NotWin64WithoutFP_OptForMinSize, 10914 GIM_CheckI64ImmPredicate, /*MI*/0, /*Predicate*/GIPFP_I64_Predicate_i32immSExt8, 10915 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 10916 // MIs[0] Operand 1 10917 // No operand predicates 10918 // (imm:{ *:[i32] })<<P:Predicate_i32immSExt8>>:$src => (MOV32ImmSExti8:{ *:[i32] } (imm:{ *:[i32] }):$src) 10919 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::MOV32ImmSExti8, 10920 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 10921 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // src 10922 GIR_EraseFromParent, /*InsnID*/0, 10923 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10924 // GIR_Coverage, 12849, 10925 GIR_Done, 10926 // Label 849: @24139 10927 GIM_Reject, 10928 // Label 842: @24140 10929 GIM_Try, /*On fail goto*//*Label 850*/ 24166, // Rule ID 12850 // 10930 GIM_CheckFeatures, GIFBS_NotWin64WithoutFP_OptForMinSize, 10931 GIM_CheckI64ImmPredicate, /*MI*/0, /*Predicate*/GIPFP_I64_Predicate_i64immSExt8, 10932 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID, 10933 // MIs[0] Operand 1 10934 // No operand predicates 10935 // (imm:{ *:[i64] })<<P:Predicate_i64immSExt8>>:$src => (MOV64ImmSExti8:{ *:[i64] } (imm:{ *:[i64] }):$src) 10936 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::MOV64ImmSExti8, 10937 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 10938 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // src 10939 GIR_EraseFromParent, /*InsnID*/0, 10940 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10941 // GIR_Coverage, 12850, 10942 GIR_Done, 10943 // Label 850: @24166 10944 GIM_Try, /*On fail goto*//*Label 851*/ 24190, // Rule ID 22 // 10945 GIM_CheckI64ImmPredicate, /*MI*/0, /*Predicate*/GIPFP_I64_Predicate_i64immSExt32, 10946 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID, 10947 // MIs[0] Operand 1 10948 // No operand predicates 10949 // (imm:{ *:[i64] })<<P:Predicate_i64immSExt32>>:$src => (MOV64ri32:{ *:[i64] } (imm:{ *:[i64] }):$src) 10950 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::MOV64ri32, 10951 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 10952 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // src 10953 GIR_EraseFromParent, /*InsnID*/0, 10954 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10955 // GIR_Coverage, 22, 10956 GIR_Done, 10957 // Label 851: @24190 10958 GIM_Reject, 10959 // Label 843: @24191 10960 GIM_Reject, 10961 // Label 13: @24192 10962 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/3, 6, /*)*//*default:*//*Label 855*/ 24338, 10963 /*GILLT_s32*//*Label 852*/ 24201, 10964 /*GILLT_s64*//*Label 853*/ 24248, 10965 /*GILLT_s80*//*Label 854*/ 24295, 10966 // Label 852: @24201 10967 GIM_Try, /*On fail goto*//*Label 856*/ 24224, // Rule ID 827 // 10968 GIM_CheckFeatures, GIFBS_FPStackf32, 10969 GIM_CheckAPFloatImmPredicate, /*MI*/0, /*Predicate*/GIPFP_APFloat_Predicate_fpimm0, 10970 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::RFP32RegClassID, 10971 // MIs[0] Operand 1 10972 // No operand predicates 10973 // (fpimm:{ *:[f32] })<<P:Predicate_fpimm0>> => (LD_Fp032:{ *:[f32] }:{ *:[i16] }) 10974 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::LD_Fp032, 10975 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 10976 GIR_EraseFromParent, /*InsnID*/0, 10977 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10978 // GIR_Coverage, 827, 10979 GIR_Done, 10980 // Label 856: @24224 10981 GIM_Try, /*On fail goto*//*Label 857*/ 24247, // Rule ID 828 // 10982 GIM_CheckFeatures, GIFBS_FPStackf32, 10983 GIM_CheckAPFloatImmPredicate, /*MI*/0, /*Predicate*/GIPFP_APFloat_Predicate_fpimm1, 10984 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::RFP32RegClassID, 10985 // MIs[0] Operand 1 10986 // No operand predicates 10987 // (fpimm:{ *:[f32] })<<P:Predicate_fpimm1>> => (LD_Fp132:{ *:[f32] }:{ *:[i16] }) 10988 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::LD_Fp132, 10989 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 10990 GIR_EraseFromParent, /*InsnID*/0, 10991 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10992 // GIR_Coverage, 828, 10993 GIR_Done, 10994 // Label 857: @24247 10995 GIM_Reject, 10996 // Label 853: @24248 10997 GIM_Try, /*On fail goto*//*Label 858*/ 24271, // Rule ID 829 // 10998 GIM_CheckFeatures, GIFBS_FPStackf64, 10999 GIM_CheckAPFloatImmPredicate, /*MI*/0, /*Predicate*/GIPFP_APFloat_Predicate_fpimm0, 11000 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::RFP64RegClassID, 11001 // MIs[0] Operand 1 11002 // No operand predicates 11003 // (fpimm:{ *:[f64] })<<P:Predicate_fpimm0>> => (LD_Fp064:{ *:[f64] }:{ *:[i16] }) 11004 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::LD_Fp064, 11005 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 11006 GIR_EraseFromParent, /*InsnID*/0, 11007 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11008 // GIR_Coverage, 829, 11009 GIR_Done, 11010 // Label 858: @24271 11011 GIM_Try, /*On fail goto*//*Label 859*/ 24294, // Rule ID 830 // 11012 GIM_CheckFeatures, GIFBS_FPStackf64, 11013 GIM_CheckAPFloatImmPredicate, /*MI*/0, /*Predicate*/GIPFP_APFloat_Predicate_fpimm1, 11014 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::RFP64RegClassID, 11015 // MIs[0] Operand 1 11016 // No operand predicates 11017 // (fpimm:{ *:[f64] })<<P:Predicate_fpimm1>> => (LD_Fp164:{ *:[f64] }:{ *:[i16] }) 11018 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::LD_Fp164, 11019 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 11020 GIR_EraseFromParent, /*InsnID*/0, 11021 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11022 // GIR_Coverage, 830, 11023 GIR_Done, 11024 // Label 859: @24294 11025 GIM_Reject, 11026 // Label 854: @24295 11027 GIM_Try, /*On fail goto*//*Label 860*/ 24316, // Rule ID 831 // 11028 GIM_CheckAPFloatImmPredicate, /*MI*/0, /*Predicate*/GIPFP_APFloat_Predicate_fpimm0, 11029 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::RFP80RegClassID, 11030 // MIs[0] Operand 1 11031 // No operand predicates 11032 // (fpimm:{ *:[f80] })<<P:Predicate_fpimm0>> => (LD_Fp080:{ *:[f80] }:{ *:[i16] }) 11033 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::LD_Fp080, 11034 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 11035 GIR_EraseFromParent, /*InsnID*/0, 11036 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11037 // GIR_Coverage, 831, 11038 GIR_Done, 11039 // Label 860: @24316 11040 GIM_Try, /*On fail goto*//*Label 861*/ 24337, // Rule ID 832 // 11041 GIM_CheckAPFloatImmPredicate, /*MI*/0, /*Predicate*/GIPFP_APFloat_Predicate_fpimm1, 11042 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::RFP80RegClassID, 11043 // MIs[0] Operand 1 11044 // No operand predicates 11045 // (fpimm:{ *:[f80] })<<P:Predicate_fpimm1>> => (LD_Fp180:{ *:[f80] }:{ *:[i16] }) 11046 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::LD_Fp180, 11047 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 11048 GIR_EraseFromParent, /*InsnID*/0, 11049 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11050 // GIR_Coverage, 832, 11051 GIR_Done, 11052 // Label 861: @24337 11053 GIM_Reject, 11054 // Label 855: @24338 11055 GIM_Reject, 11056 // Label 14: @24339 11057 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/3, 25, /*)*//*default:*//*Label 876*/ 25143, 11058 /*GILLT_s32*//*Label 862*/ 24367, 11059 /*GILLT_s64*//*Label 863*/ 24410, 0, 0, 0, 11060 /*GILLT_v2s64*//*Label 864*/ 24476, 0, 11061 /*GILLT_v4s32*//*Label 865*/ 24500, 11062 /*GILLT_v4s64*//*Label 866*/ 24524, 0, 11063 /*GILLT_v8s16*//*Label 867*/ 24594, 11064 /*GILLT_v8s32*//*Label 868*/ 24657, 11065 /*GILLT_v8s64*//*Label 869*/ 24727, 0, 11066 /*GILLT_v16s8*//*Label 870*/ 24797, 11067 /*GILLT_v16s16*//*Label 871*/ 24860, 11068 /*GILLT_v16s32*//*Label 872*/ 24978, 0, 11069 /*GILLT_v32s8*//*Label 873*/ 25048, 11070 /*GILLT_v32s16*//*Label 874*/ 25072, 0, 11071 /*GILLT_v64s8*//*Label 875*/ 25119, 11072 // Label 862: @24367 11073 GIM_Try, /*On fail goto*//*Label 877*/ 24388, // Rule ID 408 // 11074 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s8, 11075 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 11076 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR8RegClassID, 11077 // (sext:{ *:[i32] } GR8:{ *:[i8] }:$src) => (MOVSX32rr8:{ *:[i32] } GR8:{ *:[i8] }:$src) 11078 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::MOVSX32rr8, 11079 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11080 // GIR_Coverage, 408, 11081 GIR_Done, 11082 // Label 877: @24388 11083 GIM_Try, /*On fail goto*//*Label 878*/ 24409, // Rule ID 410 // 11084 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, 11085 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 11086 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR16RegClassID, 11087 // (sext:{ *:[i32] } GR16:{ *:[i16] }:$src) => (MOVSX32rr16:{ *:[i32] } GR16:{ *:[i16] }:$src) 11088 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::MOVSX32rr16, 11089 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11090 // GIR_Coverage, 410, 11091 GIR_Done, 11092 // Label 878: @24409 11093 GIM_Reject, 11094 // Label 863: @24410 11095 GIM_Try, /*On fail goto*//*Label 879*/ 24431, // Rule ID 416 // 11096 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s8, 11097 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID, 11098 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR8RegClassID, 11099 // (sext:{ *:[i64] } GR8:{ *:[i8] }:$src) => (MOVSX64rr8:{ *:[i64] } GR8:{ *:[i8] }:$src) 11100 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::MOVSX64rr8, 11101 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11102 // GIR_Coverage, 416, 11103 GIR_Done, 11104 // Label 879: @24431 11105 GIM_Try, /*On fail goto*//*Label 880*/ 24452, // Rule ID 418 // 11106 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, 11107 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID, 11108 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR16RegClassID, 11109 // (sext:{ *:[i64] } GR16:{ *:[i16] }:$src) => (MOVSX64rr16:{ *:[i64] } GR16:{ *:[i16] }:$src) 11110 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::MOVSX64rr16, 11111 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11112 // GIR_Coverage, 418, 11113 GIR_Done, 11114 // Label 880: @24452 11115 GIM_Try, /*On fail goto*//*Label 881*/ 24475, // Rule ID 420 // 11116 GIM_CheckFeatures, GIFBS_In64BitMode, 11117 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 11118 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID, 11119 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR32RegClassID, 11120 // (sext:{ *:[i64] } GR32:{ *:[i32] }:$src) => (MOVSX64rr32:{ *:[i64] } GR32:{ *:[i32] }:$src) 11121 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::MOVSX64rr32, 11122 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11123 // GIR_Coverage, 420, 11124 GIR_Done, 11125 // Label 881: @24475 11126 GIM_Reject, 11127 // Label 864: @24476 11128 GIM_Try, /*On fail goto*//*Label 882*/ 24499, // Rule ID 10573 // 11129 GIM_CheckFeatures, GIFBS_HasDQI_HasVLX, 11130 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s1, 11131 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 11132 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VK2RegClassID, 11133 // (sext:{ *:[v2i64] } VK2:{ *:[v2i1] }:$src) => (VPMOVM2QZ128rr:{ *:[v2i64] } VK2:{ *:[v2i1] }:$src) 11134 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMOVM2QZ128rr, 11135 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11136 // GIR_Coverage, 10573, 11137 GIR_Done, 11138 // Label 882: @24499 11139 GIM_Reject, 11140 // Label 865: @24500 11141 GIM_Try, /*On fail goto*//*Label 883*/ 24523, // Rule ID 10570 // 11142 GIM_CheckFeatures, GIFBS_HasDQI_HasVLX, 11143 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s1, 11144 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 11145 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VK4RegClassID, 11146 // (sext:{ *:[v4i32] } VK4:{ *:[v4i1] }:$src) => (VPMOVM2DZ128rr:{ *:[v4i32] } VK4:{ *:[v4i1] }:$src) 11147 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMOVM2DZ128rr, 11148 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11149 // GIR_Coverage, 10570, 11150 GIR_Done, 11151 // Label 883: @24523 11152 GIM_Reject, 11153 // Label 866: @24524 11154 GIM_Try, /*On fail goto*//*Label 884*/ 24547, // Rule ID 10502 // 11155 GIM_CheckFeatures, GIFBS_HasAVX512_HasVLX, 11156 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 11157 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 11158 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 11159 // (sext:{ *:[v4i64] } VR128X:{ *:[v4i32] }:$src) => (VPMOVSXDQZ256rr:{ *:[v4i64] } VR128X:{ *:[v4i32] }:$src) 11160 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMOVSXDQZ256rr, 11161 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11162 // GIR_Coverage, 10502, 11163 GIR_Done, 11164 // Label 884: @24547 11165 GIM_Try, /*On fail goto*//*Label 885*/ 24570, // Rule ID 10572 // 11166 GIM_CheckFeatures, GIFBS_HasDQI_HasVLX, 11167 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s1, 11168 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 11169 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VK4RegClassID, 11170 // (sext:{ *:[v4i64] } VK4:{ *:[v4i1] }:$src) => (VPMOVM2QZ256rr:{ *:[v4i64] } VK4:{ *:[v4i1] }:$src) 11171 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMOVM2QZ256rr, 11172 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11173 // GIR_Coverage, 10572, 11174 GIR_Done, 11175 // Label 885: @24570 11176 GIM_Try, /*On fail goto*//*Label 886*/ 24593, // Rule ID 13676 // 11177 GIM_CheckFeatures, GIFBS_HasAVX2_NoVLX, 11178 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 11179 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID, 11180 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 11181 // (sext:{ *:[v4i64] } VR128:{ *:[v4i32] }:$src) => (VPMOVSXDQYrr:{ *:[v4i64] } VR128:{ *:[v4i32] }:$src) 11182 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMOVSXDQYrr, 11183 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11184 // GIR_Coverage, 13676, 11185 GIR_Done, 11186 // Label 886: @24593 11187 GIM_Reject, 11188 // Label 867: @24594 11189 GIM_Try, /*On fail goto*//*Label 887*/ 24656, 11190 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s1, 11191 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 11192 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VK8RegClassID, 11193 GIM_Try, /*On fail goto*//*Label 888*/ 24619, // Rule ID 10567 // 11194 GIM_CheckFeatures, GIFBS_HasBWI_HasVLX, 11195 // (sext:{ *:[v8i16] } VK8:{ *:[v8i1] }:$src) => (VPMOVM2WZ128rr:{ *:[v8i16] } VK8:{ *:[v8i1] }:$src) 11196 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMOVM2WZ128rr, 11197 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11198 // GIR_Coverage, 10567, 11199 GIR_Done, 11200 // Label 888: @24619 11201 GIM_Try, /*On fail goto*//*Label 889*/ 24655, // Rule ID 16479 // 11202 GIM_CheckFeatures, GIFBS_HasDQI_HasVLX_NoBWI, 11203 // (sext:{ *:[v8i16] } VK8:{ *:[v8i1] }:$src) => (VPMOVDWZ256rr:{ *:[v8i16] } (VPMOVM2DZ256rr:{ *:[v8i32] } VK8:{ *:[v8i1] }:$src)) 11204 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s32, 11205 GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::VPMOVM2DZ256rr, 11206 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 11207 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src 11208 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 11209 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VPMOVDWZ256rr, 11210 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 11211 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 11212 GIR_EraseFromParent, /*InsnID*/0, 11213 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11214 // GIR_Coverage, 16479, 11215 GIR_Done, 11216 // Label 889: @24655 11217 GIM_Reject, 11218 // Label 887: @24656 11219 GIM_Reject, 11220 // Label 868: @24657 11221 GIM_Try, /*On fail goto*//*Label 890*/ 24680, // Rule ID 10466 // 11222 GIM_CheckFeatures, GIFBS_HasAVX512_HasVLX, 11223 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, 11224 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 11225 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 11226 // (sext:{ *:[v8i32] } VR128X:{ *:[v8i16] }:$src) => (VPMOVSXWDZ256rr:{ *:[v8i32] } VR128X:{ *:[v8i16] }:$src) 11227 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMOVSXWDZ256rr, 11228 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11229 // GIR_Coverage, 10466, 11230 GIR_Done, 11231 // Label 890: @24680 11232 GIM_Try, /*On fail goto*//*Label 891*/ 24703, // Rule ID 10569 // 11233 GIM_CheckFeatures, GIFBS_HasDQI_HasVLX, 11234 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s1, 11235 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 11236 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VK8RegClassID, 11237 // (sext:{ *:[v8i32] } VK8:{ *:[v8i1] }:$src) => (VPMOVM2DZ256rr:{ *:[v8i32] } VK8:{ *:[v8i1] }:$src) 11238 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMOVM2DZ256rr, 11239 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11240 // GIR_Coverage, 10569, 11241 GIR_Done, 11242 // Label 891: @24703 11243 GIM_Try, /*On fail goto*//*Label 892*/ 24726, // Rule ID 13674 // 11244 GIM_CheckFeatures, GIFBS_HasAVX2_NoVLX, 11245 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, 11246 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID, 11247 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 11248 // (sext:{ *:[v8i32] } VR128:{ *:[v8i16] }:$src) => (VPMOVSXWDYrr:{ *:[v8i32] } VR128:{ *:[v8i16] }:$src) 11249 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMOVSXWDYrr, 11250 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11251 // GIR_Coverage, 13674, 11252 GIR_Done, 11253 // Label 892: @24726 11254 GIM_Reject, 11255 // Label 869: @24727 11256 GIM_Try, /*On fail goto*//*Label 893*/ 24750, // Rule ID 10490 // 11257 GIM_CheckFeatures, GIFBS_HasAVX512, 11258 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, 11259 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 11260 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 11261 // (sext:{ *:[v8i64] } VR128X:{ *:[v8i16] }:$src) => (VPMOVSXWQZrr:{ *:[v8i64] } VR128X:{ *:[v8i16] }:$src) 11262 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMOVSXWQZrr, 11263 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11264 // GIR_Coverage, 10490, 11265 GIR_Done, 11266 // Label 893: @24750 11267 GIM_Try, /*On fail goto*//*Label 894*/ 24773, // Rule ID 10508 // 11268 GIM_CheckFeatures, GIFBS_HasAVX512, 11269 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s32, 11270 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 11271 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 11272 // (sext:{ *:[v8i64] } VR256X:{ *:[v8i32] }:$src) => (VPMOVSXDQZrr:{ *:[v8i64] } VR256X:{ *:[v8i32] }:$src) 11273 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMOVSXDQZrr, 11274 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11275 // GIR_Coverage, 10508, 11276 GIR_Done, 11277 // Label 894: @24773 11278 GIM_Try, /*On fail goto*//*Label 895*/ 24796, // Rule ID 10571 // 11279 GIM_CheckFeatures, GIFBS_HasDQI, 11280 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s1, 11281 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 11282 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VK8RegClassID, 11283 // (sext:{ *:[v8i64] } VK8:{ *:[v8i1] }:$src) => (VPMOVM2QZrr:{ *:[v8i64] } VK8:{ *:[v8i1] }:$src) 11284 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMOVM2QZrr, 11285 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11286 // GIR_Coverage, 10571, 11287 GIR_Done, 11288 // Label 895: @24796 11289 GIM_Reject, 11290 // Label 870: @24797 11291 GIM_Try, /*On fail goto*//*Label 896*/ 24859, 11292 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s1, 11293 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 11294 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VK16RegClassID, 11295 GIM_Try, /*On fail goto*//*Label 897*/ 24822, // Rule ID 10564 // 11296 GIM_CheckFeatures, GIFBS_HasBWI_HasVLX, 11297 // (sext:{ *:[v16i8] } VK16:{ *:[v16i1] }:$src) => (VPMOVM2BZ128rr:{ *:[v16i8] } VK16:{ *:[v16i1] }:$src) 11298 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMOVM2BZ128rr, 11299 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11300 // GIR_Coverage, 10564, 11301 GIR_Done, 11302 // Label 897: @24822 11303 GIM_Try, /*On fail goto*//*Label 898*/ 24858, // Rule ID 16475 // 11304 GIM_CheckFeatures, GIFBS_HasDQI_NoBWI, 11305 // (sext:{ *:[v16i8] } VK16:{ *:[v16i1] }:$src) => (VPMOVDBZrr:{ *:[v16i8] } (VPMOVM2DZrr:{ *:[v16i32] } VK16:{ *:[v16i1] }:$src)) 11306 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s32, 11307 GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::VPMOVM2DZrr, 11308 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 11309 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src 11310 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 11311 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VPMOVDBZrr, 11312 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 11313 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 11314 GIR_EraseFromParent, /*InsnID*/0, 11315 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11316 // GIR_Coverage, 16475, 11317 GIR_Done, 11318 // Label 898: @24858 11319 GIM_Reject, 11320 // Label 896: @24859 11321 GIM_Reject, 11322 // Label 871: @24860 11323 GIM_Try, /*On fail goto*//*Label 899*/ 24883, // Rule ID 10412 // 11324 GIM_CheckFeatures, GIFBS_HasBWI_HasVLX, 11325 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, 11326 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 11327 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 11328 // (sext:{ *:[v16i16] } VR128X:{ *:[v16i8] }:$src) => (VPMOVSXBWZ256rr:{ *:[v16i16] } VR128X:{ *:[v16i8] }:$src) 11329 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMOVSXBWZ256rr, 11330 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11331 // GIR_Coverage, 10412, 11332 GIR_Done, 11333 // Label 899: @24883 11334 GIM_Try, /*On fail goto*//*Label 900*/ 24906, // Rule ID 10566 // 11335 GIM_CheckFeatures, GIFBS_HasBWI_HasVLX, 11336 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s1, 11337 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 11338 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VK16RegClassID, 11339 // (sext:{ *:[v16i16] } VK16:{ *:[v16i1] }:$src) => (VPMOVM2WZ256rr:{ *:[v16i16] } VK16:{ *:[v16i1] }:$src) 11340 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMOVM2WZ256rr, 11341 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11342 // GIR_Coverage, 10566, 11343 GIR_Done, 11344 // Label 900: @24906 11345 GIM_Try, /*On fail goto*//*Label 901*/ 24929, // Rule ID 13671 // 11346 GIM_CheckFeatures, GIFBS_HasAVX2_NoVLX_Or_NoBWI, 11347 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, 11348 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID, 11349 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 11350 // (sext:{ *:[v16i16] } VR128:{ *:[v16i8] }:$src) => (VPMOVSXBWYrr:{ *:[v16i16] } VR128:{ *:[v16i8] }:$src) 11351 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMOVSXBWYrr, 11352 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11353 // GIR_Coverage, 13671, 11354 GIR_Done, 11355 // Label 901: @24929 11356 GIM_Try, /*On fail goto*//*Label 902*/ 24977, // Rule ID 16476 // 11357 GIM_CheckFeatures, GIFBS_HasDQI_NoBWI, 11358 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s1, 11359 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 11360 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VK16RegClassID, 11361 // (sext:{ *:[v16i16] } VK16:{ *:[v16i1] }:$src) => (VPMOVDWZrr:{ *:[v16i16] } (VPMOVM2DZrr:{ *:[v16i32] } VK16:{ *:[v16i1] }:$src)) 11362 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s32, 11363 GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::VPMOVM2DZrr, 11364 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 11365 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src 11366 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 11367 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VPMOVDWZrr, 11368 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 11369 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 11370 GIR_EraseFromParent, /*InsnID*/0, 11371 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11372 // GIR_Coverage, 16476, 11373 GIR_Done, 11374 // Label 902: @24977 11375 GIM_Reject, 11376 // Label 872: @24978 11377 GIM_Try, /*On fail goto*//*Label 903*/ 25001, // Rule ID 10436 // 11378 GIM_CheckFeatures, GIFBS_HasAVX512, 11379 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, 11380 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 11381 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 11382 // (sext:{ *:[v16i32] } VR128X:{ *:[v16i8] }:$src) => (VPMOVSXBDZrr:{ *:[v16i32] } VR128X:{ *:[v16i8] }:$src) 11383 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMOVSXBDZrr, 11384 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11385 // GIR_Coverage, 10436, 11386 GIR_Done, 11387 // Label 903: @25001 11388 GIM_Try, /*On fail goto*//*Label 904*/ 25024, // Rule ID 10472 // 11389 GIM_CheckFeatures, GIFBS_HasAVX512, 11390 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s16, 11391 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 11392 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 11393 // (sext:{ *:[v16i32] } VR256X:{ *:[v16i16] }:$src) => (VPMOVSXWDZrr:{ *:[v16i32] } VR256X:{ *:[v16i16] }:$src) 11394 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMOVSXWDZrr, 11395 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11396 // GIR_Coverage, 10472, 11397 GIR_Done, 11398 // Label 904: @25024 11399 GIM_Try, /*On fail goto*//*Label 905*/ 25047, // Rule ID 10568 // 11400 GIM_CheckFeatures, GIFBS_HasDQI, 11401 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s1, 11402 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 11403 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VK16RegClassID, 11404 // (sext:{ *:[v16i32] } VK16:{ *:[v16i1] }:$src) => (VPMOVM2DZrr:{ *:[v16i32] } VK16:{ *:[v16i1] }:$src) 11405 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMOVM2DZrr, 11406 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11407 // GIR_Coverage, 10568, 11408 GIR_Done, 11409 // Label 905: @25047 11410 GIM_Reject, 11411 // Label 873: @25048 11412 GIM_Try, /*On fail goto*//*Label 906*/ 25071, // Rule ID 10563 // 11413 GIM_CheckFeatures, GIFBS_HasBWI_HasVLX, 11414 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v32s1, 11415 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 11416 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VK32RegClassID, 11417 // (sext:{ *:[v32i8] } VK32:{ *:[v32i1] }:$src) => (VPMOVM2BZ256rr:{ *:[v32i8] } VK32:{ *:[v32i1] }:$src) 11418 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMOVM2BZ256rr, 11419 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11420 // GIR_Coverage, 10563, 11421 GIR_Done, 11422 // Label 906: @25071 11423 GIM_Reject, 11424 // Label 874: @25072 11425 GIM_Try, /*On fail goto*//*Label 907*/ 25095, // Rule ID 10418 // 11426 GIM_CheckFeatures, GIFBS_HasBWI, 11427 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v32s8, 11428 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 11429 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 11430 // (sext:{ *:[v32i16] } VR256X:{ *:[v32i8] }:$src) => (VPMOVSXBWZrr:{ *:[v32i16] } VR256X:{ *:[v32i8] }:$src) 11431 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMOVSXBWZrr, 11432 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11433 // GIR_Coverage, 10418, 11434 GIR_Done, 11435 // Label 907: @25095 11436 GIM_Try, /*On fail goto*//*Label 908*/ 25118, // Rule ID 10565 // 11437 GIM_CheckFeatures, GIFBS_HasBWI, 11438 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v32s1, 11439 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 11440 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VK32RegClassID, 11441 // (sext:{ *:[v32i16] } VK32:{ *:[v32i1] }:$src) => (VPMOVM2WZrr:{ *:[v32i16] } VK32:{ *:[v32i1] }:$src) 11442 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMOVM2WZrr, 11443 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11444 // GIR_Coverage, 10565, 11445 GIR_Done, 11446 // Label 908: @25118 11447 GIM_Reject, 11448 // Label 875: @25119 11449 GIM_Try, /*On fail goto*//*Label 909*/ 25142, // Rule ID 10562 // 11450 GIM_CheckFeatures, GIFBS_HasBWI, 11451 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v64s1, 11452 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 11453 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VK64RegClassID, 11454 // (sext:{ *:[v64i8] } VK64:{ *:[v64i1] }:$src) => (VPMOVM2BZrr:{ *:[v64i8] } VK64:{ *:[v64i1] }:$src) 11455 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMOVM2BZrr, 11456 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11457 // GIR_Coverage, 10562, 11458 GIR_Done, 11459 // Label 909: @25142 11460 GIM_Reject, 11461 // Label 876: @25143 11462 GIM_Reject, 11463 // Label 15: @25144 11464 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/3, 23, /*)*//*default:*//*Label 918*/ 25876, 11465 /*GILLT_s32*//*Label 910*/ 25170, 11466 /*GILLT_s64*//*Label 911*/ 25301, 0, 0, 0, 0, 0, 0, 11467 /*GILLT_v4s64*//*Label 912*/ 25620, 0, 0, 11468 /*GILLT_v8s32*//*Label 913*/ 25666, 11469 /*GILLT_v8s64*//*Label 914*/ 25712, 0, 0, 11470 /*GILLT_v16s16*//*Label 915*/ 25759, 11471 /*GILLT_v16s32*//*Label 916*/ 25805, 0, 0, 11472 /*GILLT_v32s16*//*Label 917*/ 25852, 11473 // Label 910: @25170 11474 GIM_Try, /*On fail goto*//*Label 919*/ 25213, // Rule ID 14537 // 11475 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, 11476 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 11477 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 11478 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_BITCAST, 11479 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s1, 11480 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::VK16RegClassID, 11481 GIM_CheckIsSafeToFold, /*InsnID*/1, 11482 // (zext:{ *:[i32] } (bitconvert:{ *:[i16] } VK16:{ *:[v16i1] }:$src)) => (KMOVWrk:{ *:[i32] } VK16:{ *:[v16i1] }:$src) 11483 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::KMOVWrk, 11484 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 11485 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src 11486 GIR_EraseFromParent, /*InsnID*/0, 11487 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11488 // GIR_Coverage, 14537, 11489 GIR_Done, 11490 // Label 919: @25213 11491 GIM_Try, /*On fail goto*//*Label 920*/ 25258, // Rule ID 14540 // 11492 GIM_CheckFeatures, GIFBS_HasDQI, 11493 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s8, 11494 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 11495 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 11496 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_BITCAST, 11497 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s1, 11498 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::VK8RegClassID, 11499 GIM_CheckIsSafeToFold, /*InsnID*/1, 11500 // (zext:{ *:[i32] } (bitconvert:{ *:[i8] } VK8:{ *:[v8i1] }:$src)) => (KMOVBrk:{ *:[i32] } VK8:{ *:[v8i1] }:$src) 11501 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::KMOVBrk, 11502 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 11503 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src 11504 GIR_EraseFromParent, /*InsnID*/0, 11505 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11506 // GIR_Coverage, 14540, 11507 GIR_Done, 11508 // Label 920: @25258 11509 GIM_Try, /*On fail goto*//*Label 921*/ 25279, // Rule ID 412 // 11510 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s8, 11511 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 11512 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR8RegClassID, 11513 // (zext:{ *:[i32] } GR8:{ *:[i8] }:$src) => (MOVZX32rr8:{ *:[i32] } GR8:{ *:[i8] }:$src) 11514 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::MOVZX32rr8, 11515 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11516 // GIR_Coverage, 412, 11517 GIR_Done, 11518 // Label 921: @25279 11519 GIM_Try, /*On fail goto*//*Label 922*/ 25300, // Rule ID 414 // 11520 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, 11521 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 11522 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR16RegClassID, 11523 // (zext:{ *:[i32] } GR16:{ *:[i16] }:$src) => (MOVZX32rr16:{ *:[i32] } GR16:{ *:[i16] }:$src) 11524 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::MOVZX32rr16, 11525 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11526 // GIR_Coverage, 414, 11527 GIR_Done, 11528 // Label 922: @25300 11529 GIM_Reject, 11530 // Label 911: @25301 11531 GIM_Try, /*On fail goto*//*Label 923*/ 25372, // Rule ID 14538 // 11532 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, 11533 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID, 11534 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 11535 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_BITCAST, 11536 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s1, 11537 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::VK16RegClassID, 11538 GIM_CheckIsSafeToFold, /*InsnID*/1, 11539 // (zext:{ *:[i64] } (bitconvert:{ *:[i16] } VK16:{ *:[v16i1] }:$src)) => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (KMOVWrk:{ *:[i32] } VK16:{ *:[v16i1] }:$src), sub_32bit:{ *:[i32] }) 11540 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, 11541 GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::KMOVWrk, 11542 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 11543 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // src 11544 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 11545 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG, 11546 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 11547 GIR_AddImm, /*InsnID*/0, /*Imm*/0, 11548 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 11549 GIR_AddImm, /*InsnID*/0, /*Imm*/6, 11550 GIR_EraseFromParent, /*InsnID*/0, 11551 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC GR64*/65, 11552 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, /*RC GR32*/33, 11553 // GIR_Coverage, 14538, 11554 GIR_Done, 11555 // Label 923: @25372 11556 GIM_Try, /*On fail goto*//*Label 924*/ 25445, // Rule ID 14541 // 11557 GIM_CheckFeatures, GIFBS_HasDQI, 11558 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s8, 11559 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID, 11560 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 11561 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_BITCAST, 11562 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s1, 11563 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/X86::VK8RegClassID, 11564 GIM_CheckIsSafeToFold, /*InsnID*/1, 11565 // (zext:{ *:[i64] } (bitconvert:{ *:[i8] } VK8:{ *:[v8i1] }:$src)) => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (KMOVBrk:{ *:[i32] } VK8:{ *:[v8i1] }:$src), sub_32bit:{ *:[i32] }) 11566 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, 11567 GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::KMOVBrk, 11568 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 11569 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // src 11570 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 11571 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG, 11572 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 11573 GIR_AddImm, /*InsnID*/0, /*Imm*/0, 11574 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 11575 GIR_AddImm, /*InsnID*/0, /*Imm*/6, 11576 GIR_EraseFromParent, /*InsnID*/0, 11577 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC GR64*/65, 11578 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, /*RC GR32*/33, 11579 // GIR_Coverage, 14541, 11580 GIR_Done, 11581 // Label 924: @25445 11582 GIM_Try, /*On fail goto*//*Label 925*/ 25503, // Rule ID 13056 // 11583 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s8, 11584 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID, 11585 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR8RegClassID, 11586 // (zext:{ *:[i64] } GR8:{ *:[i8] }:$src) => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (MOVZX32rr8:{ *:[i32] } GR8:{ *:[i8] }:$src), sub_32bit:{ *:[i32] }) 11587 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, 11588 GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::MOVZX32rr8, 11589 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 11590 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src 11591 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 11592 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG, 11593 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 11594 GIR_AddImm, /*InsnID*/0, /*Imm*/0, 11595 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 11596 GIR_AddImm, /*InsnID*/0, /*Imm*/6, 11597 GIR_EraseFromParent, /*InsnID*/0, 11598 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC GR64*/65, 11599 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, /*RC GR32*/33, 11600 // GIR_Coverage, 13056, 11601 GIR_Done, 11602 // Label 925: @25503 11603 GIM_Try, /*On fail goto*//*Label 926*/ 25561, // Rule ID 13058 // 11604 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, 11605 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID, 11606 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR16RegClassID, 11607 // (zext:{ *:[i64] } GR16:{ *:[i16] }:$src) => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (MOVZX32rr16:{ *:[i32] } GR16:{ *:[i16] }:$src), sub_32bit:{ *:[i32] }) 11608 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, 11609 GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::MOVZX32rr16, 11610 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 11611 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src 11612 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 11613 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG, 11614 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 11615 GIR_AddImm, /*InsnID*/0, /*Imm*/0, 11616 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 11617 GIR_AddImm, /*InsnID*/0, /*Imm*/6, 11618 GIR_EraseFromParent, /*InsnID*/0, 11619 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC GR64*/65, 11620 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, /*RC GR32*/33, 11621 // GIR_Coverage, 13058, 11622 GIR_Done, 11623 // Label 926: @25561 11624 GIM_Try, /*On fail goto*//*Label 927*/ 25619, // Rule ID 13060 // 11625 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 11626 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID, 11627 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR32RegClassID, 11628 // (zext:{ *:[i64] } GR32:{ *:[i32] }:$src) => (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (MOV32rr:{ *:[i32] } GR32:{ *:[i32] }:$src), sub_32bit:{ *:[i32] }) 11629 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, 11630 GIR_BuildMI, /*InsnID*/1, /*Opcode*/X86::MOV32rr, 11631 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 11632 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src 11633 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 11634 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::SUBREG_TO_REG, 11635 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 11636 GIR_AddImm, /*InsnID*/0, /*Imm*/0, 11637 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 11638 GIR_AddImm, /*InsnID*/0, /*Imm*/6, 11639 GIR_EraseFromParent, /*InsnID*/0, 11640 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC GR64*/65, 11641 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, /*RC GR32*/33, 11642 // GIR_Coverage, 13060, 11643 GIR_Done, 11644 // Label 927: @25619 11645 GIM_Reject, 11646 // Label 912: @25620 11647 GIM_Try, /*On fail goto*//*Label 928*/ 25665, 11648 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 11649 GIM_Try, /*On fail goto*//*Label 929*/ 25645, // Rule ID 10394 // 11650 GIM_CheckFeatures, GIFBS_HasAVX512_HasVLX, 11651 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 11652 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 11653 // (zext:{ *:[v4i64] } VR128X:{ *:[v4i32] }:$src) => (VPMOVZXDQZ256rr:{ *:[v4i64] } VR128X:{ *:[v4i32] }:$src) 11654 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMOVZXDQZ256rr, 11655 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11656 // GIR_Coverage, 10394, 11657 GIR_Done, 11658 // Label 929: @25645 11659 GIM_Try, /*On fail goto*//*Label 930*/ 25664, // Rule ID 13697 // 11660 GIM_CheckFeatures, GIFBS_HasAVX2_NoVLX, 11661 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID, 11662 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 11663 // (zext:{ *:[v4i64] } VR128:{ *:[v4i32] }:$src) => (VPMOVZXDQYrr:{ *:[v4i64] } VR128:{ *:[v4i32] }:$src) 11664 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMOVZXDQYrr, 11665 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11666 // GIR_Coverage, 13697, 11667 GIR_Done, 11668 // Label 930: @25664 11669 GIM_Reject, 11670 // Label 928: @25665 11671 GIM_Reject, 11672 // Label 913: @25666 11673 GIM_Try, /*On fail goto*//*Label 931*/ 25711, 11674 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, 11675 GIM_Try, /*On fail goto*//*Label 932*/ 25691, // Rule ID 10358 // 11676 GIM_CheckFeatures, GIFBS_HasAVX512_HasVLX, 11677 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 11678 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 11679 // (zext:{ *:[v8i32] } VR128X:{ *:[v8i16] }:$src) => (VPMOVZXWDZ256rr:{ *:[v8i32] } VR128X:{ *:[v8i16] }:$src) 11680 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMOVZXWDZ256rr, 11681 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11682 // GIR_Coverage, 10358, 11683 GIR_Done, 11684 // Label 932: @25691 11685 GIM_Try, /*On fail goto*//*Label 933*/ 25710, // Rule ID 13695 // 11686 GIM_CheckFeatures, GIFBS_HasAVX2_NoVLX, 11687 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID, 11688 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 11689 // (zext:{ *:[v8i32] } VR128:{ *:[v8i16] }:$src) => (VPMOVZXWDYrr:{ *:[v8i32] } VR128:{ *:[v8i16] }:$src) 11690 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMOVZXWDYrr, 11691 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11692 // GIR_Coverage, 13695, 11693 GIR_Done, 11694 // Label 933: @25710 11695 GIM_Reject, 11696 // Label 931: @25711 11697 GIM_Reject, 11698 // Label 914: @25712 11699 GIM_Try, /*On fail goto*//*Label 934*/ 25735, // Rule ID 10382 // 11700 GIM_CheckFeatures, GIFBS_HasAVX512, 11701 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, 11702 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 11703 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 11704 // (zext:{ *:[v8i64] } VR128X:{ *:[v8i16] }:$src) => (VPMOVZXWQZrr:{ *:[v8i64] } VR128X:{ *:[v8i16] }:$src) 11705 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMOVZXWQZrr, 11706 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11707 // GIR_Coverage, 10382, 11708 GIR_Done, 11709 // Label 934: @25735 11710 GIM_Try, /*On fail goto*//*Label 935*/ 25758, // Rule ID 10400 // 11711 GIM_CheckFeatures, GIFBS_HasAVX512, 11712 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s32, 11713 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 11714 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 11715 // (zext:{ *:[v8i64] } VR256X:{ *:[v8i32] }:$src) => (VPMOVZXDQZrr:{ *:[v8i64] } VR256X:{ *:[v8i32] }:$src) 11716 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMOVZXDQZrr, 11717 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11718 // GIR_Coverage, 10400, 11719 GIR_Done, 11720 // Label 935: @25758 11721 GIM_Reject, 11722 // Label 915: @25759 11723 GIM_Try, /*On fail goto*//*Label 936*/ 25804, 11724 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, 11725 GIM_Try, /*On fail goto*//*Label 937*/ 25784, // Rule ID 10304 // 11726 GIM_CheckFeatures, GIFBS_HasBWI_HasVLX, 11727 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 11728 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 11729 // (zext:{ *:[v16i16] } VR128X:{ *:[v16i8] }:$src) => (VPMOVZXBWZ256rr:{ *:[v16i16] } VR128X:{ *:[v16i8] }:$src) 11730 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMOVZXBWZ256rr, 11731 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11732 // GIR_Coverage, 10304, 11733 GIR_Done, 11734 // Label 937: @25784 11735 GIM_Try, /*On fail goto*//*Label 938*/ 25803, // Rule ID 13692 // 11736 GIM_CheckFeatures, GIFBS_HasAVX2_NoVLX_Or_NoBWI, 11737 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID, 11738 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 11739 // (zext:{ *:[v16i16] } VR128:{ *:[v16i8] }:$src) => (VPMOVZXBWYrr:{ *:[v16i16] } VR128:{ *:[v16i8] }:$src) 11740 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMOVZXBWYrr, 11741 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11742 // GIR_Coverage, 13692, 11743 GIR_Done, 11744 // Label 938: @25803 11745 GIM_Reject, 11746 // Label 936: @25804 11747 GIM_Reject, 11748 // Label 916: @25805 11749 GIM_Try, /*On fail goto*//*Label 939*/ 25828, // Rule ID 10328 // 11750 GIM_CheckFeatures, GIFBS_HasAVX512, 11751 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, 11752 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 11753 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 11754 // (zext:{ *:[v16i32] } VR128X:{ *:[v16i8] }:$src) => (VPMOVZXBDZrr:{ *:[v16i32] } VR128X:{ *:[v16i8] }:$src) 11755 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMOVZXBDZrr, 11756 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11757 // GIR_Coverage, 10328, 11758 GIR_Done, 11759 // Label 939: @25828 11760 GIM_Try, /*On fail goto*//*Label 940*/ 25851, // Rule ID 10364 // 11761 GIM_CheckFeatures, GIFBS_HasAVX512, 11762 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s16, 11763 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 11764 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 11765 // (zext:{ *:[v16i32] } VR256X:{ *:[v16i16] }:$src) => (VPMOVZXWDZrr:{ *:[v16i32] } VR256X:{ *:[v16i16] }:$src) 11766 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMOVZXWDZrr, 11767 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11768 // GIR_Coverage, 10364, 11769 GIR_Done, 11770 // Label 940: @25851 11771 GIM_Reject, 11772 // Label 917: @25852 11773 GIM_Try, /*On fail goto*//*Label 941*/ 25875, // Rule ID 10310 // 11774 GIM_CheckFeatures, GIFBS_HasBWI, 11775 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v32s8, 11776 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 11777 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 11778 // (zext:{ *:[v32i16] } VR256X:{ *:[v32i8] }:$src) => (VPMOVZXBWZrr:{ *:[v32i16] } VR256X:{ *:[v32i8] }:$src) 11779 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMOVZXBWZrr, 11780 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11781 // GIR_Coverage, 10310, 11782 GIR_Done, 11783 // Label 941: @25875 11784 GIM_Reject, 11785 // Label 918: @25876 11786 GIM_Reject, 11787 // Label 16: @25877 11788 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 5, /*)*//*default:*//*Label 946*/ 26469, 11789 /*GILLT_s8*//*Label 942*/ 25887, 11790 /*GILLT_s16*//*Label 943*/ 25996, 11791 /*GILLT_s32*//*Label 944*/ 26105, 11792 /*GILLT_s64*//*Label 945*/ 26287, 11793 // Label 942: @25887 11794 GIM_Try, /*On fail goto*//*Label 947*/ 25995, 11795 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s8, 11796 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s8, 11797 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR8RegClassID, 11798 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR8RegClassID, 11799 GIM_Try, /*On fail goto*//*Label 948*/ 25931, // Rule ID 17199 // 11800 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 1, 11801 // (shl:{ *:[i8] } GR8:{ *:[i8] }:$src1, 1:{ *:[i8] }) => (ADD8rr:{ *:[i8] }:{ *:[i32] } GR8:{ *:[i8] }:$src1, GR8:{ *:[i8] }:$src1) 11802 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::ADD8rr, 11803 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 11804 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 11805 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 11806 GIR_EraseFromParent, /*InsnID*/0, 11807 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11808 // GIR_Coverage, 17199, 11809 GIR_Done, 11810 // Label 948: @25931 11811 GIM_Try, /*On fail goto*//*Label 949*/ 25961, // Rule ID 456 // 11812 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 11813 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 11814 // MIs[1] Operand 1 11815 // No operand predicates 11816 GIM_CheckIsSafeToFold, /*InsnID*/1, 11817 // (shl:{ *:[i8] } GR8:{ *:[i8] }:$src1, (imm:{ *:[i8] }):$src2) => (SHL8ri:{ *:[i8] }:{ *:[i32] } GR8:{ *:[i8] }:$src1, (imm:{ *:[i8] }):$src2) 11818 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SHL8ri, 11819 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 11820 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 11821 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2 11822 GIR_EraseFromParent, /*InsnID*/0, 11823 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11824 // GIR_Coverage, 456, 11825 GIR_Done, 11826 // Label 949: @25961 11827 GIM_Try, /*On fail goto*//*Label 950*/ 25994, // Rule ID 452 // 11828 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR8_ABCD_LRegClassID, 11829 // (shl:{ *:[i8] } GR8:{ *:[i8] }:$src1, CL:{ *:[i8] }) => (SHL8rCL:{ *:[i8] }:{ *:[i32] } GR8:{ *:[i8] }:$src1) 11830 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, 11831 GIR_AddRegister, /*InsnID*/1, X86::CL, /*AddRegisterRegFlags*/RegState::Define, 11832 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // CL 11833 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SHL8rCL, 11834 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 11835 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 11836 GIR_EraseFromParent, /*InsnID*/0, 11837 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11838 // GIR_Coverage, 452, 11839 GIR_Done, 11840 // Label 950: @25994 11841 GIM_Reject, 11842 // Label 947: @25995 11843 GIM_Reject, 11844 // Label 943: @25996 11845 GIM_Try, /*On fail goto*//*Label 951*/ 26104, 11846 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, 11847 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s8, 11848 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR16RegClassID, 11849 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR16RegClassID, 11850 GIM_Try, /*On fail goto*//*Label 952*/ 26040, // Rule ID 17200 // 11851 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 1, 11852 // (shl:{ *:[i16] } GR16:{ *:[i16] }:$src1, 1:{ *:[i8] }) => (ADD16rr:{ *:[i16] }:{ *:[i32] } GR16:{ *:[i16] }:$src1, GR16:{ *:[i16] }:$src1) 11853 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::ADD16rr, 11854 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 11855 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 11856 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 11857 GIR_EraseFromParent, /*InsnID*/0, 11858 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11859 // GIR_Coverage, 17200, 11860 GIR_Done, 11861 // Label 952: @26040 11862 GIM_Try, /*On fail goto*//*Label 953*/ 26070, // Rule ID 457 // 11863 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 11864 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 11865 // MIs[1] Operand 1 11866 // No operand predicates 11867 GIM_CheckIsSafeToFold, /*InsnID*/1, 11868 // (shl:{ *:[i16] } GR16:{ *:[i16] }:$src1, (imm:{ *:[i8] }):$src2) => (SHL16ri:{ *:[i16] }:{ *:[i32] } GR16:{ *:[i16] }:$src1, (imm:{ *:[i8] }):$src2) 11869 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SHL16ri, 11870 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 11871 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 11872 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2 11873 GIR_EraseFromParent, /*InsnID*/0, 11874 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11875 // GIR_Coverage, 457, 11876 GIR_Done, 11877 // Label 953: @26070 11878 GIM_Try, /*On fail goto*//*Label 954*/ 26103, // Rule ID 453 // 11879 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR8_ABCD_LRegClassID, 11880 // (shl:{ *:[i16] } GR16:{ *:[i16] }:$src1, CL:{ *:[i8] }) => (SHL16rCL:{ *:[i16] }:{ *:[i32] } GR16:{ *:[i16] }:$src1) 11881 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, 11882 GIR_AddRegister, /*InsnID*/1, X86::CL, /*AddRegisterRegFlags*/RegState::Define, 11883 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // CL 11884 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SHL16rCL, 11885 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 11886 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 11887 GIR_EraseFromParent, /*InsnID*/0, 11888 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11889 // GIR_Coverage, 453, 11890 GIR_Done, 11891 // Label 954: @26103 11892 GIM_Reject, 11893 // Label 951: @26104 11894 GIM_Reject, 11895 // Label 944: @26105 11896 GIM_Try, /*On fail goto*//*Label 955*/ 26286, 11897 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 11898 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s8, 11899 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 11900 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR32RegClassID, 11901 GIM_Try, /*On fail goto*//*Label 956*/ 26149, // Rule ID 17201 // 11902 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 1, 11903 // (shl:{ *:[i32] } GR32:{ *:[i32] }:$src1, 1:{ *:[i8] }) => (ADD32rr:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src1, GR32:{ *:[i32] }:$src1) 11904 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::ADD32rr, 11905 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 11906 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 11907 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 11908 GIR_EraseFromParent, /*InsnID*/0, 11909 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11910 // GIR_Coverage, 17201, 11911 GIR_Done, 11912 // Label 956: @26149 11913 GIM_Try, /*On fail goto*//*Label 957*/ 26179, // Rule ID 458 // 11914 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 11915 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 11916 // MIs[1] Operand 1 11917 // No operand predicates 11918 GIM_CheckIsSafeToFold, /*InsnID*/1, 11919 // (shl:{ *:[i32] } GR32:{ *:[i32] }:$src1, (imm:{ *:[i8] }):$src2) => (SHL32ri:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src1, (imm:{ *:[i8] }):$src2) 11920 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SHL32ri, 11921 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 11922 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 11923 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2 11924 GIR_EraseFromParent, /*InsnID*/0, 11925 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11926 // GIR_Coverage, 458, 11927 GIR_Done, 11928 // Label 957: @26179 11929 GIM_Try, /*On fail goto*//*Label 958*/ 26252, // Rule ID 13090 // 11930 GIM_CheckFeatures, GIFBS_HasBMI2, 11931 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR8RegClassID, 11932 // (shl:{ *:[i32] } GR32:{ *:[i32] }:$src1, GR8:{ *:[i8] }:$src2) => (SHLX32rr:{ *:[i32] } GR32:{ *:[i32] }:$src1, (INSERT_SUBREG:{ *:[i32] } (IMPLICIT_DEF:{ *:[i32] }), GR8:{ *:[i8] }:$src2, sub_8bit:{ *:[i32] })) 11933 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, 11934 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, 11935 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, 11936 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 11937 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 11938 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, 11939 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 11940 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 11941 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // src2 11942 GIR_AddImm, /*InsnID*/1, /*Imm*/1, 11943 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, /*RC LOW32_ADDR_ACCESS_RBP_with_sub_8bit*/30, 11944 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, /*RC LOW32_ADDR_ACCESS_RBP_with_sub_8bit*/30, 11945 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, /*RC GR8*/0, 11946 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SHLX32rr, 11947 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 11948 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 11949 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 11950 GIR_EraseFromParent, /*InsnID*/0, 11951 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11952 // GIR_Coverage, 13090, 11953 GIR_Done, 11954 // Label 958: @26252 11955 GIM_Try, /*On fail goto*//*Label 959*/ 26285, // Rule ID 454 // 11956 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR8_ABCD_LRegClassID, 11957 // (shl:{ *:[i32] } GR32:{ *:[i32] }:$src1, CL:{ *:[i8] }) => (SHL32rCL:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src1) 11958 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, 11959 GIR_AddRegister, /*InsnID*/1, X86::CL, /*AddRegisterRegFlags*/RegState::Define, 11960 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // CL 11961 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SHL32rCL, 11962 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 11963 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 11964 GIR_EraseFromParent, /*InsnID*/0, 11965 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11966 // GIR_Coverage, 454, 11967 GIR_Done, 11968 // Label 959: @26285 11969 GIM_Reject, 11970 // Label 955: @26286 11971 GIM_Reject, 11972 // Label 945: @26287 11973 GIM_Try, /*On fail goto*//*Label 960*/ 26468, 11974 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 11975 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s8, 11976 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID, 11977 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR64RegClassID, 11978 GIM_Try, /*On fail goto*//*Label 961*/ 26331, // Rule ID 17202 // 11979 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 1, 11980 // (shl:{ *:[i64] } GR64:{ *:[i64] }:$src1, 1:{ *:[i8] }) => (ADD64rr:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src1, GR64:{ *:[i64] }:$src1) 11981 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::ADD64rr, 11982 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 11983 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 11984 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 11985 GIR_EraseFromParent, /*InsnID*/0, 11986 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11987 // GIR_Coverage, 17202, 11988 GIR_Done, 11989 // Label 961: @26331 11990 GIM_Try, /*On fail goto*//*Label 962*/ 26361, // Rule ID 459 // 11991 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 11992 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 11993 // MIs[1] Operand 1 11994 // No operand predicates 11995 GIM_CheckIsSafeToFold, /*InsnID*/1, 11996 // (shl:{ *:[i64] } GR64:{ *:[i64] }:$src1, (imm:{ *:[i8] }):$src2) => (SHL64ri:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src1, (imm:{ *:[i8] }):$src2) 11997 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SHL64ri, 11998 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 11999 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 12000 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2 12001 GIR_EraseFromParent, /*InsnID*/0, 12002 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12003 // GIR_Coverage, 459, 12004 GIR_Done, 12005 // Label 962: @26361 12006 GIM_Try, /*On fail goto*//*Label 963*/ 26434, // Rule ID 13091 // 12007 GIM_CheckFeatures, GIFBS_HasBMI2, 12008 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR8RegClassID, 12009 // (shl:{ *:[i64] } GR64:{ *:[i64] }:$src1, GR8:{ *:[i8] }:$src2) => (SHLX64rr:{ *:[i64] } GR64:{ *:[i64] }:$src1, (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), GR8:{ *:[i8] }:$src2, sub_8bit:{ *:[i32] })) 12010 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, 12011 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, 12012 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, 12013 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 12014 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 12015 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, 12016 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 12017 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 12018 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // src2 12019 GIR_AddImm, /*InsnID*/1, /*Imm*/1, 12020 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, /*RC GR64_with_sub_8bit*/68, 12021 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, /*RC GR64_with_sub_8bit*/68, 12022 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, /*RC GR8*/0, 12023 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SHLX64rr, 12024 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 12025 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 12026 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 12027 GIR_EraseFromParent, /*InsnID*/0, 12028 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12029 // GIR_Coverage, 13091, 12030 GIR_Done, 12031 // Label 963: @26434 12032 GIM_Try, /*On fail goto*//*Label 964*/ 26467, // Rule ID 455 // 12033 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR8_ABCD_LRegClassID, 12034 // (shl:{ *:[i64] } GR64:{ *:[i64] }:$src1, CL:{ *:[i8] }) => (SHL64rCL:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src1) 12035 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, 12036 GIR_AddRegister, /*InsnID*/1, X86::CL, /*AddRegisterRegFlags*/RegState::Define, 12037 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // CL 12038 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SHL64rCL, 12039 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 12040 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 12041 GIR_EraseFromParent, /*InsnID*/0, 12042 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12043 // GIR_Coverage, 455, 12044 GIR_Done, 12045 // Label 964: @26467 12046 GIM_Reject, 12047 // Label 960: @26468 12048 GIM_Reject, 12049 // Label 946: @26469 12050 GIM_Reject, 12051 // Label 17: @26470 12052 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 5, /*)*//*default:*//*Label 969*/ 27046, 12053 /*GILLT_s8*//*Label 965*/ 26480, 12054 /*GILLT_s16*//*Label 966*/ 26585, 12055 /*GILLT_s32*//*Label 967*/ 26690, 12056 /*GILLT_s64*//*Label 968*/ 26868, 12057 // Label 965: @26480 12058 GIM_Try, /*On fail goto*//*Label 970*/ 26584, 12059 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s8, 12060 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s8, 12061 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR8RegClassID, 12062 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR8RegClassID, 12063 GIM_Try, /*On fail goto*//*Label 971*/ 26520, // Rule ID 480 // 12064 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 1, 12065 // (srl:{ *:[i8] } GR8:{ *:[i8] }:$src1, 1:{ *:[i8] }) => (SHR8r1:{ *:[i8] }:{ *:[i32] } GR8:{ *:[i8] }:$src1) 12066 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SHR8r1, 12067 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 12068 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 12069 GIR_EraseFromParent, /*InsnID*/0, 12070 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12071 // GIR_Coverage, 480, 12072 GIR_Done, 12073 // Label 971: @26520 12074 GIM_Try, /*On fail goto*//*Label 972*/ 26550, // Rule ID 476 // 12075 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 12076 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 12077 // MIs[1] Operand 1 12078 // No operand predicates 12079 GIM_CheckIsSafeToFold, /*InsnID*/1, 12080 // (srl:{ *:[i8] } GR8:{ *:[i8] }:$src1, (imm:{ *:[i8] }):$src2) => (SHR8ri:{ *:[i8] }:{ *:[i32] } GR8:{ *:[i8] }:$src1, (imm:{ *:[i8] }):$src2) 12081 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SHR8ri, 12082 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 12083 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 12084 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2 12085 GIR_EraseFromParent, /*InsnID*/0, 12086 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12087 // GIR_Coverage, 476, 12088 GIR_Done, 12089 // Label 972: @26550 12090 GIM_Try, /*On fail goto*//*Label 973*/ 26583, // Rule ID 472 // 12091 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR8_ABCD_LRegClassID, 12092 // (srl:{ *:[i8] } GR8:{ *:[i8] }:$src1, CL:{ *:[i8] }) => (SHR8rCL:{ *:[i8] }:{ *:[i32] } GR8:{ *:[i8] }:$src1) 12093 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, 12094 GIR_AddRegister, /*InsnID*/1, X86::CL, /*AddRegisterRegFlags*/RegState::Define, 12095 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // CL 12096 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SHR8rCL, 12097 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 12098 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 12099 GIR_EraseFromParent, /*InsnID*/0, 12100 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12101 // GIR_Coverage, 472, 12102 GIR_Done, 12103 // Label 973: @26583 12104 GIM_Reject, 12105 // Label 970: @26584 12106 GIM_Reject, 12107 // Label 966: @26585 12108 GIM_Try, /*On fail goto*//*Label 974*/ 26689, 12109 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, 12110 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s8, 12111 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR16RegClassID, 12112 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR16RegClassID, 12113 GIM_Try, /*On fail goto*//*Label 975*/ 26625, // Rule ID 481 // 12114 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 1, 12115 // (srl:{ *:[i16] } GR16:{ *:[i16] }:$src1, 1:{ *:[i8] }) => (SHR16r1:{ *:[i16] }:{ *:[i32] } GR16:{ *:[i16] }:$src1) 12116 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SHR16r1, 12117 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 12118 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 12119 GIR_EraseFromParent, /*InsnID*/0, 12120 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12121 // GIR_Coverage, 481, 12122 GIR_Done, 12123 // Label 975: @26625 12124 GIM_Try, /*On fail goto*//*Label 976*/ 26655, // Rule ID 477 // 12125 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 12126 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 12127 // MIs[1] Operand 1 12128 // No operand predicates 12129 GIM_CheckIsSafeToFold, /*InsnID*/1, 12130 // (srl:{ *:[i16] } GR16:{ *:[i16] }:$src1, (imm:{ *:[i8] }):$src2) => (SHR16ri:{ *:[i16] }:{ *:[i32] } GR16:{ *:[i16] }:$src1, (imm:{ *:[i8] }):$src2) 12131 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SHR16ri, 12132 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 12133 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 12134 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2 12135 GIR_EraseFromParent, /*InsnID*/0, 12136 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12137 // GIR_Coverage, 477, 12138 GIR_Done, 12139 // Label 976: @26655 12140 GIM_Try, /*On fail goto*//*Label 977*/ 26688, // Rule ID 473 // 12141 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR8_ABCD_LRegClassID, 12142 // (srl:{ *:[i16] } GR16:{ *:[i16] }:$src1, CL:{ *:[i8] }) => (SHR16rCL:{ *:[i16] }:{ *:[i32] } GR16:{ *:[i16] }:$src1) 12143 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, 12144 GIR_AddRegister, /*InsnID*/1, X86::CL, /*AddRegisterRegFlags*/RegState::Define, 12145 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // CL 12146 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SHR16rCL, 12147 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 12148 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 12149 GIR_EraseFromParent, /*InsnID*/0, 12150 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12151 // GIR_Coverage, 473, 12152 GIR_Done, 12153 // Label 977: @26688 12154 GIM_Reject, 12155 // Label 974: @26689 12156 GIM_Reject, 12157 // Label 967: @26690 12158 GIM_Try, /*On fail goto*//*Label 978*/ 26867, 12159 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 12160 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s8, 12161 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 12162 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR32RegClassID, 12163 GIM_Try, /*On fail goto*//*Label 979*/ 26730, // Rule ID 482 // 12164 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 1, 12165 // (srl:{ *:[i32] } GR32:{ *:[i32] }:$src1, 1:{ *:[i8] }) => (SHR32r1:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src1) 12166 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SHR32r1, 12167 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 12168 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 12169 GIR_EraseFromParent, /*InsnID*/0, 12170 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12171 // GIR_Coverage, 482, 12172 GIR_Done, 12173 // Label 979: @26730 12174 GIM_Try, /*On fail goto*//*Label 980*/ 26760, // Rule ID 478 // 12175 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 12176 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 12177 // MIs[1] Operand 1 12178 // No operand predicates 12179 GIM_CheckIsSafeToFold, /*InsnID*/1, 12180 // (srl:{ *:[i32] } GR32:{ *:[i32] }:$src1, (imm:{ *:[i8] }):$src2) => (SHR32ri:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src1, (imm:{ *:[i8] }):$src2) 12181 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SHR32ri, 12182 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 12183 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 12184 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2 12185 GIR_EraseFromParent, /*InsnID*/0, 12186 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12187 // GIR_Coverage, 478, 12188 GIR_Done, 12189 // Label 980: @26760 12190 GIM_Try, /*On fail goto*//*Label 981*/ 26833, // Rule ID 13088 // 12191 GIM_CheckFeatures, GIFBS_HasBMI2, 12192 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR8RegClassID, 12193 // (srl:{ *:[i32] } GR32:{ *:[i32] }:$src1, GR8:{ *:[i8] }:$src2) => (SHRX32rr:{ *:[i32] } GR32:{ *:[i32] }:$src1, (INSERT_SUBREG:{ *:[i32] } (IMPLICIT_DEF:{ *:[i32] }), GR8:{ *:[i8] }:$src2, sub_8bit:{ *:[i32] })) 12194 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, 12195 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, 12196 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, 12197 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 12198 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 12199 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, 12200 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 12201 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 12202 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // src2 12203 GIR_AddImm, /*InsnID*/1, /*Imm*/1, 12204 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, /*RC LOW32_ADDR_ACCESS_RBP_with_sub_8bit*/30, 12205 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, /*RC LOW32_ADDR_ACCESS_RBP_with_sub_8bit*/30, 12206 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, /*RC GR8*/0, 12207 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SHRX32rr, 12208 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 12209 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 12210 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 12211 GIR_EraseFromParent, /*InsnID*/0, 12212 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12213 // GIR_Coverage, 13088, 12214 GIR_Done, 12215 // Label 981: @26833 12216 GIM_Try, /*On fail goto*//*Label 982*/ 26866, // Rule ID 474 // 12217 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR8_ABCD_LRegClassID, 12218 // (srl:{ *:[i32] } GR32:{ *:[i32] }:$src1, CL:{ *:[i8] }) => (SHR32rCL:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src1) 12219 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, 12220 GIR_AddRegister, /*InsnID*/1, X86::CL, /*AddRegisterRegFlags*/RegState::Define, 12221 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // CL 12222 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SHR32rCL, 12223 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 12224 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 12225 GIR_EraseFromParent, /*InsnID*/0, 12226 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12227 // GIR_Coverage, 474, 12228 GIR_Done, 12229 // Label 982: @26866 12230 GIM_Reject, 12231 // Label 978: @26867 12232 GIM_Reject, 12233 // Label 968: @26868 12234 GIM_Try, /*On fail goto*//*Label 983*/ 27045, 12235 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 12236 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s8, 12237 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID, 12238 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR64RegClassID, 12239 GIM_Try, /*On fail goto*//*Label 984*/ 26908, // Rule ID 483 // 12240 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 1, 12241 // (srl:{ *:[i64] } GR64:{ *:[i64] }:$src1, 1:{ *:[i8] }) => (SHR64r1:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src1) 12242 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SHR64r1, 12243 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 12244 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 12245 GIR_EraseFromParent, /*InsnID*/0, 12246 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12247 // GIR_Coverage, 483, 12248 GIR_Done, 12249 // Label 984: @26908 12250 GIM_Try, /*On fail goto*//*Label 985*/ 26938, // Rule ID 479 // 12251 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 12252 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 12253 // MIs[1] Operand 1 12254 // No operand predicates 12255 GIM_CheckIsSafeToFold, /*InsnID*/1, 12256 // (srl:{ *:[i64] } GR64:{ *:[i64] }:$src1, (imm:{ *:[i8] }):$src2) => (SHR64ri:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src1, (imm:{ *:[i8] }):$src2) 12257 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SHR64ri, 12258 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 12259 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 12260 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2 12261 GIR_EraseFromParent, /*InsnID*/0, 12262 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12263 // GIR_Coverage, 479, 12264 GIR_Done, 12265 // Label 985: @26938 12266 GIM_Try, /*On fail goto*//*Label 986*/ 27011, // Rule ID 13089 // 12267 GIM_CheckFeatures, GIFBS_HasBMI2, 12268 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR8RegClassID, 12269 // (srl:{ *:[i64] } GR64:{ *:[i64] }:$src1, GR8:{ *:[i8] }:$src2) => (SHRX64rr:{ *:[i64] } GR64:{ *:[i64] }:$src1, (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), GR8:{ *:[i8] }:$src2, sub_8bit:{ *:[i32] })) 12270 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, 12271 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, 12272 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, 12273 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 12274 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 12275 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, 12276 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 12277 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 12278 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // src2 12279 GIR_AddImm, /*InsnID*/1, /*Imm*/1, 12280 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, /*RC GR64_with_sub_8bit*/68, 12281 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, /*RC GR64_with_sub_8bit*/68, 12282 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, /*RC GR8*/0, 12283 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SHRX64rr, 12284 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 12285 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 12286 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 12287 GIR_EraseFromParent, /*InsnID*/0, 12288 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12289 // GIR_Coverage, 13089, 12290 GIR_Done, 12291 // Label 986: @27011 12292 GIM_Try, /*On fail goto*//*Label 987*/ 27044, // Rule ID 475 // 12293 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR8_ABCD_LRegClassID, 12294 // (srl:{ *:[i64] } GR64:{ *:[i64] }:$src1, CL:{ *:[i8] }) => (SHR64rCL:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src1) 12295 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, 12296 GIR_AddRegister, /*InsnID*/1, X86::CL, /*AddRegisterRegFlags*/RegState::Define, 12297 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // CL 12298 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SHR64rCL, 12299 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 12300 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 12301 GIR_EraseFromParent, /*InsnID*/0, 12302 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12303 // GIR_Coverage, 475, 12304 GIR_Done, 12305 // Label 987: @27044 12306 GIM_Reject, 12307 // Label 983: @27045 12308 GIM_Reject, 12309 // Label 969: @27046 12310 GIM_Reject, 12311 // Label 18: @27047 12312 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 5, /*)*//*default:*//*Label 992*/ 27623, 12313 /*GILLT_s8*//*Label 988*/ 27057, 12314 /*GILLT_s16*//*Label 989*/ 27162, 12315 /*GILLT_s32*//*Label 990*/ 27267, 12316 /*GILLT_s64*//*Label 991*/ 27445, 12317 // Label 988: @27057 12318 GIM_Try, /*On fail goto*//*Label 993*/ 27161, 12319 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s8, 12320 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s8, 12321 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR8RegClassID, 12322 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR8RegClassID, 12323 GIM_Try, /*On fail goto*//*Label 994*/ 27097, // Rule ID 504 // 12324 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 1, 12325 // (sra:{ *:[i8] } GR8:{ *:[i8] }:$src1, 1:{ *:[i8] }) => (SAR8r1:{ *:[i8] }:{ *:[i32] } GR8:{ *:[i8] }:$src1) 12326 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SAR8r1, 12327 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 12328 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 12329 GIR_EraseFromParent, /*InsnID*/0, 12330 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12331 // GIR_Coverage, 504, 12332 GIR_Done, 12333 // Label 994: @27097 12334 GIM_Try, /*On fail goto*//*Label 995*/ 27127, // Rule ID 500 // 12335 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 12336 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 12337 // MIs[1] Operand 1 12338 // No operand predicates 12339 GIM_CheckIsSafeToFold, /*InsnID*/1, 12340 // (sra:{ *:[i8] } GR8:{ *:[i8] }:$src1, (imm:{ *:[i8] }):$src2) => (SAR8ri:{ *:[i8] }:{ *:[i32] } GR8:{ *:[i8] }:$src1, (imm:{ *:[i8] }):$src2) 12341 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SAR8ri, 12342 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 12343 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 12344 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2 12345 GIR_EraseFromParent, /*InsnID*/0, 12346 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12347 // GIR_Coverage, 500, 12348 GIR_Done, 12349 // Label 995: @27127 12350 GIM_Try, /*On fail goto*//*Label 996*/ 27160, // Rule ID 496 // 12351 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR8_ABCD_LRegClassID, 12352 // (sra:{ *:[i8] } GR8:{ *:[i8] }:$src1, CL:{ *:[i8] }) => (SAR8rCL:{ *:[i8] }:{ *:[i32] } GR8:{ *:[i8] }:$src1) 12353 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, 12354 GIR_AddRegister, /*InsnID*/1, X86::CL, /*AddRegisterRegFlags*/RegState::Define, 12355 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // CL 12356 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SAR8rCL, 12357 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 12358 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 12359 GIR_EraseFromParent, /*InsnID*/0, 12360 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12361 // GIR_Coverage, 496, 12362 GIR_Done, 12363 // Label 996: @27160 12364 GIM_Reject, 12365 // Label 993: @27161 12366 GIM_Reject, 12367 // Label 989: @27162 12368 GIM_Try, /*On fail goto*//*Label 997*/ 27266, 12369 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, 12370 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s8, 12371 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR16RegClassID, 12372 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR16RegClassID, 12373 GIM_Try, /*On fail goto*//*Label 998*/ 27202, // Rule ID 505 // 12374 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 1, 12375 // (sra:{ *:[i16] } GR16:{ *:[i16] }:$src1, 1:{ *:[i8] }) => (SAR16r1:{ *:[i16] }:{ *:[i32] } GR16:{ *:[i16] }:$src1) 12376 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SAR16r1, 12377 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 12378 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 12379 GIR_EraseFromParent, /*InsnID*/0, 12380 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12381 // GIR_Coverage, 505, 12382 GIR_Done, 12383 // Label 998: @27202 12384 GIM_Try, /*On fail goto*//*Label 999*/ 27232, // Rule ID 501 // 12385 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 12386 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 12387 // MIs[1] Operand 1 12388 // No operand predicates 12389 GIM_CheckIsSafeToFold, /*InsnID*/1, 12390 // (sra:{ *:[i16] } GR16:{ *:[i16] }:$src1, (imm:{ *:[i8] }):$src2) => (SAR16ri:{ *:[i16] }:{ *:[i32] } GR16:{ *:[i16] }:$src1, (imm:{ *:[i8] }):$src2) 12391 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SAR16ri, 12392 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 12393 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 12394 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2 12395 GIR_EraseFromParent, /*InsnID*/0, 12396 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12397 // GIR_Coverage, 501, 12398 GIR_Done, 12399 // Label 999: @27232 12400 GIM_Try, /*On fail goto*//*Label 1000*/ 27265, // Rule ID 497 // 12401 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR8_ABCD_LRegClassID, 12402 // (sra:{ *:[i16] } GR16:{ *:[i16] }:$src1, CL:{ *:[i8] }) => (SAR16rCL:{ *:[i16] }:{ *:[i32] } GR16:{ *:[i16] }:$src1) 12403 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, 12404 GIR_AddRegister, /*InsnID*/1, X86::CL, /*AddRegisterRegFlags*/RegState::Define, 12405 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // CL 12406 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SAR16rCL, 12407 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 12408 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 12409 GIR_EraseFromParent, /*InsnID*/0, 12410 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12411 // GIR_Coverage, 497, 12412 GIR_Done, 12413 // Label 1000: @27265 12414 GIM_Reject, 12415 // Label 997: @27266 12416 GIM_Reject, 12417 // Label 990: @27267 12418 GIM_Try, /*On fail goto*//*Label 1001*/ 27444, 12419 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 12420 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s8, 12421 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 12422 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR32RegClassID, 12423 GIM_Try, /*On fail goto*//*Label 1002*/ 27307, // Rule ID 506 // 12424 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 1, 12425 // (sra:{ *:[i32] } GR32:{ *:[i32] }:$src1, 1:{ *:[i8] }) => (SAR32r1:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src1) 12426 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SAR32r1, 12427 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 12428 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 12429 GIR_EraseFromParent, /*InsnID*/0, 12430 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12431 // GIR_Coverage, 506, 12432 GIR_Done, 12433 // Label 1002: @27307 12434 GIM_Try, /*On fail goto*//*Label 1003*/ 27337, // Rule ID 502 // 12435 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 12436 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 12437 // MIs[1] Operand 1 12438 // No operand predicates 12439 GIM_CheckIsSafeToFold, /*InsnID*/1, 12440 // (sra:{ *:[i32] } GR32:{ *:[i32] }:$src1, (imm:{ *:[i8] }):$src2) => (SAR32ri:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src1, (imm:{ *:[i8] }):$src2) 12441 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SAR32ri, 12442 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 12443 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 12444 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2 12445 GIR_EraseFromParent, /*InsnID*/0, 12446 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12447 // GIR_Coverage, 502, 12448 GIR_Done, 12449 // Label 1003: @27337 12450 GIM_Try, /*On fail goto*//*Label 1004*/ 27410, // Rule ID 13086 // 12451 GIM_CheckFeatures, GIFBS_HasBMI2, 12452 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR8RegClassID, 12453 // (sra:{ *:[i32] } GR32:{ *:[i32] }:$src1, GR8:{ *:[i8] }:$src2) => (SARX32rr:{ *:[i32] } GR32:{ *:[i32] }:$src1, (INSERT_SUBREG:{ *:[i32] } (IMPLICIT_DEF:{ *:[i32] }), GR8:{ *:[i8] }:$src2, sub_8bit:{ *:[i32] })) 12454 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, 12455 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, 12456 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, 12457 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 12458 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 12459 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, 12460 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 12461 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 12462 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // src2 12463 GIR_AddImm, /*InsnID*/1, /*Imm*/1, 12464 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, /*RC LOW32_ADDR_ACCESS_RBP_with_sub_8bit*/30, 12465 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, /*RC LOW32_ADDR_ACCESS_RBP_with_sub_8bit*/30, 12466 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, /*RC GR8*/0, 12467 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SARX32rr, 12468 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 12469 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 12470 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 12471 GIR_EraseFromParent, /*InsnID*/0, 12472 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12473 // GIR_Coverage, 13086, 12474 GIR_Done, 12475 // Label 1004: @27410 12476 GIM_Try, /*On fail goto*//*Label 1005*/ 27443, // Rule ID 498 // 12477 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR8_ABCD_LRegClassID, 12478 // (sra:{ *:[i32] } GR32:{ *:[i32] }:$src1, CL:{ *:[i8] }) => (SAR32rCL:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src1) 12479 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, 12480 GIR_AddRegister, /*InsnID*/1, X86::CL, /*AddRegisterRegFlags*/RegState::Define, 12481 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // CL 12482 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SAR32rCL, 12483 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 12484 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 12485 GIR_EraseFromParent, /*InsnID*/0, 12486 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12487 // GIR_Coverage, 498, 12488 GIR_Done, 12489 // Label 1005: @27443 12490 GIM_Reject, 12491 // Label 1001: @27444 12492 GIM_Reject, 12493 // Label 991: @27445 12494 GIM_Try, /*On fail goto*//*Label 1006*/ 27622, 12495 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 12496 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s8, 12497 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID, 12498 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR64RegClassID, 12499 GIM_Try, /*On fail goto*//*Label 1007*/ 27485, // Rule ID 507 // 12500 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 1, 12501 // (sra:{ *:[i64] } GR64:{ *:[i64] }:$src1, 1:{ *:[i8] }) => (SAR64r1:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src1) 12502 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SAR64r1, 12503 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 12504 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 12505 GIR_EraseFromParent, /*InsnID*/0, 12506 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12507 // GIR_Coverage, 507, 12508 GIR_Done, 12509 // Label 1007: @27485 12510 GIM_Try, /*On fail goto*//*Label 1008*/ 27515, // Rule ID 503 // 12511 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 12512 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 12513 // MIs[1] Operand 1 12514 // No operand predicates 12515 GIM_CheckIsSafeToFold, /*InsnID*/1, 12516 // (sra:{ *:[i64] } GR64:{ *:[i64] }:$src1, (imm:{ *:[i8] }):$src2) => (SAR64ri:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src1, (imm:{ *:[i8] }):$src2) 12517 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SAR64ri, 12518 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 12519 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 12520 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // src2 12521 GIR_EraseFromParent, /*InsnID*/0, 12522 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12523 // GIR_Coverage, 503, 12524 GIR_Done, 12525 // Label 1008: @27515 12526 GIM_Try, /*On fail goto*//*Label 1009*/ 27588, // Rule ID 13087 // 12527 GIM_CheckFeatures, GIFBS_HasBMI2, 12528 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR8RegClassID, 12529 // (sra:{ *:[i64] } GR64:{ *:[i64] }:$src1, GR8:{ *:[i8] }:$src2) => (SARX64rr:{ *:[i64] } GR64:{ *:[i64] }:$src1, (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), GR8:{ *:[i8] }:$src2, sub_8bit:{ *:[i32] })) 12530 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, 12531 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, 12532 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::IMPLICIT_DEF, 12533 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 12534 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 12535 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::INSERT_SUBREG, 12536 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 12537 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 12538 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // src2 12539 GIR_AddImm, /*InsnID*/1, /*Imm*/1, 12540 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, /*RC GR64_with_sub_8bit*/68, 12541 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, /*RC GR64_with_sub_8bit*/68, 12542 GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, /*RC GR8*/0, 12543 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SARX64rr, 12544 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 12545 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 12546 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 12547 GIR_EraseFromParent, /*InsnID*/0, 12548 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12549 // GIR_Coverage, 13087, 12550 GIR_Done, 12551 // Label 1009: @27588 12552 GIM_Try, /*On fail goto*//*Label 1010*/ 27621, // Rule ID 499 // 12553 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::GR8_ABCD_LRegClassID, 12554 // (sra:{ *:[i64] } GR64:{ *:[i64] }:$src1, CL:{ *:[i8] }) => (SAR64rCL:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src1) 12555 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY, 12556 GIR_AddRegister, /*InsnID*/1, X86::CL, /*AddRegisterRegFlags*/RegState::Define, 12557 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // CL 12558 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::SAR64rCL, 12559 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 12560 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 12561 GIR_EraseFromParent, /*InsnID*/0, 12562 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12563 // GIR_Coverage, 499, 12564 GIR_Done, 12565 // Label 1010: @27621 12566 GIM_Reject, 12567 // Label 1006: @27622 12568 GIM_Reject, 12569 // Label 992: @27623 12570 GIM_Reject, 12571 // Label 19: @27624 12572 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/13, 23, /*)*//*default:*//*Label 1014*/ 27811, 12573 /*GILLT_v8s16*//*Label 1011*/ 27640, 0, 0, 0, 0, 12574 /*GILLT_v16s16*//*Label 1012*/ 27721, 0, 0, 0, 12575 /*GILLT_v32s16*//*Label 1013*/ 27779, 12576 // Label 1011: @27640 12577 GIM_Try, /*On fail goto*//*Label 1015*/ 27720, 12578 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, 12579 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 12580 GIM_Try, /*On fail goto*//*Label 1016*/ 27673, // Rule ID 2035 // 12581 GIM_CheckFeatures, GIFBS_HasAVX_NoVLX_Or_NoBWI, 12582 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 12583 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 12584 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 12585 // (mulhu:{ *:[v8i16] } VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2) => (VPMULHUWrr:{ *:[v8i16] } VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2) 12586 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMULHUWrr, 12587 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12588 // GIR_Coverage, 2035, 12589 GIR_Done, 12590 // Label 1016: @27673 12591 GIM_Try, /*On fail goto*//*Label 1017*/ 27696, // Rule ID 2037 // 12592 GIM_CheckFeatures, GIFBS_UseSSE2, 12593 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 12594 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 12595 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 12596 // (mulhu:{ *:[v8i16] } VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2) => (PMULHUWrr:{ *:[v8i16] } VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2) 12597 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::PMULHUWrr, 12598 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12599 // GIR_Coverage, 2037, 12600 GIR_Done, 12601 // Label 1017: @27696 12602 GIM_Try, /*On fail goto*//*Label 1018*/ 27719, // Rule ID 4321 // 12603 GIM_CheckFeatures, GIFBS_HasBWI_HasVLX, 12604 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 12605 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 12606 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128XRegClassID, 12607 // (mulhu:{ *:[v8i16] } VR128X:{ *:[v8i16] }:$src1, VR128X:{ *:[v8i16] }:$src2) => (VPMULHUWZ128rr:{ *:[v8i16] } VR128X:{ *:[v8i16] }:$src1, VR128X:{ *:[v8i16] }:$src2) 12608 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMULHUWZ128rr, 12609 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12610 // GIR_Coverage, 4321, 12611 GIR_Done, 12612 // Label 1018: @27719 12613 GIM_Reject, 12614 // Label 1015: @27720 12615 GIM_Reject, 12616 // Label 1012: @27721 12617 GIM_Try, /*On fail goto*//*Label 1019*/ 27778, 12618 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s16, 12619 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s16, 12620 GIM_Try, /*On fail goto*//*Label 1020*/ 27754, // Rule ID 2039 // 12621 GIM_CheckFeatures, GIFBS_HasAVX2_NoVLX_Or_NoBWI, 12622 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID, 12623 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256RegClassID, 12624 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID, 12625 // (mulhu:{ *:[v16i16] } VR256:{ *:[v16i16] }:$src1, VR256:{ *:[v16i16] }:$src2) => (VPMULHUWYrr:{ *:[v16i16] } VR256:{ *:[v16i16] }:$src1, VR256:{ *:[v16i16] }:$src2) 12626 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMULHUWYrr, 12627 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12628 // GIR_Coverage, 2039, 12629 GIR_Done, 12630 // Label 1020: @27754 12631 GIM_Try, /*On fail goto*//*Label 1021*/ 27777, // Rule ID 4315 // 12632 GIM_CheckFeatures, GIFBS_HasBWI_HasVLX, 12633 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 12634 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 12635 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256XRegClassID, 12636 // (mulhu:{ *:[v16i16] } VR256X:{ *:[v16i16] }:$src1, VR256X:{ *:[v16i16] }:$src2) => (VPMULHUWZ256rr:{ *:[v16i16] } VR256X:{ *:[v16i16] }:$src1, VR256X:{ *:[v16i16] }:$src2) 12637 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMULHUWZ256rr, 12638 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12639 // GIR_Coverage, 4315, 12640 GIR_Done, 12641 // Label 1021: @27777 12642 GIM_Reject, 12643 // Label 1019: @27778 12644 GIM_Reject, 12645 // Label 1013: @27779 12646 GIM_Try, /*On fail goto*//*Label 1022*/ 27810, // Rule ID 4309 // 12647 GIM_CheckFeatures, GIFBS_HasBWI, 12648 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v32s16, 12649 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v32s16, 12650 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 12651 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID, 12652 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR512RegClassID, 12653 // (mulhu:{ *:[v32i16] } VR512:{ *:[v32i16] }:$src1, VR512:{ *:[v32i16] }:$src2) => (VPMULHUWZrr:{ *:[v32i16] } VR512:{ *:[v32i16] }:$src1, VR512:{ *:[v32i16] }:$src2) 12654 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMULHUWZrr, 12655 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12656 // GIR_Coverage, 4309, 12657 GIR_Done, 12658 // Label 1022: @27810 12659 GIM_Reject, 12660 // Label 1014: @27811 12661 GIM_Reject, 12662 // Label 20: @27812 12663 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/13, 23, /*)*//*default:*//*Label 1026*/ 27999, 12664 /*GILLT_v8s16*//*Label 1023*/ 27828, 0, 0, 0, 0, 12665 /*GILLT_v16s16*//*Label 1024*/ 27909, 0, 0, 0, 12666 /*GILLT_v32s16*//*Label 1025*/ 27967, 12667 // Label 1023: @27828 12668 GIM_Try, /*On fail goto*//*Label 1027*/ 27908, 12669 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, 12670 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 12671 GIM_Try, /*On fail goto*//*Label 1028*/ 27861, // Rule ID 2041 // 12672 GIM_CheckFeatures, GIFBS_HasAVX_NoVLX_Or_NoBWI, 12673 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 12674 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 12675 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 12676 // (mulhs:{ *:[v8i16] } VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2) => (VPMULHWrr:{ *:[v8i16] } VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2) 12677 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMULHWrr, 12678 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12679 // GIR_Coverage, 2041, 12680 GIR_Done, 12681 // Label 1028: @27861 12682 GIM_Try, /*On fail goto*//*Label 1029*/ 27884, // Rule ID 2043 // 12683 GIM_CheckFeatures, GIFBS_UseSSE2, 12684 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 12685 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 12686 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 12687 // (mulhs:{ *:[v8i16] } VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2) => (PMULHWrr:{ *:[v8i16] } VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2) 12688 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::PMULHWrr, 12689 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12690 // GIR_Coverage, 2043, 12691 GIR_Done, 12692 // Label 1029: @27884 12693 GIM_Try, /*On fail goto*//*Label 1030*/ 27907, // Rule ID 4303 // 12694 GIM_CheckFeatures, GIFBS_HasBWI_HasVLX, 12695 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 12696 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 12697 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128XRegClassID, 12698 // (mulhs:{ *:[v8i16] } VR128X:{ *:[v8i16] }:$src1, VR128X:{ *:[v8i16] }:$src2) => (VPMULHWZ128rr:{ *:[v8i16] } VR128X:{ *:[v8i16] }:$src1, VR128X:{ *:[v8i16] }:$src2) 12699 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMULHWZ128rr, 12700 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12701 // GIR_Coverage, 4303, 12702 GIR_Done, 12703 // Label 1030: @27907 12704 GIM_Reject, 12705 // Label 1027: @27908 12706 GIM_Reject, 12707 // Label 1024: @27909 12708 GIM_Try, /*On fail goto*//*Label 1031*/ 27966, 12709 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s16, 12710 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s16, 12711 GIM_Try, /*On fail goto*//*Label 1032*/ 27942, // Rule ID 2045 // 12712 GIM_CheckFeatures, GIFBS_HasAVX2_NoVLX_Or_NoBWI, 12713 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID, 12714 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256RegClassID, 12715 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID, 12716 // (mulhs:{ *:[v16i16] } VR256:{ *:[v16i16] }:$src1, VR256:{ *:[v16i16] }:$src2) => (VPMULHWYrr:{ *:[v16i16] } VR256:{ *:[v16i16] }:$src1, VR256:{ *:[v16i16] }:$src2) 12717 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMULHWYrr, 12718 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12719 // GIR_Coverage, 2045, 12720 GIR_Done, 12721 // Label 1032: @27942 12722 GIM_Try, /*On fail goto*//*Label 1033*/ 27965, // Rule ID 4297 // 12723 GIM_CheckFeatures, GIFBS_HasBWI_HasVLX, 12724 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 12725 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 12726 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256XRegClassID, 12727 // (mulhs:{ *:[v16i16] } VR256X:{ *:[v16i16] }:$src1, VR256X:{ *:[v16i16] }:$src2) => (VPMULHWZ256rr:{ *:[v16i16] } VR256X:{ *:[v16i16] }:$src1, VR256X:{ *:[v16i16] }:$src2) 12728 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMULHWZ256rr, 12729 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12730 // GIR_Coverage, 4297, 12731 GIR_Done, 12732 // Label 1033: @27965 12733 GIM_Reject, 12734 // Label 1031: @27966 12735 GIM_Reject, 12736 // Label 1025: @27967 12737 GIM_Try, /*On fail goto*//*Label 1034*/ 27998, // Rule ID 4291 // 12738 GIM_CheckFeatures, GIFBS_HasBWI, 12739 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v32s16, 12740 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v32s16, 12741 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 12742 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID, 12743 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR512RegClassID, 12744 // (mulhs:{ *:[v32i16] } VR512:{ *:[v32i16] }:$src1, VR512:{ *:[v32i16] }:$src2) => (VPMULHWZrr:{ *:[v32i16] } VR512:{ *:[v32i16] }:$src1, VR512:{ *:[v32i16] }:$src2) 12745 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMULHWZrr, 12746 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12747 // GIR_Coverage, 4291, 12748 GIR_Done, 12749 // Label 1034: @27998 12750 GIM_Reject, 12751 // Label 1026: @27999 12752 GIM_Reject, 12753 // Label 21: @28000 12754 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/3, 20, /*)*//*default:*//*Label 1044*/ 28675, 12755 /*GILLT_s32*//*Label 1035*/ 28023, 12756 /*GILLT_s64*//*Label 1036*/ 28142, 12757 /*GILLT_s80*//*Label 1037*/ 28261, 0, 0, 12758 /*GILLT_v2s64*//*Label 1038*/ 28297, 0, 12759 /*GILLT_v4s32*//*Label 1039*/ 28387, 12760 /*GILLT_v4s64*//*Label 1040*/ 28477, 0, 0, 12761 /*GILLT_v8s32*//*Label 1041*/ 28541, 12762 /*GILLT_v8s64*//*Label 1042*/ 28605, 0, 0, 0, 12763 /*GILLT_v16s32*//*Label 1043*/ 28640, 12764 // Label 1035: @28023 12765 GIM_Try, /*On fail goto*//*Label 1045*/ 28141, 12766 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 12767 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 12768 GIM_Try, /*On fail goto*//*Label 1046*/ 28062, // Rule ID 606 // 12769 GIM_CheckFeatures, GIFBS_FPStackf32, 12770 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::RFP32RegClassID, 12771 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::RFP32RegClassID, 12772 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::RFP32RegClassID, 12773 // (fadd:{ *:[f32] } RFP32:{ *:[f32] }:$src1, RFP32:{ *:[f32] }:$src2) => (ADD_Fp32:{ *:[f32] }:{ *:[i16] } RFP32:{ *:[f32] }:$src1, RFP32:{ *:[f32] }:$src2) 12774 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::ADD_Fp32, 12775 GIR_AddImplicitDef, /*InsnID*/0, X86::FPSW, 12776 GIR_AddImplicitUse, /*InsnID*/0, X86::FPCW, 12777 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12778 // GIR_Coverage, 606, 12779 GIR_Done, 12780 // Label 1046: @28062 12781 GIM_Try, /*On fail goto*//*Label 1047*/ 28088, // Rule ID 1674 // 12782 GIM_CheckFeatures, GIFBS_UseAVX, 12783 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::FR32RegClassID, 12784 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR32RegClassID, 12785 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::FR32RegClassID, 12786 // (fadd:{ *:[f32] } FR32:{ *:[f32] }:$src1, FR32:{ *:[f32] }:$src2) => (VADDSSrr:{ *:[f32] } FR32:{ *:[f32] }:$src1, FR32:{ *:[f32] }:$src2) 12787 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VADDSSrr, 12788 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 12789 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12790 // GIR_Coverage, 1674, 12791 GIR_Done, 12792 // Label 1047: @28088 12793 GIM_Try, /*On fail goto*//*Label 1048*/ 28114, // Rule ID 1682 // 12794 GIM_CheckFeatures, GIFBS_UseSSE1, 12795 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::FR32RegClassID, 12796 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR32RegClassID, 12797 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::FR32RegClassID, 12798 // (fadd:{ *:[f32] } FR32:{ *:[f32] }:$src1, FR32:{ *:[f32] }:$src2) => (ADDSSrr:{ *:[f32] } FR32:{ *:[f32] }:$src1, FR32:{ *:[f32] }:$src2) 12799 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::ADDSSrr, 12800 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 12801 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12802 // GIR_Coverage, 1682, 12803 GIR_Done, 12804 // Label 1048: @28114 12805 GIM_Try, /*On fail goto*//*Label 1049*/ 28140, // Rule ID 5171 // 12806 GIM_CheckFeatures, GIFBS_HasAVX512, 12807 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::FR32XRegClassID, 12808 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR32XRegClassID, 12809 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::FR32XRegClassID, 12810 // (fadd:{ *:[f32] } FR32X:{ *:[f32] }:$src1, FR32X:{ *:[f32] }:$src2) => (VADDSSZrr:{ *:[f32] } FR32X:{ *:[f32] }:$src1, FR32X:{ *:[f32] }:$src2) 12811 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VADDSSZrr, 12812 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 12813 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12814 // GIR_Coverage, 5171, 12815 GIR_Done, 12816 // Label 1049: @28140 12817 GIM_Reject, 12818 // Label 1045: @28141 12819 GIM_Reject, 12820 // Label 1036: @28142 12821 GIM_Try, /*On fail goto*//*Label 1050*/ 28260, 12822 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 12823 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 12824 GIM_Try, /*On fail goto*//*Label 1051*/ 28181, // Rule ID 608 // 12825 GIM_CheckFeatures, GIFBS_FPStackf64, 12826 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::RFP64RegClassID, 12827 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::RFP64RegClassID, 12828 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::RFP64RegClassID, 12829 // (fadd:{ *:[f64] } RFP64:{ *:[f64] }:$src1, RFP64:{ *:[f64] }:$src2) => (ADD_Fp64:{ *:[f64] }:{ *:[i16] } RFP64:{ *:[f64] }:$src1, RFP64:{ *:[f64] }:$src2) 12830 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::ADD_Fp64, 12831 GIR_AddImplicitDef, /*InsnID*/0, X86::FPSW, 12832 GIR_AddImplicitUse, /*InsnID*/0, X86::FPCW, 12833 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12834 // GIR_Coverage, 608, 12835 GIR_Done, 12836 // Label 1051: @28181 12837 GIM_Try, /*On fail goto*//*Label 1052*/ 28207, // Rule ID 1678 // 12838 GIM_CheckFeatures, GIFBS_UseAVX, 12839 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::FR64RegClassID, 12840 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR64RegClassID, 12841 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::FR64RegClassID, 12842 // (fadd:{ *:[f64] } FR64:{ *:[f64] }:$src1, FR64:{ *:[f64] }:$src2) => (VADDSDrr:{ *:[f64] } FR64:{ *:[f64] }:$src1, FR64:{ *:[f64] }:$src2) 12843 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VADDSDrr, 12844 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 12845 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12846 // GIR_Coverage, 1678, 12847 GIR_Done, 12848 // Label 1052: @28207 12849 GIM_Try, /*On fail goto*//*Label 1053*/ 28233, // Rule ID 1686 // 12850 GIM_CheckFeatures, GIFBS_UseSSE2, 12851 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::FR64RegClassID, 12852 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR64RegClassID, 12853 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::FR64RegClassID, 12854 // (fadd:{ *:[f64] } FR64:{ *:[f64] }:$src1, FR64:{ *:[f64] }:$src2) => (ADDSDrr:{ *:[f64] } FR64:{ *:[f64] }:$src1, FR64:{ *:[f64] }:$src2) 12855 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::ADDSDrr, 12856 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 12857 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12858 // GIR_Coverage, 1686, 12859 GIR_Done, 12860 // Label 1053: @28233 12861 GIM_Try, /*On fail goto*//*Label 1054*/ 28259, // Rule ID 5184 // 12862 GIM_CheckFeatures, GIFBS_HasAVX512, 12863 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::FR64XRegClassID, 12864 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR64XRegClassID, 12865 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::FR64XRegClassID, 12866 // (fadd:{ *:[f64] } FR64X:{ *:[f64] }:$src1, FR64X:{ *:[f64] }:$src2) => (VADDSDZrr:{ *:[f64] } FR64X:{ *:[f64] }:$src1, FR64X:{ *:[f64] }:$src2) 12867 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VADDSDZrr, 12868 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 12869 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12870 // GIR_Coverage, 5184, 12871 GIR_Done, 12872 // Label 1054: @28259 12873 GIM_Reject, 12874 // Label 1050: @28260 12875 GIM_Reject, 12876 // Label 1037: @28261 12877 GIM_Try, /*On fail goto*//*Label 1055*/ 28296, // Rule ID 610 // 12878 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s80, 12879 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s80, 12880 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::RFP80RegClassID, 12881 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::RFP80RegClassID, 12882 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::RFP80RegClassID, 12883 // (fadd:{ *:[f80] } RFP80:{ *:[f80] }:$src1, RFP80:{ *:[f80] }:$src2) => (ADD_Fp80:{ *:[f80] }:{ *:[i16] } RFP80:{ *:[f80] }:$src1, RFP80:{ *:[f80] }:$src2) 12884 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::ADD_Fp80, 12885 GIR_AddImplicitDef, /*InsnID*/0, X86::FPSW, 12886 GIR_AddImplicitUse, /*InsnID*/0, X86::FPCW, 12887 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12888 // GIR_Coverage, 610, 12889 GIR_Done, 12890 // Label 1055: @28296 12891 GIM_Reject, 12892 // Label 1038: @28297 12893 GIM_Try, /*On fail goto*//*Label 1056*/ 28386, 12894 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, 12895 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 12896 GIM_Try, /*On fail goto*//*Label 1057*/ 28333, // Rule ID 1654 // 12897 GIM_CheckFeatures, GIFBS_HasAVX_NoVLX, 12898 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 12899 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 12900 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 12901 // (fadd:{ *:[v2f64] } VR128:{ *:[v2f64] }:$src1, VR128:{ *:[v2f64] }:$src2) => (VADDPDrr:{ *:[v2f64] } VR128:{ *:[v2f64] }:$src1, VR128:{ *:[v2f64] }:$src2) 12902 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VADDPDrr, 12903 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 12904 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12905 // GIR_Coverage, 1654, 12906 GIR_Done, 12907 // Label 1057: @28333 12908 GIM_Try, /*On fail goto*//*Label 1058*/ 28359, // Rule ID 1670 // 12909 GIM_CheckFeatures, GIFBS_UseSSE2, 12910 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 12911 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 12912 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 12913 // (fadd:{ *:[v2f64] } VR128:{ *:[v2f64] }:$src1, VR128:{ *:[v2f64] }:$src2) => (ADDPDrr:{ *:[v2f64] } VR128:{ *:[v2f64] }:$src1, VR128:{ *:[v2f64] }:$src2) 12914 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::ADDPDrr, 12915 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 12916 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12917 // GIR_Coverage, 1670, 12918 GIR_Done, 12919 // Label 1058: @28359 12920 GIM_Try, /*On fail goto*//*Label 1059*/ 28385, // Rule ID 5393 // 12921 GIM_CheckFeatures, GIFBS_HasAVX512_HasVLX, 12922 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 12923 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 12924 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128XRegClassID, 12925 // (fadd:{ *:[v2f64] } VR128X:{ *:[v2f64] }:$src1, VR128X:{ *:[v2f64] }:$src2) => (VADDPDZ128rr:{ *:[v2f64] } VR128X:{ *:[v2f64] }:$src1, VR128X:{ *:[v2f64] }:$src2) 12926 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VADDPDZ128rr, 12927 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 12928 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12929 // GIR_Coverage, 5393, 12930 GIR_Done, 12931 // Label 1059: @28385 12932 GIM_Reject, 12933 // Label 1056: @28386 12934 GIM_Reject, 12935 // Label 1039: @28387 12936 GIM_Try, /*On fail goto*//*Label 1060*/ 28476, 12937 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 12938 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 12939 GIM_Try, /*On fail goto*//*Label 1061*/ 28423, // Rule ID 1650 // 12940 GIM_CheckFeatures, GIFBS_HasAVX_NoVLX, 12941 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 12942 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 12943 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 12944 // (fadd:{ *:[v4f32] } VR128:{ *:[v4f32] }:$src1, VR128:{ *:[v4f32] }:$src2) => (VADDPSrr:{ *:[v4f32] } VR128:{ *:[v4f32] }:$src1, VR128:{ *:[v4f32] }:$src2) 12945 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VADDPSrr, 12946 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 12947 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12948 // GIR_Coverage, 1650, 12949 GIR_Done, 12950 // Label 1061: @28423 12951 GIM_Try, /*On fail goto*//*Label 1062*/ 28449, // Rule ID 1666 // 12952 GIM_CheckFeatures, GIFBS_UseSSE1, 12953 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 12954 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 12955 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 12956 // (fadd:{ *:[v4f32] } VR128:{ *:[v4f32] }:$src1, VR128:{ *:[v4f32] }:$src2) => (ADDPSrr:{ *:[v4f32] } VR128:{ *:[v4f32] }:$src1, VR128:{ *:[v4f32] }:$src2) 12957 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::ADDPSrr, 12958 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 12959 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12960 // GIR_Coverage, 1666, 12961 GIR_Done, 12962 // Label 1062: @28449 12963 GIM_Try, /*On fail goto*//*Label 1063*/ 28475, // Rule ID 5357 // 12964 GIM_CheckFeatures, GIFBS_HasAVX512_HasVLX, 12965 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 12966 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 12967 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128XRegClassID, 12968 // (fadd:{ *:[v4f32] } VR128X:{ *:[v4f32] }:$src1, VR128X:{ *:[v4f32] }:$src2) => (VADDPSZ128rr:{ *:[v4f32] } VR128X:{ *:[v4f32] }:$src1, VR128X:{ *:[v4f32] }:$src2) 12969 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VADDPSZ128rr, 12970 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 12971 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12972 // GIR_Coverage, 5357, 12973 GIR_Done, 12974 // Label 1063: @28475 12975 GIM_Reject, 12976 // Label 1060: @28476 12977 GIM_Reject, 12978 // Label 1040: @28477 12979 GIM_Try, /*On fail goto*//*Label 1064*/ 28540, 12980 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s64, 12981 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s64, 12982 GIM_Try, /*On fail goto*//*Label 1065*/ 28513, // Rule ID 1662 // 12983 GIM_CheckFeatures, GIFBS_HasAVX_NoVLX, 12984 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID, 12985 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256RegClassID, 12986 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID, 12987 // (fadd:{ *:[v4f64] } VR256:{ *:[v4f64] }:$src1, VR256:{ *:[v4f64] }:$src2) => (VADDPDYrr:{ *:[v4f64] } VR256:{ *:[v4f64] }:$src1, VR256:{ *:[v4f64] }:$src2) 12988 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VADDPDYrr, 12989 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 12990 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12991 // GIR_Coverage, 1662, 12992 GIR_Done, 12993 // Label 1065: @28513 12994 GIM_Try, /*On fail goto*//*Label 1066*/ 28539, // Rule ID 5411 // 12995 GIM_CheckFeatures, GIFBS_HasAVX512_HasVLX, 12996 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 12997 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 12998 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256XRegClassID, 12999 // (fadd:{ *:[v4f64] } VR256X:{ *:[v4f64] }:$src1, VR256X:{ *:[v4f64] }:$src2) => (VADDPDZ256rr:{ *:[v4f64] } VR256X:{ *:[v4f64] }:$src1, VR256X:{ *:[v4f64] }:$src2) 13000 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VADDPDZ256rr, 13001 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 13002 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13003 // GIR_Coverage, 5411, 13004 GIR_Done, 13005 // Label 1066: @28539 13006 GIM_Reject, 13007 // Label 1064: @28540 13008 GIM_Reject, 13009 // Label 1041: @28541 13010 GIM_Try, /*On fail goto*//*Label 1067*/ 28604, 13011 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s32, 13012 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s32, 13013 GIM_Try, /*On fail goto*//*Label 1068*/ 28577, // Rule ID 1658 // 13014 GIM_CheckFeatures, GIFBS_HasAVX_NoVLX, 13015 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID, 13016 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256RegClassID, 13017 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID, 13018 // (fadd:{ *:[v8f32] } VR256:{ *:[v8f32] }:$src1, VR256:{ *:[v8f32] }:$src2) => (VADDPSYrr:{ *:[v8f32] } VR256:{ *:[v8f32] }:$src1, VR256:{ *:[v8f32] }:$src2) 13019 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VADDPSYrr, 13020 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 13021 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13022 // GIR_Coverage, 1658, 13023 GIR_Done, 13024 // Label 1068: @28577 13025 GIM_Try, /*On fail goto*//*Label 1069*/ 28603, // Rule ID 5375 // 13026 GIM_CheckFeatures, GIFBS_HasAVX512_HasVLX, 13027 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 13028 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 13029 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256XRegClassID, 13030 // (fadd:{ *:[v8f32] } VR256X:{ *:[v8f32] }:$src1, VR256X:{ *:[v8f32] }:$src2) => (VADDPSZ256rr:{ *:[v8f32] } VR256X:{ *:[v8f32] }:$src1, VR256X:{ *:[v8f32] }:$src2) 13031 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VADDPSZ256rr, 13032 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 13033 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13034 // GIR_Coverage, 5375, 13035 GIR_Done, 13036 // Label 1069: @28603 13037 GIM_Reject, 13038 // Label 1067: @28604 13039 GIM_Reject, 13040 // Label 1042: @28605 13041 GIM_Try, /*On fail goto*//*Label 1070*/ 28639, // Rule ID 5339 // 13042 GIM_CheckFeatures, GIFBS_HasAVX512, 13043 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s64, 13044 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s64, 13045 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 13046 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID, 13047 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR512RegClassID, 13048 // (fadd:{ *:[v8f64] } VR512:{ *:[v8f64] }:$src1, VR512:{ *:[v8f64] }:$src2) => (VADDPDZrr:{ *:[v8f64] } VR512:{ *:[v8f64] }:$src1, VR512:{ *:[v8f64] }:$src2) 13049 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VADDPDZrr, 13050 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 13051 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13052 // GIR_Coverage, 5339, 13053 GIR_Done, 13054 // Label 1070: @28639 13055 GIM_Reject, 13056 // Label 1043: @28640 13057 GIM_Try, /*On fail goto*//*Label 1071*/ 28674, // Rule ID 5321 // 13058 GIM_CheckFeatures, GIFBS_HasAVX512, 13059 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s32, 13060 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s32, 13061 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 13062 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID, 13063 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR512RegClassID, 13064 // (fadd:{ *:[v16f32] } VR512:{ *:[v16f32] }:$src1, VR512:{ *:[v16f32] }:$src2) => (VADDPSZrr:{ *:[v16f32] } VR512:{ *:[v16f32] }:$src1, VR512:{ *:[v16f32] }:$src2) 13065 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VADDPSZrr, 13066 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 13067 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13068 // GIR_Coverage, 5321, 13069 GIR_Done, 13070 // Label 1071: @28674 13071 GIM_Reject, 13072 // Label 1044: @28675 13073 GIM_Reject, 13074 // Label 22: @28676 13075 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/3, 20, /*)*//*default:*//*Label 1081*/ 29351, 13076 /*GILLT_s32*//*Label 1072*/ 28699, 13077 /*GILLT_s64*//*Label 1073*/ 28818, 13078 /*GILLT_s80*//*Label 1074*/ 28937, 0, 0, 13079 /*GILLT_v2s64*//*Label 1075*/ 28973, 0, 13080 /*GILLT_v4s32*//*Label 1076*/ 29063, 13081 /*GILLT_v4s64*//*Label 1077*/ 29153, 0, 0, 13082 /*GILLT_v8s32*//*Label 1078*/ 29217, 13083 /*GILLT_v8s64*//*Label 1079*/ 29281, 0, 0, 0, 13084 /*GILLT_v16s32*//*Label 1080*/ 29316, 13085 // Label 1072: @28699 13086 GIM_Try, /*On fail goto*//*Label 1082*/ 28817, 13087 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 13088 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 13089 GIM_Try, /*On fail goto*//*Label 1083*/ 28738, // Rule ID 612 // 13090 GIM_CheckFeatures, GIFBS_FPStackf32, 13091 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::RFP32RegClassID, 13092 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::RFP32RegClassID, 13093 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::RFP32RegClassID, 13094 // (fsub:{ *:[f32] } RFP32:{ *:[f32] }:$src1, RFP32:{ *:[f32] }:$src2) => (SUB_Fp32:{ *:[f32] }:{ *:[i16] } RFP32:{ *:[f32] }:$src1, RFP32:{ *:[f32] }:$src2) 13095 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::SUB_Fp32, 13096 GIR_AddImplicitDef, /*InsnID*/0, X86::FPSW, 13097 GIR_AddImplicitUse, /*InsnID*/0, X86::FPCW, 13098 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13099 // GIR_Coverage, 612, 13100 GIR_Done, 13101 // Label 1083: @28738 13102 GIM_Try, /*On fail goto*//*Label 1084*/ 28764, // Rule ID 1754 // 13103 GIM_CheckFeatures, GIFBS_UseAVX, 13104 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::FR32RegClassID, 13105 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR32RegClassID, 13106 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::FR32RegClassID, 13107 // (fsub:{ *:[f32] } FR32:{ *:[f32] }:$src1, FR32:{ *:[f32] }:$src2) => (VSUBSSrr:{ *:[f32] } FR32:{ *:[f32] }:$src1, FR32:{ *:[f32] }:$src2) 13108 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VSUBSSrr, 13109 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 13110 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13111 // GIR_Coverage, 1754, 13112 GIR_Done, 13113 // Label 1084: @28764 13114 GIM_Try, /*On fail goto*//*Label 1085*/ 28790, // Rule ID 1762 // 13115 GIM_CheckFeatures, GIFBS_UseSSE1, 13116 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::FR32RegClassID, 13117 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR32RegClassID, 13118 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::FR32RegClassID, 13119 // (fsub:{ *:[f32] } FR32:{ *:[f32] }:$src1, FR32:{ *:[f32] }:$src2) => (SUBSSrr:{ *:[f32] } FR32:{ *:[f32] }:$src1, FR32:{ *:[f32] }:$src2) 13120 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::SUBSSrr, 13121 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 13122 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13123 // GIR_Coverage, 1762, 13124 GIR_Done, 13125 // Label 1085: @28790 13126 GIM_Try, /*On fail goto*//*Label 1086*/ 28816, // Rule ID 5223 // 13127 GIM_CheckFeatures, GIFBS_HasAVX512, 13128 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::FR32XRegClassID, 13129 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR32XRegClassID, 13130 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::FR32XRegClassID, 13131 // (fsub:{ *:[f32] } FR32X:{ *:[f32] }:$src1, FR32X:{ *:[f32] }:$src2) => (VSUBSSZrr:{ *:[f32] } FR32X:{ *:[f32] }:$src1, FR32X:{ *:[f32] }:$src2) 13132 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VSUBSSZrr, 13133 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 13134 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13135 // GIR_Coverage, 5223, 13136 GIR_Done, 13137 // Label 1086: @28816 13138 GIM_Reject, 13139 // Label 1082: @28817 13140 GIM_Reject, 13141 // Label 1073: @28818 13142 GIM_Try, /*On fail goto*//*Label 1087*/ 28936, 13143 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 13144 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 13145 GIM_Try, /*On fail goto*//*Label 1088*/ 28857, // Rule ID 614 // 13146 GIM_CheckFeatures, GIFBS_FPStackf64, 13147 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::RFP64RegClassID, 13148 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::RFP64RegClassID, 13149 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::RFP64RegClassID, 13150 // (fsub:{ *:[f64] } RFP64:{ *:[f64] }:$src1, RFP64:{ *:[f64] }:$src2) => (SUB_Fp64:{ *:[f64] }:{ *:[i16] } RFP64:{ *:[f64] }:$src1, RFP64:{ *:[f64] }:$src2) 13151 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::SUB_Fp64, 13152 GIR_AddImplicitDef, /*InsnID*/0, X86::FPSW, 13153 GIR_AddImplicitUse, /*InsnID*/0, X86::FPCW, 13154 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13155 // GIR_Coverage, 614, 13156 GIR_Done, 13157 // Label 1088: @28857 13158 GIM_Try, /*On fail goto*//*Label 1089*/ 28883, // Rule ID 1758 // 13159 GIM_CheckFeatures, GIFBS_UseAVX, 13160 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::FR64RegClassID, 13161 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR64RegClassID, 13162 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::FR64RegClassID, 13163 // (fsub:{ *:[f64] } FR64:{ *:[f64] }:$src1, FR64:{ *:[f64] }:$src2) => (VSUBSDrr:{ *:[f64] } FR64:{ *:[f64] }:$src1, FR64:{ *:[f64] }:$src2) 13164 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VSUBSDrr, 13165 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 13166 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13167 // GIR_Coverage, 1758, 13168 GIR_Done, 13169 // Label 1089: @28883 13170 GIM_Try, /*On fail goto*//*Label 1090*/ 28909, // Rule ID 1766 // 13171 GIM_CheckFeatures, GIFBS_UseSSE2, 13172 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::FR64RegClassID, 13173 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR64RegClassID, 13174 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::FR64RegClassID, 13175 // (fsub:{ *:[f64] } FR64:{ *:[f64] }:$src1, FR64:{ *:[f64] }:$src2) => (SUBSDrr:{ *:[f64] } FR64:{ *:[f64] }:$src1, FR64:{ *:[f64] }:$src2) 13176 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::SUBSDrr, 13177 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 13178 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13179 // GIR_Coverage, 1766, 13180 GIR_Done, 13181 // Label 1090: @28909 13182 GIM_Try, /*On fail goto*//*Label 1091*/ 28935, // Rule ID 5236 // 13183 GIM_CheckFeatures, GIFBS_HasAVX512, 13184 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::FR64XRegClassID, 13185 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR64XRegClassID, 13186 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::FR64XRegClassID, 13187 // (fsub:{ *:[f64] } FR64X:{ *:[f64] }:$src1, FR64X:{ *:[f64] }:$src2) => (VSUBSDZrr:{ *:[f64] } FR64X:{ *:[f64] }:$src1, FR64X:{ *:[f64] }:$src2) 13188 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VSUBSDZrr, 13189 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 13190 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13191 // GIR_Coverage, 5236, 13192 GIR_Done, 13193 // Label 1091: @28935 13194 GIM_Reject, 13195 // Label 1087: @28936 13196 GIM_Reject, 13197 // Label 1074: @28937 13198 GIM_Try, /*On fail goto*//*Label 1092*/ 28972, // Rule ID 616 // 13199 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s80, 13200 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s80, 13201 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::RFP80RegClassID, 13202 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::RFP80RegClassID, 13203 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::RFP80RegClassID, 13204 // (fsub:{ *:[f80] } RFP80:{ *:[f80] }:$src1, RFP80:{ *:[f80] }:$src2) => (SUB_Fp80:{ *:[f80] }:{ *:[i16] } RFP80:{ *:[f80] }:$src1, RFP80:{ *:[f80] }:$src2) 13205 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::SUB_Fp80, 13206 GIR_AddImplicitDef, /*InsnID*/0, X86::FPSW, 13207 GIR_AddImplicitUse, /*InsnID*/0, X86::FPCW, 13208 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13209 // GIR_Coverage, 616, 13210 GIR_Done, 13211 // Label 1092: @28972 13212 GIM_Reject, 13213 // Label 1075: @28973 13214 GIM_Try, /*On fail goto*//*Label 1093*/ 29062, 13215 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, 13216 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 13217 GIM_Try, /*On fail goto*//*Label 1094*/ 29009, // Rule ID 1734 // 13218 GIM_CheckFeatures, GIFBS_HasAVX_NoVLX, 13219 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 13220 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 13221 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 13222 // (fsub:{ *:[v2f64] } VR128:{ *:[v2f64] }:$src1, VR128:{ *:[v2f64] }:$src2) => (VSUBPDrr:{ *:[v2f64] } VR128:{ *:[v2f64] }:$src1, VR128:{ *:[v2f64] }:$src2) 13223 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VSUBPDrr, 13224 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 13225 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13226 // GIR_Coverage, 1734, 13227 GIR_Done, 13228 // Label 1094: @29009 13229 GIM_Try, /*On fail goto*//*Label 1095*/ 29035, // Rule ID 1750 // 13230 GIM_CheckFeatures, GIFBS_UseSSE2, 13231 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 13232 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 13233 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 13234 // (fsub:{ *:[v2f64] } VR128:{ *:[v2f64] }:$src1, VR128:{ *:[v2f64] }:$src2) => (SUBPDrr:{ *:[v2f64] } VR128:{ *:[v2f64] }:$src1, VR128:{ *:[v2f64] }:$src2) 13235 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::SUBPDrr, 13236 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 13237 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13238 // GIR_Coverage, 1750, 13239 GIR_Done, 13240 // Label 1095: @29035 13241 GIM_Try, /*On fail goto*//*Label 1096*/ 29061, // Rule ID 5621 // 13242 GIM_CheckFeatures, GIFBS_HasAVX512_HasVLX, 13243 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 13244 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 13245 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128XRegClassID, 13246 // (fsub:{ *:[v2f64] } VR128X:{ *:[v2f64] }:$src1, VR128X:{ *:[v2f64] }:$src2) => (VSUBPDZ128rr:{ *:[v2f64] } VR128X:{ *:[v2f64] }:$src1, VR128X:{ *:[v2f64] }:$src2) 13247 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VSUBPDZ128rr, 13248 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 13249 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13250 // GIR_Coverage, 5621, 13251 GIR_Done, 13252 // Label 1096: @29061 13253 GIM_Reject, 13254 // Label 1093: @29062 13255 GIM_Reject, 13256 // Label 1076: @29063 13257 GIM_Try, /*On fail goto*//*Label 1097*/ 29152, 13258 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 13259 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 13260 GIM_Try, /*On fail goto*//*Label 1098*/ 29099, // Rule ID 1730 // 13261 GIM_CheckFeatures, GIFBS_HasAVX_NoVLX, 13262 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 13263 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 13264 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 13265 // (fsub:{ *:[v4f32] } VR128:{ *:[v4f32] }:$src1, VR128:{ *:[v4f32] }:$src2) => (VSUBPSrr:{ *:[v4f32] } VR128:{ *:[v4f32] }:$src1, VR128:{ *:[v4f32] }:$src2) 13266 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VSUBPSrr, 13267 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 13268 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13269 // GIR_Coverage, 1730, 13270 GIR_Done, 13271 // Label 1098: @29099 13272 GIM_Try, /*On fail goto*//*Label 1099*/ 29125, // Rule ID 1746 // 13273 GIM_CheckFeatures, GIFBS_UseSSE1, 13274 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 13275 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 13276 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 13277 // (fsub:{ *:[v4f32] } VR128:{ *:[v4f32] }:$src1, VR128:{ *:[v4f32] }:$src2) => (SUBPSrr:{ *:[v4f32] } VR128:{ *:[v4f32] }:$src1, VR128:{ *:[v4f32] }:$src2) 13278 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::SUBPSrr, 13279 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 13280 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13281 // GIR_Coverage, 1746, 13282 GIR_Done, 13283 // Label 1099: @29125 13284 GIM_Try, /*On fail goto*//*Label 1100*/ 29151, // Rule ID 5585 // 13285 GIM_CheckFeatures, GIFBS_HasAVX512_HasVLX, 13286 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 13287 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 13288 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128XRegClassID, 13289 // (fsub:{ *:[v4f32] } VR128X:{ *:[v4f32] }:$src1, VR128X:{ *:[v4f32] }:$src2) => (VSUBPSZ128rr:{ *:[v4f32] } VR128X:{ *:[v4f32] }:$src1, VR128X:{ *:[v4f32] }:$src2) 13290 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VSUBPSZ128rr, 13291 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 13292 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13293 // GIR_Coverage, 5585, 13294 GIR_Done, 13295 // Label 1100: @29151 13296 GIM_Reject, 13297 // Label 1097: @29152 13298 GIM_Reject, 13299 // Label 1077: @29153 13300 GIM_Try, /*On fail goto*//*Label 1101*/ 29216, 13301 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s64, 13302 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s64, 13303 GIM_Try, /*On fail goto*//*Label 1102*/ 29189, // Rule ID 1742 // 13304 GIM_CheckFeatures, GIFBS_HasAVX_NoVLX, 13305 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID, 13306 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256RegClassID, 13307 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID, 13308 // (fsub:{ *:[v4f64] } VR256:{ *:[v4f64] }:$src1, VR256:{ *:[v4f64] }:$src2) => (VSUBPDYrr:{ *:[v4f64] } VR256:{ *:[v4f64] }:$src1, VR256:{ *:[v4f64] }:$src2) 13309 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VSUBPDYrr, 13310 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 13311 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13312 // GIR_Coverage, 1742, 13313 GIR_Done, 13314 // Label 1102: @29189 13315 GIM_Try, /*On fail goto*//*Label 1103*/ 29215, // Rule ID 5639 // 13316 GIM_CheckFeatures, GIFBS_HasAVX512_HasVLX, 13317 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 13318 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 13319 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256XRegClassID, 13320 // (fsub:{ *:[v4f64] } VR256X:{ *:[v4f64] }:$src1, VR256X:{ *:[v4f64] }:$src2) => (VSUBPDZ256rr:{ *:[v4f64] } VR256X:{ *:[v4f64] }:$src1, VR256X:{ *:[v4f64] }:$src2) 13321 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VSUBPDZ256rr, 13322 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 13323 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13324 // GIR_Coverage, 5639, 13325 GIR_Done, 13326 // Label 1103: @29215 13327 GIM_Reject, 13328 // Label 1101: @29216 13329 GIM_Reject, 13330 // Label 1078: @29217 13331 GIM_Try, /*On fail goto*//*Label 1104*/ 29280, 13332 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s32, 13333 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s32, 13334 GIM_Try, /*On fail goto*//*Label 1105*/ 29253, // Rule ID 1738 // 13335 GIM_CheckFeatures, GIFBS_HasAVX_NoVLX, 13336 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID, 13337 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256RegClassID, 13338 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID, 13339 // (fsub:{ *:[v8f32] } VR256:{ *:[v8f32] }:$src1, VR256:{ *:[v8f32] }:$src2) => (VSUBPSYrr:{ *:[v8f32] } VR256:{ *:[v8f32] }:$src1, VR256:{ *:[v8f32] }:$src2) 13340 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VSUBPSYrr, 13341 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 13342 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13343 // GIR_Coverage, 1738, 13344 GIR_Done, 13345 // Label 1105: @29253 13346 GIM_Try, /*On fail goto*//*Label 1106*/ 29279, // Rule ID 5603 // 13347 GIM_CheckFeatures, GIFBS_HasAVX512_HasVLX, 13348 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 13349 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 13350 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256XRegClassID, 13351 // (fsub:{ *:[v8f32] } VR256X:{ *:[v8f32] }:$src1, VR256X:{ *:[v8f32] }:$src2) => (VSUBPSZ256rr:{ *:[v8f32] } VR256X:{ *:[v8f32] }:$src1, VR256X:{ *:[v8f32] }:$src2) 13352 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VSUBPSZ256rr, 13353 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 13354 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13355 // GIR_Coverage, 5603, 13356 GIR_Done, 13357 // Label 1106: @29279 13358 GIM_Reject, 13359 // Label 1104: @29280 13360 GIM_Reject, 13361 // Label 1079: @29281 13362 GIM_Try, /*On fail goto*//*Label 1107*/ 29315, // Rule ID 5567 // 13363 GIM_CheckFeatures, GIFBS_HasAVX512, 13364 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s64, 13365 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s64, 13366 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 13367 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID, 13368 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR512RegClassID, 13369 // (fsub:{ *:[v8f64] } VR512:{ *:[v8f64] }:$src1, VR512:{ *:[v8f64] }:$src2) => (VSUBPDZrr:{ *:[v8f64] } VR512:{ *:[v8f64] }:$src1, VR512:{ *:[v8f64] }:$src2) 13370 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VSUBPDZrr, 13371 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 13372 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13373 // GIR_Coverage, 5567, 13374 GIR_Done, 13375 // Label 1107: @29315 13376 GIM_Reject, 13377 // Label 1080: @29316 13378 GIM_Try, /*On fail goto*//*Label 1108*/ 29350, // Rule ID 5549 // 13379 GIM_CheckFeatures, GIFBS_HasAVX512, 13380 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s32, 13381 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s32, 13382 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 13383 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID, 13384 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR512RegClassID, 13385 // (fsub:{ *:[v16f32] } VR512:{ *:[v16f32] }:$src1, VR512:{ *:[v16f32] }:$src2) => (VSUBPSZrr:{ *:[v16f32] } VR512:{ *:[v16f32] }:$src1, VR512:{ *:[v16f32] }:$src2) 13386 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VSUBPSZrr, 13387 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 13388 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13389 // GIR_Coverage, 5549, 13390 GIR_Done, 13391 // Label 1108: @29350 13392 GIM_Reject, 13393 // Label 1081: @29351 13394 GIM_Reject, 13395 // Label 23: @29352 13396 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/3, 20, /*)*//*default:*//*Label 1118*/ 30027, 13397 /*GILLT_s32*//*Label 1109*/ 29375, 13398 /*GILLT_s64*//*Label 1110*/ 29494, 13399 /*GILLT_s80*//*Label 1111*/ 29613, 0, 0, 13400 /*GILLT_v2s64*//*Label 1112*/ 29649, 0, 13401 /*GILLT_v4s32*//*Label 1113*/ 29739, 13402 /*GILLT_v4s64*//*Label 1114*/ 29829, 0, 0, 13403 /*GILLT_v8s32*//*Label 1115*/ 29893, 13404 /*GILLT_v8s64*//*Label 1116*/ 29957, 0, 0, 0, 13405 /*GILLT_v16s32*//*Label 1117*/ 29992, 13406 // Label 1109: @29375 13407 GIM_Try, /*On fail goto*//*Label 1119*/ 29493, 13408 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 13409 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 13410 GIM_Try, /*On fail goto*//*Label 1120*/ 29414, // Rule ID 618 // 13411 GIM_CheckFeatures, GIFBS_FPStackf32, 13412 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::RFP32RegClassID, 13413 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::RFP32RegClassID, 13414 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::RFP32RegClassID, 13415 // (fmul:{ *:[f32] } RFP32:{ *:[f32] }:$src1, RFP32:{ *:[f32] }:$src2) => (MUL_Fp32:{ *:[f32] }:{ *:[i16] } RFP32:{ *:[f32] }:$src1, RFP32:{ *:[f32] }:$src2) 13416 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::MUL_Fp32, 13417 GIR_AddImplicitDef, /*InsnID*/0, X86::FPSW, 13418 GIR_AddImplicitUse, /*InsnID*/0, X86::FPCW, 13419 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13420 // GIR_Coverage, 618, 13421 GIR_Done, 13422 // Label 1120: @29414 13423 GIM_Try, /*On fail goto*//*Label 1121*/ 29440, // Rule ID 1714 // 13424 GIM_CheckFeatures, GIFBS_UseAVX, 13425 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::FR32RegClassID, 13426 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR32RegClassID, 13427 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::FR32RegClassID, 13428 // (fmul:{ *:[f32] } FR32:{ *:[f32] }:$src1, FR32:{ *:[f32] }:$src2) => (VMULSSrr:{ *:[f32] } FR32:{ *:[f32] }:$src1, FR32:{ *:[f32] }:$src2) 13429 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VMULSSrr, 13430 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 13431 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13432 // GIR_Coverage, 1714, 13433 GIR_Done, 13434 // Label 1121: @29440 13435 GIM_Try, /*On fail goto*//*Label 1122*/ 29466, // Rule ID 1722 // 13436 GIM_CheckFeatures, GIFBS_UseSSE1, 13437 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::FR32RegClassID, 13438 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR32RegClassID, 13439 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::FR32RegClassID, 13440 // (fmul:{ *:[f32] } FR32:{ *:[f32] }:$src1, FR32:{ *:[f32] }:$src2) => (MULSSrr:{ *:[f32] } FR32:{ *:[f32] }:$src1, FR32:{ *:[f32] }:$src2) 13441 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::MULSSrr, 13442 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 13443 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13444 // GIR_Coverage, 1722, 13445 GIR_Done, 13446 // Label 1122: @29466 13447 GIM_Try, /*On fail goto*//*Label 1123*/ 29492, // Rule ID 5197 // 13448 GIM_CheckFeatures, GIFBS_HasAVX512, 13449 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::FR32XRegClassID, 13450 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR32XRegClassID, 13451 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::FR32XRegClassID, 13452 // (fmul:{ *:[f32] } FR32X:{ *:[f32] }:$src1, FR32X:{ *:[f32] }:$src2) => (VMULSSZrr:{ *:[f32] } FR32X:{ *:[f32] }:$src1, FR32X:{ *:[f32] }:$src2) 13453 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VMULSSZrr, 13454 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 13455 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13456 // GIR_Coverage, 5197, 13457 GIR_Done, 13458 // Label 1123: @29492 13459 GIM_Reject, 13460 // Label 1119: @29493 13461 GIM_Reject, 13462 // Label 1110: @29494 13463 GIM_Try, /*On fail goto*//*Label 1124*/ 29612, 13464 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 13465 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 13466 GIM_Try, /*On fail goto*//*Label 1125*/ 29533, // Rule ID 620 // 13467 GIM_CheckFeatures, GIFBS_FPStackf64, 13468 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::RFP64RegClassID, 13469 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::RFP64RegClassID, 13470 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::RFP64RegClassID, 13471 // (fmul:{ *:[f64] } RFP64:{ *:[f64] }:$src1, RFP64:{ *:[f64] }:$src2) => (MUL_Fp64:{ *:[f64] }:{ *:[i16] } RFP64:{ *:[f64] }:$src1, RFP64:{ *:[f64] }:$src2) 13472 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::MUL_Fp64, 13473 GIR_AddImplicitDef, /*InsnID*/0, X86::FPSW, 13474 GIR_AddImplicitUse, /*InsnID*/0, X86::FPCW, 13475 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13476 // GIR_Coverage, 620, 13477 GIR_Done, 13478 // Label 1125: @29533 13479 GIM_Try, /*On fail goto*//*Label 1126*/ 29559, // Rule ID 1718 // 13480 GIM_CheckFeatures, GIFBS_UseAVX, 13481 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::FR64RegClassID, 13482 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR64RegClassID, 13483 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::FR64RegClassID, 13484 // (fmul:{ *:[f64] } FR64:{ *:[f64] }:$src1, FR64:{ *:[f64] }:$src2) => (VMULSDrr:{ *:[f64] } FR64:{ *:[f64] }:$src1, FR64:{ *:[f64] }:$src2) 13485 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VMULSDrr, 13486 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 13487 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13488 // GIR_Coverage, 1718, 13489 GIR_Done, 13490 // Label 1126: @29559 13491 GIM_Try, /*On fail goto*//*Label 1127*/ 29585, // Rule ID 1726 // 13492 GIM_CheckFeatures, GIFBS_UseSSE2, 13493 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::FR64RegClassID, 13494 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR64RegClassID, 13495 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::FR64RegClassID, 13496 // (fmul:{ *:[f64] } FR64:{ *:[f64] }:$src1, FR64:{ *:[f64] }:$src2) => (MULSDrr:{ *:[f64] } FR64:{ *:[f64] }:$src1, FR64:{ *:[f64] }:$src2) 13497 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::MULSDrr, 13498 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 13499 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13500 // GIR_Coverage, 1726, 13501 GIR_Done, 13502 // Label 1127: @29585 13503 GIM_Try, /*On fail goto*//*Label 1128*/ 29611, // Rule ID 5210 // 13504 GIM_CheckFeatures, GIFBS_HasAVX512, 13505 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::FR64XRegClassID, 13506 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR64XRegClassID, 13507 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::FR64XRegClassID, 13508 // (fmul:{ *:[f64] } FR64X:{ *:[f64] }:$src1, FR64X:{ *:[f64] }:$src2) => (VMULSDZrr:{ *:[f64] } FR64X:{ *:[f64] }:$src1, FR64X:{ *:[f64] }:$src2) 13509 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VMULSDZrr, 13510 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 13511 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13512 // GIR_Coverage, 5210, 13513 GIR_Done, 13514 // Label 1128: @29611 13515 GIM_Reject, 13516 // Label 1124: @29612 13517 GIM_Reject, 13518 // Label 1111: @29613 13519 GIM_Try, /*On fail goto*//*Label 1129*/ 29648, // Rule ID 622 // 13520 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s80, 13521 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s80, 13522 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::RFP80RegClassID, 13523 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::RFP80RegClassID, 13524 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::RFP80RegClassID, 13525 // (fmul:{ *:[f80] } RFP80:{ *:[f80] }:$src1, RFP80:{ *:[f80] }:$src2) => (MUL_Fp80:{ *:[f80] }:{ *:[i16] } RFP80:{ *:[f80] }:$src1, RFP80:{ *:[f80] }:$src2) 13526 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::MUL_Fp80, 13527 GIR_AddImplicitDef, /*InsnID*/0, X86::FPSW, 13528 GIR_AddImplicitUse, /*InsnID*/0, X86::FPCW, 13529 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13530 // GIR_Coverage, 622, 13531 GIR_Done, 13532 // Label 1129: @29648 13533 GIM_Reject, 13534 // Label 1112: @29649 13535 GIM_Try, /*On fail goto*//*Label 1130*/ 29738, 13536 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, 13537 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 13538 GIM_Try, /*On fail goto*//*Label 1131*/ 29685, // Rule ID 1694 // 13539 GIM_CheckFeatures, GIFBS_HasAVX_NoVLX, 13540 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 13541 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 13542 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 13543 // (fmul:{ *:[v2f64] } VR128:{ *:[v2f64] }:$src1, VR128:{ *:[v2f64] }:$src2) => (VMULPDrr:{ *:[v2f64] } VR128:{ *:[v2f64] }:$src1, VR128:{ *:[v2f64] }:$src2) 13544 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VMULPDrr, 13545 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 13546 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13547 // GIR_Coverage, 1694, 13548 GIR_Done, 13549 // Label 1131: @29685 13550 GIM_Try, /*On fail goto*//*Label 1132*/ 29711, // Rule ID 1710 // 13551 GIM_CheckFeatures, GIFBS_UseSSE2, 13552 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 13553 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 13554 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 13555 // (fmul:{ *:[v2f64] } VR128:{ *:[v2f64] }:$src1, VR128:{ *:[v2f64] }:$src2) => (MULPDrr:{ *:[v2f64] } VR128:{ *:[v2f64] }:$src1, VR128:{ *:[v2f64] }:$src2) 13556 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::MULPDrr, 13557 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 13558 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13559 // GIR_Coverage, 1710, 13560 GIR_Done, 13561 // Label 1132: @29711 13562 GIM_Try, /*On fail goto*//*Label 1133*/ 29737, // Rule ID 5507 // 13563 GIM_CheckFeatures, GIFBS_HasAVX512_HasVLX, 13564 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 13565 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 13566 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128XRegClassID, 13567 // (fmul:{ *:[v2f64] } VR128X:{ *:[v2f64] }:$src1, VR128X:{ *:[v2f64] }:$src2) => (VMULPDZ128rr:{ *:[v2f64] } VR128X:{ *:[v2f64] }:$src1, VR128X:{ *:[v2f64] }:$src2) 13568 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VMULPDZ128rr, 13569 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 13570 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13571 // GIR_Coverage, 5507, 13572 GIR_Done, 13573 // Label 1133: @29737 13574 GIM_Reject, 13575 // Label 1130: @29738 13576 GIM_Reject, 13577 // Label 1113: @29739 13578 GIM_Try, /*On fail goto*//*Label 1134*/ 29828, 13579 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 13580 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 13581 GIM_Try, /*On fail goto*//*Label 1135*/ 29775, // Rule ID 1690 // 13582 GIM_CheckFeatures, GIFBS_HasAVX_NoVLX, 13583 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 13584 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 13585 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 13586 // (fmul:{ *:[v4f32] } VR128:{ *:[v4f32] }:$src1, VR128:{ *:[v4f32] }:$src2) => (VMULPSrr:{ *:[v4f32] } VR128:{ *:[v4f32] }:$src1, VR128:{ *:[v4f32] }:$src2) 13587 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VMULPSrr, 13588 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 13589 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13590 // GIR_Coverage, 1690, 13591 GIR_Done, 13592 // Label 1135: @29775 13593 GIM_Try, /*On fail goto*//*Label 1136*/ 29801, // Rule ID 1706 // 13594 GIM_CheckFeatures, GIFBS_UseSSE1, 13595 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 13596 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 13597 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 13598 // (fmul:{ *:[v4f32] } VR128:{ *:[v4f32] }:$src1, VR128:{ *:[v4f32] }:$src2) => (MULPSrr:{ *:[v4f32] } VR128:{ *:[v4f32] }:$src1, VR128:{ *:[v4f32] }:$src2) 13599 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::MULPSrr, 13600 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 13601 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13602 // GIR_Coverage, 1706, 13603 GIR_Done, 13604 // Label 1136: @29801 13605 GIM_Try, /*On fail goto*//*Label 1137*/ 29827, // Rule ID 5471 // 13606 GIM_CheckFeatures, GIFBS_HasAVX512_HasVLX, 13607 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 13608 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 13609 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128XRegClassID, 13610 // (fmul:{ *:[v4f32] } VR128X:{ *:[v4f32] }:$src1, VR128X:{ *:[v4f32] }:$src2) => (VMULPSZ128rr:{ *:[v4f32] } VR128X:{ *:[v4f32] }:$src1, VR128X:{ *:[v4f32] }:$src2) 13611 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VMULPSZ128rr, 13612 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 13613 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13614 // GIR_Coverage, 5471, 13615 GIR_Done, 13616 // Label 1137: @29827 13617 GIM_Reject, 13618 // Label 1134: @29828 13619 GIM_Reject, 13620 // Label 1114: @29829 13621 GIM_Try, /*On fail goto*//*Label 1138*/ 29892, 13622 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s64, 13623 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s64, 13624 GIM_Try, /*On fail goto*//*Label 1139*/ 29865, // Rule ID 1702 // 13625 GIM_CheckFeatures, GIFBS_HasAVX_NoVLX, 13626 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID, 13627 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256RegClassID, 13628 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID, 13629 // (fmul:{ *:[v4f64] } VR256:{ *:[v4f64] }:$src1, VR256:{ *:[v4f64] }:$src2) => (VMULPDYrr:{ *:[v4f64] } VR256:{ *:[v4f64] }:$src1, VR256:{ *:[v4f64] }:$src2) 13630 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VMULPDYrr, 13631 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 13632 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13633 // GIR_Coverage, 1702, 13634 GIR_Done, 13635 // Label 1139: @29865 13636 GIM_Try, /*On fail goto*//*Label 1140*/ 29891, // Rule ID 5525 // 13637 GIM_CheckFeatures, GIFBS_HasAVX512_HasVLX, 13638 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 13639 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 13640 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256XRegClassID, 13641 // (fmul:{ *:[v4f64] } VR256X:{ *:[v4f64] }:$src1, VR256X:{ *:[v4f64] }:$src2) => (VMULPDZ256rr:{ *:[v4f64] } VR256X:{ *:[v4f64] }:$src1, VR256X:{ *:[v4f64] }:$src2) 13642 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VMULPDZ256rr, 13643 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 13644 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13645 // GIR_Coverage, 5525, 13646 GIR_Done, 13647 // Label 1140: @29891 13648 GIM_Reject, 13649 // Label 1138: @29892 13650 GIM_Reject, 13651 // Label 1115: @29893 13652 GIM_Try, /*On fail goto*//*Label 1141*/ 29956, 13653 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s32, 13654 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s32, 13655 GIM_Try, /*On fail goto*//*Label 1142*/ 29929, // Rule ID 1698 // 13656 GIM_CheckFeatures, GIFBS_HasAVX_NoVLX, 13657 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID, 13658 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256RegClassID, 13659 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID, 13660 // (fmul:{ *:[v8f32] } VR256:{ *:[v8f32] }:$src1, VR256:{ *:[v8f32] }:$src2) => (VMULPSYrr:{ *:[v8f32] } VR256:{ *:[v8f32] }:$src1, VR256:{ *:[v8f32] }:$src2) 13661 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VMULPSYrr, 13662 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 13663 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13664 // GIR_Coverage, 1698, 13665 GIR_Done, 13666 // Label 1142: @29929 13667 GIM_Try, /*On fail goto*//*Label 1143*/ 29955, // Rule ID 5489 // 13668 GIM_CheckFeatures, GIFBS_HasAVX512_HasVLX, 13669 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 13670 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 13671 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256XRegClassID, 13672 // (fmul:{ *:[v8f32] } VR256X:{ *:[v8f32] }:$src1, VR256X:{ *:[v8f32] }:$src2) => (VMULPSZ256rr:{ *:[v8f32] } VR256X:{ *:[v8f32] }:$src1, VR256X:{ *:[v8f32] }:$src2) 13673 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VMULPSZ256rr, 13674 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 13675 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13676 // GIR_Coverage, 5489, 13677 GIR_Done, 13678 // Label 1143: @29955 13679 GIM_Reject, 13680 // Label 1141: @29956 13681 GIM_Reject, 13682 // Label 1116: @29957 13683 GIM_Try, /*On fail goto*//*Label 1144*/ 29991, // Rule ID 5453 // 13684 GIM_CheckFeatures, GIFBS_HasAVX512, 13685 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s64, 13686 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s64, 13687 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 13688 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID, 13689 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR512RegClassID, 13690 // (fmul:{ *:[v8f64] } VR512:{ *:[v8f64] }:$src1, VR512:{ *:[v8f64] }:$src2) => (VMULPDZrr:{ *:[v8f64] } VR512:{ *:[v8f64] }:$src1, VR512:{ *:[v8f64] }:$src2) 13691 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VMULPDZrr, 13692 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 13693 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13694 // GIR_Coverage, 5453, 13695 GIR_Done, 13696 // Label 1144: @29991 13697 GIM_Reject, 13698 // Label 1117: @29992 13699 GIM_Try, /*On fail goto*//*Label 1145*/ 30026, // Rule ID 5435 // 13700 GIM_CheckFeatures, GIFBS_HasAVX512, 13701 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s32, 13702 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s32, 13703 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 13704 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID, 13705 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR512RegClassID, 13706 // (fmul:{ *:[v16f32] } VR512:{ *:[v16f32] }:$src1, VR512:{ *:[v16f32] }:$src2) => (VMULPSZrr:{ *:[v16f32] } VR512:{ *:[v16f32] }:$src1, VR512:{ *:[v16f32] }:$src2) 13707 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VMULPSZrr, 13708 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 13709 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13710 // GIR_Coverage, 5435, 13711 GIR_Done, 13712 // Label 1145: @30026 13713 GIM_Reject, 13714 // Label 1118: @30027 13715 GIM_Reject, 13716 // Label 24: @30028 13717 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/3, 20, /*)*//*default:*//*Label 1155*/ 30703, 13718 /*GILLT_s32*//*Label 1146*/ 30051, 13719 /*GILLT_s64*//*Label 1147*/ 30170, 13720 /*GILLT_s80*//*Label 1148*/ 30289, 0, 0, 13721 /*GILLT_v2s64*//*Label 1149*/ 30325, 0, 13722 /*GILLT_v4s32*//*Label 1150*/ 30415, 13723 /*GILLT_v4s64*//*Label 1151*/ 30505, 0, 0, 13724 /*GILLT_v8s32*//*Label 1152*/ 30569, 13725 /*GILLT_v8s64*//*Label 1153*/ 30633, 0, 0, 0, 13726 /*GILLT_v16s32*//*Label 1154*/ 30668, 13727 // Label 1146: @30051 13728 GIM_Try, /*On fail goto*//*Label 1156*/ 30169, 13729 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 13730 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 13731 GIM_Try, /*On fail goto*//*Label 1157*/ 30090, // Rule ID 624 // 13732 GIM_CheckFeatures, GIFBS_FPStackf32, 13733 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::RFP32RegClassID, 13734 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::RFP32RegClassID, 13735 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::RFP32RegClassID, 13736 // (fdiv:{ *:[f32] } RFP32:{ *:[f32] }:$src1, RFP32:{ *:[f32] }:$src2) => (DIV_Fp32:{ *:[f32] }:{ *:[i16] } RFP32:{ *:[f32] }:$src1, RFP32:{ *:[f32] }:$src2) 13737 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::DIV_Fp32, 13738 GIR_AddImplicitDef, /*InsnID*/0, X86::FPSW, 13739 GIR_AddImplicitUse, /*InsnID*/0, X86::FPCW, 13740 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13741 // GIR_Coverage, 624, 13742 GIR_Done, 13743 // Label 1157: @30090 13744 GIM_Try, /*On fail goto*//*Label 1158*/ 30116, // Rule ID 1794 // 13745 GIM_CheckFeatures, GIFBS_UseAVX, 13746 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::FR32RegClassID, 13747 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR32RegClassID, 13748 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::FR32RegClassID, 13749 // (fdiv:{ *:[f32] } FR32:{ *:[f32] }:$src1, FR32:{ *:[f32] }:$src2) => (VDIVSSrr:{ *:[f32] } FR32:{ *:[f32] }:$src1, FR32:{ *:[f32] }:$src2) 13750 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VDIVSSrr, 13751 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 13752 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13753 // GIR_Coverage, 1794, 13754 GIR_Done, 13755 // Label 1158: @30116 13756 GIM_Try, /*On fail goto*//*Label 1159*/ 30142, // Rule ID 1802 // 13757 GIM_CheckFeatures, GIFBS_UseSSE1, 13758 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::FR32RegClassID, 13759 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR32RegClassID, 13760 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::FR32RegClassID, 13761 // (fdiv:{ *:[f32] } FR32:{ *:[f32] }:$src1, FR32:{ *:[f32] }:$src2) => (DIVSSrr:{ *:[f32] } FR32:{ *:[f32] }:$src1, FR32:{ *:[f32] }:$src2) 13762 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::DIVSSrr, 13763 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 13764 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13765 // GIR_Coverage, 1802, 13766 GIR_Done, 13767 // Label 1159: @30142 13768 GIM_Try, /*On fail goto*//*Label 1160*/ 30168, // Rule ID 5249 // 13769 GIM_CheckFeatures, GIFBS_HasAVX512, 13770 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::FR32XRegClassID, 13771 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR32XRegClassID, 13772 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::FR32XRegClassID, 13773 // (fdiv:{ *:[f32] } FR32X:{ *:[f32] }:$src1, FR32X:{ *:[f32] }:$src2) => (VDIVSSZrr:{ *:[f32] } FR32X:{ *:[f32] }:$src1, FR32X:{ *:[f32] }:$src2) 13774 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VDIVSSZrr, 13775 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 13776 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13777 // GIR_Coverage, 5249, 13778 GIR_Done, 13779 // Label 1160: @30168 13780 GIM_Reject, 13781 // Label 1156: @30169 13782 GIM_Reject, 13783 // Label 1147: @30170 13784 GIM_Try, /*On fail goto*//*Label 1161*/ 30288, 13785 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 13786 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 13787 GIM_Try, /*On fail goto*//*Label 1162*/ 30209, // Rule ID 626 // 13788 GIM_CheckFeatures, GIFBS_FPStackf64, 13789 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::RFP64RegClassID, 13790 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::RFP64RegClassID, 13791 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::RFP64RegClassID, 13792 // (fdiv:{ *:[f64] } RFP64:{ *:[f64] }:$src1, RFP64:{ *:[f64] }:$src2) => (DIV_Fp64:{ *:[f64] }:{ *:[i16] } RFP64:{ *:[f64] }:$src1, RFP64:{ *:[f64] }:$src2) 13793 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::DIV_Fp64, 13794 GIR_AddImplicitDef, /*InsnID*/0, X86::FPSW, 13795 GIR_AddImplicitUse, /*InsnID*/0, X86::FPCW, 13796 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13797 // GIR_Coverage, 626, 13798 GIR_Done, 13799 // Label 1162: @30209 13800 GIM_Try, /*On fail goto*//*Label 1163*/ 30235, // Rule ID 1798 // 13801 GIM_CheckFeatures, GIFBS_UseAVX, 13802 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::FR64RegClassID, 13803 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR64RegClassID, 13804 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::FR64RegClassID, 13805 // (fdiv:{ *:[f64] } FR64:{ *:[f64] }:$src1, FR64:{ *:[f64] }:$src2) => (VDIVSDrr:{ *:[f64] } FR64:{ *:[f64] }:$src1, FR64:{ *:[f64] }:$src2) 13806 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VDIVSDrr, 13807 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 13808 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13809 // GIR_Coverage, 1798, 13810 GIR_Done, 13811 // Label 1163: @30235 13812 GIM_Try, /*On fail goto*//*Label 1164*/ 30261, // Rule ID 1806 // 13813 GIM_CheckFeatures, GIFBS_UseSSE2, 13814 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::FR64RegClassID, 13815 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR64RegClassID, 13816 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::FR64RegClassID, 13817 // (fdiv:{ *:[f64] } FR64:{ *:[f64] }:$src1, FR64:{ *:[f64] }:$src2) => (DIVSDrr:{ *:[f64] } FR64:{ *:[f64] }:$src1, FR64:{ *:[f64] }:$src2) 13818 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::DIVSDrr, 13819 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 13820 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13821 // GIR_Coverage, 1806, 13822 GIR_Done, 13823 // Label 1164: @30261 13824 GIM_Try, /*On fail goto*//*Label 1165*/ 30287, // Rule ID 5262 // 13825 GIM_CheckFeatures, GIFBS_HasAVX512, 13826 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::FR64XRegClassID, 13827 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR64XRegClassID, 13828 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::FR64XRegClassID, 13829 // (fdiv:{ *:[f64] } FR64X:{ *:[f64] }:$src1, FR64X:{ *:[f64] }:$src2) => (VDIVSDZrr:{ *:[f64] } FR64X:{ *:[f64] }:$src1, FR64X:{ *:[f64] }:$src2) 13830 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VDIVSDZrr, 13831 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 13832 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13833 // GIR_Coverage, 5262, 13834 GIR_Done, 13835 // Label 1165: @30287 13836 GIM_Reject, 13837 // Label 1161: @30288 13838 GIM_Reject, 13839 // Label 1148: @30289 13840 GIM_Try, /*On fail goto*//*Label 1166*/ 30324, // Rule ID 628 // 13841 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s80, 13842 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s80, 13843 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::RFP80RegClassID, 13844 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::RFP80RegClassID, 13845 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::RFP80RegClassID, 13846 // (fdiv:{ *:[f80] } RFP80:{ *:[f80] }:$src1, RFP80:{ *:[f80] }:$src2) => (DIV_Fp80:{ *:[f80] }:{ *:[i16] } RFP80:{ *:[f80] }:$src1, RFP80:{ *:[f80] }:$src2) 13847 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::DIV_Fp80, 13848 GIR_AddImplicitDef, /*InsnID*/0, X86::FPSW, 13849 GIR_AddImplicitUse, /*InsnID*/0, X86::FPCW, 13850 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13851 // GIR_Coverage, 628, 13852 GIR_Done, 13853 // Label 1166: @30324 13854 GIM_Reject, 13855 // Label 1149: @30325 13856 GIM_Try, /*On fail goto*//*Label 1167*/ 30414, 13857 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, 13858 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 13859 GIM_Try, /*On fail goto*//*Label 1168*/ 30361, // Rule ID 1774 // 13860 GIM_CheckFeatures, GIFBS_HasAVX_NoVLX, 13861 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 13862 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 13863 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 13864 // (fdiv:{ *:[v2f64] } VR128:{ *:[v2f64] }:$src1, VR128:{ *:[v2f64] }:$src2) => (VDIVPDrr:{ *:[v2f64] } VR128:{ *:[v2f64] }:$src1, VR128:{ *:[v2f64] }:$src2) 13865 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VDIVPDrr, 13866 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 13867 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13868 // GIR_Coverage, 1774, 13869 GIR_Done, 13870 // Label 1168: @30361 13871 GIM_Try, /*On fail goto*//*Label 1169*/ 30387, // Rule ID 1790 // 13872 GIM_CheckFeatures, GIFBS_UseSSE2, 13873 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 13874 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 13875 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 13876 // (fdiv:{ *:[v2f64] } VR128:{ *:[v2f64] }:$src1, VR128:{ *:[v2f64] }:$src2) => (DIVPDrr:{ *:[v2f64] } VR128:{ *:[v2f64] }:$src1, VR128:{ *:[v2f64] }:$src2) 13877 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::DIVPDrr, 13878 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 13879 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13880 // GIR_Coverage, 1790, 13881 GIR_Done, 13882 // Label 1169: @30387 13883 GIM_Try, /*On fail goto*//*Label 1170*/ 30413, // Rule ID 5735 // 13884 GIM_CheckFeatures, GIFBS_HasAVX512_HasVLX, 13885 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 13886 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 13887 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128XRegClassID, 13888 // (fdiv:{ *:[v2f64] } VR128X:{ *:[v2f64] }:$src1, VR128X:{ *:[v2f64] }:$src2) => (VDIVPDZ128rr:{ *:[v2f64] } VR128X:{ *:[v2f64] }:$src1, VR128X:{ *:[v2f64] }:$src2) 13889 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VDIVPDZ128rr, 13890 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 13891 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13892 // GIR_Coverage, 5735, 13893 GIR_Done, 13894 // Label 1170: @30413 13895 GIM_Reject, 13896 // Label 1167: @30414 13897 GIM_Reject, 13898 // Label 1150: @30415 13899 GIM_Try, /*On fail goto*//*Label 1171*/ 30504, 13900 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 13901 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 13902 GIM_Try, /*On fail goto*//*Label 1172*/ 30451, // Rule ID 1770 // 13903 GIM_CheckFeatures, GIFBS_HasAVX_NoVLX, 13904 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 13905 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 13906 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 13907 // (fdiv:{ *:[v4f32] } VR128:{ *:[v4f32] }:$src1, VR128:{ *:[v4f32] }:$src2) => (VDIVPSrr:{ *:[v4f32] } VR128:{ *:[v4f32] }:$src1, VR128:{ *:[v4f32] }:$src2) 13908 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VDIVPSrr, 13909 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 13910 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13911 // GIR_Coverage, 1770, 13912 GIR_Done, 13913 // Label 1172: @30451 13914 GIM_Try, /*On fail goto*//*Label 1173*/ 30477, // Rule ID 1786 // 13915 GIM_CheckFeatures, GIFBS_UseSSE1, 13916 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 13917 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 13918 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 13919 // (fdiv:{ *:[v4f32] } VR128:{ *:[v4f32] }:$src1, VR128:{ *:[v4f32] }:$src2) => (DIVPSrr:{ *:[v4f32] } VR128:{ *:[v4f32] }:$src1, VR128:{ *:[v4f32] }:$src2) 13920 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::DIVPSrr, 13921 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 13922 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13923 // GIR_Coverage, 1786, 13924 GIR_Done, 13925 // Label 1173: @30477 13926 GIM_Try, /*On fail goto*//*Label 1174*/ 30503, // Rule ID 5699 // 13927 GIM_CheckFeatures, GIFBS_HasAVX512_HasVLX, 13928 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 13929 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 13930 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128XRegClassID, 13931 // (fdiv:{ *:[v4f32] } VR128X:{ *:[v4f32] }:$src1, VR128X:{ *:[v4f32] }:$src2) => (VDIVPSZ128rr:{ *:[v4f32] } VR128X:{ *:[v4f32] }:$src1, VR128X:{ *:[v4f32] }:$src2) 13932 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VDIVPSZ128rr, 13933 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 13934 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13935 // GIR_Coverage, 5699, 13936 GIR_Done, 13937 // Label 1174: @30503 13938 GIM_Reject, 13939 // Label 1171: @30504 13940 GIM_Reject, 13941 // Label 1151: @30505 13942 GIM_Try, /*On fail goto*//*Label 1175*/ 30568, 13943 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s64, 13944 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s64, 13945 GIM_Try, /*On fail goto*//*Label 1176*/ 30541, // Rule ID 1782 // 13946 GIM_CheckFeatures, GIFBS_HasAVX_NoVLX, 13947 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID, 13948 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256RegClassID, 13949 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID, 13950 // (fdiv:{ *:[v4f64] } VR256:{ *:[v4f64] }:$src1, VR256:{ *:[v4f64] }:$src2) => (VDIVPDYrr:{ *:[v4f64] } VR256:{ *:[v4f64] }:$src1, VR256:{ *:[v4f64] }:$src2) 13951 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VDIVPDYrr, 13952 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 13953 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13954 // GIR_Coverage, 1782, 13955 GIR_Done, 13956 // Label 1176: @30541 13957 GIM_Try, /*On fail goto*//*Label 1177*/ 30567, // Rule ID 5753 // 13958 GIM_CheckFeatures, GIFBS_HasAVX512_HasVLX, 13959 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 13960 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 13961 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256XRegClassID, 13962 // (fdiv:{ *:[v4f64] } VR256X:{ *:[v4f64] }:$src1, VR256X:{ *:[v4f64] }:$src2) => (VDIVPDZ256rr:{ *:[v4f64] } VR256X:{ *:[v4f64] }:$src1, VR256X:{ *:[v4f64] }:$src2) 13963 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VDIVPDZ256rr, 13964 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 13965 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13966 // GIR_Coverage, 5753, 13967 GIR_Done, 13968 // Label 1177: @30567 13969 GIM_Reject, 13970 // Label 1175: @30568 13971 GIM_Reject, 13972 // Label 1152: @30569 13973 GIM_Try, /*On fail goto*//*Label 1178*/ 30632, 13974 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s32, 13975 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s32, 13976 GIM_Try, /*On fail goto*//*Label 1179*/ 30605, // Rule ID 1778 // 13977 GIM_CheckFeatures, GIFBS_HasAVX_NoVLX, 13978 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID, 13979 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256RegClassID, 13980 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID, 13981 // (fdiv:{ *:[v8f32] } VR256:{ *:[v8f32] }:$src1, VR256:{ *:[v8f32] }:$src2) => (VDIVPSYrr:{ *:[v8f32] } VR256:{ *:[v8f32] }:$src1, VR256:{ *:[v8f32] }:$src2) 13982 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VDIVPSYrr, 13983 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 13984 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13985 // GIR_Coverage, 1778, 13986 GIR_Done, 13987 // Label 1179: @30605 13988 GIM_Try, /*On fail goto*//*Label 1180*/ 30631, // Rule ID 5717 // 13989 GIM_CheckFeatures, GIFBS_HasAVX512_HasVLX, 13990 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 13991 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 13992 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256XRegClassID, 13993 // (fdiv:{ *:[v8f32] } VR256X:{ *:[v8f32] }:$src1, VR256X:{ *:[v8f32] }:$src2) => (VDIVPSZ256rr:{ *:[v8f32] } VR256X:{ *:[v8f32] }:$src1, VR256X:{ *:[v8f32] }:$src2) 13994 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VDIVPSZ256rr, 13995 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 13996 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 13997 // GIR_Coverage, 5717, 13998 GIR_Done, 13999 // Label 1180: @30631 14000 GIM_Reject, 14001 // Label 1178: @30632 14002 GIM_Reject, 14003 // Label 1153: @30633 14004 GIM_Try, /*On fail goto*//*Label 1181*/ 30667, // Rule ID 5681 // 14005 GIM_CheckFeatures, GIFBS_HasAVX512, 14006 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s64, 14007 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s64, 14008 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 14009 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID, 14010 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR512RegClassID, 14011 // (fdiv:{ *:[v8f64] } VR512:{ *:[v8f64] }:$src1, VR512:{ *:[v8f64] }:$src2) => (VDIVPDZrr:{ *:[v8f64] } VR512:{ *:[v8f64] }:$src1, VR512:{ *:[v8f64] }:$src2) 14012 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VDIVPDZrr, 14013 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 14014 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14015 // GIR_Coverage, 5681, 14016 GIR_Done, 14017 // Label 1181: @30667 14018 GIM_Reject, 14019 // Label 1154: @30668 14020 GIM_Try, /*On fail goto*//*Label 1182*/ 30702, // Rule ID 5663 // 14021 GIM_CheckFeatures, GIFBS_HasAVX512, 14022 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s32, 14023 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s32, 14024 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 14025 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID, 14026 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR512RegClassID, 14027 // (fdiv:{ *:[v16f32] } VR512:{ *:[v16f32] }:$src1, VR512:{ *:[v16f32] }:$src2) => (VDIVPSZrr:{ *:[v16f32] } VR512:{ *:[v16f32] }:$src1, VR512:{ *:[v16f32] }:$src2) 14028 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VDIVPSZrr, 14029 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 14030 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14031 // GIR_Coverage, 5663, 14032 GIR_Done, 14033 // Label 1182: @30702 14034 GIM_Reject, 14035 // Label 1155: @30703 14036 GIM_Reject, 14037 // Label 25: @30704 14038 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/3, 6, /*)*//*default:*//*Label 1186*/ 30792, 14039 /*GILLT_s32*//*Label 1183*/ 30713, 14040 /*GILLT_s64*//*Label 1184*/ 30740, 14041 /*GILLT_s80*//*Label 1185*/ 30767, 14042 // Label 1183: @30713 14043 GIM_Try, /*On fail goto*//*Label 1187*/ 30739, // Rule ID 761 // 14044 GIM_CheckFeatures, GIFBS_FPStackf32, 14045 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 14046 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::RFP32RegClassID, 14047 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::RFP32RegClassID, 14048 // (fneg:{ *:[f32] } RFP32:{ *:[f32] }:$src) => (CHS_Fp32:{ *:[f32] }:{ *:[i16] } RFP32:{ *:[f32] }:$src) 14049 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::CHS_Fp32, 14050 GIR_AddImplicitDef, /*InsnID*/0, X86::FPSW, 14051 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14052 // GIR_Coverage, 761, 14053 GIR_Done, 14054 // Label 1187: @30739 14055 GIM_Reject, 14056 // Label 1184: @30740 14057 GIM_Try, /*On fail goto*//*Label 1188*/ 30766, // Rule ID 762 // 14058 GIM_CheckFeatures, GIFBS_FPStackf64, 14059 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 14060 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::RFP64RegClassID, 14061 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::RFP64RegClassID, 14062 // (fneg:{ *:[f64] } RFP64:{ *:[f64] }:$src) => (CHS_Fp64:{ *:[f64] }:{ *:[i16] } RFP64:{ *:[f64] }:$src) 14063 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::CHS_Fp64, 14064 GIR_AddImplicitDef, /*InsnID*/0, X86::FPSW, 14065 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14066 // GIR_Coverage, 762, 14067 GIR_Done, 14068 // Label 1188: @30766 14069 GIM_Reject, 14070 // Label 1185: @30767 14071 GIM_Try, /*On fail goto*//*Label 1189*/ 30791, // Rule ID 763 // 14072 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s80, 14073 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::RFP80RegClassID, 14074 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::RFP80RegClassID, 14075 // (fneg:{ *:[f80] } RFP80:{ *:[f80] }:$src) => (CHS_Fp80:{ *:[f80] }:{ *:[i16] } RFP80:{ *:[f80] }:$src) 14076 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::CHS_Fp80, 14077 GIR_AddImplicitDef, /*InsnID*/0, X86::FPSW, 14078 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14079 // GIR_Coverage, 763, 14080 GIR_Done, 14081 // Label 1189: @30791 14082 GIM_Reject, 14083 // Label 1186: @30792 14084 GIM_Reject, 14085 // Label 26: @30793 14086 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/4, 16, /*)*//*default:*//*Label 1194*/ 31080, 14087 /*GILLT_s64*//*Label 1190*/ 30811, 14088 /*GILLT_s80*//*Label 1191*/ 30950, 0, 0, 0, 0, 0, 14089 /*GILLT_v4s64*//*Label 1192*/ 31001, 0, 0, 0, 14090 /*GILLT_v8s64*//*Label 1193*/ 31053, 14091 // Label 1190: @30811 14092 GIM_Try, /*On fail goto*//*Label 1195*/ 30949, 14093 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 14094 GIM_Try, /*On fail goto*//*Label 1196*/ 30839, // Rule ID 1431 // 14095 GIM_CheckFeatures, GIFBS_UseSSE2, 14096 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::FR64RegClassID, 14097 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR32RegClassID, 14098 // (fpextend:{ *:[f64] } FR32:{ *:[f32] }:$src) => (CVTSS2SDrr:{ *:[f64] } FR32:{ *:[f32] }:$src) 14099 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::CVTSS2SDrr, 14100 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 14101 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14102 // GIR_Coverage, 1431, 14103 GIR_Done, 14104 // Label 1196: @30839 14105 GIM_Try, /*On fail goto*//*Label 1197*/ 30860, // Rule ID 13120 // 14106 GIM_CheckFeatures, GIFBS_FPStackf32, 14107 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::RFP64RegClassID, 14108 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::RFP32RegClassID, 14109 // (fpextend:{ *:[f64] } RFP32:{ *:[f32] }:$src) => (COPY_TO_REGCLASS:{ *:[f64] } RFP32:{ *:[f32] }:$src, RFP64:{ *:[i32] }) 14110 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, 14111 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC RFP64*/63, 14112 // GIR_Coverage, 13120, 14113 GIR_Done, 14114 // Label 1197: @30860 14115 GIM_Try, /*On fail goto*//*Label 1198*/ 30904, // Rule ID 13325 // 14116 GIM_CheckFeatures, GIFBS_UseAVX, 14117 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::FR64RegClassID, 14118 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR32RegClassID, 14119 // (fpextend:{ *:[f64] } FR32:{ *:[f32] }:$src) => (VCVTSS2SDrr:{ *:[f64] } (IMPLICIT_DEF:{ *:[f64] }), FR32:{ *:[f32] }:$src) 14120 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, 14121 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, 14122 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 14123 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 14124 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VCVTSS2SDrr, 14125 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 14126 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 14127 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 14128 GIR_EraseFromParent, /*InsnID*/0, 14129 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14130 // GIR_Coverage, 13325, 14131 GIR_Done, 14132 // Label 1198: @30904 14133 GIM_Try, /*On fail goto*//*Label 1199*/ 30948, // Rule ID 16118 // 14134 GIM_CheckFeatures, GIFBS_HasAVX512, 14135 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::FR64XRegClassID, 14136 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR32XRegClassID, 14137 // (fpextend:{ *:[f64] } FR32X:{ *:[f32] }:$src) => (VCVTSS2SDZrr:{ *:[f64] } (IMPLICIT_DEF:{ *:[f64] }), FR32X:{ *:[f32] }:$src) 14138 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, 14139 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, 14140 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 14141 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 14142 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VCVTSS2SDZrr, 14143 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 14144 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 14145 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 14146 GIR_EraseFromParent, /*InsnID*/0, 14147 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14148 // GIR_Coverage, 16118, 14149 GIR_Done, 14150 // Label 1199: @30948 14151 GIM_Reject, 14152 // Label 1195: @30949 14153 GIM_Reject, 14154 // Label 1191: @30950 14155 GIM_Try, /*On fail goto*//*Label 1200*/ 30975, // Rule ID 13122 // 14156 GIM_CheckFeatures, GIFBS_FPStackf32, 14157 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 14158 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::RFP80RegClassID, 14159 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::RFP32RegClassID, 14160 // (fpextend:{ *:[f80] } RFP32:{ *:[f32] }:$src) => (COPY_TO_REGCLASS:{ *:[f80] } RFP32:{ *:[f32] }:$src, RFP80:{ *:[i32] }) 14161 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, 14162 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC RFP80*/109, 14163 // GIR_Coverage, 13122, 14164 GIR_Done, 14165 // Label 1200: @30975 14166 GIM_Try, /*On fail goto*//*Label 1201*/ 31000, // Rule ID 13124 // 14167 GIM_CheckFeatures, GIFBS_FPStackf64, 14168 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 14169 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::RFP80RegClassID, 14170 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::RFP64RegClassID, 14171 // (fpextend:{ *:[f80] } RFP64:{ *:[f64] }:$src) => (COPY_TO_REGCLASS:{ *:[f80] } RFP64:{ *:[f64] }:$src, RFP80:{ *:[i32] }) 14172 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, 14173 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC RFP80*/109, 14174 // GIR_Coverage, 13124, 14175 GIR_Done, 14176 // Label 1201: @31000 14177 GIM_Reject, 14178 // Label 1192: @31001 14179 GIM_Try, /*On fail goto*//*Label 1202*/ 31052, 14180 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 14181 GIM_Try, /*On fail goto*//*Label 1203*/ 31029, // Rule ID 1474 // 14182 GIM_CheckFeatures, GIFBS_HasAVX_NoVLX, 14183 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID, 14184 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 14185 // (fpextend:{ *:[v4f64] } VR128:{ *:[v4f32] }:$src) => (VCVTPS2PDYrr:{ *:[v4f64] } VR128:{ *:[v4f32] }:$src) 14186 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VCVTPS2PDYrr, 14187 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 14188 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14189 // GIR_Coverage, 1474, 14190 GIR_Done, 14191 // Label 1203: @31029 14192 GIM_Try, /*On fail goto*//*Label 1204*/ 31051, // Rule ID 8548 // 14193 GIM_CheckFeatures, GIFBS_HasVLX, 14194 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 14195 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 14196 // (fpextend:{ *:[v4f64] } VR128X:{ *:[v4f32] }:$src) => (VCVTPS2PDZ256rr:{ *:[v4f64] } VR128X:{ *:[v4f32] }:$src) 14197 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VCVTPS2PDZ256rr, 14198 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 14199 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14200 // GIR_Coverage, 8548, 14201 GIR_Done, 14202 // Label 1204: @31051 14203 GIM_Reject, 14204 // Label 1202: @31052 14205 GIM_Reject, 14206 // Label 1193: @31053 14207 GIM_Try, /*On fail goto*//*Label 1205*/ 31079, // Rule ID 8515 // 14208 GIM_CheckFeatures, GIFBS_HasAVX512, 14209 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s32, 14210 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 14211 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 14212 // (fpextend:{ *:[v8f64] } VR256X:{ *:[v8f32] }:$src) => (VCVTPS2PDZrr:{ *:[v8f64] } VR256X:{ *:[v8f32] }:$src) 14213 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VCVTPS2PDZrr, 14214 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 14215 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14216 // GIR_Coverage, 8515, 14217 GIR_Done, 14218 // Label 1205: @31079 14219 GIM_Reject, 14220 // Label 1194: @31080 14221 GIM_Reject, 14222 // Label 27: @31081 14223 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/3, 5, /*)*//*default:*//*Label 1208*/ 31288, 14224 /*GILLT_s32*//*Label 1206*/ 31089, 14225 /*GILLT_s64*//*Label 1207*/ 31262, 14226 // Label 1206: @31089 14227 GIM_Try, /*On fail goto*//*Label 1209*/ 31115, // Rule ID 1423 // 14228 GIM_CheckFeatures, GIFBS_UseSSE2, 14229 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 14230 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::FR32RegClassID, 14231 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR64RegClassID, 14232 // (fpround:{ *:[f32] } FR64:{ *:[f64] }:$src) => (CVTSD2SSrr:{ *:[f32] } FR64:{ *:[f64] }:$src) 14233 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::CVTSD2SSrr, 14234 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 14235 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14236 // GIR_Coverage, 1423, 14237 GIR_Done, 14238 // Label 1209: @31115 14239 GIM_Try, /*On fail goto*//*Label 1210*/ 31140, // Rule ID 13126 // 14240 GIM_CheckFeatures, GIFBS_FPStackf32, 14241 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 14242 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::RFP32RegClassID, 14243 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::RFP64RegClassID, 14244 // (fpround:{ *:[f32] } RFP64:{ *:[f64] }:$src) => (COPY_TO_REGCLASS:{ *:[f32] } RFP64:{ *:[f64] }:$src, RFP32:{ *:[i32] }) 14245 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, 14246 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC RFP32*/39, 14247 // GIR_Coverage, 13126, 14248 GIR_Done, 14249 // Label 1210: @31140 14250 GIM_Try, /*On fail goto*//*Label 1211*/ 31165, // Rule ID 13128 // 14251 GIM_CheckFeatures, GIFBS_FPStackf32, 14252 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s80, 14253 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::RFP32RegClassID, 14254 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::RFP80RegClassID, 14255 // (fpround:{ *:[f32] } RFP80:{ *:[f80] }:$src) => (COPY_TO_REGCLASS:{ *:[f32] } RFP80:{ *:[f80] }:$src, RFP32:{ *:[i32] }) 14256 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, 14257 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC RFP32*/39, 14258 // GIR_Coverage, 13128, 14259 GIR_Done, 14260 // Label 1211: @31165 14261 GIM_Try, /*On fail goto*//*Label 1212*/ 31213, // Rule ID 13323 // 14262 GIM_CheckFeatures, GIFBS_UseAVX, 14263 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 14264 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::FR32RegClassID, 14265 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR64RegClassID, 14266 // (fpround:{ *:[f32] } FR64:{ *:[f64] }:$src) => (VCVTSD2SSrr:{ *:[f32] } (IMPLICIT_DEF:{ *:[f32] }), FR64:{ *:[f64] }:$src) 14267 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, 14268 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, 14269 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 14270 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 14271 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VCVTSD2SSrr, 14272 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 14273 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 14274 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 14275 GIR_EraseFromParent, /*InsnID*/0, 14276 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14277 // GIR_Coverage, 13323, 14278 GIR_Done, 14279 // Label 1212: @31213 14280 GIM_Try, /*On fail goto*//*Label 1213*/ 31261, // Rule ID 16122 // 14281 GIM_CheckFeatures, GIFBS_HasAVX512, 14282 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 14283 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::FR32XRegClassID, 14284 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR64XRegClassID, 14285 // (fpround:{ *:[f32] } FR64X:{ *:[f64] }:$src) => (VCVTSD2SSZrr:{ *:[f32] } (IMPLICIT_DEF:{ *:[f32] }), FR64X:{ *:[f64] }:$src) 14286 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, 14287 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, 14288 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 14289 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 14290 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VCVTSD2SSZrr, 14291 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 14292 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 14293 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 14294 GIR_EraseFromParent, /*InsnID*/0, 14295 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14296 // GIR_Coverage, 16122, 14297 GIR_Done, 14298 // Label 1213: @31261 14299 GIM_Reject, 14300 // Label 1207: @31262 14301 GIM_Try, /*On fail goto*//*Label 1214*/ 31287, // Rule ID 13130 // 14302 GIM_CheckFeatures, GIFBS_FPStackf64, 14303 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s80, 14304 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::RFP64RegClassID, 14305 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::RFP80RegClassID, 14306 // (fpround:{ *:[f64] } RFP80:{ *:[f80] }:$src) => (COPY_TO_REGCLASS:{ *:[f64] } RFP80:{ *:[f80] }:$src, RFP64:{ *:[i32] }) 14307 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY, 14308 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC RFP64*/63, 14309 // GIR_Coverage, 13130, 14310 GIR_Done, 14311 // Label 1214: @31287 14312 GIM_Reject, 14313 // Label 1208: @31288 14314 GIM_Reject, 14315 // Label 28: @31289 14316 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/3, 11, /*)*//*default:*//*Label 1218*/ 31644, 14317 /*GILLT_s32*//*Label 1215*/ 31303, 14318 /*GILLT_s64*//*Label 1216*/ 31460, 0, 0, 0, 0, 0, 14319 /*GILLT_v4s32*//*Label 1217*/ 31617, 14320 // Label 1215: @31303 14321 GIM_Try, /*On fail goto*//*Label 1219*/ 31329, // Rule ID 1331 // 14322 GIM_CheckFeatures, GIFBS_UseAVX, 14323 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 14324 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 14325 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR32RegClassID, 14326 // (fp_to_sint:{ *:[i32] } FR32:{ *:[f32] }:$src) => (VCVTTSS2SIrr:{ *:[i32] } FR32:{ *:[f32] }:$src) 14327 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VCVTTSS2SIrr, 14328 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 14329 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14330 // GIR_Coverage, 1331, 14331 GIR_Done, 14332 // Label 1219: @31329 14333 GIM_Try, /*On fail goto*//*Label 1220*/ 31355, // Rule ID 1339 // 14334 GIM_CheckFeatures, GIFBS_UseAVX, 14335 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 14336 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 14337 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR64RegClassID, 14338 // (fp_to_sint:{ *:[i32] } FR64:{ *:[f64] }:$src) => (VCVTTSD2SIrr:{ *:[i32] } FR64:{ *:[f64] }:$src) 14339 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VCVTTSD2SIrr, 14340 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 14341 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14342 // GIR_Coverage, 1339, 14343 GIR_Done, 14344 // Label 1220: @31355 14345 GIM_Try, /*On fail goto*//*Label 1221*/ 31381, // Rule ID 1347 // 14346 GIM_CheckFeatures, GIFBS_UseSSE1, 14347 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 14348 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 14349 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR32RegClassID, 14350 // (fp_to_sint:{ *:[i32] } FR32:{ *:[f32] }:$src) => (CVTTSS2SIrr:{ *:[i32] } FR32:{ *:[f32] }:$src) 14351 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::CVTTSS2SIrr, 14352 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 14353 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14354 // GIR_Coverage, 1347, 14355 GIR_Done, 14356 // Label 1221: @31381 14357 GIM_Try, /*On fail goto*//*Label 1222*/ 31407, // Rule ID 1355 // 14358 GIM_CheckFeatures, GIFBS_UseSSE2, 14359 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 14360 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 14361 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR64RegClassID, 14362 // (fp_to_sint:{ *:[i32] } FR64:{ *:[f64] }:$src) => (CVTTSD2SIrr:{ *:[i32] } FR64:{ *:[f64] }:$src) 14363 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::CVTTSD2SIrr, 14364 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 14365 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14366 // GIR_Coverage, 1355, 14367 GIR_Done, 14368 // Label 1222: @31407 14369 GIM_Try, /*On fail goto*//*Label 1223*/ 31433, // Rule ID 8402 // 14370 GIM_CheckFeatures, GIFBS_HasAVX512, 14371 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 14372 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 14373 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR32XRegClassID, 14374 // (fp_to_sint:{ *:[i32] } FR32X:{ *:[f32] }:$src) => (VCVTTSS2SIZrr:{ *:[i32] } FR32X:{ *:[f32] }:$src) 14375 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VCVTTSS2SIZrr, 14376 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 14377 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14378 // GIR_Coverage, 8402, 14379 GIR_Done, 14380 // Label 1223: @31433 14381 GIM_Try, /*On fail goto*//*Label 1224*/ 31459, // Rule ID 8416 // 14382 GIM_CheckFeatures, GIFBS_HasAVX512, 14383 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 14384 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 14385 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR64XRegClassID, 14386 // (fp_to_sint:{ *:[i32] } FR64X:{ *:[f64] }:$src) => (VCVTTSD2SIZrr:{ *:[i32] } FR64X:{ *:[f64] }:$src) 14387 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VCVTTSD2SIZrr, 14388 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 14389 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14390 // GIR_Coverage, 8416, 14391 GIR_Done, 14392 // Label 1224: @31459 14393 GIM_Reject, 14394 // Label 1216: @31460 14395 GIM_Try, /*On fail goto*//*Label 1225*/ 31486, // Rule ID 1335 // 14396 GIM_CheckFeatures, GIFBS_UseAVX, 14397 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 14398 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID, 14399 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR32RegClassID, 14400 // (fp_to_sint:{ *:[i64] } FR32:{ *:[f32] }:$src) => (VCVTTSS2SI64rr:{ *:[i64] } FR32:{ *:[f32] }:$src) 14401 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VCVTTSS2SI64rr, 14402 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 14403 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14404 // GIR_Coverage, 1335, 14405 GIR_Done, 14406 // Label 1225: @31486 14407 GIM_Try, /*On fail goto*//*Label 1226*/ 31512, // Rule ID 1343 // 14408 GIM_CheckFeatures, GIFBS_UseAVX, 14409 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 14410 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID, 14411 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR64RegClassID, 14412 // (fp_to_sint:{ *:[i64] } FR64:{ *:[f64] }:$src) => (VCVTTSD2SI64rr:{ *:[i64] } FR64:{ *:[f64] }:$src) 14413 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VCVTTSD2SI64rr, 14414 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 14415 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14416 // GIR_Coverage, 1343, 14417 GIR_Done, 14418 // Label 1226: @31512 14419 GIM_Try, /*On fail goto*//*Label 1227*/ 31538, // Rule ID 1351 // 14420 GIM_CheckFeatures, GIFBS_UseSSE1, 14421 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 14422 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID, 14423 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR32RegClassID, 14424 // (fp_to_sint:{ *:[i64] } FR32:{ *:[f32] }:$src) => (CVTTSS2SI64rr:{ *:[i64] } FR32:{ *:[f32] }:$src) 14425 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::CVTTSS2SI64rr, 14426 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 14427 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14428 // GIR_Coverage, 1351, 14429 GIR_Done, 14430 // Label 1227: @31538 14431 GIM_Try, /*On fail goto*//*Label 1228*/ 31564, // Rule ID 1359 // 14432 GIM_CheckFeatures, GIFBS_UseSSE2, 14433 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 14434 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID, 14435 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR64RegClassID, 14436 // (fp_to_sint:{ *:[i64] } FR64:{ *:[f64] }:$src) => (CVTTSD2SI64rr:{ *:[i64] } FR64:{ *:[f64] }:$src) 14437 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::CVTTSD2SI64rr, 14438 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 14439 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14440 // GIR_Coverage, 1359, 14441 GIR_Done, 14442 // Label 1228: @31564 14443 GIM_Try, /*On fail goto*//*Label 1229*/ 31590, // Rule ID 8409 // 14444 GIM_CheckFeatures, GIFBS_HasAVX512, 14445 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 14446 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID, 14447 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR32XRegClassID, 14448 // (fp_to_sint:{ *:[i64] } FR32X:{ *:[f32] }:$src) => (VCVTTSS2SI64Zrr:{ *:[i64] } FR32X:{ *:[f32] }:$src) 14449 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VCVTTSS2SI64Zrr, 14450 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 14451 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14452 // GIR_Coverage, 8409, 14453 GIR_Done, 14454 // Label 1229: @31590 14455 GIM_Try, /*On fail goto*//*Label 1230*/ 31616, // Rule ID 8423 // 14456 GIM_CheckFeatures, GIFBS_HasAVX512, 14457 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 14458 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID, 14459 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR64XRegClassID, 14460 // (fp_to_sint:{ *:[i64] } FR64X:{ *:[f64] }:$src) => (VCVTTSD2SI64Zrr:{ *:[i64] } FR64X:{ *:[f64] }:$src) 14461 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VCVTTSD2SI64Zrr, 14462 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 14463 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14464 // GIR_Coverage, 8423, 14465 GIR_Done, 14466 // Label 1230: @31616 14467 GIM_Reject, 14468 // Label 1217: @31617 14469 GIM_Try, /*On fail goto*//*Label 1231*/ 31643, // Rule ID 13369 // 14470 GIM_CheckFeatures, GIFBS_HasAVX_NoVLX, 14471 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s64, 14472 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 14473 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256RegClassID, 14474 // (fp_to_sint:{ *:[v4i32] } VR256:{ *:[v4f64] }:$src) => (VCVTTPD2DQYrr:{ *:[v4i32] } VR256:{ *:[v4f64] }:$src) 14475 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VCVTTPD2DQYrr, 14476 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 14477 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14478 // GIR_Coverage, 13369, 14479 GIR_Done, 14480 // Label 1231: @31643 14481 GIM_Reject, 14482 // Label 1218: @31644 14483 GIM_Reject, 14484 // Label 29: @31645 14485 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/3, 5, /*)*//*default:*//*Label 1234*/ 31759, 14486 /*GILLT_s32*//*Label 1232*/ 31653, 14487 /*GILLT_s64*//*Label 1233*/ 31706, 14488 // Label 1232: @31653 14489 GIM_Try, /*On fail goto*//*Label 1235*/ 31679, // Rule ID 8430 // 14490 GIM_CheckFeatures, GIFBS_HasAVX512, 14491 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 14492 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 14493 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR32XRegClassID, 14494 // (fp_to_uint:{ *:[i32] } FR32X:{ *:[f32] }:$src) => (VCVTTSS2USIZrr:{ *:[i32] } FR32X:{ *:[f32] }:$src) 14495 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VCVTTSS2USIZrr, 14496 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 14497 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14498 // GIR_Coverage, 8430, 14499 GIR_Done, 14500 // Label 1235: @31679 14501 GIM_Try, /*On fail goto*//*Label 1236*/ 31705, // Rule ID 8444 // 14502 GIM_CheckFeatures, GIFBS_HasAVX512, 14503 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 14504 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 14505 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR64XRegClassID, 14506 // (fp_to_uint:{ *:[i32] } FR64X:{ *:[f64] }:$src) => (VCVTTSD2USIZrr:{ *:[i32] } FR64X:{ *:[f64] }:$src) 14507 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VCVTTSD2USIZrr, 14508 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 14509 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14510 // GIR_Coverage, 8444, 14511 GIR_Done, 14512 // Label 1236: @31705 14513 GIM_Reject, 14514 // Label 1233: @31706 14515 GIM_Try, /*On fail goto*//*Label 1237*/ 31732, // Rule ID 8437 // 14516 GIM_CheckFeatures, GIFBS_HasAVX512, 14517 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 14518 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID, 14519 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR32XRegClassID, 14520 // (fp_to_uint:{ *:[i64] } FR32X:{ *:[f32] }:$src) => (VCVTTSS2USI64Zrr:{ *:[i64] } FR32X:{ *:[f32] }:$src) 14521 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VCVTTSS2USI64Zrr, 14522 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 14523 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14524 // GIR_Coverage, 8437, 14525 GIR_Done, 14526 // Label 1237: @31732 14527 GIM_Try, /*On fail goto*//*Label 1238*/ 31758, // Rule ID 8451 // 14528 GIM_CheckFeatures, GIFBS_HasAVX512, 14529 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 14530 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID, 14531 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR64XRegClassID, 14532 // (fp_to_uint:{ *:[i64] } FR64X:{ *:[f64] }:$src) => (VCVTTSD2USI64Zrr:{ *:[i64] } FR64X:{ *:[f64] }:$src) 14533 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VCVTTSD2USI64Zrr, 14534 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 14535 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14536 // GIR_Coverage, 8451, 14537 GIR_Done, 14538 // Label 1238: @31758 14539 GIM_Reject, 14540 // Label 1234: @31759 14541 GIM_Reject, 14542 // Label 30: @31760 14543 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/3, 20, /*)*//*default:*//*Label 1247*/ 32631, 14544 /*GILLT_s32*//*Label 1239*/ 31783, 14545 /*GILLT_s64*//*Label 1240*/ 32028, 0, 0, 0, 14546 /*GILLT_v2s64*//*Label 1241*/ 32270, 0, 14547 /*GILLT_v4s32*//*Label 1242*/ 32297, 14548 /*GILLT_v4s64*//*Label 1243*/ 32402, 0, 0, 14549 /*GILLT_v8s32*//*Label 1244*/ 32475, 14550 /*GILLT_v8s64*//*Label 1245*/ 32554, 0, 0, 0, 14551 /*GILLT_v16s32*//*Label 1246*/ 32604, 14552 // Label 1239: @31783 14553 GIM_Try, /*On fail goto*//*Label 1248*/ 31809, // Rule ID 1363 // 14554 GIM_CheckFeatures, GIFBS_UseSSE1, 14555 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 14556 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::FR32RegClassID, 14557 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR32RegClassID, 14558 // (sint_to_fp:{ *:[f32] } GR32:{ *:[i32] }:$src) => (CVTSI2SSrr:{ *:[f32] } GR32:{ *:[i32] }:$src) 14559 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::CVTSI2SSrr, 14560 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 14561 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14562 // GIR_Coverage, 1363, 14563 GIR_Done, 14564 // Label 1248: @31809 14565 GIM_Try, /*On fail goto*//*Label 1249*/ 31835, // Rule ID 1367 // 14566 GIM_CheckFeatures, GIFBS_UseSSE1, 14567 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 14568 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::FR32RegClassID, 14569 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR64RegClassID, 14570 // (sint_to_fp:{ *:[f32] } GR64:{ *:[i64] }:$src) => (CVTSI642SSrr:{ *:[f32] } GR64:{ *:[i64] }:$src) 14571 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::CVTSI642SSrr, 14572 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 14573 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14574 // GIR_Coverage, 1367, 14575 GIR_Done, 14576 // Label 1249: @31835 14577 GIM_Try, /*On fail goto*//*Label 1250*/ 31883, // Rule ID 13315 // 14578 GIM_CheckFeatures, GIFBS_UseAVX, 14579 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 14580 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::FR32RegClassID, 14581 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR32RegClassID, 14582 // (sint_to_fp:{ *:[f32] } GR32:{ *:[i32] }:$src) => (VCVTSI2SSrr:{ *:[f32] } (IMPLICIT_DEF:{ *:[f32] }), GR32:{ *:[i32] }:$src) 14583 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, 14584 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, 14585 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 14586 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 14587 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VCVTSI2SSrr, 14588 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 14589 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 14590 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 14591 GIR_EraseFromParent, /*InsnID*/0, 14592 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14593 // GIR_Coverage, 13315, 14594 GIR_Done, 14595 // Label 1250: @31883 14596 GIM_Try, /*On fail goto*//*Label 1251*/ 31931, // Rule ID 13317 // 14597 GIM_CheckFeatures, GIFBS_UseAVX, 14598 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 14599 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::FR32RegClassID, 14600 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR64RegClassID, 14601 // (sint_to_fp:{ *:[f32] } GR64:{ *:[i64] }:$src) => (VCVTSI642SSrr:{ *:[f32] } (IMPLICIT_DEF:{ *:[f32] }), GR64:{ *:[i64] }:$src) 14602 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, 14603 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, 14604 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 14605 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 14606 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VCVTSI642SSrr, 14607 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 14608 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 14609 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 14610 GIR_EraseFromParent, /*InsnID*/0, 14611 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14612 // GIR_Coverage, 13317, 14613 GIR_Done, 14614 // Label 1251: @31931 14615 GIM_Try, /*On fail goto*//*Label 1252*/ 31979, // Rule ID 16062 // 14616 GIM_CheckFeatures, GIFBS_HasAVX512, 14617 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 14618 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::FR32XRegClassID, 14619 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR32RegClassID, 14620 // (sint_to_fp:{ *:[f32] } GR32:{ *:[i32] }:$src) => (VCVTSI2SSZrr:{ *:[f32] } (IMPLICIT_DEF:{ *:[f32] }), GR32:{ *:[i32] }:$src) 14621 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, 14622 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, 14623 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 14624 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 14625 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VCVTSI2SSZrr, 14626 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 14627 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 14628 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 14629 GIR_EraseFromParent, /*InsnID*/0, 14630 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14631 // GIR_Coverage, 16062, 14632 GIR_Done, 14633 // Label 1252: @31979 14634 GIM_Try, /*On fail goto*//*Label 1253*/ 32027, // Rule ID 16064 // 14635 GIM_CheckFeatures, GIFBS_HasAVX512, 14636 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 14637 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::FR32XRegClassID, 14638 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR64RegClassID, 14639 // (sint_to_fp:{ *:[f32] } GR64:{ *:[i64] }:$src) => (VCVTSI642SSZrr:{ *:[f32] } (IMPLICIT_DEF:{ *:[f32] }), GR64:{ *:[i64] }:$src) 14640 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, 14641 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, 14642 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 14643 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 14644 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VCVTSI642SSZrr, 14645 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 14646 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 14647 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 14648 GIR_EraseFromParent, /*InsnID*/0, 14649 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14650 // GIR_Coverage, 16064, 14651 GIR_Done, 14652 // Label 1253: @32027 14653 GIM_Reject, 14654 // Label 1240: @32028 14655 GIM_Try, /*On fail goto*//*Label 1254*/ 32051, // Rule ID 1371 // 14656 GIM_CheckFeatures, GIFBS_UseSSE2, 14657 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 14658 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::FR64RegClassID, 14659 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR32RegClassID, 14660 // (sint_to_fp:{ *:[f64] } GR32:{ *:[i32] }:$src) => (CVTSI2SDrr:{ *:[f64] } GR32:{ *:[i32] }:$src) 14661 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::CVTSI2SDrr, 14662 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14663 // GIR_Coverage, 1371, 14664 GIR_Done, 14665 // Label 1254: @32051 14666 GIM_Try, /*On fail goto*//*Label 1255*/ 32077, // Rule ID 1375 // 14667 GIM_CheckFeatures, GIFBS_UseSSE2, 14668 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 14669 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::FR64RegClassID, 14670 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR64RegClassID, 14671 // (sint_to_fp:{ *:[f64] } GR64:{ *:[i64] }:$src) => (CVTSI642SDrr:{ *:[f64] } GR64:{ *:[i64] }:$src) 14672 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::CVTSI642SDrr, 14673 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 14674 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14675 // GIR_Coverage, 1375, 14676 GIR_Done, 14677 // Label 1255: @32077 14678 GIM_Try, /*On fail goto*//*Label 1256*/ 32125, // Rule ID 13319 // 14679 GIM_CheckFeatures, GIFBS_UseAVX, 14680 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 14681 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::FR64RegClassID, 14682 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR32RegClassID, 14683 // (sint_to_fp:{ *:[f64] } GR32:{ *:[i32] }:$src) => (VCVTSI2SDrr:{ *:[f64] } (IMPLICIT_DEF:{ *:[f64] }), GR32:{ *:[i32] }:$src) 14684 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, 14685 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, 14686 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 14687 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 14688 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VCVTSI2SDrr, 14689 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 14690 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 14691 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 14692 GIR_EraseFromParent, /*InsnID*/0, 14693 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14694 // GIR_Coverage, 13319, 14695 GIR_Done, 14696 // Label 1256: @32125 14697 GIM_Try, /*On fail goto*//*Label 1257*/ 32173, // Rule ID 13321 // 14698 GIM_CheckFeatures, GIFBS_UseAVX, 14699 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 14700 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::FR64RegClassID, 14701 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR64RegClassID, 14702 // (sint_to_fp:{ *:[f64] } GR64:{ *:[i64] }:$src) => (VCVTSI642SDrr:{ *:[f64] } (IMPLICIT_DEF:{ *:[f64] }), GR64:{ *:[i64] }:$src) 14703 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, 14704 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, 14705 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 14706 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 14707 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VCVTSI642SDrr, 14708 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 14709 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 14710 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 14711 GIR_EraseFromParent, /*InsnID*/0, 14712 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14713 // GIR_Coverage, 13321, 14714 GIR_Done, 14715 // Label 1257: @32173 14716 GIM_Try, /*On fail goto*//*Label 1258*/ 32221, // Rule ID 16066 // 14717 GIM_CheckFeatures, GIFBS_HasAVX512, 14718 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 14719 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::FR64XRegClassID, 14720 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR32RegClassID, 14721 // (sint_to_fp:{ *:[f64] } GR32:{ *:[i32] }:$src) => (VCVTSI2SDZrr:{ *:[f64] } (IMPLICIT_DEF:{ *:[f64] }), GR32:{ *:[i32] }:$src) 14722 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, 14723 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, 14724 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 14725 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 14726 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VCVTSI2SDZrr, 14727 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 14728 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 14729 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 14730 GIR_EraseFromParent, /*InsnID*/0, 14731 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14732 // GIR_Coverage, 16066, 14733 GIR_Done, 14734 // Label 1258: @32221 14735 GIM_Try, /*On fail goto*//*Label 1259*/ 32269, // Rule ID 16068 // 14736 GIM_CheckFeatures, GIFBS_HasAVX512, 14737 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 14738 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::FR64XRegClassID, 14739 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR64RegClassID, 14740 // (sint_to_fp:{ *:[f64] } GR64:{ *:[i64] }:$src) => (VCVTSI642SDZrr:{ *:[f64] } (IMPLICIT_DEF:{ *:[f64] }), GR64:{ *:[i64] }:$src) 14741 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, 14742 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, 14743 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 14744 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 14745 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VCVTSI642SDZrr, 14746 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 14747 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 14748 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 14749 GIR_EraseFromParent, /*InsnID*/0, 14750 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14751 // GIR_Coverage, 16068, 14752 GIR_Done, 14753 // Label 1259: @32269 14754 GIM_Reject, 14755 // Label 1241: @32270 14756 GIM_Try, /*On fail goto*//*Label 1260*/ 32296, // Rule ID 9448 // 14757 GIM_CheckFeatures, GIFBS_HasDQI_HasVLX, 14758 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, 14759 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 14760 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 14761 // (sint_to_fp:{ *:[v2f64] } VR128X:{ *:[v2i64] }:$src) => (VCVTQQ2PDZ128rr:{ *:[v2f64] } VR128X:{ *:[v2i64] }:$src) 14762 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VCVTQQ2PDZ128rr, 14763 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 14764 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14765 // GIR_Coverage, 9448, 14766 GIR_Done, 14767 // Label 1260: @32296 14768 GIM_Reject, 14769 // Label 1242: @32297 14770 GIM_Try, /*On fail goto*//*Label 1261*/ 32323, // Rule ID 1411 // 14771 GIM_CheckFeatures, GIFBS_HasAVX_NoVLX, 14772 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 14773 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 14774 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 14775 // (sint_to_fp:{ *:[v4f32] } VR128:{ *:[v4i32] }:$src) => (VCVTDQ2PSrr:{ *:[v4f32] } VR128:{ *:[v4i32] }:$src) 14776 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VCVTDQ2PSrr, 14777 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 14778 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14779 // GIR_Coverage, 1411, 14780 GIR_Done, 14781 // Label 1261: @32323 14782 GIM_Try, /*On fail goto*//*Label 1262*/ 32349, // Rule ID 1419 // 14783 GIM_CheckFeatures, GIFBS_UseSSE2, 14784 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 14785 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 14786 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 14787 // (sint_to_fp:{ *:[v4f32] } VR128:{ *:[v4i32] }:$src) => (CVTDQ2PSrr:{ *:[v4f32] } VR128:{ *:[v4i32] }:$src) 14788 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::CVTDQ2PSrr, 14789 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 14790 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14791 // GIR_Coverage, 1419, 14792 GIR_Done, 14793 // Label 1262: @32349 14794 GIM_Try, /*On fail goto*//*Label 1263*/ 32375, // Rule ID 8638 // 14795 GIM_CheckFeatures, GIFBS_HasVLX, 14796 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 14797 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 14798 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 14799 // (sint_to_fp:{ *:[v4f32] } VR128X:{ *:[v4i32] }:$src) => (VCVTDQ2PSZ128rr:{ *:[v4f32] } VR128X:{ *:[v4i32] }:$src) 14800 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VCVTDQ2PSZ128rr, 14801 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 14802 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14803 // GIR_Coverage, 8638, 14804 GIR_Done, 14805 // Label 1263: @32375 14806 GIM_Try, /*On fail goto*//*Label 1264*/ 32401, // Rule ID 9562 // 14807 GIM_CheckFeatures, GIFBS_HasDQI_HasVLX, 14808 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s64, 14809 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 14810 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 14811 // (sint_to_fp:{ *:[v4f32] } VR256X:{ *:[v4i64] }:$src) => (VCVTQQ2PSZ256rr:{ *:[v4f32] } VR256X:{ *:[v4i64] }:$src) 14812 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VCVTQQ2PSZ256rr, 14813 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 14814 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14815 // GIR_Coverage, 9562, 14816 GIR_Done, 14817 // Label 1264: @32401 14818 GIM_Reject, 14819 // Label 1243: @32402 14820 GIM_Try, /*On fail goto*//*Label 1265*/ 32425, // Rule ID 1486 // 14821 GIM_CheckFeatures, GIFBS_HasAVX_NoVLX, 14822 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 14823 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID, 14824 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 14825 // (sint_to_fp:{ *:[v4f64] } VR128:{ *:[v4i32] }:$src) => (VCVTDQ2PDYrr:{ *:[v4f64] } VR128:{ *:[v4i32] }:$src) 14826 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VCVTDQ2PDYrr, 14827 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14828 // GIR_Coverage, 1486, 14829 GIR_Done, 14830 // Label 1265: @32425 14831 GIM_Try, /*On fail goto*//*Label 1266*/ 32448, // Rule ID 8599 // 14832 GIM_CheckFeatures, GIFBS_HasVLX, 14833 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 14834 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 14835 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 14836 // (sint_to_fp:{ *:[v4f64] } VR128X:{ *:[v4i32] }:$src) => (VCVTDQ2PDZ256rr:{ *:[v4f64] } VR128X:{ *:[v4i32] }:$src) 14837 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VCVTDQ2PDZ256rr, 14838 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14839 // GIR_Coverage, 8599, 14840 GIR_Done, 14841 // Label 1266: @32448 14842 GIM_Try, /*On fail goto*//*Label 1267*/ 32474, // Rule ID 9466 // 14843 GIM_CheckFeatures, GIFBS_HasDQI_HasVLX, 14844 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s64, 14845 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 14846 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 14847 // (sint_to_fp:{ *:[v4f64] } VR256X:{ *:[v4i64] }:$src) => (VCVTQQ2PDZ256rr:{ *:[v4f64] } VR256X:{ *:[v4i64] }:$src) 14848 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VCVTQQ2PDZ256rr, 14849 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 14850 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14851 // GIR_Coverage, 9466, 14852 GIR_Done, 14853 // Label 1267: @32474 14854 GIM_Reject, 14855 // Label 1244: @32475 14856 GIM_Try, /*On fail goto*//*Label 1268*/ 32501, // Rule ID 1415 // 14857 GIM_CheckFeatures, GIFBS_HasAVX_NoVLX, 14858 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s32, 14859 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID, 14860 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256RegClassID, 14861 // (sint_to_fp:{ *:[v8f32] } VR256:{ *:[v8i32] }:$src) => (VCVTDQ2PSYrr:{ *:[v8f32] } VR256:{ *:[v8i32] }:$src) 14862 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VCVTDQ2PSYrr, 14863 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 14864 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14865 // GIR_Coverage, 1415, 14866 GIR_Done, 14867 // Label 1268: @32501 14868 GIM_Try, /*On fail goto*//*Label 1269*/ 32527, // Rule ID 8656 // 14869 GIM_CheckFeatures, GIFBS_HasVLX, 14870 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s32, 14871 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 14872 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 14873 // (sint_to_fp:{ *:[v8f32] } VR256X:{ *:[v8i32] }:$src) => (VCVTDQ2PSZ256rr:{ *:[v8f32] } VR256X:{ *:[v8i32] }:$src) 14874 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VCVTDQ2PSZ256rr, 14875 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 14876 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14877 // GIR_Coverage, 8656, 14878 GIR_Done, 14879 // Label 1269: @32527 14880 GIM_Try, /*On fail goto*//*Label 1270*/ 32553, // Rule ID 9541 // 14881 GIM_CheckFeatures, GIFBS_HasDQI, 14882 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s64, 14883 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 14884 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID, 14885 // (sint_to_fp:{ *:[v8f32] } VR512:{ *:[v8i64] }:$src) => (VCVTQQ2PSZrr:{ *:[v8f32] } VR512:{ *:[v8i64] }:$src) 14886 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VCVTQQ2PSZrr, 14887 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 14888 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14889 // GIR_Coverage, 9541, 14890 GIR_Done, 14891 // Label 1270: @32553 14892 GIM_Reject, 14893 // Label 1245: @32554 14894 GIM_Try, /*On fail goto*//*Label 1271*/ 32577, // Rule ID 8563 // 14895 GIM_CheckFeatures, GIFBS_HasAVX512, 14896 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s32, 14897 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 14898 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 14899 // (sint_to_fp:{ *:[v8f64] } VR256X:{ *:[v8i32] }:$src) => (VCVTDQ2PDZrr:{ *:[v8f64] } VR256X:{ *:[v8i32] }:$src) 14900 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VCVTDQ2PDZrr, 14901 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14902 // GIR_Coverage, 8563, 14903 GIR_Done, 14904 // Label 1271: @32577 14905 GIM_Try, /*On fail goto*//*Label 1272*/ 32603, // Rule ID 9427 // 14906 GIM_CheckFeatures, GIFBS_HasDQI, 14907 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s64, 14908 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 14909 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID, 14910 // (sint_to_fp:{ *:[v8f64] } VR512:{ *:[v8i64] }:$src) => (VCVTQQ2PDZrr:{ *:[v8f64] } VR512:{ *:[v8i64] }:$src) 14911 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VCVTQQ2PDZrr, 14912 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 14913 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14914 // GIR_Coverage, 9427, 14915 GIR_Done, 14916 // Label 1272: @32603 14917 GIM_Reject, 14918 // Label 1246: @32604 14919 GIM_Try, /*On fail goto*//*Label 1273*/ 32630, // Rule ID 8617 // 14920 GIM_CheckFeatures, GIFBS_HasAVX512, 14921 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s32, 14922 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 14923 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID, 14924 // (sint_to_fp:{ *:[v16f32] } VR512:{ *:[v16i32] }:$src) => (VCVTDQ2PSZrr:{ *:[v16f32] } VR512:{ *:[v16i32] }:$src) 14925 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VCVTDQ2PSZrr, 14926 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 14927 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14928 // GIR_Coverage, 8617, 14929 GIR_Done, 14930 // Label 1273: @32630 14931 GIM_Reject, 14932 // Label 1247: @32631 14933 GIM_Reject, 14934 // Label 31: @32632 14935 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/3, 20, /*)*//*default:*//*Label 1282*/ 33109, 14936 /*GILLT_s32*//*Label 1274*/ 32655, 14937 /*GILLT_s64*//*Label 1275*/ 32752, 0, 0, 0, 14938 /*GILLT_v2s64*//*Label 1276*/ 32849, 0, 14939 /*GILLT_v4s32*//*Label 1277*/ 32876, 14940 /*GILLT_v4s64*//*Label 1278*/ 32929, 0, 0, 14941 /*GILLT_v8s32*//*Label 1279*/ 32979, 14942 /*GILLT_v8s64*//*Label 1280*/ 33032, 0, 0, 0, 14943 /*GILLT_v16s32*//*Label 1281*/ 33082, 14944 // Label 1274: @32655 14945 GIM_Try, /*On fail goto*//*Label 1283*/ 32703, // Rule ID 16078 // 14946 GIM_CheckFeatures, GIFBS_HasAVX512, 14947 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 14948 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::FR32XRegClassID, 14949 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR32RegClassID, 14950 // (uint_to_fp:{ *:[f32] } GR32:{ *:[i32] }:$src) => (VCVTUSI2SSZrr:{ *:[f32] } (IMPLICIT_DEF:{ *:[f32] }), GR32:{ *:[i32] }:$src) 14951 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, 14952 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, 14953 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 14954 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 14955 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VCVTUSI2SSZrr, 14956 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 14957 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 14958 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 14959 GIR_EraseFromParent, /*InsnID*/0, 14960 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14961 // GIR_Coverage, 16078, 14962 GIR_Done, 14963 // Label 1283: @32703 14964 GIM_Try, /*On fail goto*//*Label 1284*/ 32751, // Rule ID 16080 // 14965 GIM_CheckFeatures, GIFBS_HasAVX512, 14966 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 14967 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::FR32XRegClassID, 14968 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR64RegClassID, 14969 // (uint_to_fp:{ *:[f32] } GR64:{ *:[i64] }:$src) => (VCVTUSI642SSZrr:{ *:[f32] } (IMPLICIT_DEF:{ *:[f32] }), GR64:{ *:[i64] }:$src) 14970 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, 14971 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, 14972 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 14973 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 14974 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VCVTUSI642SSZrr, 14975 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 14976 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 14977 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 14978 GIR_EraseFromParent, /*InsnID*/0, 14979 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 14980 // GIR_Coverage, 16080, 14981 GIR_Done, 14982 // Label 1284: @32751 14983 GIM_Reject, 14984 // Label 1275: @32752 14985 GIM_Try, /*On fail goto*//*Label 1285*/ 32800, // Rule ID 16082 // 14986 GIM_CheckFeatures, GIFBS_HasAVX512, 14987 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 14988 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::FR64XRegClassID, 14989 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR32RegClassID, 14990 // (uint_to_fp:{ *:[f64] } GR32:{ *:[i32] }:$src) => (VCVTUSI2SDZrr:{ *:[f64] } (IMPLICIT_DEF:{ *:[f64] }), GR32:{ *:[i32] }:$src) 14991 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, 14992 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, 14993 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 14994 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 14995 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VCVTUSI2SDZrr, 14996 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 14997 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 14998 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 14999 GIR_EraseFromParent, /*InsnID*/0, 15000 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15001 // GIR_Coverage, 16082, 15002 GIR_Done, 15003 // Label 1285: @32800 15004 GIM_Try, /*On fail goto*//*Label 1286*/ 32848, // Rule ID 16084 // 15005 GIM_CheckFeatures, GIFBS_HasAVX512, 15006 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 15007 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::FR64XRegClassID, 15008 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR64RegClassID, 15009 // (uint_to_fp:{ *:[f64] } GR64:{ *:[i64] }:$src) => (VCVTUSI642SDZrr:{ *:[f64] } (IMPLICIT_DEF:{ *:[f64] }), GR64:{ *:[i64] }:$src) 15010 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, 15011 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, 15012 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 15013 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 15014 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VCVTUSI642SDZrr, 15015 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 15016 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 15017 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 15018 GIR_EraseFromParent, /*InsnID*/0, 15019 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15020 // GIR_Coverage, 16084, 15021 GIR_Done, 15022 // Label 1286: @32848 15023 GIM_Reject, 15024 // Label 1276: @32849 15025 GIM_Try, /*On fail goto*//*Label 1287*/ 32875, // Rule ID 9505 // 15026 GIM_CheckFeatures, GIFBS_HasDQI_HasVLX, 15027 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, 15028 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 15029 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 15030 // (uint_to_fp:{ *:[v2f64] } VR128X:{ *:[v2i64] }:$src) => (VCVTUQQ2PDZ128rr:{ *:[v2f64] } VR128X:{ *:[v2i64] }:$src) 15031 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VCVTUQQ2PDZ128rr, 15032 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 15033 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15034 // GIR_Coverage, 9505, 15035 GIR_Done, 15036 // Label 1287: @32875 15037 GIM_Reject, 15038 // Label 1277: @32876 15039 GIM_Try, /*On fail goto*//*Label 1288*/ 32902, // Rule ID 8941 // 15040 GIM_CheckFeatures, GIFBS_HasVLX, 15041 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 15042 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 15043 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 15044 // (uint_to_fp:{ *:[v4f32] } VR128X:{ *:[v4i32] }:$src) => (VCVTUDQ2PSZ128rr:{ *:[v4f32] } VR128X:{ *:[v4i32] }:$src) 15045 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VCVTUDQ2PSZ128rr, 15046 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 15047 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15048 // GIR_Coverage, 8941, 15049 GIR_Done, 15050 // Label 1288: @32902 15051 GIM_Try, /*On fail goto*//*Label 1289*/ 32928, // Rule ID 9601 // 15052 GIM_CheckFeatures, GIFBS_HasDQI_HasVLX, 15053 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s64, 15054 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 15055 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 15056 // (uint_to_fp:{ *:[v4f32] } VR256X:{ *:[v4i64] }:$src) => (VCVTUQQ2PSZ256rr:{ *:[v4f32] } VR256X:{ *:[v4i64] }:$src) 15057 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VCVTUQQ2PSZ256rr, 15058 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 15059 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15060 // GIR_Coverage, 9601, 15061 GIR_Done, 15062 // Label 1289: @32928 15063 GIM_Reject, 15064 // Label 1278: @32929 15065 GIM_Try, /*On fail goto*//*Label 1290*/ 32952, // Rule ID 8902 // 15066 GIM_CheckFeatures, GIFBS_HasVLX, 15067 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 15068 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 15069 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 15070 // (uint_to_fp:{ *:[v4f64] } VR128X:{ *:[v4i32] }:$src) => (VCVTUDQ2PDZ256rr:{ *:[v4f64] } VR128X:{ *:[v4i32] }:$src) 15071 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VCVTUDQ2PDZ256rr, 15072 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15073 // GIR_Coverage, 8902, 15074 GIR_Done, 15075 // Label 1290: @32952 15076 GIM_Try, /*On fail goto*//*Label 1291*/ 32978, // Rule ID 9523 // 15077 GIM_CheckFeatures, GIFBS_HasDQI_HasVLX, 15078 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s64, 15079 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 15080 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 15081 // (uint_to_fp:{ *:[v4f64] } VR256X:{ *:[v4i64] }:$src) => (VCVTUQQ2PDZ256rr:{ *:[v4f64] } VR256X:{ *:[v4i64] }:$src) 15082 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VCVTUQQ2PDZ256rr, 15083 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 15084 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15085 // GIR_Coverage, 9523, 15086 GIR_Done, 15087 // Label 1291: @32978 15088 GIM_Reject, 15089 // Label 1279: @32979 15090 GIM_Try, /*On fail goto*//*Label 1292*/ 33005, // Rule ID 8959 // 15091 GIM_CheckFeatures, GIFBS_HasVLX, 15092 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s32, 15093 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 15094 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 15095 // (uint_to_fp:{ *:[v8f32] } VR256X:{ *:[v8i32] }:$src) => (VCVTUDQ2PSZ256rr:{ *:[v8f32] } VR256X:{ *:[v8i32] }:$src) 15096 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VCVTUDQ2PSZ256rr, 15097 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 15098 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15099 // GIR_Coverage, 8959, 15100 GIR_Done, 15101 // Label 1292: @33005 15102 GIM_Try, /*On fail goto*//*Label 1293*/ 33031, // Rule ID 9580 // 15103 GIM_CheckFeatures, GIFBS_HasDQI, 15104 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s64, 15105 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 15106 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID, 15107 // (uint_to_fp:{ *:[v8f32] } VR512:{ *:[v8i64] }:$src) => (VCVTUQQ2PSZrr:{ *:[v8f32] } VR512:{ *:[v8i64] }:$src) 15108 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VCVTUQQ2PSZrr, 15109 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 15110 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15111 // GIR_Coverage, 9580, 15112 GIR_Done, 15113 // Label 1293: @33031 15114 GIM_Reject, 15115 // Label 1280: @33032 15116 GIM_Try, /*On fail goto*//*Label 1294*/ 33055, // Rule ID 8866 // 15117 GIM_CheckFeatures, GIFBS_HasAVX512, 15118 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s32, 15119 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 15120 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 15121 // (uint_to_fp:{ *:[v8f64] } VR256X:{ *:[v8i32] }:$src) => (VCVTUDQ2PDZrr:{ *:[v8f64] } VR256X:{ *:[v8i32] }:$src) 15122 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VCVTUDQ2PDZrr, 15123 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15124 // GIR_Coverage, 8866, 15125 GIR_Done, 15126 // Label 1294: @33055 15127 GIM_Try, /*On fail goto*//*Label 1295*/ 33081, // Rule ID 9484 // 15128 GIM_CheckFeatures, GIFBS_HasDQI, 15129 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s64, 15130 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 15131 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID, 15132 // (uint_to_fp:{ *:[v8f64] } VR512:{ *:[v8i64] }:$src) => (VCVTUQQ2PDZrr:{ *:[v8f64] } VR512:{ *:[v8i64] }:$src) 15133 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VCVTUQQ2PDZrr, 15134 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 15135 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15136 // GIR_Coverage, 9484, 15137 GIR_Done, 15138 // Label 1295: @33081 15139 GIM_Reject, 15140 // Label 1281: @33082 15141 GIM_Try, /*On fail goto*//*Label 1296*/ 33108, // Rule ID 8920 // 15142 GIM_CheckFeatures, GIFBS_HasAVX512, 15143 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s32, 15144 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 15145 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID, 15146 // (uint_to_fp:{ *:[v16f32] } VR512:{ *:[v16i32] }:$src) => (VCVTUDQ2PSZrr:{ *:[v16f32] } VR512:{ *:[v16i32] }:$src) 15147 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VCVTUDQ2PSZrr, 15148 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 15149 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15150 // GIR_Coverage, 8920, 15151 GIR_Done, 15152 // Label 1296: @33108 15153 GIM_Reject, 15154 // Label 1282: @33109 15155 GIM_Reject, 15156 // Label 32: @33110 15157 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/3, 6, /*)*//*default:*//*Label 1300*/ 33198, 15158 /*GILLT_s32*//*Label 1297*/ 33119, 15159 /*GILLT_s64*//*Label 1298*/ 33146, 15160 /*GILLT_s80*//*Label 1299*/ 33173, 15161 // Label 1297: @33119 15162 GIM_Try, /*On fail goto*//*Label 1301*/ 33145, // Rule ID 764 // 15163 GIM_CheckFeatures, GIFBS_FPStackf32, 15164 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 15165 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::RFP32RegClassID, 15166 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::RFP32RegClassID, 15167 // (fabs:{ *:[f32] } RFP32:{ *:[f32] }:$src) => (ABS_Fp32:{ *:[f32] }:{ *:[i16] } RFP32:{ *:[f32] }:$src) 15168 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::ABS_Fp32, 15169 GIR_AddImplicitDef, /*InsnID*/0, X86::FPSW, 15170 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15171 // GIR_Coverage, 764, 15172 GIR_Done, 15173 // Label 1301: @33145 15174 GIM_Reject, 15175 // Label 1298: @33146 15176 GIM_Try, /*On fail goto*//*Label 1302*/ 33172, // Rule ID 765 // 15177 GIM_CheckFeatures, GIFBS_FPStackf64, 15178 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 15179 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::RFP64RegClassID, 15180 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::RFP64RegClassID, 15181 // (fabs:{ *:[f64] } RFP64:{ *:[f64] }:$src) => (ABS_Fp64:{ *:[f64] }:{ *:[i16] } RFP64:{ *:[f64] }:$src) 15182 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::ABS_Fp64, 15183 GIR_AddImplicitDef, /*InsnID*/0, X86::FPSW, 15184 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15185 // GIR_Coverage, 765, 15186 GIR_Done, 15187 // Label 1302: @33172 15188 GIM_Reject, 15189 // Label 1299: @33173 15190 GIM_Try, /*On fail goto*//*Label 1303*/ 33197, // Rule ID 766 // 15191 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s80, 15192 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::RFP80RegClassID, 15193 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::RFP80RegClassID, 15194 // (fabs:{ *:[f80] } RFP80:{ *:[f80] }:$src) => (ABS_Fp80:{ *:[f80] }:{ *:[i16] } RFP80:{ *:[f80] }:$src) 15195 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::ABS_Fp80, 15196 GIR_AddImplicitDef, /*InsnID*/0, X86::FPSW, 15197 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15198 // GIR_Coverage, 766, 15199 GIR_Done, 15200 // Label 1303: @33197 15201 GIM_Reject, 15202 // Label 1300: @33198 15203 GIM_Reject, 15204 // Label 33: @33199 15205 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/8, 25, /*)*//*default:*//*Label 1316*/ 33831, 15206 /*GILLT_v2s64*//*Label 1304*/ 33222, 0, 15207 /*GILLT_v4s32*//*Label 1305*/ 33254, 15208 /*GILLT_v4s64*//*Label 1306*/ 33335, 0, 15209 /*GILLT_v8s16*//*Label 1307*/ 33367, 15210 /*GILLT_v8s32*//*Label 1308*/ 33448, 15211 /*GILLT_v8s64*//*Label 1309*/ 33506, 0, 15212 /*GILLT_v16s8*//*Label 1310*/ 33538, 15213 /*GILLT_v16s16*//*Label 1311*/ 33619, 15214 /*GILLT_v16s32*//*Label 1312*/ 33677, 0, 15215 /*GILLT_v32s8*//*Label 1313*/ 33709, 15216 /*GILLT_v32s16*//*Label 1314*/ 33767, 0, 15217 /*GILLT_v64s8*//*Label 1315*/ 33799, 15218 // Label 1304: @33222 15219 GIM_Try, /*On fail goto*//*Label 1317*/ 33253, // Rule ID 4849 // 15220 GIM_CheckFeatures, GIFBS_HasAVX512_HasVLX, 15221 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, 15222 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 15223 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 15224 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 15225 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128XRegClassID, 15226 // (smin:{ *:[v2i64] } VR128X:{ *:[v2i64] }:$src1, VR128X:{ *:[v2i64] }:$src2) => (VPMINSQZ128rr:{ *:[v2i64] } VR128X:{ *:[v2i64] }:$src1, VR128X:{ *:[v2i64] }:$src2) 15227 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMINSQZ128rr, 15228 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15229 // GIR_Coverage, 4849, 15230 GIR_Done, 15231 // Label 1317: @33253 15232 GIM_Reject, 15233 // Label 1305: @33254 15234 GIM_Try, /*On fail goto*//*Label 1318*/ 33334, 15235 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 15236 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 15237 GIM_Try, /*On fail goto*//*Label 1319*/ 33287, // Rule ID 2636 // 15238 GIM_CheckFeatures, GIFBS_HasAVX_NoVLX, 15239 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 15240 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 15241 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 15242 // (smin:{ *:[v4i32] } VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2) => (VPMINSDrr:{ *:[v4i32] } VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2) 15243 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMINSDrr, 15244 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15245 // GIR_Coverage, 2636, 15246 GIR_Done, 15247 // Label 1319: @33287 15248 GIM_Try, /*On fail goto*//*Label 1320*/ 33310, // Rule ID 2674 // 15249 GIM_CheckFeatures, GIFBS_UseSSE41, 15250 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 15251 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 15252 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 15253 // (smin:{ *:[v4i32] } VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2) => (PMINSDrr:{ *:[v4i32] } VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2) 15254 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::PMINSDrr, 15255 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15256 // GIR_Coverage, 2674, 15257 GIR_Done, 15258 // Label 1320: @33310 15259 GIM_Try, /*On fail goto*//*Label 1321*/ 33333, // Rule ID 4822 // 15260 GIM_CheckFeatures, GIFBS_HasAVX512_HasVLX, 15261 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 15262 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 15263 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128XRegClassID, 15264 // (smin:{ *:[v4i32] } VR128X:{ *:[v4i32] }:$src1, VR128X:{ *:[v4i32] }:$src2) => (VPMINSDZ128rr:{ *:[v4i32] } VR128X:{ *:[v4i32] }:$src1, VR128X:{ *:[v4i32] }:$src2) 15265 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMINSDZ128rr, 15266 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15267 // GIR_Coverage, 4822, 15268 GIR_Done, 15269 // Label 1321: @33333 15270 GIM_Reject, 15271 // Label 1318: @33334 15272 GIM_Reject, 15273 // Label 1306: @33335 15274 GIM_Try, /*On fail goto*//*Label 1322*/ 33366, // Rule ID 4840 // 15275 GIM_CheckFeatures, GIFBS_HasAVX512_HasVLX, 15276 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s64, 15277 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s64, 15278 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 15279 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 15280 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256XRegClassID, 15281 // (smin:{ *:[v4i64] } VR256X:{ *:[v4i64] }:$src1, VR256X:{ *:[v4i64] }:$src2) => (VPMINSQZ256rr:{ *:[v4i64] } VR256X:{ *:[v4i64] }:$src1, VR256X:{ *:[v4i64] }:$src2) 15282 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMINSQZ256rr, 15283 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15284 // GIR_Coverage, 4840, 15285 GIR_Done, 15286 // Label 1322: @33366 15287 GIM_Reject, 15288 // Label 1307: @33367 15289 GIM_Try, /*On fail goto*//*Label 1323*/ 33447, 15290 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, 15291 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 15292 GIM_Try, /*On fail goto*//*Label 1324*/ 33400, // Rule ID 2101 // 15293 GIM_CheckFeatures, GIFBS_HasAVX_NoVLX_Or_NoBWI, 15294 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 15295 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 15296 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 15297 // (smin:{ *:[v8i16] } VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2) => (VPMINSWrr:{ *:[v8i16] } VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2) 15298 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMINSWrr, 15299 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15300 // GIR_Coverage, 2101, 15301 GIR_Done, 15302 // Label 1324: @33400 15303 GIM_Try, /*On fail goto*//*Label 1325*/ 33423, // Rule ID 2103 // 15304 GIM_CheckFeatures, GIFBS_UseSSE2, 15305 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 15306 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 15307 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 15308 // (smin:{ *:[v8i16] } VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2) => (PMINSWrr:{ *:[v8i16] } VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2) 15309 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::PMINSWrr, 15310 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15311 // GIR_Coverage, 2103, 15312 GIR_Done, 15313 // Label 1325: @33423 15314 GIM_Try, /*On fail goto*//*Label 1326*/ 33446, // Rule ID 4798 // 15315 GIM_CheckFeatures, GIFBS_HasBWI_HasVLX, 15316 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 15317 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 15318 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128XRegClassID, 15319 // (smin:{ *:[v8i16] } VR128X:{ *:[v8i16] }:$src1, VR128X:{ *:[v8i16] }:$src2) => (VPMINSWZ128rr:{ *:[v8i16] } VR128X:{ *:[v8i16] }:$src1, VR128X:{ *:[v8i16] }:$src2) 15320 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMINSWZ128rr, 15321 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15322 // GIR_Coverage, 4798, 15323 GIR_Done, 15324 // Label 1326: @33446 15325 GIM_Reject, 15326 // Label 1323: @33447 15327 GIM_Reject, 15328 // Label 1308: @33448 15329 GIM_Try, /*On fail goto*//*Label 1327*/ 33505, 15330 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s32, 15331 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s32, 15332 GIM_Try, /*On fail goto*//*Label 1328*/ 33481, // Rule ID 2654 // 15333 GIM_CheckFeatures, GIFBS_HasAVX2_NoVLX, 15334 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID, 15335 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256RegClassID, 15336 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID, 15337 // (smin:{ *:[v8i32] } VR256:{ *:[v8i32] }:$src1, VR256:{ *:[v8i32] }:$src2) => (VPMINSDYrr:{ *:[v8i32] } VR256:{ *:[v8i32] }:$src1, VR256:{ *:[v8i32] }:$src2) 15338 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMINSDYrr, 15339 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15340 // GIR_Coverage, 2654, 15341 GIR_Done, 15342 // Label 1328: @33481 15343 GIM_Try, /*On fail goto*//*Label 1329*/ 33504, // Rule ID 4813 // 15344 GIM_CheckFeatures, GIFBS_HasAVX512_HasVLX, 15345 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 15346 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 15347 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256XRegClassID, 15348 // (smin:{ *:[v8i32] } VR256X:{ *:[v8i32] }:$src1, VR256X:{ *:[v8i32] }:$src2) => (VPMINSDZ256rr:{ *:[v8i32] } VR256X:{ *:[v8i32] }:$src1, VR256X:{ *:[v8i32] }:$src2) 15349 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMINSDZ256rr, 15350 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15351 // GIR_Coverage, 4813, 15352 GIR_Done, 15353 // Label 1329: @33504 15354 GIM_Reject, 15355 // Label 1327: @33505 15356 GIM_Reject, 15357 // Label 1309: @33506 15358 GIM_Try, /*On fail goto*//*Label 1330*/ 33537, // Rule ID 4831 // 15359 GIM_CheckFeatures, GIFBS_HasAVX512, 15360 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s64, 15361 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s64, 15362 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 15363 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID, 15364 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR512RegClassID, 15365 // (smin:{ *:[v8i64] } VR512:{ *:[v8i64] }:$src1, VR512:{ *:[v8i64] }:$src2) => (VPMINSQZrr:{ *:[v8i64] } VR512:{ *:[v8i64] }:$src1, VR512:{ *:[v8i64] }:$src2) 15366 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMINSQZrr, 15367 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15368 // GIR_Coverage, 4831, 15369 GIR_Done, 15370 // Label 1330: @33537 15371 GIM_Reject, 15372 // Label 1310: @33538 15373 GIM_Try, /*On fail goto*//*Label 1331*/ 33618, 15374 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, 15375 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 15376 GIM_Try, /*On fail goto*//*Label 1332*/ 33571, // Rule ID 2646 // 15377 GIM_CheckFeatures, GIFBS_HasAVX_NoVLX_Or_NoBWI, 15378 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 15379 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 15380 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 15381 // (smin:{ *:[v16i8] } VR128:{ *:[v16i8] }:$src1, VR128:{ *:[v16i8] }:$src2) => (VPMINSBrr:{ *:[v16i8] } VR128:{ *:[v16i8] }:$src1, VR128:{ *:[v16i8] }:$src2) 15382 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMINSBrr, 15383 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15384 // GIR_Coverage, 2646, 15385 GIR_Done, 15386 // Label 1332: @33571 15387 GIM_Try, /*On fail goto*//*Label 1333*/ 33594, // Rule ID 2672 // 15388 GIM_CheckFeatures, GIFBS_UseSSE41, 15389 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 15390 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 15391 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 15392 // (smin:{ *:[v16i8] } VR128:{ *:[v16i8] }:$src1, VR128:{ *:[v16i8] }:$src2) => (PMINSBrr:{ *:[v16i8] } VR128:{ *:[v16i8] }:$src1, VR128:{ *:[v16i8] }:$src2) 15393 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::PMINSBrr, 15394 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15395 // GIR_Coverage, 2672, 15396 GIR_Done, 15397 // Label 1333: @33594 15398 GIM_Try, /*On fail goto*//*Label 1334*/ 33617, // Rule ID 4780 // 15399 GIM_CheckFeatures, GIFBS_HasBWI_HasVLX, 15400 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 15401 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 15402 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128XRegClassID, 15403 // (smin:{ *:[v16i8] } VR128X:{ *:[v16i8] }:$src1, VR128X:{ *:[v16i8] }:$src2) => (VPMINSBZ128rr:{ *:[v16i8] } VR128X:{ *:[v16i8] }:$src1, VR128X:{ *:[v16i8] }:$src2) 15404 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMINSBZ128rr, 15405 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15406 // GIR_Coverage, 4780, 15407 GIR_Done, 15408 // Label 1334: @33617 15409 GIM_Reject, 15410 // Label 1331: @33618 15411 GIM_Reject, 15412 // Label 1311: @33619 15413 GIM_Try, /*On fail goto*//*Label 1335*/ 33676, 15414 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s16, 15415 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s16, 15416 GIM_Try, /*On fail goto*//*Label 1336*/ 33652, // Rule ID 2105 // 15417 GIM_CheckFeatures, GIFBS_HasAVX2_NoVLX_Or_NoBWI, 15418 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID, 15419 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256RegClassID, 15420 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID, 15421 // (smin:{ *:[v16i16] } VR256:{ *:[v16i16] }:$src1, VR256:{ *:[v16i16] }:$src2) => (VPMINSWYrr:{ *:[v16i16] } VR256:{ *:[v16i16] }:$src1, VR256:{ *:[v16i16] }:$src2) 15422 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMINSWYrr, 15423 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15424 // GIR_Coverage, 2105, 15425 GIR_Done, 15426 // Label 1336: @33652 15427 GIM_Try, /*On fail goto*//*Label 1337*/ 33675, // Rule ID 4792 // 15428 GIM_CheckFeatures, GIFBS_HasBWI_HasVLX, 15429 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 15430 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 15431 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256XRegClassID, 15432 // (smin:{ *:[v16i16] } VR256X:{ *:[v16i16] }:$src1, VR256X:{ *:[v16i16] }:$src2) => (VPMINSWZ256rr:{ *:[v16i16] } VR256X:{ *:[v16i16] }:$src1, VR256X:{ *:[v16i16] }:$src2) 15433 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMINSWZ256rr, 15434 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15435 // GIR_Coverage, 4792, 15436 GIR_Done, 15437 // Label 1337: @33675 15438 GIM_Reject, 15439 // Label 1335: @33676 15440 GIM_Reject, 15441 // Label 1312: @33677 15442 GIM_Try, /*On fail goto*//*Label 1338*/ 33708, // Rule ID 4804 // 15443 GIM_CheckFeatures, GIFBS_HasAVX512, 15444 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s32, 15445 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s32, 15446 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 15447 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID, 15448 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR512RegClassID, 15449 // (smin:{ *:[v16i32] } VR512:{ *:[v16i32] }:$src1, VR512:{ *:[v16i32] }:$src2) => (VPMINSDZrr:{ *:[v16i32] } VR512:{ *:[v16i32] }:$src1, VR512:{ *:[v16i32] }:$src2) 15450 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMINSDZrr, 15451 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15452 // GIR_Coverage, 4804, 15453 GIR_Done, 15454 // Label 1338: @33708 15455 GIM_Reject, 15456 // Label 1313: @33709 15457 GIM_Try, /*On fail goto*//*Label 1339*/ 33766, 15458 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v32s8, 15459 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v32s8, 15460 GIM_Try, /*On fail goto*//*Label 1340*/ 33742, // Rule ID 2664 // 15461 GIM_CheckFeatures, GIFBS_HasAVX2_NoVLX_Or_NoBWI, 15462 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID, 15463 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256RegClassID, 15464 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID, 15465 // (smin:{ *:[v32i8] } VR256:{ *:[v32i8] }:$src1, VR256:{ *:[v32i8] }:$src2) => (VPMINSBYrr:{ *:[v32i8] } VR256:{ *:[v32i8] }:$src1, VR256:{ *:[v32i8] }:$src2) 15466 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMINSBYrr, 15467 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15468 // GIR_Coverage, 2664, 15469 GIR_Done, 15470 // Label 1340: @33742 15471 GIM_Try, /*On fail goto*//*Label 1341*/ 33765, // Rule ID 4774 // 15472 GIM_CheckFeatures, GIFBS_HasBWI_HasVLX, 15473 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 15474 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 15475 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256XRegClassID, 15476 // (smin:{ *:[v32i8] } VR256X:{ *:[v32i8] }:$src1, VR256X:{ *:[v32i8] }:$src2) => (VPMINSBZ256rr:{ *:[v32i8] } VR256X:{ *:[v32i8] }:$src1, VR256X:{ *:[v32i8] }:$src2) 15477 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMINSBZ256rr, 15478 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15479 // GIR_Coverage, 4774, 15480 GIR_Done, 15481 // Label 1341: @33765 15482 GIM_Reject, 15483 // Label 1339: @33766 15484 GIM_Reject, 15485 // Label 1314: @33767 15486 GIM_Try, /*On fail goto*//*Label 1342*/ 33798, // Rule ID 4786 // 15487 GIM_CheckFeatures, GIFBS_HasBWI, 15488 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v32s16, 15489 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v32s16, 15490 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 15491 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID, 15492 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR512RegClassID, 15493 // (smin:{ *:[v32i16] } VR512:{ *:[v32i16] }:$src1, VR512:{ *:[v32i16] }:$src2) => (VPMINSWZrr:{ *:[v32i16] } VR512:{ *:[v32i16] }:$src1, VR512:{ *:[v32i16] }:$src2) 15494 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMINSWZrr, 15495 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15496 // GIR_Coverage, 4786, 15497 GIR_Done, 15498 // Label 1342: @33798 15499 GIM_Reject, 15500 // Label 1315: @33799 15501 GIM_Try, /*On fail goto*//*Label 1343*/ 33830, // Rule ID 4768 // 15502 GIM_CheckFeatures, GIFBS_HasBWI, 15503 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v64s8, 15504 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v64s8, 15505 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 15506 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID, 15507 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR512RegClassID, 15508 // (smin:{ *:[v64i8] } VR512:{ *:[v64i8] }:$src1, VR512:{ *:[v64i8] }:$src2) => (VPMINSBZrr:{ *:[v64i8] } VR512:{ *:[v64i8] }:$src1, VR512:{ *:[v64i8] }:$src2) 15509 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMINSBZrr, 15510 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15511 // GIR_Coverage, 4768, 15512 GIR_Done, 15513 // Label 1343: @33830 15514 GIM_Reject, 15515 // Label 1316: @33831 15516 GIM_Reject, 15517 // Label 34: @33832 15518 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/8, 25, /*)*//*default:*//*Label 1356*/ 34464, 15519 /*GILLT_v2s64*//*Label 1344*/ 33855, 0, 15520 /*GILLT_v4s32*//*Label 1345*/ 33887, 15521 /*GILLT_v4s64*//*Label 1346*/ 33968, 0, 15522 /*GILLT_v8s16*//*Label 1347*/ 34000, 15523 /*GILLT_v8s32*//*Label 1348*/ 34081, 15524 /*GILLT_v8s64*//*Label 1349*/ 34139, 0, 15525 /*GILLT_v16s8*//*Label 1350*/ 34171, 15526 /*GILLT_v16s16*//*Label 1351*/ 34252, 15527 /*GILLT_v16s32*//*Label 1352*/ 34310, 0, 15528 /*GILLT_v32s8*//*Label 1353*/ 34342, 15529 /*GILLT_v32s16*//*Label 1354*/ 34400, 0, 15530 /*GILLT_v64s8*//*Label 1355*/ 34432, 15531 // Label 1344: @33855 15532 GIM_Try, /*On fail goto*//*Label 1357*/ 33886, // Rule ID 4669 // 15533 GIM_CheckFeatures, GIFBS_HasAVX512_HasVLX, 15534 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, 15535 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 15536 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 15537 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 15538 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128XRegClassID, 15539 // (smax:{ *:[v2i64] } VR128X:{ *:[v2i64] }:$src1, VR128X:{ *:[v2i64] }:$src2) => (VPMAXSQZ128rr:{ *:[v2i64] } VR128X:{ *:[v2i64] }:$src1, VR128X:{ *:[v2i64] }:$src2) 15540 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMAXSQZ128rr, 15541 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15542 // GIR_Coverage, 4669, 15543 GIR_Done, 15544 // Label 1357: @33886 15545 GIM_Reject, 15546 // Label 1345: @33887 15547 GIM_Try, /*On fail goto*//*Label 1358*/ 33967, 15548 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 15549 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 15550 GIM_Try, /*On fail goto*//*Label 1359*/ 33920, // Rule ID 2640 // 15551 GIM_CheckFeatures, GIFBS_HasAVX_NoVLX, 15552 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 15553 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 15554 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 15555 // (smax:{ *:[v4i32] } VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2) => (VPMAXSDrr:{ *:[v4i32] } VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2) 15556 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMAXSDrr, 15557 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15558 // GIR_Coverage, 2640, 15559 GIR_Done, 15560 // Label 1359: @33920 15561 GIM_Try, /*On fail goto*//*Label 1360*/ 33943, // Rule ID 2682 // 15562 GIM_CheckFeatures, GIFBS_UseSSE41, 15563 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 15564 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 15565 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 15566 // (smax:{ *:[v4i32] } VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2) => (PMAXSDrr:{ *:[v4i32] } VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2) 15567 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::PMAXSDrr, 15568 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15569 // GIR_Coverage, 2682, 15570 GIR_Done, 15571 // Label 1360: @33943 15572 GIM_Try, /*On fail goto*//*Label 1361*/ 33966, // Rule ID 4642 // 15573 GIM_CheckFeatures, GIFBS_HasAVX512_HasVLX, 15574 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 15575 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 15576 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128XRegClassID, 15577 // (smax:{ *:[v4i32] } VR128X:{ *:[v4i32] }:$src1, VR128X:{ *:[v4i32] }:$src2) => (VPMAXSDZ128rr:{ *:[v4i32] } VR128X:{ *:[v4i32] }:$src1, VR128X:{ *:[v4i32] }:$src2) 15578 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMAXSDZ128rr, 15579 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15580 // GIR_Coverage, 4642, 15581 GIR_Done, 15582 // Label 1361: @33966 15583 GIM_Reject, 15584 // Label 1358: @33967 15585 GIM_Reject, 15586 // Label 1346: @33968 15587 GIM_Try, /*On fail goto*//*Label 1362*/ 33999, // Rule ID 4660 // 15588 GIM_CheckFeatures, GIFBS_HasAVX512_HasVLX, 15589 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s64, 15590 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s64, 15591 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 15592 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 15593 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256XRegClassID, 15594 // (smax:{ *:[v4i64] } VR256X:{ *:[v4i64] }:$src1, VR256X:{ *:[v4i64] }:$src2) => (VPMAXSQZ256rr:{ *:[v4i64] } VR256X:{ *:[v4i64] }:$src1, VR256X:{ *:[v4i64] }:$src2) 15595 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMAXSQZ256rr, 15596 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15597 // GIR_Coverage, 4660, 15598 GIR_Done, 15599 // Label 1362: @33999 15600 GIM_Reject, 15601 // Label 1347: @34000 15602 GIM_Try, /*On fail goto*//*Label 1363*/ 34080, 15603 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, 15604 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 15605 GIM_Try, /*On fail goto*//*Label 1364*/ 34033, // Rule ID 2113 // 15606 GIM_CheckFeatures, GIFBS_HasAVX_NoVLX_Or_NoBWI, 15607 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 15608 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 15609 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 15610 // (smax:{ *:[v8i16] } VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2) => (VPMAXSWrr:{ *:[v8i16] } VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2) 15611 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMAXSWrr, 15612 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15613 // GIR_Coverage, 2113, 15614 GIR_Done, 15615 // Label 1364: @34033 15616 GIM_Try, /*On fail goto*//*Label 1365*/ 34056, // Rule ID 2115 // 15617 GIM_CheckFeatures, GIFBS_UseSSE2, 15618 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 15619 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 15620 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 15621 // (smax:{ *:[v8i16] } VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2) => (PMAXSWrr:{ *:[v8i16] } VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2) 15622 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::PMAXSWrr, 15623 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15624 // GIR_Coverage, 2115, 15625 GIR_Done, 15626 // Label 1365: @34056 15627 GIM_Try, /*On fail goto*//*Label 1366*/ 34079, // Rule ID 4618 // 15628 GIM_CheckFeatures, GIFBS_HasBWI_HasVLX, 15629 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 15630 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 15631 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128XRegClassID, 15632 // (smax:{ *:[v8i16] } VR128X:{ *:[v8i16] }:$src1, VR128X:{ *:[v8i16] }:$src2) => (VPMAXSWZ128rr:{ *:[v8i16] } VR128X:{ *:[v8i16] }:$src1, VR128X:{ *:[v8i16] }:$src2) 15633 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMAXSWZ128rr, 15634 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15635 // GIR_Coverage, 4618, 15636 GIR_Done, 15637 // Label 1366: @34079 15638 GIM_Reject, 15639 // Label 1363: @34080 15640 GIM_Reject, 15641 // Label 1348: @34081 15642 GIM_Try, /*On fail goto*//*Label 1367*/ 34138, 15643 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s32, 15644 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s32, 15645 GIM_Try, /*On fail goto*//*Label 1368*/ 34114, // Rule ID 2658 // 15646 GIM_CheckFeatures, GIFBS_HasAVX2_NoVLX, 15647 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID, 15648 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256RegClassID, 15649 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID, 15650 // (smax:{ *:[v8i32] } VR256:{ *:[v8i32] }:$src1, VR256:{ *:[v8i32] }:$src2) => (VPMAXSDYrr:{ *:[v8i32] } VR256:{ *:[v8i32] }:$src1, VR256:{ *:[v8i32] }:$src2) 15651 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMAXSDYrr, 15652 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15653 // GIR_Coverage, 2658, 15654 GIR_Done, 15655 // Label 1368: @34114 15656 GIM_Try, /*On fail goto*//*Label 1369*/ 34137, // Rule ID 4633 // 15657 GIM_CheckFeatures, GIFBS_HasAVX512_HasVLX, 15658 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 15659 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 15660 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256XRegClassID, 15661 // (smax:{ *:[v8i32] } VR256X:{ *:[v8i32] }:$src1, VR256X:{ *:[v8i32] }:$src2) => (VPMAXSDZ256rr:{ *:[v8i32] } VR256X:{ *:[v8i32] }:$src1, VR256X:{ *:[v8i32] }:$src2) 15662 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMAXSDZ256rr, 15663 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15664 // GIR_Coverage, 4633, 15665 GIR_Done, 15666 // Label 1369: @34137 15667 GIM_Reject, 15668 // Label 1367: @34138 15669 GIM_Reject, 15670 // Label 1349: @34139 15671 GIM_Try, /*On fail goto*//*Label 1370*/ 34170, // Rule ID 4651 // 15672 GIM_CheckFeatures, GIFBS_HasAVX512, 15673 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s64, 15674 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s64, 15675 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 15676 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID, 15677 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR512RegClassID, 15678 // (smax:{ *:[v8i64] } VR512:{ *:[v8i64] }:$src1, VR512:{ *:[v8i64] }:$src2) => (VPMAXSQZrr:{ *:[v8i64] } VR512:{ *:[v8i64] }:$src1, VR512:{ *:[v8i64] }:$src2) 15679 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMAXSQZrr, 15680 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15681 // GIR_Coverage, 4651, 15682 GIR_Done, 15683 // Label 1370: @34170 15684 GIM_Reject, 15685 // Label 1350: @34171 15686 GIM_Try, /*On fail goto*//*Label 1371*/ 34251, 15687 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, 15688 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 15689 GIM_Try, /*On fail goto*//*Label 1372*/ 34204, // Rule ID 2650 // 15690 GIM_CheckFeatures, GIFBS_HasAVX_NoVLX_Or_NoBWI, 15691 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 15692 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 15693 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 15694 // (smax:{ *:[v16i8] } VR128:{ *:[v16i8] }:$src1, VR128:{ *:[v16i8] }:$src2) => (VPMAXSBrr:{ *:[v16i8] } VR128:{ *:[v16i8] }:$src1, VR128:{ *:[v16i8] }:$src2) 15695 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMAXSBrr, 15696 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15697 // GIR_Coverage, 2650, 15698 GIR_Done, 15699 // Label 1372: @34204 15700 GIM_Try, /*On fail goto*//*Label 1373*/ 34227, // Rule ID 2680 // 15701 GIM_CheckFeatures, GIFBS_UseSSE41, 15702 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 15703 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 15704 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 15705 // (smax:{ *:[v16i8] } VR128:{ *:[v16i8] }:$src1, VR128:{ *:[v16i8] }:$src2) => (PMAXSBrr:{ *:[v16i8] } VR128:{ *:[v16i8] }:$src1, VR128:{ *:[v16i8] }:$src2) 15706 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::PMAXSBrr, 15707 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15708 // GIR_Coverage, 2680, 15709 GIR_Done, 15710 // Label 1373: @34227 15711 GIM_Try, /*On fail goto*//*Label 1374*/ 34250, // Rule ID 4600 // 15712 GIM_CheckFeatures, GIFBS_HasBWI_HasVLX, 15713 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 15714 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 15715 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128XRegClassID, 15716 // (smax:{ *:[v16i8] } VR128X:{ *:[v16i8] }:$src1, VR128X:{ *:[v16i8] }:$src2) => (VPMAXSBZ128rr:{ *:[v16i8] } VR128X:{ *:[v16i8] }:$src1, VR128X:{ *:[v16i8] }:$src2) 15717 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMAXSBZ128rr, 15718 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15719 // GIR_Coverage, 4600, 15720 GIR_Done, 15721 // Label 1374: @34250 15722 GIM_Reject, 15723 // Label 1371: @34251 15724 GIM_Reject, 15725 // Label 1351: @34252 15726 GIM_Try, /*On fail goto*//*Label 1375*/ 34309, 15727 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s16, 15728 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s16, 15729 GIM_Try, /*On fail goto*//*Label 1376*/ 34285, // Rule ID 2117 // 15730 GIM_CheckFeatures, GIFBS_HasAVX2_NoVLX_Or_NoBWI, 15731 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID, 15732 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256RegClassID, 15733 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID, 15734 // (smax:{ *:[v16i16] } VR256:{ *:[v16i16] }:$src1, VR256:{ *:[v16i16] }:$src2) => (VPMAXSWYrr:{ *:[v16i16] } VR256:{ *:[v16i16] }:$src1, VR256:{ *:[v16i16] }:$src2) 15735 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMAXSWYrr, 15736 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15737 // GIR_Coverage, 2117, 15738 GIR_Done, 15739 // Label 1376: @34285 15740 GIM_Try, /*On fail goto*//*Label 1377*/ 34308, // Rule ID 4612 // 15741 GIM_CheckFeatures, GIFBS_HasBWI_HasVLX, 15742 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 15743 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 15744 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256XRegClassID, 15745 // (smax:{ *:[v16i16] } VR256X:{ *:[v16i16] }:$src1, VR256X:{ *:[v16i16] }:$src2) => (VPMAXSWZ256rr:{ *:[v16i16] } VR256X:{ *:[v16i16] }:$src1, VR256X:{ *:[v16i16] }:$src2) 15746 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMAXSWZ256rr, 15747 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15748 // GIR_Coverage, 4612, 15749 GIR_Done, 15750 // Label 1377: @34308 15751 GIM_Reject, 15752 // Label 1375: @34309 15753 GIM_Reject, 15754 // Label 1352: @34310 15755 GIM_Try, /*On fail goto*//*Label 1378*/ 34341, // Rule ID 4624 // 15756 GIM_CheckFeatures, GIFBS_HasAVX512, 15757 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s32, 15758 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s32, 15759 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 15760 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID, 15761 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR512RegClassID, 15762 // (smax:{ *:[v16i32] } VR512:{ *:[v16i32] }:$src1, VR512:{ *:[v16i32] }:$src2) => (VPMAXSDZrr:{ *:[v16i32] } VR512:{ *:[v16i32] }:$src1, VR512:{ *:[v16i32] }:$src2) 15763 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMAXSDZrr, 15764 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15765 // GIR_Coverage, 4624, 15766 GIR_Done, 15767 // Label 1378: @34341 15768 GIM_Reject, 15769 // Label 1353: @34342 15770 GIM_Try, /*On fail goto*//*Label 1379*/ 34399, 15771 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v32s8, 15772 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v32s8, 15773 GIM_Try, /*On fail goto*//*Label 1380*/ 34375, // Rule ID 2668 // 15774 GIM_CheckFeatures, GIFBS_HasAVX2_NoVLX_Or_NoBWI, 15775 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID, 15776 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256RegClassID, 15777 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID, 15778 // (smax:{ *:[v32i8] } VR256:{ *:[v32i8] }:$src1, VR256:{ *:[v32i8] }:$src2) => (VPMAXSBYrr:{ *:[v32i8] } VR256:{ *:[v32i8] }:$src1, VR256:{ *:[v32i8] }:$src2) 15779 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMAXSBYrr, 15780 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15781 // GIR_Coverage, 2668, 15782 GIR_Done, 15783 // Label 1380: @34375 15784 GIM_Try, /*On fail goto*//*Label 1381*/ 34398, // Rule ID 4594 // 15785 GIM_CheckFeatures, GIFBS_HasBWI_HasVLX, 15786 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 15787 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 15788 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256XRegClassID, 15789 // (smax:{ *:[v32i8] } VR256X:{ *:[v32i8] }:$src1, VR256X:{ *:[v32i8] }:$src2) => (VPMAXSBZ256rr:{ *:[v32i8] } VR256X:{ *:[v32i8] }:$src1, VR256X:{ *:[v32i8] }:$src2) 15790 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMAXSBZ256rr, 15791 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15792 // GIR_Coverage, 4594, 15793 GIR_Done, 15794 // Label 1381: @34398 15795 GIM_Reject, 15796 // Label 1379: @34399 15797 GIM_Reject, 15798 // Label 1354: @34400 15799 GIM_Try, /*On fail goto*//*Label 1382*/ 34431, // Rule ID 4606 // 15800 GIM_CheckFeatures, GIFBS_HasBWI, 15801 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v32s16, 15802 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v32s16, 15803 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 15804 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID, 15805 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR512RegClassID, 15806 // (smax:{ *:[v32i16] } VR512:{ *:[v32i16] }:$src1, VR512:{ *:[v32i16] }:$src2) => (VPMAXSWZrr:{ *:[v32i16] } VR512:{ *:[v32i16] }:$src1, VR512:{ *:[v32i16] }:$src2) 15807 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMAXSWZrr, 15808 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15809 // GIR_Coverage, 4606, 15810 GIR_Done, 15811 // Label 1382: @34431 15812 GIM_Reject, 15813 // Label 1355: @34432 15814 GIM_Try, /*On fail goto*//*Label 1383*/ 34463, // Rule ID 4588 // 15815 GIM_CheckFeatures, GIFBS_HasBWI, 15816 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v64s8, 15817 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v64s8, 15818 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 15819 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID, 15820 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR512RegClassID, 15821 // (smax:{ *:[v64i8] } VR512:{ *:[v64i8] }:$src1, VR512:{ *:[v64i8] }:$src2) => (VPMAXSBZrr:{ *:[v64i8] } VR512:{ *:[v64i8] }:$src1, VR512:{ *:[v64i8] }:$src2) 15822 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMAXSBZrr, 15823 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15824 // GIR_Coverage, 4588, 15825 GIR_Done, 15826 // Label 1383: @34463 15827 GIM_Reject, 15828 // Label 1356: @34464 15829 GIM_Reject, 15830 // Label 35: @34465 15831 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/8, 25, /*)*//*default:*//*Label 1396*/ 35097, 15832 /*GILLT_v2s64*//*Label 1384*/ 34488, 0, 15833 /*GILLT_v4s32*//*Label 1385*/ 34520, 15834 /*GILLT_v4s64*//*Label 1386*/ 34601, 0, 15835 /*GILLT_v8s16*//*Label 1387*/ 34633, 15836 /*GILLT_v8s32*//*Label 1388*/ 34714, 15837 /*GILLT_v8s64*//*Label 1389*/ 34772, 0, 15838 /*GILLT_v16s8*//*Label 1390*/ 34804, 15839 /*GILLT_v16s16*//*Label 1391*/ 34885, 15840 /*GILLT_v16s32*//*Label 1392*/ 34943, 0, 15841 /*GILLT_v32s8*//*Label 1393*/ 34975, 15842 /*GILLT_v32s16*//*Label 1394*/ 35033, 0, 15843 /*GILLT_v64s8*//*Label 1395*/ 35065, 15844 // Label 1384: @34488 15845 GIM_Try, /*On fail goto*//*Label 1397*/ 34519, // Rule ID 4939 // 15846 GIM_CheckFeatures, GIFBS_HasAVX512_HasVLX, 15847 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, 15848 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 15849 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 15850 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 15851 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128XRegClassID, 15852 // (umin:{ *:[v2i64] } VR128X:{ *:[v2i64] }:$src1, VR128X:{ *:[v2i64] }:$src2) => (VPMINUQZ128rr:{ *:[v2i64] } VR128X:{ *:[v2i64] }:$src1, VR128X:{ *:[v2i64] }:$src2) 15853 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMINUQZ128rr, 15854 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15855 // GIR_Coverage, 4939, 15856 GIR_Done, 15857 // Label 1397: @34519 15858 GIM_Reject, 15859 // Label 1385: @34520 15860 GIM_Try, /*On fail goto*//*Label 1398*/ 34600, 15861 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 15862 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 15863 GIM_Try, /*On fail goto*//*Label 1399*/ 34553, // Rule ID 2638 // 15864 GIM_CheckFeatures, GIFBS_HasAVX_NoVLX, 15865 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 15866 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 15867 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 15868 // (umin:{ *:[v4i32] } VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2) => (VPMINUDrr:{ *:[v4i32] } VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2) 15869 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMINUDrr, 15870 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15871 // GIR_Coverage, 2638, 15872 GIR_Done, 15873 // Label 1399: @34553 15874 GIM_Try, /*On fail goto*//*Label 1400*/ 34576, // Rule ID 2676 // 15875 GIM_CheckFeatures, GIFBS_UseSSE41, 15876 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 15877 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 15878 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 15879 // (umin:{ *:[v4i32] } VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2) => (PMINUDrr:{ *:[v4i32] } VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2) 15880 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::PMINUDrr, 15881 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15882 // GIR_Coverage, 2676, 15883 GIR_Done, 15884 // Label 1400: @34576 15885 GIM_Try, /*On fail goto*//*Label 1401*/ 34599, // Rule ID 4912 // 15886 GIM_CheckFeatures, GIFBS_HasAVX512_HasVLX, 15887 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 15888 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 15889 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128XRegClassID, 15890 // (umin:{ *:[v4i32] } VR128X:{ *:[v4i32] }:$src1, VR128X:{ *:[v4i32] }:$src2) => (VPMINUDZ128rr:{ *:[v4i32] } VR128X:{ *:[v4i32] }:$src1, VR128X:{ *:[v4i32] }:$src2) 15891 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMINUDZ128rr, 15892 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15893 // GIR_Coverage, 4912, 15894 GIR_Done, 15895 // Label 1401: @34599 15896 GIM_Reject, 15897 // Label 1398: @34600 15898 GIM_Reject, 15899 // Label 1386: @34601 15900 GIM_Try, /*On fail goto*//*Label 1402*/ 34632, // Rule ID 4930 // 15901 GIM_CheckFeatures, GIFBS_HasAVX512_HasVLX, 15902 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s64, 15903 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s64, 15904 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 15905 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 15906 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256XRegClassID, 15907 // (umin:{ *:[v4i64] } VR256X:{ *:[v4i64] }:$src1, VR256X:{ *:[v4i64] }:$src2) => (VPMINUQZ256rr:{ *:[v4i64] } VR256X:{ *:[v4i64] }:$src1, VR256X:{ *:[v4i64] }:$src2) 15908 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMINUQZ256rr, 15909 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15910 // GIR_Coverage, 4930, 15911 GIR_Done, 15912 // Label 1402: @34632 15913 GIM_Reject, 15914 // Label 1387: @34633 15915 GIM_Try, /*On fail goto*//*Label 1403*/ 34713, 15916 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, 15917 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 15918 GIM_Try, /*On fail goto*//*Label 1404*/ 34666, // Rule ID 2648 // 15919 GIM_CheckFeatures, GIFBS_HasAVX_NoVLX_Or_NoBWI, 15920 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 15921 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 15922 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 15923 // (umin:{ *:[v8i16] } VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2) => (VPMINUWrr:{ *:[v8i16] } VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2) 15924 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMINUWrr, 15925 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15926 // GIR_Coverage, 2648, 15927 GIR_Done, 15928 // Label 1404: @34666 15929 GIM_Try, /*On fail goto*//*Label 1405*/ 34689, // Rule ID 2678 // 15930 GIM_CheckFeatures, GIFBS_UseSSE41, 15931 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 15932 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 15933 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 15934 // (umin:{ *:[v8i16] } VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2) => (PMINUWrr:{ *:[v8i16] } VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2) 15935 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::PMINUWrr, 15936 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15937 // GIR_Coverage, 2678, 15938 GIR_Done, 15939 // Label 1405: @34689 15940 GIM_Try, /*On fail goto*//*Label 1406*/ 34712, // Rule ID 4888 // 15941 GIM_CheckFeatures, GIFBS_HasBWI_HasVLX, 15942 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 15943 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 15944 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128XRegClassID, 15945 // (umin:{ *:[v8i16] } VR128X:{ *:[v8i16] }:$src1, VR128X:{ *:[v8i16] }:$src2) => (VPMINUWZ128rr:{ *:[v8i16] } VR128X:{ *:[v8i16] }:$src1, VR128X:{ *:[v8i16] }:$src2) 15946 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMINUWZ128rr, 15947 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15948 // GIR_Coverage, 4888, 15949 GIR_Done, 15950 // Label 1406: @34712 15951 GIM_Reject, 15952 // Label 1403: @34713 15953 GIM_Reject, 15954 // Label 1388: @34714 15955 GIM_Try, /*On fail goto*//*Label 1407*/ 34771, 15956 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s32, 15957 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s32, 15958 GIM_Try, /*On fail goto*//*Label 1408*/ 34747, // Rule ID 2656 // 15959 GIM_CheckFeatures, GIFBS_HasAVX2_NoVLX, 15960 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID, 15961 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256RegClassID, 15962 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID, 15963 // (umin:{ *:[v8i32] } VR256:{ *:[v8i32] }:$src1, VR256:{ *:[v8i32] }:$src2) => (VPMINUDYrr:{ *:[v8i32] } VR256:{ *:[v8i32] }:$src1, VR256:{ *:[v8i32] }:$src2) 15964 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMINUDYrr, 15965 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15966 // GIR_Coverage, 2656, 15967 GIR_Done, 15968 // Label 1408: @34747 15969 GIM_Try, /*On fail goto*//*Label 1409*/ 34770, // Rule ID 4903 // 15970 GIM_CheckFeatures, GIFBS_HasAVX512_HasVLX, 15971 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 15972 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 15973 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256XRegClassID, 15974 // (umin:{ *:[v8i32] } VR256X:{ *:[v8i32] }:$src1, VR256X:{ *:[v8i32] }:$src2) => (VPMINUDZ256rr:{ *:[v8i32] } VR256X:{ *:[v8i32] }:$src1, VR256X:{ *:[v8i32] }:$src2) 15975 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMINUDZ256rr, 15976 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15977 // GIR_Coverage, 4903, 15978 GIR_Done, 15979 // Label 1409: @34770 15980 GIM_Reject, 15981 // Label 1407: @34771 15982 GIM_Reject, 15983 // Label 1389: @34772 15984 GIM_Try, /*On fail goto*//*Label 1410*/ 34803, // Rule ID 4921 // 15985 GIM_CheckFeatures, GIFBS_HasAVX512, 15986 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s64, 15987 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s64, 15988 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 15989 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID, 15990 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR512RegClassID, 15991 // (umin:{ *:[v8i64] } VR512:{ *:[v8i64] }:$src1, VR512:{ *:[v8i64] }:$src2) => (VPMINUQZrr:{ *:[v8i64] } VR512:{ *:[v8i64] }:$src1, VR512:{ *:[v8i64] }:$src2) 15992 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMINUQZrr, 15993 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 15994 // GIR_Coverage, 4921, 15995 GIR_Done, 15996 // Label 1410: @34803 15997 GIM_Reject, 15998 // Label 1390: @34804 15999 GIM_Try, /*On fail goto*//*Label 1411*/ 34884, 16000 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, 16001 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 16002 GIM_Try, /*On fail goto*//*Label 1412*/ 34837, // Rule ID 2095 // 16003 GIM_CheckFeatures, GIFBS_HasAVX_NoVLX_Or_NoBWI, 16004 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 16005 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 16006 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 16007 // (umin:{ *:[v16i8] } VR128:{ *:[v16i8] }:$src1, VR128:{ *:[v16i8] }:$src2) => (VPMINUBrr:{ *:[v16i8] } VR128:{ *:[v16i8] }:$src1, VR128:{ *:[v16i8] }:$src2) 16008 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMINUBrr, 16009 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16010 // GIR_Coverage, 2095, 16011 GIR_Done, 16012 // Label 1412: @34837 16013 GIM_Try, /*On fail goto*//*Label 1413*/ 34860, // Rule ID 2097 // 16014 GIM_CheckFeatures, GIFBS_UseSSE2, 16015 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 16016 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 16017 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 16018 // (umin:{ *:[v16i8] } VR128:{ *:[v16i8] }:$src1, VR128:{ *:[v16i8] }:$src2) => (PMINUBrr:{ *:[v16i8] } VR128:{ *:[v16i8] }:$src1, VR128:{ *:[v16i8] }:$src2) 16019 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::PMINUBrr, 16020 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16021 // GIR_Coverage, 2097, 16022 GIR_Done, 16023 // Label 1413: @34860 16024 GIM_Try, /*On fail goto*//*Label 1414*/ 34883, // Rule ID 4870 // 16025 GIM_CheckFeatures, GIFBS_HasBWI_HasVLX, 16026 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 16027 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 16028 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128XRegClassID, 16029 // (umin:{ *:[v16i8] } VR128X:{ *:[v16i8] }:$src1, VR128X:{ *:[v16i8] }:$src2) => (VPMINUBZ128rr:{ *:[v16i8] } VR128X:{ *:[v16i8] }:$src1, VR128X:{ *:[v16i8] }:$src2) 16030 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMINUBZ128rr, 16031 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16032 // GIR_Coverage, 4870, 16033 GIR_Done, 16034 // Label 1414: @34883 16035 GIM_Reject, 16036 // Label 1411: @34884 16037 GIM_Reject, 16038 // Label 1391: @34885 16039 GIM_Try, /*On fail goto*//*Label 1415*/ 34942, 16040 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s16, 16041 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s16, 16042 GIM_Try, /*On fail goto*//*Label 1416*/ 34918, // Rule ID 2666 // 16043 GIM_CheckFeatures, GIFBS_HasAVX2_NoVLX_Or_NoBWI, 16044 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID, 16045 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256RegClassID, 16046 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID, 16047 // (umin:{ *:[v16i16] } VR256:{ *:[v16i16] }:$src1, VR256:{ *:[v16i16] }:$src2) => (VPMINUWYrr:{ *:[v16i16] } VR256:{ *:[v16i16] }:$src1, VR256:{ *:[v16i16] }:$src2) 16048 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMINUWYrr, 16049 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16050 // GIR_Coverage, 2666, 16051 GIR_Done, 16052 // Label 1416: @34918 16053 GIM_Try, /*On fail goto*//*Label 1417*/ 34941, // Rule ID 4882 // 16054 GIM_CheckFeatures, GIFBS_HasBWI_HasVLX, 16055 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 16056 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 16057 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256XRegClassID, 16058 // (umin:{ *:[v16i16] } VR256X:{ *:[v16i16] }:$src1, VR256X:{ *:[v16i16] }:$src2) => (VPMINUWZ256rr:{ *:[v16i16] } VR256X:{ *:[v16i16] }:$src1, VR256X:{ *:[v16i16] }:$src2) 16059 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMINUWZ256rr, 16060 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16061 // GIR_Coverage, 4882, 16062 GIR_Done, 16063 // Label 1417: @34941 16064 GIM_Reject, 16065 // Label 1415: @34942 16066 GIM_Reject, 16067 // Label 1392: @34943 16068 GIM_Try, /*On fail goto*//*Label 1418*/ 34974, // Rule ID 4894 // 16069 GIM_CheckFeatures, GIFBS_HasAVX512, 16070 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s32, 16071 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s32, 16072 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 16073 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID, 16074 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR512RegClassID, 16075 // (umin:{ *:[v16i32] } VR512:{ *:[v16i32] }:$src1, VR512:{ *:[v16i32] }:$src2) => (VPMINUDZrr:{ *:[v16i32] } VR512:{ *:[v16i32] }:$src1, VR512:{ *:[v16i32] }:$src2) 16076 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMINUDZrr, 16077 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16078 // GIR_Coverage, 4894, 16079 GIR_Done, 16080 // Label 1418: @34974 16081 GIM_Reject, 16082 // Label 1393: @34975 16083 GIM_Try, /*On fail goto*//*Label 1419*/ 35032, 16084 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v32s8, 16085 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v32s8, 16086 GIM_Try, /*On fail goto*//*Label 1420*/ 35008, // Rule ID 2099 // 16087 GIM_CheckFeatures, GIFBS_HasAVX2_NoVLX_Or_NoBWI, 16088 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID, 16089 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256RegClassID, 16090 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID, 16091 // (umin:{ *:[v32i8] } VR256:{ *:[v32i8] }:$src1, VR256:{ *:[v32i8] }:$src2) => (VPMINUBYrr:{ *:[v32i8] } VR256:{ *:[v32i8] }:$src1, VR256:{ *:[v32i8] }:$src2) 16092 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMINUBYrr, 16093 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16094 // GIR_Coverage, 2099, 16095 GIR_Done, 16096 // Label 1420: @35008 16097 GIM_Try, /*On fail goto*//*Label 1421*/ 35031, // Rule ID 4864 // 16098 GIM_CheckFeatures, GIFBS_HasBWI_HasVLX, 16099 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 16100 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 16101 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256XRegClassID, 16102 // (umin:{ *:[v32i8] } VR256X:{ *:[v32i8] }:$src1, VR256X:{ *:[v32i8] }:$src2) => (VPMINUBZ256rr:{ *:[v32i8] } VR256X:{ *:[v32i8] }:$src1, VR256X:{ *:[v32i8] }:$src2) 16103 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMINUBZ256rr, 16104 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16105 // GIR_Coverage, 4864, 16106 GIR_Done, 16107 // Label 1421: @35031 16108 GIM_Reject, 16109 // Label 1419: @35032 16110 GIM_Reject, 16111 // Label 1394: @35033 16112 GIM_Try, /*On fail goto*//*Label 1422*/ 35064, // Rule ID 4876 // 16113 GIM_CheckFeatures, GIFBS_HasBWI, 16114 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v32s16, 16115 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v32s16, 16116 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 16117 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID, 16118 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR512RegClassID, 16119 // (umin:{ *:[v32i16] } VR512:{ *:[v32i16] }:$src1, VR512:{ *:[v32i16] }:$src2) => (VPMINUWZrr:{ *:[v32i16] } VR512:{ *:[v32i16] }:$src1, VR512:{ *:[v32i16] }:$src2) 16120 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMINUWZrr, 16121 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16122 // GIR_Coverage, 4876, 16123 GIR_Done, 16124 // Label 1422: @35064 16125 GIM_Reject, 16126 // Label 1395: @35065 16127 GIM_Try, /*On fail goto*//*Label 1423*/ 35096, // Rule ID 4858 // 16128 GIM_CheckFeatures, GIFBS_HasBWI, 16129 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v64s8, 16130 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v64s8, 16131 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 16132 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID, 16133 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR512RegClassID, 16134 // (umin:{ *:[v64i8] } VR512:{ *:[v64i8] }:$src1, VR512:{ *:[v64i8] }:$src2) => (VPMINUBZrr:{ *:[v64i8] } VR512:{ *:[v64i8] }:$src1, VR512:{ *:[v64i8] }:$src2) 16135 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMINUBZrr, 16136 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16137 // GIR_Coverage, 4858, 16138 GIR_Done, 16139 // Label 1423: @35096 16140 GIM_Reject, 16141 // Label 1396: @35097 16142 GIM_Reject, 16143 // Label 36: @35098 16144 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/8, 25, /*)*//*default:*//*Label 1436*/ 35730, 16145 /*GILLT_v2s64*//*Label 1424*/ 35121, 0, 16146 /*GILLT_v4s32*//*Label 1425*/ 35153, 16147 /*GILLT_v4s64*//*Label 1426*/ 35234, 0, 16148 /*GILLT_v8s16*//*Label 1427*/ 35266, 16149 /*GILLT_v8s32*//*Label 1428*/ 35347, 16150 /*GILLT_v8s64*//*Label 1429*/ 35405, 0, 16151 /*GILLT_v16s8*//*Label 1430*/ 35437, 16152 /*GILLT_v16s16*//*Label 1431*/ 35518, 16153 /*GILLT_v16s32*//*Label 1432*/ 35576, 0, 16154 /*GILLT_v32s8*//*Label 1433*/ 35608, 16155 /*GILLT_v32s16*//*Label 1434*/ 35666, 0, 16156 /*GILLT_v64s8*//*Label 1435*/ 35698, 16157 // Label 1424: @35121 16158 GIM_Try, /*On fail goto*//*Label 1437*/ 35152, // Rule ID 4759 // 16159 GIM_CheckFeatures, GIFBS_HasAVX512_HasVLX, 16160 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, 16161 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64, 16162 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 16163 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 16164 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128XRegClassID, 16165 // (umax:{ *:[v2i64] } VR128X:{ *:[v2i64] }:$src1, VR128X:{ *:[v2i64] }:$src2) => (VPMAXUQZ128rr:{ *:[v2i64] } VR128X:{ *:[v2i64] }:$src1, VR128X:{ *:[v2i64] }:$src2) 16166 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMAXUQZ128rr, 16167 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16168 // GIR_Coverage, 4759, 16169 GIR_Done, 16170 // Label 1437: @35152 16171 GIM_Reject, 16172 // Label 1425: @35153 16173 GIM_Try, /*On fail goto*//*Label 1438*/ 35233, 16174 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 16175 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32, 16176 GIM_Try, /*On fail goto*//*Label 1439*/ 35186, // Rule ID 2642 // 16177 GIM_CheckFeatures, GIFBS_HasAVX_NoVLX, 16178 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 16179 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 16180 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 16181 // (umax:{ *:[v4i32] } VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2) => (VPMAXUDrr:{ *:[v4i32] } VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2) 16182 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMAXUDrr, 16183 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16184 // GIR_Coverage, 2642, 16185 GIR_Done, 16186 // Label 1439: @35186 16187 GIM_Try, /*On fail goto*//*Label 1440*/ 35209, // Rule ID 2684 // 16188 GIM_CheckFeatures, GIFBS_UseSSE41, 16189 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 16190 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 16191 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 16192 // (umax:{ *:[v4i32] } VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2) => (PMAXUDrr:{ *:[v4i32] } VR128:{ *:[v4i32] }:$src1, VR128:{ *:[v4i32] }:$src2) 16193 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::PMAXUDrr, 16194 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16195 // GIR_Coverage, 2684, 16196 GIR_Done, 16197 // Label 1440: @35209 16198 GIM_Try, /*On fail goto*//*Label 1441*/ 35232, // Rule ID 4732 // 16199 GIM_CheckFeatures, GIFBS_HasAVX512_HasVLX, 16200 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 16201 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 16202 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128XRegClassID, 16203 // (umax:{ *:[v4i32] } VR128X:{ *:[v4i32] }:$src1, VR128X:{ *:[v4i32] }:$src2) => (VPMAXUDZ128rr:{ *:[v4i32] } VR128X:{ *:[v4i32] }:$src1, VR128X:{ *:[v4i32] }:$src2) 16204 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMAXUDZ128rr, 16205 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16206 // GIR_Coverage, 4732, 16207 GIR_Done, 16208 // Label 1441: @35232 16209 GIM_Reject, 16210 // Label 1438: @35233 16211 GIM_Reject, 16212 // Label 1426: @35234 16213 GIM_Try, /*On fail goto*//*Label 1442*/ 35265, // Rule ID 4750 // 16214 GIM_CheckFeatures, GIFBS_HasAVX512_HasVLX, 16215 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s64, 16216 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s64, 16217 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 16218 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 16219 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256XRegClassID, 16220 // (umax:{ *:[v4i64] } VR256X:{ *:[v4i64] }:$src1, VR256X:{ *:[v4i64] }:$src2) => (VPMAXUQZ256rr:{ *:[v4i64] } VR256X:{ *:[v4i64] }:$src1, VR256X:{ *:[v4i64] }:$src2) 16221 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMAXUQZ256rr, 16222 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16223 // GIR_Coverage, 4750, 16224 GIR_Done, 16225 // Label 1442: @35265 16226 GIM_Reject, 16227 // Label 1427: @35266 16228 GIM_Try, /*On fail goto*//*Label 1443*/ 35346, 16229 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, 16230 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16, 16231 GIM_Try, /*On fail goto*//*Label 1444*/ 35299, // Rule ID 2652 // 16232 GIM_CheckFeatures, GIFBS_HasAVX_NoVLX_Or_NoBWI, 16233 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 16234 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 16235 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 16236 // (umax:{ *:[v8i16] } VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2) => (VPMAXUWrr:{ *:[v8i16] } VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2) 16237 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMAXUWrr, 16238 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16239 // GIR_Coverage, 2652, 16240 GIR_Done, 16241 // Label 1444: @35299 16242 GIM_Try, /*On fail goto*//*Label 1445*/ 35322, // Rule ID 2686 // 16243 GIM_CheckFeatures, GIFBS_UseSSE41, 16244 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 16245 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 16246 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 16247 // (umax:{ *:[v8i16] } VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2) => (PMAXUWrr:{ *:[v8i16] } VR128:{ *:[v8i16] }:$src1, VR128:{ *:[v8i16] }:$src2) 16248 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::PMAXUWrr, 16249 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16250 // GIR_Coverage, 2686, 16251 GIR_Done, 16252 // Label 1445: @35322 16253 GIM_Try, /*On fail goto*//*Label 1446*/ 35345, // Rule ID 4708 // 16254 GIM_CheckFeatures, GIFBS_HasBWI_HasVLX, 16255 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 16256 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 16257 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128XRegClassID, 16258 // (umax:{ *:[v8i16] } VR128X:{ *:[v8i16] }:$src1, VR128X:{ *:[v8i16] }:$src2) => (VPMAXUWZ128rr:{ *:[v8i16] } VR128X:{ *:[v8i16] }:$src1, VR128X:{ *:[v8i16] }:$src2) 16259 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMAXUWZ128rr, 16260 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16261 // GIR_Coverage, 4708, 16262 GIR_Done, 16263 // Label 1446: @35345 16264 GIM_Reject, 16265 // Label 1443: @35346 16266 GIM_Reject, 16267 // Label 1428: @35347 16268 GIM_Try, /*On fail goto*//*Label 1447*/ 35404, 16269 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s32, 16270 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s32, 16271 GIM_Try, /*On fail goto*//*Label 1448*/ 35380, // Rule ID 2660 // 16272 GIM_CheckFeatures, GIFBS_HasAVX2_NoVLX, 16273 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID, 16274 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256RegClassID, 16275 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID, 16276 // (umax:{ *:[v8i32] } VR256:{ *:[v8i32] }:$src1, VR256:{ *:[v8i32] }:$src2) => (VPMAXUDYrr:{ *:[v8i32] } VR256:{ *:[v8i32] }:$src1, VR256:{ *:[v8i32] }:$src2) 16277 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMAXUDYrr, 16278 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16279 // GIR_Coverage, 2660, 16280 GIR_Done, 16281 // Label 1448: @35380 16282 GIM_Try, /*On fail goto*//*Label 1449*/ 35403, // Rule ID 4723 // 16283 GIM_CheckFeatures, GIFBS_HasAVX512_HasVLX, 16284 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 16285 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 16286 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256XRegClassID, 16287 // (umax:{ *:[v8i32] } VR256X:{ *:[v8i32] }:$src1, VR256X:{ *:[v8i32] }:$src2) => (VPMAXUDZ256rr:{ *:[v8i32] } VR256X:{ *:[v8i32] }:$src1, VR256X:{ *:[v8i32] }:$src2) 16288 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMAXUDZ256rr, 16289 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16290 // GIR_Coverage, 4723, 16291 GIR_Done, 16292 // Label 1449: @35403 16293 GIM_Reject, 16294 // Label 1447: @35404 16295 GIM_Reject, 16296 // Label 1429: @35405 16297 GIM_Try, /*On fail goto*//*Label 1450*/ 35436, // Rule ID 4741 // 16298 GIM_CheckFeatures, GIFBS_HasAVX512, 16299 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s64, 16300 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s64, 16301 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 16302 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID, 16303 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR512RegClassID, 16304 // (umax:{ *:[v8i64] } VR512:{ *:[v8i64] }:$src1, VR512:{ *:[v8i64] }:$src2) => (VPMAXUQZrr:{ *:[v8i64] } VR512:{ *:[v8i64] }:$src1, VR512:{ *:[v8i64] }:$src2) 16305 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMAXUQZrr, 16306 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16307 // GIR_Coverage, 4741, 16308 GIR_Done, 16309 // Label 1450: @35436 16310 GIM_Reject, 16311 // Label 1430: @35437 16312 GIM_Try, /*On fail goto*//*Label 1451*/ 35517, 16313 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, 16314 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8, 16315 GIM_Try, /*On fail goto*//*Label 1452*/ 35470, // Rule ID 2107 // 16316 GIM_CheckFeatures, GIFBS_HasAVX_NoVLX_Or_NoBWI, 16317 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 16318 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 16319 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 16320 // (umax:{ *:[v16i8] } VR128:{ *:[v16i8] }:$src1, VR128:{ *:[v16i8] }:$src2) => (VPMAXUBrr:{ *:[v16i8] } VR128:{ *:[v16i8] }:$src1, VR128:{ *:[v16i8] }:$src2) 16321 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMAXUBrr, 16322 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16323 // GIR_Coverage, 2107, 16324 GIR_Done, 16325 // Label 1452: @35470 16326 GIM_Try, /*On fail goto*//*Label 1453*/ 35493, // Rule ID 2109 // 16327 GIM_CheckFeatures, GIFBS_UseSSE2, 16328 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 16329 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 16330 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128RegClassID, 16331 // (umax:{ *:[v16i8] } VR128:{ *:[v16i8] }:$src1, VR128:{ *:[v16i8] }:$src2) => (PMAXUBrr:{ *:[v16i8] } VR128:{ *:[v16i8] }:$src1, VR128:{ *:[v16i8] }:$src2) 16332 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::PMAXUBrr, 16333 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16334 // GIR_Coverage, 2109, 16335 GIR_Done, 16336 // Label 1453: @35493 16337 GIM_Try, /*On fail goto*//*Label 1454*/ 35516, // Rule ID 4690 // 16338 GIM_CheckFeatures, GIFBS_HasBWI_HasVLX, 16339 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 16340 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 16341 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR128XRegClassID, 16342 // (umax:{ *:[v16i8] } VR128X:{ *:[v16i8] }:$src1, VR128X:{ *:[v16i8] }:$src2) => (VPMAXUBZ128rr:{ *:[v16i8] } VR128X:{ *:[v16i8] }:$src1, VR128X:{ *:[v16i8] }:$src2) 16343 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMAXUBZ128rr, 16344 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16345 // GIR_Coverage, 4690, 16346 GIR_Done, 16347 // Label 1454: @35516 16348 GIM_Reject, 16349 // Label 1451: @35517 16350 GIM_Reject, 16351 // Label 1431: @35518 16352 GIM_Try, /*On fail goto*//*Label 1455*/ 35575, 16353 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s16, 16354 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s16, 16355 GIM_Try, /*On fail goto*//*Label 1456*/ 35551, // Rule ID 2670 // 16356 GIM_CheckFeatures, GIFBS_HasAVX2_NoVLX_Or_NoBWI, 16357 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID, 16358 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256RegClassID, 16359 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID, 16360 // (umax:{ *:[v16i16] } VR256:{ *:[v16i16] }:$src1, VR256:{ *:[v16i16] }:$src2) => (VPMAXUWYrr:{ *:[v16i16] } VR256:{ *:[v16i16] }:$src1, VR256:{ *:[v16i16] }:$src2) 16361 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMAXUWYrr, 16362 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16363 // GIR_Coverage, 2670, 16364 GIR_Done, 16365 // Label 1456: @35551 16366 GIM_Try, /*On fail goto*//*Label 1457*/ 35574, // Rule ID 4702 // 16367 GIM_CheckFeatures, GIFBS_HasBWI_HasVLX, 16368 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 16369 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 16370 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256XRegClassID, 16371 // (umax:{ *:[v16i16] } VR256X:{ *:[v16i16] }:$src1, VR256X:{ *:[v16i16] }:$src2) => (VPMAXUWZ256rr:{ *:[v16i16] } VR256X:{ *:[v16i16] }:$src1, VR256X:{ *:[v16i16] }:$src2) 16372 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMAXUWZ256rr, 16373 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16374 // GIR_Coverage, 4702, 16375 GIR_Done, 16376 // Label 1457: @35574 16377 GIM_Reject, 16378 // Label 1455: @35575 16379 GIM_Reject, 16380 // Label 1432: @35576 16381 GIM_Try, /*On fail goto*//*Label 1458*/ 35607, // Rule ID 4714 // 16382 GIM_CheckFeatures, GIFBS_HasAVX512, 16383 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s32, 16384 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s32, 16385 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 16386 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID, 16387 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR512RegClassID, 16388 // (umax:{ *:[v16i32] } VR512:{ *:[v16i32] }:$src1, VR512:{ *:[v16i32] }:$src2) => (VPMAXUDZrr:{ *:[v16i32] } VR512:{ *:[v16i32] }:$src1, VR512:{ *:[v16i32] }:$src2) 16389 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMAXUDZrr, 16390 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16391 // GIR_Coverage, 4714, 16392 GIR_Done, 16393 // Label 1458: @35607 16394 GIM_Reject, 16395 // Label 1433: @35608 16396 GIM_Try, /*On fail goto*//*Label 1459*/ 35665, 16397 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v32s8, 16398 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v32s8, 16399 GIM_Try, /*On fail goto*//*Label 1460*/ 35641, // Rule ID 2111 // 16400 GIM_CheckFeatures, GIFBS_HasAVX2_NoVLX_Or_NoBWI, 16401 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID, 16402 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256RegClassID, 16403 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256RegClassID, 16404 // (umax:{ *:[v32i8] } VR256:{ *:[v32i8] }:$src1, VR256:{ *:[v32i8] }:$src2) => (VPMAXUBYrr:{ *:[v32i8] } VR256:{ *:[v32i8] }:$src1, VR256:{ *:[v32i8] }:$src2) 16405 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMAXUBYrr, 16406 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16407 // GIR_Coverage, 2111, 16408 GIR_Done, 16409 // Label 1460: @35641 16410 GIM_Try, /*On fail goto*//*Label 1461*/ 35664, // Rule ID 4684 // 16411 GIM_CheckFeatures, GIFBS_HasBWI_HasVLX, 16412 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 16413 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 16414 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR256XRegClassID, 16415 // (umax:{ *:[v32i8] } VR256X:{ *:[v32i8] }:$src1, VR256X:{ *:[v32i8] }:$src2) => (VPMAXUBZ256rr:{ *:[v32i8] } VR256X:{ *:[v32i8] }:$src1, VR256X:{ *:[v32i8] }:$src2) 16416 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMAXUBZ256rr, 16417 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16418 // GIR_Coverage, 4684, 16419 GIR_Done, 16420 // Label 1461: @35664 16421 GIM_Reject, 16422 // Label 1459: @35665 16423 GIM_Reject, 16424 // Label 1434: @35666 16425 GIM_Try, /*On fail goto*//*Label 1462*/ 35697, // Rule ID 4696 // 16426 GIM_CheckFeatures, GIFBS_HasBWI, 16427 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v32s16, 16428 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v32s16, 16429 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 16430 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID, 16431 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR512RegClassID, 16432 // (umax:{ *:[v32i16] } VR512:{ *:[v32i16] }:$src1, VR512:{ *:[v32i16] }:$src2) => (VPMAXUWZrr:{ *:[v32i16] } VR512:{ *:[v32i16] }:$src1, VR512:{ *:[v32i16] }:$src2) 16433 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMAXUWZrr, 16434 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16435 // GIR_Coverage, 4696, 16436 GIR_Done, 16437 // Label 1462: @35697 16438 GIM_Reject, 16439 // Label 1435: @35698 16440 GIM_Try, /*On fail goto*//*Label 1463*/ 35729, // Rule ID 4678 // 16441 GIM_CheckFeatures, GIFBS_HasBWI, 16442 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v64s8, 16443 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v64s8, 16444 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 16445 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID, 16446 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/X86::VR512RegClassID, 16447 // (umax:{ *:[v64i8] } VR512:{ *:[v64i8] }:$src1, VR512:{ *:[v64i8] }:$src2) => (VPMAXUBZrr:{ *:[v64i8] } VR512:{ *:[v64i8] }:$src1, VR512:{ *:[v64i8] }:$src2) 16448 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPMAXUBZrr, 16449 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16450 // GIR_Coverage, 4678, 16451 GIR_Done, 16452 // Label 1463: @35729 16453 GIM_Reject, 16454 // Label 1436: @35730 16455 GIM_Reject, 16456 // Label 37: @35731 16457 GIM_Try, /*On fail goto*//*Label 1464*/ 35743, // Rule ID 424 // 16458 // MIs[0] dst 16459 GIM_CheckIsMBB, /*MI*/0, /*Op*/0, 16460 // (br (bb:{ *:[Other] }):$dst) => (JMP_1 (bb:{ *:[Other] }):$dst) 16461 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::JMP_1, 16462 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16463 // GIR_Coverage, 424, 16464 GIR_Done, 16465 // Label 1464: @35743 16466 GIM_Reject, 16467 // Label 38: @35744 16468 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/2, 5, /*)*//*default:*//*Label 1468*/ 35828, 16469 /*GILLT_s16*//*Label 1465*/ 35753, 16470 /*GILLT_s32*//*Label 1466*/ 35778, 16471 /*GILLT_s64*//*Label 1467*/ 35803, 16472 // Label 1465: @35753 16473 GIM_Try, /*On fail goto*//*Label 1469*/ 35777, // Rule ID 17396 // 16474 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, 16475 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR16RegClassID, 16476 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR16RegClassID, 16477 // (cttz_zero_undef:{ *:[i16] } GR16:{ *:[i16] }:$src) => (BSF16rr:{ *:[i16] }:{ *:[i32] } GR16:{ *:[i16] }:$src) 16478 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::BSF16rr, 16479 GIR_AddImplicitDef, /*InsnID*/0, X86::EFLAGS, 16480 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16481 // GIR_Coverage, 17396, 16482 GIR_Done, 16483 // Label 1469: @35777 16484 GIM_Reject, 16485 // Label 1466: @35778 16486 GIM_Try, /*On fail goto*//*Label 1470*/ 35802, // Rule ID 17397 // 16487 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 16488 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 16489 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR32RegClassID, 16490 // (cttz_zero_undef:{ *:[i32] } GR32:{ *:[i32] }:$src) => (BSF32rr:{ *:[i32] }:{ *:[i32] } GR32:{ *:[i32] }:$src) 16491 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::BSF32rr, 16492 GIR_AddImplicitDef, /*InsnID*/0, X86::EFLAGS, 16493 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16494 // GIR_Coverage, 17397, 16495 GIR_Done, 16496 // Label 1470: @35802 16497 GIM_Reject, 16498 // Label 1467: @35803 16499 GIM_Try, /*On fail goto*//*Label 1471*/ 35827, // Rule ID 17398 // 16500 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 16501 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID, 16502 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR64RegClassID, 16503 // (cttz_zero_undef:{ *:[i64] } GR64:{ *:[i64] }:$src) => (BSF64rr:{ *:[i64] }:{ *:[i32] } GR64:{ *:[i64] }:$src) 16504 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::BSF64rr, 16505 GIR_AddImplicitDef, /*InsnID*/0, X86::EFLAGS, 16506 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16507 // GIR_Coverage, 17398, 16508 GIR_Done, 16509 // Label 1471: @35827 16510 GIM_Reject, 16511 // Label 1468: @35828 16512 GIM_Reject, 16513 // Label 39: @35829 16514 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/8, 20, /*)*//*default:*//*Label 1478*/ 35991, 16515 /*GILLT_v2s64*//*Label 1472*/ 35847, 0, 16516 /*GILLT_v4s32*//*Label 1473*/ 35871, 16517 /*GILLT_v4s64*//*Label 1474*/ 35895, 0, 0, 16518 /*GILLT_v8s32*//*Label 1475*/ 35919, 16519 /*GILLT_v8s64*//*Label 1476*/ 35943, 0, 0, 0, 16520 /*GILLT_v16s32*//*Label 1477*/ 35967, 16521 // Label 1472: @35847 16522 GIM_Try, /*On fail goto*//*Label 1479*/ 35870, // Rule ID 11204 // 16523 GIM_CheckFeatures, GIFBS_HasCDI_HasVLX, 16524 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, 16525 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 16526 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 16527 // (ctlz:{ *:[v2i64] } VR128X:{ *:[v2i64] }:$src1) => (VPLZCNTQZ128rr:{ *:[v2i64] } VR128X:{ *:[v2i64] }:$src1) 16528 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPLZCNTQZ128rr, 16529 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16530 // GIR_Coverage, 11204, 16531 GIR_Done, 16532 // Label 1479: @35870 16533 GIM_Reject, 16534 // Label 1473: @35871 16535 GIM_Try, /*On fail goto*//*Label 1480*/ 35894, // Rule ID 11231 // 16536 GIM_CheckFeatures, GIFBS_HasCDI_HasVLX, 16537 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 16538 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 16539 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 16540 // (ctlz:{ *:[v4i32] } VR128X:{ *:[v4i32] }:$src1) => (VPLZCNTDZ128rr:{ *:[v4i32] } VR128X:{ *:[v4i32] }:$src1) 16541 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPLZCNTDZ128rr, 16542 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16543 // GIR_Coverage, 11231, 16544 GIR_Done, 16545 // Label 1480: @35894 16546 GIM_Reject, 16547 // Label 1474: @35895 16548 GIM_Try, /*On fail goto*//*Label 1481*/ 35918, // Rule ID 11195 // 16549 GIM_CheckFeatures, GIFBS_HasCDI_HasVLX, 16550 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s64, 16551 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 16552 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 16553 // (ctlz:{ *:[v4i64] } VR256X:{ *:[v4i64] }:$src1) => (VPLZCNTQZ256rr:{ *:[v4i64] } VR256X:{ *:[v4i64] }:$src1) 16554 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPLZCNTQZ256rr, 16555 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16556 // GIR_Coverage, 11195, 16557 GIR_Done, 16558 // Label 1481: @35918 16559 GIM_Reject, 16560 // Label 1475: @35919 16561 GIM_Try, /*On fail goto*//*Label 1482*/ 35942, // Rule ID 11222 // 16562 GIM_CheckFeatures, GIFBS_HasCDI_HasVLX, 16563 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s32, 16564 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 16565 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 16566 // (ctlz:{ *:[v8i32] } VR256X:{ *:[v8i32] }:$src1) => (VPLZCNTDZ256rr:{ *:[v8i32] } VR256X:{ *:[v8i32] }:$src1) 16567 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPLZCNTDZ256rr, 16568 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16569 // GIR_Coverage, 11222, 16570 GIR_Done, 16571 // Label 1482: @35942 16572 GIM_Reject, 16573 // Label 1476: @35943 16574 GIM_Try, /*On fail goto*//*Label 1483*/ 35966, // Rule ID 11186 // 16575 GIM_CheckFeatures, GIFBS_HasCDI, 16576 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s64, 16577 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 16578 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID, 16579 // (ctlz:{ *:[v8i64] } VR512:{ *:[v8i64] }:$src1) => (VPLZCNTQZrr:{ *:[v8i64] } VR512:{ *:[v8i64] }:$src1) 16580 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPLZCNTQZrr, 16581 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16582 // GIR_Coverage, 11186, 16583 GIR_Done, 16584 // Label 1483: @35966 16585 GIM_Reject, 16586 // Label 1477: @35967 16587 GIM_Try, /*On fail goto*//*Label 1484*/ 35990, // Rule ID 11213 // 16588 GIM_CheckFeatures, GIFBS_HasCDI, 16589 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s32, 16590 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 16591 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID, 16592 // (ctlz:{ *:[v16i32] } VR512:{ *:[v16i32] }:$src1) => (VPLZCNTDZrr:{ *:[v16i32] } VR512:{ *:[v16i32] }:$src1) 16593 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPLZCNTDZrr, 16594 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16595 // GIR_Coverage, 11213, 16596 GIR_Done, 16597 // Label 1484: @35990 16598 GIM_Reject, 16599 // Label 1478: @35991 16600 GIM_Reject, 16601 // Label 40: @35992 16602 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/8, 25, /*)*//*default:*//*Label 1497*/ 36303, 16603 /*GILLT_v2s64*//*Label 1485*/ 36015, 0, 16604 /*GILLT_v4s32*//*Label 1486*/ 36039, 16605 /*GILLT_v4s64*//*Label 1487*/ 36063, 0, 16606 /*GILLT_v8s16*//*Label 1488*/ 36087, 16607 /*GILLT_v8s32*//*Label 1489*/ 36111, 16608 /*GILLT_v8s64*//*Label 1490*/ 36135, 0, 16609 /*GILLT_v16s8*//*Label 1491*/ 36159, 16610 /*GILLT_v16s16*//*Label 1492*/ 36183, 16611 /*GILLT_v16s32*//*Label 1493*/ 36207, 0, 16612 /*GILLT_v32s8*//*Label 1494*/ 36231, 16613 /*GILLT_v32s16*//*Label 1495*/ 36255, 0, 16614 /*GILLT_v64s8*//*Label 1496*/ 36279, 16615 // Label 1485: @36015 16616 GIM_Try, /*On fail goto*//*Label 1498*/ 36038, // Rule ID 11312 // 16617 GIM_CheckFeatures, GIFBS_HasVLX_HasVPOPCNTDQ, 16618 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, 16619 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 16620 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 16621 // (ctpop:{ *:[v2i64] } VR128X:{ *:[v2i64] }:$src1) => (VPOPCNTQZ128rr:{ *:[v2i64] } VR128X:{ *:[v2i64] }:$src1) 16622 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPOPCNTQZ128rr, 16623 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16624 // GIR_Coverage, 11312, 16625 GIR_Done, 16626 // Label 1498: @36038 16627 GIM_Reject, 16628 // Label 1486: @36039 16629 GIM_Try, /*On fail goto*//*Label 1499*/ 36062, // Rule ID 11339 // 16630 GIM_CheckFeatures, GIFBS_HasVLX_HasVPOPCNTDQ, 16631 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 16632 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 16633 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 16634 // (ctpop:{ *:[v4i32] } VR128X:{ *:[v4i32] }:$src1) => (VPOPCNTDZ128rr:{ *:[v4i32] } VR128X:{ *:[v4i32] }:$src1) 16635 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPOPCNTDZ128rr, 16636 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16637 // GIR_Coverage, 11339, 16638 GIR_Done, 16639 // Label 1499: @36062 16640 GIM_Reject, 16641 // Label 1487: @36063 16642 GIM_Try, /*On fail goto*//*Label 1500*/ 36086, // Rule ID 11303 // 16643 GIM_CheckFeatures, GIFBS_HasVLX_HasVPOPCNTDQ, 16644 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s64, 16645 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 16646 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 16647 // (ctpop:{ *:[v4i64] } VR256X:{ *:[v4i64] }:$src1) => (VPOPCNTQZ256rr:{ *:[v4i64] } VR256X:{ *:[v4i64] }:$src1) 16648 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPOPCNTQZ256rr, 16649 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16650 // GIR_Coverage, 11303, 16651 GIR_Done, 16652 // Label 1500: @36086 16653 GIM_Reject, 16654 // Label 1488: @36087 16655 GIM_Try, /*On fail goto*//*Label 1501*/ 36110, // Rule ID 12366 // 16656 GIM_CheckFeatures, GIFBS_HasBITALG_HasVLX, 16657 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16, 16658 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 16659 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 16660 // (ctpop:{ *:[v8i16] } VR128X:{ *:[v8i16] }:$src1) => (VPOPCNTWZ128rr:{ *:[v8i16] } VR128X:{ *:[v8i16] }:$src1) 16661 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPOPCNTWZ128rr, 16662 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16663 // GIR_Coverage, 12366, 16664 GIR_Done, 16665 // Label 1501: @36110 16666 GIM_Reject, 16667 // Label 1489: @36111 16668 GIM_Try, /*On fail goto*//*Label 1502*/ 36134, // Rule ID 11330 // 16669 GIM_CheckFeatures, GIFBS_HasVLX_HasVPOPCNTDQ, 16670 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s32, 16671 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 16672 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 16673 // (ctpop:{ *:[v8i32] } VR256X:{ *:[v8i32] }:$src1) => (VPOPCNTDZ256rr:{ *:[v8i32] } VR256X:{ *:[v8i32] }:$src1) 16674 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPOPCNTDZ256rr, 16675 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16676 // GIR_Coverage, 11330, 16677 GIR_Done, 16678 // Label 1502: @36134 16679 GIM_Reject, 16680 // Label 1490: @36135 16681 GIM_Try, /*On fail goto*//*Label 1503*/ 36158, // Rule ID 11294 // 16682 GIM_CheckFeatures, GIFBS_HasVPOPCNTDQ, 16683 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s64, 16684 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 16685 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID, 16686 // (ctpop:{ *:[v8i64] } VR512:{ *:[v8i64] }:$src1) => (VPOPCNTQZrr:{ *:[v8i64] } VR512:{ *:[v8i64] }:$src1) 16687 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPOPCNTQZrr, 16688 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16689 // GIR_Coverage, 11294, 16690 GIR_Done, 16691 // Label 1503: @36158 16692 GIM_Reject, 16693 // Label 1491: @36159 16694 GIM_Try, /*On fail goto*//*Label 1504*/ 36182, // Rule ID 12348 // 16695 GIM_CheckFeatures, GIFBS_HasBITALG_HasVLX, 16696 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8, 16697 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 16698 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 16699 // (ctpop:{ *:[v16i8] } VR128X:{ *:[v16i8] }:$src1) => (VPOPCNTBZ128rr:{ *:[v16i8] } VR128X:{ *:[v16i8] }:$src1) 16700 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPOPCNTBZ128rr, 16701 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16702 // GIR_Coverage, 12348, 16703 GIR_Done, 16704 // Label 1504: @36182 16705 GIM_Reject, 16706 // Label 1492: @36183 16707 GIM_Try, /*On fail goto*//*Label 1505*/ 36206, // Rule ID 12360 // 16708 GIM_CheckFeatures, GIFBS_HasBITALG_HasVLX, 16709 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s16, 16710 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 16711 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 16712 // (ctpop:{ *:[v16i16] } VR256X:{ *:[v16i16] }:$src1) => (VPOPCNTWZ256rr:{ *:[v16i16] } VR256X:{ *:[v16i16] }:$src1) 16713 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPOPCNTWZ256rr, 16714 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16715 // GIR_Coverage, 12360, 16716 GIR_Done, 16717 // Label 1505: @36206 16718 GIM_Reject, 16719 // Label 1493: @36207 16720 GIM_Try, /*On fail goto*//*Label 1506*/ 36230, // Rule ID 11321 // 16721 GIM_CheckFeatures, GIFBS_HasVPOPCNTDQ, 16722 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s32, 16723 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 16724 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID, 16725 // (ctpop:{ *:[v16i32] } VR512:{ *:[v16i32] }:$src1) => (VPOPCNTDZrr:{ *:[v16i32] } VR512:{ *:[v16i32] }:$src1) 16726 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPOPCNTDZrr, 16727 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16728 // GIR_Coverage, 11321, 16729 GIR_Done, 16730 // Label 1506: @36230 16731 GIM_Reject, 16732 // Label 1494: @36231 16733 GIM_Try, /*On fail goto*//*Label 1507*/ 36254, // Rule ID 12342 // 16734 GIM_CheckFeatures, GIFBS_HasBITALG_HasVLX, 16735 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v32s8, 16736 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 16737 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 16738 // (ctpop:{ *:[v32i8] } VR256X:{ *:[v32i8] }:$src1) => (VPOPCNTBZ256rr:{ *:[v32i8] } VR256X:{ *:[v32i8] }:$src1) 16739 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPOPCNTBZ256rr, 16740 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16741 // GIR_Coverage, 12342, 16742 GIR_Done, 16743 // Label 1507: @36254 16744 GIM_Reject, 16745 // Label 1495: @36255 16746 GIM_Try, /*On fail goto*//*Label 1508*/ 36278, // Rule ID 12354 // 16747 GIM_CheckFeatures, GIFBS_HasBITALG, 16748 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v32s16, 16749 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 16750 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID, 16751 // (ctpop:{ *:[v32i16] } VR512:{ *:[v32i16] }:$src1) => (VPOPCNTWZrr:{ *:[v32i16] } VR512:{ *:[v32i16] }:$src1) 16752 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPOPCNTWZrr, 16753 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16754 // GIR_Coverage, 12354, 16755 GIR_Done, 16756 // Label 1508: @36278 16757 GIM_Reject, 16758 // Label 1496: @36279 16759 GIM_Try, /*On fail goto*//*Label 1509*/ 36302, // Rule ID 12336 // 16760 GIM_CheckFeatures, GIFBS_HasBITALG, 16761 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v64s8, 16762 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 16763 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID, 16764 // (ctpop:{ *:[v64i8] } VR512:{ *:[v64i8] }:$src1) => (VPOPCNTBZrr:{ *:[v64i8] } VR512:{ *:[v64i8] }:$src1) 16765 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VPOPCNTBZrr, 16766 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16767 // GIR_Coverage, 12336, 16768 GIR_Done, 16769 // Label 1509: @36302 16770 GIM_Reject, 16771 // Label 1497: @36303 16772 GIM_Reject, 16773 // Label 41: @36304 16774 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/2, 5, /*)*//*default:*//*Label 1513*/ 36393, 16775 /*GILLT_s16*//*Label 1510*/ 36313, 16776 /*GILLT_s32*//*Label 1511*/ 36349, 16777 /*GILLT_s64*//*Label 1512*/ 36371, 16778 // Label 1510: @36313 16779 GIM_Try, /*On fail goto*//*Label 1514*/ 36348, // Rule ID 17402 // 16780 GIM_CheckFeatures, GIFBS_HasMOVBE, 16781 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, 16782 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR16RegClassID, 16783 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR16RegClassID, 16784 // (bswap:{ *:[i16] } GR16:{ *:[i16] }:$src) => (ROL16ri:{ *:[i16] }:{ *:[i32] } GR16:{ *:[i16] }:$src, 8:{ *:[i8] }) 16785 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::ROL16ri, 16786 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 16787 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 16788 GIR_AddImm, /*InsnID*/0, /*Imm*/8, 16789 GIR_EraseFromParent, /*InsnID*/0, 16790 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16791 // GIR_Coverage, 17402, 16792 GIR_Done, 16793 // Label 1514: @36348 16794 GIM_Reject, 16795 // Label 1511: @36349 16796 GIM_Try, /*On fail goto*//*Label 1515*/ 36370, // Rule ID 5 // 16797 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 16798 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR32RegClassID, 16799 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR32RegClassID, 16800 // (bswap:{ *:[i32] } GR32:{ *:[i32] }:$src) => (BSWAP32r:{ *:[i32] } GR32:{ *:[i32] }:$src) 16801 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::BSWAP32r, 16802 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16803 // GIR_Coverage, 5, 16804 GIR_Done, 16805 // Label 1515: @36370 16806 GIM_Reject, 16807 // Label 1512: @36371 16808 GIM_Try, /*On fail goto*//*Label 1516*/ 36392, // Rule ID 6 // 16809 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 16810 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::GR64RegClassID, 16811 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::GR64RegClassID, 16812 // (bswap:{ *:[i64] } GR64:{ *:[i64] }:$src) => (BSWAP64r:{ *:[i64] } GR64:{ *:[i64] }:$src) 16813 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::BSWAP64r, 16814 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16815 // GIR_Coverage, 6, 16816 GIR_Done, 16817 // Label 1516: @36392 16818 GIM_Reject, 16819 // Label 1513: @36393 16820 GIM_Reject, 16821 // Label 42: @36394 16822 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/3, 20, /*)*//*default:*//*Label 1526*/ 37037, 16823 /*GILLT_s32*//*Label 1517*/ 36417, 16824 /*GILLT_s64*//*Label 1518*/ 36560, 16825 /*GILLT_s80*//*Label 1519*/ 36703, 0, 0, 16826 /*GILLT_v2s64*//*Label 1520*/ 36731, 0, 16827 /*GILLT_v4s32*//*Label 1521*/ 36805, 16828 /*GILLT_v4s64*//*Label 1522*/ 36879, 0, 0, 16829 /*GILLT_v8s32*//*Label 1523*/ 36931, 16830 /*GILLT_v8s64*//*Label 1524*/ 36983, 0, 0, 0, 16831 /*GILLT_v16s32*//*Label 1525*/ 37010, 16832 // Label 1517: @36417 16833 GIM_Try, /*On fail goto*//*Label 1527*/ 36559, 16834 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 16835 GIM_Try, /*On fail goto*//*Label 1528*/ 36448, // Rule ID 768 // 16836 GIM_CheckFeatures, GIFBS_FPStackf32, 16837 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::RFP32RegClassID, 16838 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::RFP32RegClassID, 16839 // (fsqrt:{ *:[f32] } RFP32:{ *:[f32] }:$src) => (SQRT_Fp32:{ *:[f32] }:{ *:[i16] } RFP32:{ *:[f32] }:$src) 16840 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::SQRT_Fp32, 16841 GIR_AddImplicitDef, /*InsnID*/0, X86::FPSW, 16842 GIR_AddImplicitUse, /*InsnID*/0, X86::FPCW, 16843 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16844 // GIR_Coverage, 768, 16845 GIR_Done, 16846 // Label 1528: @36448 16847 GIM_Try, /*On fail goto*//*Label 1529*/ 36470, // Rule ID 1906 // 16848 GIM_CheckFeatures, GIFBS_UseSSE1, 16849 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::FR32RegClassID, 16850 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR32RegClassID, 16851 // (fsqrt:{ *:[f32] } FR32:{ *:[f32] }:$src1) => (SQRTSSr:{ *:[f32] } FR32:{ *:[f32] }:$src1) 16852 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::SQRTSSr, 16853 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 16854 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16855 // GIR_Coverage, 1906, 16856 GIR_Done, 16857 // Label 1529: @36470 16858 GIM_Try, /*On fail goto*//*Label 1530*/ 36514, // Rule ID 13588 // 16859 GIM_CheckFeatures, GIFBS_UseAVX, 16860 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::FR32RegClassID, 16861 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR32RegClassID, 16862 // (fsqrt:{ *:[f32] } FR32:{ *:[f32] }:$src) => (VSQRTSSr:{ *:[f32] } (IMPLICIT_DEF:{ *:[f32] }), FR32:{ *:[f32] }:$src) 16863 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, 16864 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, 16865 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 16866 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 16867 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VSQRTSSr, 16868 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 16869 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 16870 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 16871 GIR_EraseFromParent, /*InsnID*/0, 16872 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16873 // GIR_Coverage, 13588, 16874 GIR_Done, 16875 // Label 1530: @36514 16876 GIM_Try, /*On fail goto*//*Label 1531*/ 36558, // Rule ID 16241 // 16877 GIM_CheckFeatures, GIFBS_HasAVX512, 16878 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::FR32XRegClassID, 16879 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR32XRegClassID, 16880 // (fsqrt:{ *:[f32] } FR32X:{ *:[f32] }:$src) => (VSQRTSSZr:{ *:[f32] } (IMPLICIT_DEF:{ *:[f32] }), FR32X:{ *:[f32] }:$src) 16881 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, 16882 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, 16883 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 16884 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 16885 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VSQRTSSZr, 16886 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 16887 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 16888 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 16889 GIR_EraseFromParent, /*InsnID*/0, 16890 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16891 // GIR_Coverage, 16241, 16892 GIR_Done, 16893 // Label 1531: @36558 16894 GIM_Reject, 16895 // Label 1527: @36559 16896 GIM_Reject, 16897 // Label 1518: @36560 16898 GIM_Try, /*On fail goto*//*Label 1532*/ 36702, 16899 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 16900 GIM_Try, /*On fail goto*//*Label 1533*/ 36591, // Rule ID 770 // 16901 GIM_CheckFeatures, GIFBS_FPStackf64, 16902 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::RFP64RegClassID, 16903 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::RFP64RegClassID, 16904 // (fsqrt:{ *:[f64] } RFP64:{ *:[f64] }:$src) => (SQRT_Fp64:{ *:[f64] }:{ *:[i16] } RFP64:{ *:[f64] }:$src) 16905 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::SQRT_Fp64, 16906 GIR_AddImplicitDef, /*InsnID*/0, X86::FPSW, 16907 GIR_AddImplicitUse, /*InsnID*/0, X86::FPCW, 16908 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16909 // GIR_Coverage, 770, 16910 GIR_Done, 16911 // Label 1533: @36591 16912 GIM_Try, /*On fail goto*//*Label 1534*/ 36613, // Rule ID 1922 // 16913 GIM_CheckFeatures, GIFBS_UseSSE2, 16914 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::FR64RegClassID, 16915 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR64RegClassID, 16916 // (fsqrt:{ *:[f64] } FR64:{ *:[f64] }:$src1) => (SQRTSDr:{ *:[f64] } FR64:{ *:[f64] }:$src1) 16917 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::SQRTSDr, 16918 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 16919 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16920 // GIR_Coverage, 1922, 16921 GIR_Done, 16922 // Label 1534: @36613 16923 GIM_Try, /*On fail goto*//*Label 1535*/ 36657, // Rule ID 13592 // 16924 GIM_CheckFeatures, GIFBS_UseAVX, 16925 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::FR64RegClassID, 16926 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR64RegClassID, 16927 // (fsqrt:{ *:[f64] } FR64:{ *:[f64] }:$src) => (VSQRTSDr:{ *:[f64] } (IMPLICIT_DEF:{ *:[f64] }), FR64:{ *:[f64] }:$src) 16928 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, 16929 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, 16930 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 16931 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 16932 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VSQRTSDr, 16933 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 16934 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 16935 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 16936 GIR_EraseFromParent, /*InsnID*/0, 16937 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16938 // GIR_Coverage, 13592, 16939 GIR_Done, 16940 // Label 1535: @36657 16941 GIM_Try, /*On fail goto*//*Label 1536*/ 36701, // Rule ID 16245 // 16942 GIM_CheckFeatures, GIFBS_HasAVX512, 16943 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::FR64XRegClassID, 16944 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::FR64XRegClassID, 16945 // (fsqrt:{ *:[f64] } FR64X:{ *:[f64] }:$src) => (VSQRTSDZr:{ *:[f64] } (IMPLICIT_DEF:{ *:[f64] }), FR64X:{ *:[f64] }:$src) 16946 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, 16947 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::IMPLICIT_DEF, 16948 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 16949 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 16950 GIR_BuildMI, /*InsnID*/0, /*Opcode*/X86::VSQRTSDZr, 16951 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst 16952 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 16953 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src 16954 GIR_EraseFromParent, /*InsnID*/0, 16955 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16956 // GIR_Coverage, 16245, 16957 GIR_Done, 16958 // Label 1536: @36701 16959 GIM_Reject, 16960 // Label 1532: @36702 16961 GIM_Reject, 16962 // Label 1519: @36703 16963 GIM_Try, /*On fail goto*//*Label 1537*/ 36730, // Rule ID 772 // 16964 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s80, 16965 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::RFP80RegClassID, 16966 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::RFP80RegClassID, 16967 // (fsqrt:{ *:[f80] } RFP80:{ *:[f80] }:$src) => (SQRT_Fp80:{ *:[f80] }:{ *:[i16] } RFP80:{ *:[f80] }:$src) 16968 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::SQRT_Fp80, 16969 GIR_AddImplicitDef, /*InsnID*/0, X86::FPSW, 16970 GIR_AddImplicitUse, /*InsnID*/0, X86::FPCW, 16971 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16972 // GIR_Coverage, 772, 16973 GIR_Done, 16974 // Label 1537: @36730 16975 GIM_Reject, 16976 // Label 1520: @36731 16977 GIM_Try, /*On fail goto*//*Label 1538*/ 36804, 16978 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64, 16979 GIM_Try, /*On fail goto*//*Label 1539*/ 36759, // Rule ID 1926 // 16980 GIM_CheckFeatures, GIFBS_HasAVX_NoVLX, 16981 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 16982 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 16983 // (fsqrt:{ *:[v2f64] } VR128:{ *:[v2f64] }:$src) => (VSQRTPDr:{ *:[v2f64] } VR128:{ *:[v2f64] }:$src) 16984 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VSQRTPDr, 16985 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 16986 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16987 // GIR_Coverage, 1926, 16988 GIR_Done, 16989 // Label 1539: @36759 16990 GIM_Try, /*On fail goto*//*Label 1540*/ 36781, // Rule ID 1934 // 16991 GIM_CheckFeatures, GIFBS_UseSSE2, 16992 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 16993 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 16994 // (fsqrt:{ *:[v2f64] } VR128:{ *:[v2f64] }:$src) => (SQRTPDr:{ *:[v2f64] } VR128:{ *:[v2f64] }:$src) 16995 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::SQRTPDr, 16996 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 16997 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 16998 // GIR_Coverage, 1934, 16999 GIR_Done, 17000 // Label 1540: @36781 17001 GIM_Try, /*On fail goto*//*Label 1541*/ 36803, // Rule ID 10059 // 17002 GIM_CheckFeatures, GIFBS_HasVLX, 17003 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 17004 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 17005 // (fsqrt:{ *:[v2f64] } VR128X:{ *:[v2f64] }:$src) => (VSQRTPDZ128r:{ *:[v2f64] } VR128X:{ *:[v2f64] }:$src) 17006 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VSQRTPDZ128r, 17007 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 17008 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 17009 // GIR_Coverage, 10059, 17010 GIR_Done, 17011 // Label 1541: @36803 17012 GIM_Reject, 17013 // Label 1538: @36804 17014 GIM_Reject, 17015 // Label 1521: @36805 17016 GIM_Try, /*On fail goto*//*Label 1542*/ 36878, 17017 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32, 17018 GIM_Try, /*On fail goto*//*Label 1543*/ 36833, // Rule ID 1910 // 17019 GIM_CheckFeatures, GIFBS_HasAVX_NoVLX, 17020 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 17021 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 17022 // (fsqrt:{ *:[v4f32] } VR128:{ *:[v4f32] }:$src) => (VSQRTPSr:{ *:[v4f32] } VR128:{ *:[v4f32] }:$src) 17023 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VSQRTPSr, 17024 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 17025 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 17026 // GIR_Coverage, 1910, 17027 GIR_Done, 17028 // Label 1543: @36833 17029 GIM_Try, /*On fail goto*//*Label 1544*/ 36855, // Rule ID 1918 // 17030 GIM_CheckFeatures, GIFBS_UseSSE1, 17031 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128RegClassID, 17032 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128RegClassID, 17033 // (fsqrt:{ *:[v4f32] } VR128:{ *:[v4f32] }:$src) => (SQRTPSr:{ *:[v4f32] } VR128:{ *:[v4f32] }:$src) 17034 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::SQRTPSr, 17035 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 17036 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 17037 // GIR_Coverage, 1918, 17038 GIR_Done, 17039 // Label 1544: @36855 17040 GIM_Try, /*On fail goto*//*Label 1545*/ 36877, // Rule ID 10023 // 17041 GIM_CheckFeatures, GIFBS_HasVLX, 17042 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR128XRegClassID, 17043 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR128XRegClassID, 17044 // (fsqrt:{ *:[v4f32] } VR128X:{ *:[v4f32] }:$src) => (VSQRTPSZ128r:{ *:[v4f32] } VR128X:{ *:[v4f32] }:$src) 17045 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VSQRTPSZ128r, 17046 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 17047 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 17048 // GIR_Coverage, 10023, 17049 GIR_Done, 17050 // Label 1545: @36877 17051 GIM_Reject, 17052 // Label 1542: @36878 17053 GIM_Reject, 17054 // Label 1522: @36879 17055 GIM_Try, /*On fail goto*//*Label 1546*/ 36930, 17056 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s64, 17057 GIM_Try, /*On fail goto*//*Label 1547*/ 36907, // Rule ID 1930 // 17058 GIM_CheckFeatures, GIFBS_HasAVX_NoVLX, 17059 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID, 17060 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256RegClassID, 17061 // (fsqrt:{ *:[v4f64] } VR256:{ *:[v4f64] }:$src) => (VSQRTPDYr:{ *:[v4f64] } VR256:{ *:[v4f64] }:$src) 17062 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VSQRTPDYr, 17063 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 17064 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 17065 // GIR_Coverage, 1930, 17066 GIR_Done, 17067 // Label 1547: @36907 17068 GIM_Try, /*On fail goto*//*Label 1548*/ 36929, // Rule ID 10077 // 17069 GIM_CheckFeatures, GIFBS_HasVLX, 17070 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 17071 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 17072 // (fsqrt:{ *:[v4f64] } VR256X:{ *:[v4f64] }:$src) => (VSQRTPDZ256r:{ *:[v4f64] } VR256X:{ *:[v4f64] }:$src) 17073 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VSQRTPDZ256r, 17074 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 17075 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 17076 // GIR_Coverage, 10077, 17077 GIR_Done, 17078 // Label 1548: @36929 17079 GIM_Reject, 17080 // Label 1546: @36930 17081 GIM_Reject, 17082 // Label 1523: @36931 17083 GIM_Try, /*On fail goto*//*Label 1549*/ 36982, 17084 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s32, 17085 GIM_Try, /*On fail goto*//*Label 1550*/ 36959, // Rule ID 1914 // 17086 GIM_CheckFeatures, GIFBS_HasAVX_NoVLX, 17087 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256RegClassID, 17088 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256RegClassID, 17089 // (fsqrt:{ *:[v8f32] } VR256:{ *:[v8f32] }:$src) => (VSQRTPSYr:{ *:[v8f32] } VR256:{ *:[v8f32] }:$src) 17090 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VSQRTPSYr, 17091 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 17092 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 17093 // GIR_Coverage, 1914, 17094 GIR_Done, 17095 // Label 1550: @36959 17096 GIM_Try, /*On fail goto*//*Label 1551*/ 36981, // Rule ID 10041 // 17097 GIM_CheckFeatures, GIFBS_HasVLX, 17098 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR256XRegClassID, 17099 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR256XRegClassID, 17100 // (fsqrt:{ *:[v8f32] } VR256X:{ *:[v8f32] }:$src) => (VSQRTPSZ256r:{ *:[v8f32] } VR256X:{ *:[v8f32] }:$src) 17101 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VSQRTPSZ256r, 17102 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 17103 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 17104 // GIR_Coverage, 10041, 17105 GIR_Done, 17106 // Label 1551: @36981 17107 GIM_Reject, 17108 // Label 1549: @36982 17109 GIM_Reject, 17110 // Label 1524: @36983 17111 GIM_Try, /*On fail goto*//*Label 1552*/ 37009, // Rule ID 10005 // 17112 GIM_CheckFeatures, GIFBS_HasAVX512, 17113 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s64, 17114 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 17115 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID, 17116 // (fsqrt:{ *:[v8f64] } VR512:{ *:[v8f64] }:$src) => (VSQRTPDZr:{ *:[v8f64] } VR512:{ *:[v8f64] }:$src) 17117 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VSQRTPDZr, 17118 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 17119 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 17120 // GIR_Coverage, 10005, 17121 GIR_Done, 17122 // Label 1552: @37009 17123 GIM_Reject, 17124 // Label 1525: @37010 17125 GIM_Try, /*On fail goto*//*Label 1553*/ 37036, // Rule ID 9987 // 17126 GIM_CheckFeatures, GIFBS_HasAVX512, 17127 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s32, 17128 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/X86::VR512RegClassID, 17129 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/X86::VR512RegClassID, 17130 // (fsqrt:{ *:[v16f32] } VR512:{ *:[v16f32] }:$src) => (VSQRTPSZr:{ *:[v16f32] } VR512:{ *:[v16f32] }:$src) 17131 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/X86::VSQRTPSZr, 17132 GIR_AddImplicitUse, /*InsnID*/0, X86::MXCSR, 17133 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 17134 // GIR_Coverage, 9987, 17135 GIR_Done, 17136 // Label 1553: @37036 17137 GIM_Reject, 17138 // Label 1526: @37037 17139 GIM_Reject, 17140 // Label 43: @37038 17141 GIM_Reject, 17142 }; 17143 return MatchTable0; 17144} 17145#endif // ifdef GET_GLOBALISEL_IMPL 17146#ifdef GET_GLOBALISEL_PREDICATES_DECL 17147PredicateBitset AvailableModuleFeatures; 17148mutable PredicateBitset AvailableFunctionFeatures; 17149PredicateBitset getAvailableFeatures() const { 17150 return AvailableModuleFeatures | AvailableFunctionFeatures; 17151} 17152PredicateBitset 17153computeAvailableModuleFeatures(const X86Subtarget *Subtarget) const; 17154PredicateBitset 17155computeAvailableFunctionFeatures(const X86Subtarget *Subtarget, 17156 const MachineFunction *MF) const; 17157void setupGeneratedPerFunctionState(MachineFunction &MF) override; 17158#endif // ifdef GET_GLOBALISEL_PREDICATES_DECL 17159#ifdef GET_GLOBALISEL_PREDICATES_INIT 17160AvailableModuleFeatures(computeAvailableModuleFeatures(&STI)), 17161AvailableFunctionFeatures() 17162#endif // ifdef GET_GLOBALISEL_PREDICATES_INIT 17163