1-- Additionneur 2 3ENTITY alu IS 4 PORT ( 5 a : in bit_vector(3 downto 0); 6 b : in bit_vector(3 downto 0); 7 s : out bit_vector(3 downto 0); 8 vdd : in bit; 9 vss : in bit 10 ); 11END alu; 12 13 14-- Architecture Declaration 15 16ARCHITECTURE behaviour_data_flow OF alu IS 17 18-- carry 19 20 SIGNAL carry : BIT_VECTOR(3 downto 0) ; 21 22BEGIN 23 24-- fabrication de la retenue 25 26carry(0) <= '0'; 27carry(3 downto 1) <= ( ( b(2 downto 0) and a(2 downto 0) ) or 28 ( a(2 downto 0) and carry(2 downto 0) ) or 29 ( carry(2 downto 0) and b(2 downto 0) ) ) ; 30 31-- fabrication de la somme 32 33s <= b xor a xor carry ; 34 35END; 36