1/* $OpenBSD: cp0access.S,v 1.24 2022/08/22 00:35:06 cheloha Exp $ */ 2 3/* 4 * Copyright (c) 2001-2003 Opsycon AB (www.opsycon.se / www.opsycon.com) 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS 16 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 17 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY 19 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 */ 28 29/* 30 * Low level code to manage processor specific registers. 31 */ 32 33#include <sys/errno.h> 34#include <sys/syscall.h> 35 36#include <machine/param.h> 37#include <machine/asm.h> 38#include <machine/cpu.h> 39#include <mips64/mips_cpu.h> 40#include <machine/regnum.h> 41 42#include "assym.h" 43 44 .set mips3 45 .set noreorder # Noreorder is default style! 46 47/* 48 * Set/clear software interrupt. 49 */ 50 51LEAF(setsoftintr0, 0) 52 MFC0 v0, COP_0_CAUSE_REG # read cause register 53 MFC0_HAZARD 54 NOP 55 or v0, v0, SOFT_INT_MASK_0 # set soft clock interrupt 56 MTC0 v0, COP_0_CAUSE_REG # save it 57 MTC0_HAZARD 58 j ra 59 NOP 60END(setsoftintr0) 61 62LEAF(clearsoftintr0, 0) 63 MFC0 v0, COP_0_CAUSE_REG # read cause register 64 MFC0_HAZARD 65 NOP 66 and v0, v0, ~SOFT_INT_MASK_0 # clear soft clock interrupt 67 MTC0 v0, COP_0_CAUSE_REG # save it 68 MTC0_HAZARD 69 j ra 70 NOP 71END(clearsoftintr0) 72 73LEAF(setsoftintr1, 0) 74 MFC0 v0, COP_0_CAUSE_REG # read cause register 75 MFC0_HAZARD 76 NOP 77 or v0, v0, SOFT_INT_MASK_1 # set soft net interrupt 78 MTC0 v0, COP_0_CAUSE_REG # save it 79 MTC0_HAZARD 80 j ra 81 NOP 82END(setsoftintr1) 83 84LEAF(clearsoftintr1, 0) 85 MFC0 v0, COP_0_CAUSE_REG # read cause register 86 MFC0_HAZARD 87 NOP 88 and v0, v0, ~SOFT_INT_MASK_1 # clear soft net interrupt 89 MTC0 v0, COP_0_CAUSE_REG # save it 90 MTC0_HAZARD 91 j ra 92 NOP 93END(clearsoftintr1) 94 95/* 96 * Set/change interrupt priority routines. 97 * These routines return the previous state. 98 */ 99 100LEAF(enableintr, 0) 101 MFC0 v0, COP_0_STATUS_REG # read status register 102 MFC0_HAZARD 103 NOP 104 or v1, v0, SR_INT_ENAB 105 MTC0 v1, COP_0_STATUS_REG # enable all interrupts 106 MTC0_SR_IE_HAZARD 107 j ra 108 NOP 109END(enableintr) 110 111LEAF(disableintr, 0) 112 MFC0 v0, COP_0_STATUS_REG # read status register 113 MFC0_HAZARD 114 NOP 115 and v1, v0, ~SR_INT_ENAB 116 MTC0 v1, COP_0_STATUS_REG # disable all interrupts 117 MTC0_SR_IE_HAZARD 118 j ra 119 NOP 120END(disableintr) 121 122LEAF(updateimask, 0) 123 lw t0, idle_mask 124 not a0, a0 # 1 means masked so invert. 125 and a0, t0 # never upgrade to higher than max 126 MFC0 v0, COP_0_STATUS_REG 127 MFC0_HAZARD 128 LI v1, ~SR_INT_MASK 129 and v1, v0 130 and v0, a0, SR_INT_MASK 131 or v1, v0 132 MTC0 v1, COP_0_STATUS_REG 133 MTC0_SR_IE_HAZARD 134 ori v1, SR_INT_ENAB # enable interrupts 135 MTC0 v1, COP_0_STATUS_REG 136 MTC0_SR_IE_HAZARD 137 jr ra 138 move v0, v1 139END(updateimask) 140 141LEAF(setsr, 0) 142 MTC0 a0, COP_0_STATUS_REG 143 MTC0_SR_IE_HAZARD 144 jr ra 145 move v0, a0 146END(setsr) 147 148LEAF(getsr, 0) 149 MFC0 v0, COP_0_STATUS_REG 150 MFC0_HAZARD 151 j ra 152 NOP 153END(getsr) 154 155LEAF(cp0_get_config, 0) 156 MFC0 v0, COP_0_CONFIG 157 MFC0_HAZARD 158 j ra 159 NOP 160END(cp0_get_config) 161 162/* WARNING! 163 Needs to be invoked from uncached address if changing cache settings. */ 164LEAF(cp0_set_config, 0) 165 MTC0 a0, COP_0_CONFIG 166 MTC0_HAZARD 167 j ra 168 NOP 169END(cp0_set_config) 170 171LEAF(cp0_get_prid, 0) 172 MFC0 v0, COP_0_PRID 173 MFC0_HAZARD 174 j ra 175 NOP 176END(cp0_get_prid) 177 178LEAF(cp0_get_count, 0) 179 MFC0 v0, COP_0_COUNT 180 MFC0_HAZARD 181 j ra 182 NOP 183END(cp0_get_count) 184 185LEAF(cp0_set_compare, 0) 186 MTC0 a0, COP_0_COMPARE 187 MTC0_HAZARD 188 j ra 189 NOP 190END(cp0_set_compare) 191 192LEAF(cpu_rnd_messybits, 0) 193 MFC0 v0, COP_0_COUNT 194 MFC0_HAZARD 195 MFC0 v1, COP_0_BAD_VADDR 196 MFC0_HAZARD 197 xor v0, v1 198 j ra 199 NOP 200END(cpu_rnd_messybits) 201 202LEAF(cp0_get_cause, 0) 203 MFC0 v0, COP_0_CAUSE_REG 204 MFC0_HAZARD 205 j ra 206 NOP 207END(cp0_get_cause) 208