1 /*	$NetBSD: pmap.h,v 1.144 2016/07/14 05:00:51 skrll Exp $	*/
2 
3 /*
4  * Copyright (c) 2002, 2003 Wasabi Systems, Inc.
5  * All rights reserved.
6  *
7  * Written by Jason R. Thorpe & Steve C. Woodford for Wasabi Systems, Inc.
8  *
9  * Redistribution and use in source and binary forms, with or without
10  * modification, are permitted provided that the following conditions
11  * are met:
12  * 1. Redistributions of source code must retain the above copyright
13  *    notice, this list of conditions and the following disclaimer.
14  * 2. Redistributions in binary form must reproduce the above copyright
15  *    notice, this list of conditions and the following disclaimer in the
16  *    documentation and/or other materials provided with the distribution.
17  * 3. All advertising materials mentioning features or use of this software
18  *    must display the following acknowledgement:
19  *	This product includes software developed for the NetBSD Project by
20  *	Wasabi Systems, Inc.
21  * 4. The name of Wasabi Systems, Inc. may not be used to endorse
22  *    or promote products derived from this software without specific prior
23  *    written permission.
24  *
25  * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
26  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
27  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
28  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL WASABI SYSTEMS, INC
29  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
30  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
31  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
32  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
33  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
34  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
35  * POSSIBILITY OF SUCH DAMAGE.
36  */
37 
38 /*
39  * Copyright (c) 1994,1995 Mark Brinicombe.
40  * All rights reserved.
41  *
42  * Redistribution and use in source and binary forms, with or without
43  * modification, are permitted provided that the following conditions
44  * are met:
45  * 1. Redistributions of source code must retain the above copyright
46  *    notice, this list of conditions and the following disclaimer.
47  * 2. Redistributions in binary form must reproduce the above copyright
48  *    notice, this list of conditions and the following disclaimer in the
49  *    documentation and/or other materials provided with the distribution.
50  * 3. All advertising materials mentioning features or use of this software
51  *    must display the following acknowledgement:
52  *	This product includes software developed by Mark Brinicombe
53  * 4. The name of the author may not be used to endorse or promote products
54  *    derived from this software without specific prior written permission.
55  *
56  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
57  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
58  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
59  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
60  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
61  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
62  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
63  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
64  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
65  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
66  */
67 
68 #ifndef	_ARM32_PMAP_H_
69 #define	_ARM32_PMAP_H_
70 
71 #ifdef _KERNEL
72 
73 #include <arm/cpuconf.h>
74 #include <arm/arm32/pte.h>
75 #ifndef _LOCORE
76 #if defined(_KERNEL_OPT)
77 #include "opt_arm32_pmap.h"
78 #include "opt_multiprocessor.h"
79 #endif
80 #include <arm/cpufunc.h>
81 #include <arm/locore.h>
82 #include <uvm/uvm_object.h>
83 #include <uvm/pmap/pmap_pvt.h>
84 #endif
85 
86 #ifdef ARM_MMU_EXTENDED
87 #define PMAP_TLB_MAX			1
88 #define PMAP_TLB_HWPAGEWALKER		1
89 #if PMAP_TLB_MAX > 1
90 #define PMAP_TLB_NEED_SHOOTDOWN		1
91 #endif
92 #define PMAP_TLB_FLUSH_ASID_ON_RESET	(arm_has_tlbiasid_p)
93 #define PMAP_TLB_NUM_PIDS		256
94 #define cpu_set_tlb_info(ci, ti)        ((void)((ci)->ci_tlb_info = (ti)))
95 #if PMAP_TLB_MAX > 1
96 #define cpu_tlb_info(ci)		((ci)->ci_tlb_info)
97 #else
98 #define cpu_tlb_info(ci)		(&pmap_tlb0_info)
99 #endif
100 #define pmap_md_tlb_asid_max()		(PMAP_TLB_NUM_PIDS - 1)
101 #include <uvm/pmap/tlb.h>
102 #include <uvm/pmap/pmap_tlb.h>
103 
104 /*
105  * If we have an EXTENDED MMU and the address space is split evenly between
106  * user and kernel, we can use the TTBR0/TTBR1 to have separate L1 tables for
107  * user and kernel address spaces.
108  */
109 #if (KERNEL_BASE & 0x80000000) == 0
110 #error ARMv6 or later systems must have a KERNEL_BASE >= 0x80000000
111 #endif
112 #endif  /* ARM_MMU_EXTENDED */
113 
114 /*
115  * a pmap describes a processes' 4GB virtual address space.  this
116  * virtual address space can be broken up into 4096 1MB regions which
117  * are described by L1 PTEs in the L1 table.
118  *
119  * There is a line drawn at KERNEL_BASE.  Everything below that line
120  * changes when the VM context is switched.  Everything above that line
121  * is the same no matter which VM context is running.  This is achieved
122  * by making the L1 PTEs for those slots above KERNEL_BASE reference
123  * kernel L2 tables.
124  *
125  * The basic layout of the virtual address space thus looks like this:
126  *
127  *	0xffffffff
128  *	.
129  *	.
130  *	.
131  *	KERNEL_BASE
132  *	--------------------
133  *	.
134  *	.
135  *	.
136  *	0x00000000
137  */
138 
139 /*
140  * The number of L2 descriptor tables which can be tracked by an l2_dtable.
141  * A bucket size of 16 provides for 16MB of contiguous virtual address
142  * space per l2_dtable. Most processes will, therefore, require only two or
143  * three of these to map their whole working set.
144  */
145 #define	L2_BUCKET_XLOG2	(L1_S_SHIFT)
146 #define L2_BUCKET_XSIZE	(1 << L2_BUCKET_XLOG2)
147 #define	L2_BUCKET_LOG2	4
148 #define	L2_BUCKET_SIZE	(1 << L2_BUCKET_LOG2)
149 
150 /*
151  * Given the above "L2-descriptors-per-l2_dtable" constant, the number
152  * of l2_dtable structures required to track all possible page descriptors
153  * mappable by an L1 translation table is given by the following constants:
154  */
155 #define	L2_LOG2		(32 - (L2_BUCKET_XLOG2 + L2_BUCKET_LOG2))
156 #define	L2_SIZE		(1 << L2_LOG2)
157 
158 /*
159  * tell MI code that the cache is virtually-indexed.
160  * ARMv6 is physically-tagged but all others are virtually-tagged.
161  */
162 #if (ARM_MMU_V6 + ARM_MMU_V7) > 0
163 #define PMAP_CACHE_VIPT
164 #else
165 #define PMAP_CACHE_VIVT
166 #endif
167 
168 #ifndef _LOCORE
169 
170 #ifndef PMAP_MMU_EXTENDED
171 struct l1_ttable;
172 struct l2_dtable;
173 
174 /*
175  * Track cache/tlb occupancy using the following structure
176  */
177 union pmap_cache_state {
178 	struct {
179 		union {
180 			uint8_t csu_cache_b[2];
181 			uint16_t csu_cache;
182 		} cs_cache_u;
183 
184 		union {
185 			uint8_t csu_tlb_b[2];
186 			uint16_t csu_tlb;
187 		} cs_tlb_u;
188 	} cs_s;
189 	uint32_t cs_all;
190 };
191 #define	cs_cache_id	cs_s.cs_cache_u.csu_cache_b[0]
192 #define	cs_cache_d	cs_s.cs_cache_u.csu_cache_b[1]
193 #define	cs_cache	cs_s.cs_cache_u.csu_cache
194 #define	cs_tlb_id	cs_s.cs_tlb_u.csu_tlb_b[0]
195 #define	cs_tlb_d	cs_s.cs_tlb_u.csu_tlb_b[1]
196 #define	cs_tlb		cs_s.cs_tlb_u.csu_tlb
197 
198 /*
199  * Assigned to cs_all to force cacheops to work for a particular pmap
200  */
201 #define	PMAP_CACHE_STATE_ALL	0xffffffffu
202 #endif /* !ARM_MMU_EXTENDED */
203 
204 /*
205  * This structure is used by machine-dependent code to describe
206  * static mappings of devices, created at bootstrap time.
207  */
208 struct pmap_devmap {
209 	vaddr_t		pd_va;		/* virtual address */
210 	paddr_t		pd_pa;		/* physical address */
211 	psize_t		pd_size;	/* size of region */
212 	vm_prot_t	pd_prot;	/* protection code */
213 	int		pd_cache;	/* cache attributes */
214 };
215 
216 /*
217  * The pmap structure itself
218  */
219 struct pmap {
220 	struct uvm_object	pm_obj;
221 	kmutex_t		pm_obj_lock;
222 #define	pm_lock pm_obj.vmobjlock
223 #ifndef ARM_HAS_VBAR
224 	pd_entry_t		*pm_pl1vec;
225 	pd_entry_t		pm_l1vec;
226 #endif
227 	struct l2_dtable	*pm_l2[L2_SIZE];
228 	struct pmap_statistics	pm_stats;
229 	LIST_ENTRY(pmap)	pm_list;
230 #ifdef ARM_MMU_EXTENDED
231 	pd_entry_t		*pm_l1;
232 	paddr_t			pm_l1_pa;
233 	bool			pm_remove_all;
234 #ifdef MULTIPROCESSOR
235 	kcpuset_t		*pm_onproc;
236 	kcpuset_t		*pm_active;
237 #if PMAP_TLB_MAX > 1
238 	u_int			pm_shootdown_pending;
239 #endif
240 #endif
241 	struct pmap_asid_info	pm_pai[PMAP_TLB_MAX];
242 #else
243 	struct l1_ttable	*pm_l1;
244 	union pmap_cache_state	pm_cstate;
245 	uint8_t			pm_domain;
246 	bool			pm_activated;
247 	bool			pm_remove_all;
248 #endif
249 };
250 
251 struct pmap_kernel {
252 	struct pmap		kernel_pmap;
253 };
254 
255 /*
256  * Physical / virtual address structure. In a number of places (particularly
257  * during bootstrapping) we need to keep track of the physical and virtual
258  * addresses of various pages
259  */
260 typedef struct pv_addr {
261 	SLIST_ENTRY(pv_addr) pv_list;
262 	paddr_t pv_pa;
263 	vaddr_t pv_va;
264 	vsize_t pv_size;
265 	uint8_t pv_cache;
266 	uint8_t pv_prot;
267 } pv_addr_t;
268 typedef SLIST_HEAD(, pv_addr) pv_addrqh_t;
269 
270 extern pv_addrqh_t pmap_freeq;
271 extern pv_addr_t kernelstack;
272 extern pv_addr_t abtstack;
273 extern pv_addr_t fiqstack;
274 extern pv_addr_t irqstack;
275 extern pv_addr_t undstack;
276 extern pv_addr_t idlestack;
277 extern pv_addr_t systempage;
278 extern pv_addr_t kernel_l1pt;
279 
280 #ifdef ARM_MMU_EXTENDED
281 extern bool arm_has_tlbiasid_p;	/* also in <arm/locore.h> */
282 #endif
283 
284 /*
285  * Determine various modes for PTEs (user vs. kernel, cacheable
286  * vs. non-cacheable).
287  */
288 #define	PTE_KERNEL	0
289 #define	PTE_USER	1
290 #define	PTE_NOCACHE	0
291 #define	PTE_CACHE	1
292 #define	PTE_PAGETABLE	2
293 
294 /*
295  * Flags that indicate attributes of pages or mappings of pages.
296  *
297  * The PVF_MOD and PVF_REF flags are stored in the mdpage for each
298  * page.  PVF_WIRED, PVF_WRITE, and PVF_NC are kept in individual
299  * pv_entry's for each page.  They live in the same "namespace" so
300  * that we can clear multiple attributes at a time.
301  *
302  * Note the "non-cacheable" flag generally means the page has
303  * multiple mappings in a given address space.
304  */
305 #define	PVF_MOD		0x01		/* page is modified */
306 #define	PVF_REF		0x02		/* page is referenced */
307 #define	PVF_WIRED	0x04		/* mapping is wired */
308 #define	PVF_WRITE	0x08		/* mapping is writable */
309 #define	PVF_EXEC	0x10		/* mapping is executable */
310 #ifdef PMAP_CACHE_VIVT
311 #define	PVF_UNC		0x20		/* mapping is 'user' non-cacheable */
312 #define	PVF_KNC		0x40		/* mapping is 'kernel' non-cacheable */
313 #define	PVF_NC		(PVF_UNC|PVF_KNC)
314 #endif
315 #ifdef PMAP_CACHE_VIPT
316 #define	PVF_NC		0x20		/* mapping is 'kernel' non-cacheable */
317 #define	PVF_MULTCLR	0x40		/* mapping is multi-colored */
318 #endif
319 #define	PVF_COLORED	0x80		/* page has or had a color */
320 #define	PVF_KENTRY	0x0100		/* page entered via pmap_kenter_pa */
321 #define	PVF_KMPAGE	0x0200		/* page is used for kmem */
322 #define	PVF_DIRTY	0x0400		/* page may have dirty cache lines */
323 #define	PVF_KMOD	0x0800		/* unmanaged page is modified  */
324 #define	PVF_KWRITE	(PVF_KENTRY|PVF_WRITE)
325 #define	PVF_DMOD	(PVF_MOD|PVF_KMOD|PVF_KMPAGE)
326 
327 /*
328  * Commonly referenced structures
329  */
330 extern int		pmap_debug_level; /* Only exists if PMAP_DEBUG */
331 extern int		arm_poolpage_vmfreelist;
332 
333 /*
334  * Macros that we need to export
335  */
336 #define	pmap_resident_count(pmap)	((pmap)->pm_stats.resident_count)
337 #define	pmap_wired_count(pmap)		((pmap)->pm_stats.wired_count)
338 
339 #define	pmap_is_modified(pg)	\
340 	(((pg)->mdpage.pvh_attrs & PVF_MOD) != 0)
341 #define	pmap_is_referenced(pg)	\
342 	(((pg)->mdpage.pvh_attrs & PVF_REF) != 0)
343 #define	pmap_is_page_colored_p(md)	\
344 	(((md)->pvh_attrs & PVF_COLORED) != 0)
345 
346 #define	pmap_copy(dp, sp, da, l, sa)	/* nothing */
347 
348 #define pmap_phys_address(ppn)		(arm_ptob((ppn)))
349 u_int arm32_mmap_flags(paddr_t);
350 #define ARM32_MMAP_WRITECOMBINE		0x40000000
351 #define ARM32_MMAP_CACHEABLE		0x20000000
352 #define pmap_mmap_flags(ppn)		arm32_mmap_flags(ppn)
353 
354 #define	PMAP_PTE			0x10000000 /* kenter_pa */
355 
356 /*
357  * Functions that we need to export
358  */
359 void	pmap_procwr(struct proc *, vaddr_t, int);
360 void	pmap_remove_all(pmap_t);
361 bool	pmap_extract(pmap_t, vaddr_t, paddr_t *);
362 
363 #define	PMAP_NEED_PROCWR
364 #define PMAP_GROWKERNEL		/* turn on pmap_growkernel interface */
365 #define	PMAP_ENABLE_PMAP_KMPAGE	/* enable the PMAP_KMPAGE flag */
366 
367 #if (ARM_MMU_V6 + ARM_MMU_V7) > 0
368 #define	PMAP_PREFER(hint, vap, sz, td)	pmap_prefer((hint), (vap), (td))
369 void	pmap_prefer(vaddr_t, vaddr_t *, int);
370 #endif
371 
372 void	pmap_icache_sync_range(pmap_t, vaddr_t, vaddr_t);
373 
374 /* Functions we use internally. */
375 #ifdef PMAP_STEAL_MEMORY
376 void	pmap_boot_pagealloc(psize_t, psize_t, psize_t, pv_addr_t *);
377 void	pmap_boot_pageadd(pv_addr_t *);
378 vaddr_t	pmap_steal_memory(vsize_t, vaddr_t *, vaddr_t *);
379 #endif
380 void	pmap_bootstrap(vaddr_t, vaddr_t);
381 
382 void	pmap_do_remove(pmap_t, vaddr_t, vaddr_t, int);
383 int	pmap_fault_fixup(pmap_t, vaddr_t, vm_prot_t, int);
384 int	pmap_prefetchabt_fixup(void *);
385 bool	pmap_get_pde_pte(pmap_t, vaddr_t, pd_entry_t **, pt_entry_t **);
386 bool	pmap_get_pde(pmap_t, vaddr_t, pd_entry_t **);
387 struct pcb;
388 void	pmap_set_pcb_pagedir(pmap_t, struct pcb *);
389 
390 void	pmap_debug(int);
391 void	pmap_postinit(void);
392 
393 void	vector_page_setprot(int);
394 
395 const struct pmap_devmap *pmap_devmap_find_pa(paddr_t, psize_t);
396 const struct pmap_devmap *pmap_devmap_find_va(vaddr_t, vsize_t);
397 
398 /* Bootstrapping routines. */
399 void	pmap_map_section(vaddr_t, vaddr_t, paddr_t, int, int);
400 void	pmap_map_entry(vaddr_t, vaddr_t, paddr_t, int, int);
401 vsize_t	pmap_map_chunk(vaddr_t, vaddr_t, paddr_t, vsize_t, int, int);
402 void	pmap_link_l2pt(vaddr_t, vaddr_t, pv_addr_t *);
403 void	pmap_devmap_bootstrap(vaddr_t, const struct pmap_devmap *);
404 void	pmap_devmap_register(const struct pmap_devmap *);
405 
406 /*
407  * Special page zero routine for use by the idle loop (no cache cleans).
408  */
409 bool	pmap_pageidlezero(paddr_t);
410 #define PMAP_PAGEIDLEZERO(pa)	pmap_pageidlezero((pa))
411 
412 #ifdef __HAVE_MM_MD_DIRECT_MAPPED_PHYS
413 /*
414  * For the pmap, this is a more useful way to map a direct mapped page.
415  * It returns either the direct-mapped VA or the VA supplied if it can't
416  * be direct mapped.
417  */
418 vaddr_t	pmap_direct_mapped_phys(paddr_t, bool *, vaddr_t);
419 #endif
420 
421 /*
422  * used by dumpsys to record the PA of the L1 table
423  */
424 uint32_t pmap_kernel_L1_addr(void);
425 /*
426  * The current top of kernel VM
427  */
428 extern vaddr_t	pmap_curmaxkvaddr;
429 
430 #if defined(ARM_MMU_EXTENDED) && defined(__HAVE_MM_MD_DIRECT_MAPPED_PHYS)
431 /*
432  * Ending VA of direct mapped memory (usually KERNEL_VM_BASE).
433  */
434 extern vaddr_t pmap_directlimit;
435 #endif
436 
437 /*
438  * Useful macros and constants
439  */
440 
441 /* Virtual address to page table entry */
442 static inline pt_entry_t *
vtopte(vaddr_t va)443 vtopte(vaddr_t va)
444 {
445 	pd_entry_t *pdep;
446 	pt_entry_t *ptep;
447 
448 	KASSERT(trunc_page(va) == va);
449 
450 	if (pmap_get_pde_pte(pmap_kernel(), va, &pdep, &ptep) == false)
451 		return (NULL);
452 	return (ptep);
453 }
454 
455 /*
456  * Virtual address to physical address
457  */
458 static inline paddr_t
vtophys(vaddr_t va)459 vtophys(vaddr_t va)
460 {
461 	paddr_t pa;
462 
463 	if (pmap_extract(pmap_kernel(), va, &pa) == false)
464 		return (0);	/* XXXSCW: Panic? */
465 
466 	return (pa);
467 }
468 
469 /*
470  * The new pmap ensures that page-tables are always mapping Write-Thru.
471  * Thus, on some platforms we can run fast and loose and avoid syncing PTEs
472  * on every change.
473  *
474  * Unfortunately, not all CPUs have a write-through cache mode.  So we
475  * define PMAP_NEEDS_PTE_SYNC for C code to conditionally do PTE syncs,
476  * and if there is the chance for PTE syncs to be needed, we define
477  * PMAP_INCLUDE_PTE_SYNC so e.g. assembly code can include (and run)
478  * the code.
479  */
480 extern int pmap_needs_pte_sync;
481 #if defined(_KERNEL_OPT)
482 /*
483  * StrongARM SA-1 caches do not have a write-through mode.  So, on these,
484  * we need to do PTE syncs.  If only SA-1 is configured, then evaluate
485  * this at compile time.
486  */
487 #if (ARM_MMU_SA1 + ARM_MMU_V6 != 0) && (ARM_NMMUS == 1)
488 #define	PMAP_INCLUDE_PTE_SYNC
489 #if (ARM_MMU_V6 > 0)
490 #define	PMAP_NEEDS_PTE_SYNC	1
491 #elif (ARM_MMU_SA1 == 0)
492 #define	PMAP_NEEDS_PTE_SYNC	0
493 #endif
494 #endif
495 #endif /* _KERNEL_OPT */
496 
497 /*
498  * Provide a fallback in case we were not able to determine it at
499  * compile-time.
500  */
501 #ifndef PMAP_NEEDS_PTE_SYNC
502 #define	PMAP_NEEDS_PTE_SYNC	pmap_needs_pte_sync
503 #define	PMAP_INCLUDE_PTE_SYNC
504 #endif
505 
506 static inline void
pmap_ptesync(pt_entry_t * ptep,size_t cnt)507 pmap_ptesync(pt_entry_t *ptep, size_t cnt)
508 {
509 	if (PMAP_NEEDS_PTE_SYNC) {
510 		cpu_dcache_wb_range((vaddr_t)ptep, cnt * sizeof(pt_entry_t));
511 #ifdef SHEEVA_L2_CACHE
512 		cpu_sdcache_wb_range((vaddr_t)ptep, -1,
513 		    cnt * sizeof(pt_entry_t));
514 #endif
515 	}
516 	arm_dsb();
517 }
518 
519 #define	PDE_SYNC(pdep)			pmap_ptesync((pdep), 1)
520 #define	PDE_SYNC_RANGE(pdep, cnt)	pmap_ptesync((pdep), (cnt))
521 #define	PTE_SYNC(ptep)			pmap_ptesync((ptep), PAGE_SIZE / L2_S_SIZE)
522 #define	PTE_SYNC_RANGE(ptep, cnt)	pmap_ptesync((ptep), (cnt))
523 
524 #define l1pte_valid_p(pde)	((pde) != 0)
525 #define l1pte_section_p(pde)	(((pde) & L1_TYPE_MASK) == L1_TYPE_S)
526 #define l1pte_supersection_p(pde) (l1pte_section_p(pde)	\
527 				&& ((pde) & L1_S_V6_SUPER) != 0)
528 #define l1pte_page_p(pde)	(((pde) & L1_TYPE_MASK) == L1_TYPE_C)
529 #define l1pte_fpage_p(pde)	(((pde) & L1_TYPE_MASK) == L1_TYPE_F)
530 #define l1pte_pa(pde)		((pde) & L1_C_ADDR_MASK)
531 #define l1pte_index(v)		((vaddr_t)(v) >> L1_S_SHIFT)
532 #define l1pte_pgindex(v)	l1pte_index((v) & L1_ADDR_BITS \
533 		& ~(PAGE_SIZE * PAGE_SIZE / sizeof(pt_entry_t) - 1))
534 
535 static inline void
l1pte_setone(pt_entry_t * pdep,pt_entry_t pde)536 l1pte_setone(pt_entry_t *pdep, pt_entry_t pde)
537 {
538 	*pdep = pde;
539 }
540 
541 static inline void
l1pte_set(pt_entry_t * pdep,pt_entry_t pde)542 l1pte_set(pt_entry_t *pdep, pt_entry_t pde)
543 {
544 	*pdep = pde;
545 	if (l1pte_page_p(pde)) {
546 		KASSERTMSG((((uintptr_t)pdep / sizeof(pde)) & (PAGE_SIZE / L2_T_SIZE - 1)) == 0, "%p", pdep);
547 		for (size_t k = 1; k < PAGE_SIZE / L2_T_SIZE; k++) {
548 			pde += L2_T_SIZE;
549 			pdep[k] = pde;
550 		}
551 	} else if (l1pte_supersection_p(pde)) {
552 		KASSERTMSG((((uintptr_t)pdep / sizeof(pde)) & (L1_SS_SIZE / L1_S_SIZE - 1)) == 0, "%p", pdep);
553 		for (size_t k = 1; k < L1_SS_SIZE / L1_S_SIZE; k++) {
554 			pdep[k] = pde;
555 		}
556 	}
557 }
558 
559 #define l2pte_index(v)		((((v) & L2_ADDR_BITS) >> PGSHIFT) << (PGSHIFT-L2_S_SHIFT))
560 #define l2pte_valid_p(pte)	(((pte) & L2_TYPE_MASK) != L2_TYPE_INV)
561 #define l2pte_pa(pte)		((pte) & L2_S_FRAME)
562 #define l1pte_lpage_p(pte)	(((pte) & L2_TYPE_MASK) == L2_TYPE_L)
563 #define l2pte_minidata_p(pte)	(((pte) & \
564 				 (L2_B | L2_C | L2_XS_T_TEX(TEX_XSCALE_X)))\
565 				 == (L2_C | L2_XS_T_TEX(TEX_XSCALE_X)))
566 
567 static inline void
l2pte_set(pt_entry_t * ptep,pt_entry_t pte,pt_entry_t opte)568 l2pte_set(pt_entry_t *ptep, pt_entry_t pte, pt_entry_t opte)
569 {
570 	if (l1pte_lpage_p(pte)) {
571 		KASSERTMSG((((uintptr_t)ptep / sizeof(pte)) & (L2_L_SIZE / L2_S_SIZE - 1)) == 0, "%p", ptep);
572 		for (size_t k = 0; k < L2_L_SIZE / L2_S_SIZE; k++) {
573 			*ptep++ = pte;
574 		}
575 	} else {
576 		KASSERTMSG((((uintptr_t)ptep / sizeof(pte)) & (PAGE_SIZE / L2_S_SIZE - 1)) == 0, "%p", ptep);
577 		for (size_t k = 0; k < PAGE_SIZE / L2_S_SIZE; k++) {
578 			KASSERTMSG(*ptep == opte, "%#x [*%p] != %#x", *ptep, ptep, opte);
579 			*ptep++ = pte;
580 			pte += L2_S_SIZE;
581 			if (opte)
582 				opte += L2_S_SIZE;
583 		}
584 	}
585 }
586 
587 static inline void
l2pte_reset(pt_entry_t * ptep)588 l2pte_reset(pt_entry_t *ptep)
589 {
590 	KASSERTMSG((((uintptr_t)ptep / sizeof(*ptep)) & (PAGE_SIZE / L2_S_SIZE - 1)) == 0, "%p", ptep);
591 	*ptep = 0;
592 	for (vsize_t k = 1; k < PAGE_SIZE / L2_S_SIZE; k++) {
593 		ptep[k] = 0;
594 	}
595 }
596 
597 /* L1 and L2 page table macros */
598 #define pmap_pde_v(pde)		l1pte_valid(*(pde))
599 #define pmap_pde_section(pde)	l1pte_section_p(*(pde))
600 #define pmap_pde_supersection(pde)	l1pte_supersection_p(*(pde))
601 #define pmap_pde_page(pde)	l1pte_page_p(*(pde))
602 #define pmap_pde_fpage(pde)	l1pte_fpage_p(*(pde))
603 
604 #define	pmap_pte_v(pte)		l2pte_valid_p(*(pte))
605 #define	pmap_pte_pa(pte)	l2pte_pa(*(pte))
606 
607 /* Size of the kernel part of the L1 page table */
608 #define KERNEL_PD_SIZE	\
609 	(L1_TABLE_SIZE - (KERNEL_BASE >> L1_S_SHIFT) * sizeof(pd_entry_t))
610 
611 void	bzero_page(vaddr_t);
612 void	bcopy_page(vaddr_t, vaddr_t);
613 
614 #ifdef FPU_VFP
615 void	bzero_page_vfp(vaddr_t);
616 void	bcopy_page_vfp(vaddr_t, vaddr_t);
617 #endif
618 
619 /************************* ARM MMU configuration *****************************/
620 
621 #if (ARM_MMU_GENERIC + ARM_MMU_SA1 + ARM_MMU_V6 + ARM_MMU_V7) != 0
622 void	pmap_copy_page_generic(paddr_t, paddr_t);
623 void	pmap_zero_page_generic(paddr_t);
624 
625 void	pmap_pte_init_generic(void);
626 #if defined(CPU_ARM8)
627 void	pmap_pte_init_arm8(void);
628 #endif
629 #if defined(CPU_ARM9)
630 void	pmap_pte_init_arm9(void);
631 #endif /* CPU_ARM9 */
632 #if defined(CPU_ARM10)
633 void	pmap_pte_init_arm10(void);
634 #endif /* CPU_ARM10 */
635 #if defined(CPU_ARM11)	/* ARM_MMU_V6 */
636 void	pmap_pte_init_arm11(void);
637 #endif /* CPU_ARM11 */
638 #if defined(CPU_ARM11MPCORE)	/* ARM_MMU_V6 */
639 void	pmap_pte_init_arm11mpcore(void);
640 #endif
641 #if ARM_MMU_V7 == 1
642 void	pmap_pte_init_armv7(void);
643 #endif /* ARM_MMU_V7 */
644 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 */
645 
646 #if ARM_MMU_SA1 == 1
647 void	pmap_pte_init_sa1(void);
648 #endif /* ARM_MMU_SA1 == 1 */
649 
650 #if ARM_MMU_XSCALE == 1
651 void	pmap_copy_page_xscale(paddr_t, paddr_t);
652 void	pmap_zero_page_xscale(paddr_t);
653 
654 void	pmap_pte_init_xscale(void);
655 
656 void	xscale_setup_minidata(vaddr_t, vaddr_t, paddr_t);
657 
658 #define	PMAP_UAREA(va)		pmap_uarea(va)
659 void	pmap_uarea(vaddr_t);
660 #endif /* ARM_MMU_XSCALE == 1 */
661 
662 extern pt_entry_t		pte_l1_s_cache_mode;
663 extern pt_entry_t		pte_l1_s_cache_mask;
664 
665 extern pt_entry_t		pte_l2_l_cache_mode;
666 extern pt_entry_t		pte_l2_l_cache_mask;
667 
668 extern pt_entry_t		pte_l2_s_cache_mode;
669 extern pt_entry_t		pte_l2_s_cache_mask;
670 
671 extern pt_entry_t		pte_l1_s_cache_mode_pt;
672 extern pt_entry_t		pte_l2_l_cache_mode_pt;
673 extern pt_entry_t		pte_l2_s_cache_mode_pt;
674 
675 extern pt_entry_t		pte_l1_s_wc_mode;
676 extern pt_entry_t		pte_l2_l_wc_mode;
677 extern pt_entry_t		pte_l2_s_wc_mode;
678 
679 extern pt_entry_t		pte_l1_s_prot_u;
680 extern pt_entry_t		pte_l1_s_prot_w;
681 extern pt_entry_t		pte_l1_s_prot_ro;
682 extern pt_entry_t		pte_l1_s_prot_mask;
683 
684 extern pt_entry_t		pte_l2_s_prot_u;
685 extern pt_entry_t		pte_l2_s_prot_w;
686 extern pt_entry_t		pte_l2_s_prot_ro;
687 extern pt_entry_t		pte_l2_s_prot_mask;
688 
689 extern pt_entry_t		pte_l2_l_prot_u;
690 extern pt_entry_t		pte_l2_l_prot_w;
691 extern pt_entry_t		pte_l2_l_prot_ro;
692 extern pt_entry_t		pte_l2_l_prot_mask;
693 
694 extern pt_entry_t		pte_l1_ss_proto;
695 extern pt_entry_t		pte_l1_s_proto;
696 extern pt_entry_t		pte_l1_c_proto;
697 extern pt_entry_t		pte_l2_s_proto;
698 
699 extern void (*pmap_copy_page_func)(paddr_t, paddr_t);
700 extern void (*pmap_zero_page_func)(paddr_t);
701 
702 #endif /* !_LOCORE */
703 
704 /*****************************************************************************/
705 
706 #define	KERNEL_PID		0	/* The kernel uses ASID 0 */
707 
708 /*
709  * Definitions for MMU domains
710  */
711 #define	PMAP_DOMAINS		15	/* 15 'user' domains (1-15) */
712 #define	PMAP_DOMAIN_KERNEL	0	/* The kernel pmap uses domain #0 */
713 #ifdef ARM_MMU_EXTENDED
714 #define	PMAP_DOMAIN_USER	1	/* User pmaps use domain #1 */
715 #endif
716 
717 /*
718  * These macros define the various bit masks in the PTE.
719  *
720  * We use these macros since we use different bits on different processor
721  * models.
722  */
723 #define	L1_S_PROT_U_generic	(L1_S_AP(AP_U))
724 #define	L1_S_PROT_W_generic	(L1_S_AP(AP_W))
725 #define	L1_S_PROT_RO_generic	(0)
726 #define	L1_S_PROT_MASK_generic	(L1_S_PROT_U|L1_S_PROT_W|L1_S_PROT_RO)
727 
728 #define	L1_S_PROT_U_xscale	(L1_S_AP(AP_U))
729 #define	L1_S_PROT_W_xscale	(L1_S_AP(AP_W))
730 #define	L1_S_PROT_RO_xscale	(0)
731 #define	L1_S_PROT_MASK_xscale	(L1_S_PROT_U|L1_S_PROT_W|L1_S_PROT_RO)
732 
733 #define	L1_S_PROT_U_armv6	(L1_S_AP(AP_R) | L1_S_AP(AP_U))
734 #define	L1_S_PROT_W_armv6	(L1_S_AP(AP_W))
735 #define	L1_S_PROT_RO_armv6	(L1_S_AP(AP_R) | L1_S_AP(AP_RO))
736 #define	L1_S_PROT_MASK_armv6	(L1_S_PROT_U|L1_S_PROT_W|L1_S_PROT_RO)
737 
738 #define	L1_S_PROT_U_armv7	(L1_S_AP(AP_R) | L1_S_AP(AP_U))
739 #define	L1_S_PROT_W_armv7	(L1_S_AP(AP_W))
740 #define	L1_S_PROT_RO_armv7	(L1_S_AP(AP_R) | L1_S_AP(AP_RO))
741 #define	L1_S_PROT_MASK_armv7	(L1_S_PROT_U|L1_S_PROT_W|L1_S_PROT_RO)
742 
743 #define	L1_S_CACHE_MASK_generic	(L1_S_B|L1_S_C)
744 #define	L1_S_CACHE_MASK_xscale	(L1_S_B|L1_S_C|L1_S_XS_TEX(TEX_XSCALE_X))
745 #define	L1_S_CACHE_MASK_armv6	(L1_S_B|L1_S_C|L1_S_XS_TEX(TEX_ARMV6_TEX))
746 #define	L1_S_CACHE_MASK_armv6n	(L1_S_B|L1_S_C|L1_S_XS_TEX(TEX_ARMV6_TEX)|L1_S_V6_S)
747 #define	L1_S_CACHE_MASK_armv7	(L1_S_B|L1_S_C|L1_S_XS_TEX(TEX_ARMV6_TEX)|L1_S_V6_S)
748 
749 #define	L2_L_PROT_U_generic	(L2_AP(AP_U))
750 #define	L2_L_PROT_W_generic	(L2_AP(AP_W))
751 #define	L2_L_PROT_RO_generic	(0)
752 #define	L2_L_PROT_MASK_generic	(L2_L_PROT_U|L2_L_PROT_W|L2_L_PROT_RO)
753 
754 #define	L2_L_PROT_U_xscale	(L2_AP(AP_U))
755 #define	L2_L_PROT_W_xscale	(L2_AP(AP_W))
756 #define	L2_L_PROT_RO_xscale	(0)
757 #define	L2_L_PROT_MASK_xscale	(L2_L_PROT_U|L2_L_PROT_W|L2_L_PROT_RO)
758 
759 #define	L2_L_PROT_U_armv6n	(L2_AP0(AP_R) | L2_AP0(AP_U))
760 #define	L2_L_PROT_W_armv6n	(L2_AP0(AP_W))
761 #define	L2_L_PROT_RO_armv6n	(L2_AP0(AP_R) | L2_AP0(AP_RO))
762 #define	L2_L_PROT_MASK_armv6n	(L2_L_PROT_U|L2_L_PROT_W|L2_L_PROT_RO)
763 
764 #define	L2_L_PROT_U_armv7	(L2_AP0(AP_R) | L2_AP0(AP_U))
765 #define	L2_L_PROT_W_armv7	(L2_AP0(AP_W))
766 #define	L2_L_PROT_RO_armv7	(L2_AP0(AP_R) | L2_AP0(AP_RO))
767 #define	L2_L_PROT_MASK_armv7	(L2_L_PROT_U|L2_L_PROT_W|L2_L_PROT_RO)
768 
769 #define	L2_L_CACHE_MASK_generic	(L2_B|L2_C)
770 #define	L2_L_CACHE_MASK_xscale	(L2_B|L2_C|L2_XS_L_TEX(TEX_XSCALE_X))
771 #define	L2_L_CACHE_MASK_armv6	(L2_B|L2_C|L2_V6_L_TEX(TEX_ARMV6_TEX))
772 #define	L2_L_CACHE_MASK_armv6n	(L2_B|L2_C|L2_V6_L_TEX(TEX_ARMV6_TEX)|L2_XS_S)
773 #define	L2_L_CACHE_MASK_armv7	(L2_B|L2_C|L2_V6_L_TEX(TEX_ARMV6_TEX)|L2_XS_S)
774 
775 #define	L2_S_PROT_U_generic	(L2_AP(AP_U))
776 #define	L2_S_PROT_W_generic	(L2_AP(AP_W))
777 #define	L2_S_PROT_RO_generic	(0)
778 #define	L2_S_PROT_MASK_generic	(L2_S_PROT_U|L2_S_PROT_W|L2_S_PROT_RO)
779 
780 #define	L2_S_PROT_U_xscale	(L2_AP0(AP_U))
781 #define	L2_S_PROT_W_xscale	(L2_AP0(AP_W))
782 #define	L2_S_PROT_RO_xscale	(0)
783 #define	L2_S_PROT_MASK_xscale	(L2_S_PROT_U|L2_S_PROT_W|L2_S_PROT_RO)
784 
785 #define	L2_S_PROT_U_armv6n	(L2_AP0(AP_R) | L2_AP0(AP_U))
786 #define	L2_S_PROT_W_armv6n	(L2_AP0(AP_W))
787 #define	L2_S_PROT_RO_armv6n	(L2_AP0(AP_R) | L2_AP0(AP_RO))
788 #define	L2_S_PROT_MASK_armv6n	(L2_S_PROT_U|L2_S_PROT_W|L2_S_PROT_RO)
789 
790 #define	L2_S_PROT_U_armv7	(L2_AP0(AP_R) | L2_AP0(AP_U))
791 #define	L2_S_PROT_W_armv7	(L2_AP0(AP_W))
792 #define	L2_S_PROT_RO_armv7	(L2_AP0(AP_R) | L2_AP0(AP_RO))
793 #define	L2_S_PROT_MASK_armv7	(L2_S_PROT_U|L2_S_PROT_W|L2_S_PROT_RO)
794 
795 #define	L2_S_CACHE_MASK_generic	(L2_B|L2_C)
796 #define	L2_S_CACHE_MASK_xscale	(L2_B|L2_C|L2_XS_T_TEX(TEX_XSCALE_X))
797 #define	L2_XS_CACHE_MASK_armv6	(L2_B|L2_C|L2_V6_XS_TEX(TEX_ARMV6_TEX))
798 #ifdef	ARMV6_EXTENDED_SMALL_PAGE
799 #define	L2_S_CACHE_MASK_armv6c	L2_XS_CACHE_MASK_armv6
800 #else
801 #define	L2_S_CACHE_MASK_armv6c	L2_S_CACHE_MASK_generic
802 #endif
803 #define	L2_S_CACHE_MASK_armv6n	(L2_B|L2_C|L2_V6_XS_TEX(TEX_ARMV6_TEX)|L2_XS_S)
804 #define	L2_S_CACHE_MASK_armv7	(L2_B|L2_C|L2_V6_XS_TEX(TEX_ARMV6_TEX)|L2_XS_S)
805 
806 
807 #define	L1_S_PROTO_generic	(L1_TYPE_S | L1_S_IMP)
808 #define	L1_S_PROTO_xscale	(L1_TYPE_S)
809 #define	L1_S_PROTO_armv6	(L1_TYPE_S)
810 #define	L1_S_PROTO_armv7	(L1_TYPE_S)
811 
812 #define	L1_SS_PROTO_generic	0
813 #define	L1_SS_PROTO_xscale	0
814 #define	L1_SS_PROTO_armv6	(L1_TYPE_S | L1_S_V6_SS)
815 #define	L1_SS_PROTO_armv7	(L1_TYPE_S | L1_S_V6_SS)
816 
817 #define	L1_C_PROTO_generic	(L1_TYPE_C | L1_C_IMP2)
818 #define	L1_C_PROTO_xscale	(L1_TYPE_C)
819 #define	L1_C_PROTO_armv6	(L1_TYPE_C)
820 #define	L1_C_PROTO_armv7	(L1_TYPE_C)
821 
822 #define	L2_L_PROTO		(L2_TYPE_L)
823 
824 #define	L2_S_PROTO_generic	(L2_TYPE_S)
825 #define	L2_S_PROTO_xscale	(L2_TYPE_XS)
826 #ifdef	ARMV6_EXTENDED_SMALL_PAGE
827 #define	L2_S_PROTO_armv6c	(L2_TYPE_XS)    /* XP=0, extended small page */
828 #else
829 #define	L2_S_PROTO_armv6c	(L2_TYPE_S)	/* XP=0, subpage APs */
830 #endif
831 #ifdef ARM_MMU_EXTENDED
832 #define	L2_S_PROTO_armv6n	(L2_TYPE_S|L2_XS_XN)
833 #else
834 #define	L2_S_PROTO_armv6n	(L2_TYPE_S)	/* with XP=1 */
835 #endif
836 #ifdef ARM_MMU_EXTENDED
837 #define	L2_S_PROTO_armv7	(L2_TYPE_S|L2_XS_XN)
838 #else
839 #define	L2_S_PROTO_armv7	(L2_TYPE_S)
840 #endif
841 
842 /*
843  * User-visible names for the ones that vary with MMU class.
844  */
845 
846 #if ARM_NMMUS > 1
847 /* More than one MMU class configured; use variables. */
848 #define	L1_S_PROT_U		pte_l1_s_prot_u
849 #define	L1_S_PROT_W		pte_l1_s_prot_w
850 #define	L1_S_PROT_RO		pte_l1_s_prot_ro
851 #define	L1_S_PROT_MASK		pte_l1_s_prot_mask
852 
853 #define	L2_S_PROT_U		pte_l2_s_prot_u
854 #define	L2_S_PROT_W		pte_l2_s_prot_w
855 #define	L2_S_PROT_RO		pte_l2_s_prot_ro
856 #define	L2_S_PROT_MASK		pte_l2_s_prot_mask
857 
858 #define	L2_L_PROT_U		pte_l2_l_prot_u
859 #define	L2_L_PROT_W		pte_l2_l_prot_w
860 #define	L2_L_PROT_RO		pte_l2_l_prot_ro
861 #define	L2_L_PROT_MASK		pte_l2_l_prot_mask
862 
863 #define	L1_S_CACHE_MASK		pte_l1_s_cache_mask
864 #define	L2_L_CACHE_MASK		pte_l2_l_cache_mask
865 #define	L2_S_CACHE_MASK		pte_l2_s_cache_mask
866 
867 #define	L1_SS_PROTO		pte_l1_ss_proto
868 #define	L1_S_PROTO		pte_l1_s_proto
869 #define	L1_C_PROTO		pte_l1_c_proto
870 #define	L2_S_PROTO		pte_l2_s_proto
871 
872 #define	pmap_copy_page(s, d)	(*pmap_copy_page_func)((s), (d))
873 #define	pmap_zero_page(d)	(*pmap_zero_page_func)((d))
874 #elif (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0
875 #define	L1_S_PROT_U		L1_S_PROT_U_generic
876 #define	L1_S_PROT_W		L1_S_PROT_W_generic
877 #define	L1_S_PROT_RO		L1_S_PROT_RO_generic
878 #define	L1_S_PROT_MASK		L1_S_PROT_MASK_generic
879 
880 #define	L2_S_PROT_U		L2_S_PROT_U_generic
881 #define	L2_S_PROT_W		L2_S_PROT_W_generic
882 #define	L2_S_PROT_RO		L2_S_PROT_RO_generic
883 #define	L2_S_PROT_MASK		L2_S_PROT_MASK_generic
884 
885 #define	L2_L_PROT_U		L2_L_PROT_U_generic
886 #define	L2_L_PROT_W		L2_L_PROT_W_generic
887 #define	L2_L_PROT_RO		L2_L_PROT_RO_generic
888 #define	L2_L_PROT_MASK		L2_L_PROT_MASK_generic
889 
890 #define	L1_S_CACHE_MASK		L1_S_CACHE_MASK_generic
891 #define	L2_L_CACHE_MASK		L2_L_CACHE_MASK_generic
892 #define	L2_S_CACHE_MASK		L2_S_CACHE_MASK_generic
893 
894 #define	L1_SS_PROTO		L1_SS_PROTO_generic
895 #define	L1_S_PROTO		L1_S_PROTO_generic
896 #define	L1_C_PROTO		L1_C_PROTO_generic
897 #define	L2_S_PROTO		L2_S_PROTO_generic
898 
899 #define	pmap_copy_page(s, d)	pmap_copy_page_generic((s), (d))
900 #define	pmap_zero_page(d)	pmap_zero_page_generic((d))
901 #elif ARM_MMU_V6N != 0
902 #define	L1_S_PROT_U		L1_S_PROT_U_armv6
903 #define	L1_S_PROT_W		L1_S_PROT_W_armv6
904 #define	L1_S_PROT_RO		L1_S_PROT_RO_armv6
905 #define	L1_S_PROT_MASK		L1_S_PROT_MASK_armv6
906 
907 #define	L2_S_PROT_U		L2_S_PROT_U_armv6n
908 #define	L2_S_PROT_W		L2_S_PROT_W_armv6n
909 #define	L2_S_PROT_RO		L2_S_PROT_RO_armv6n
910 #define	L2_S_PROT_MASK		L2_S_PROT_MASK_armv6n
911 
912 #define	L2_L_PROT_U		L2_L_PROT_U_armv6n
913 #define	L2_L_PROT_W		L2_L_PROT_W_armv6n
914 #define	L2_L_PROT_RO		L2_L_PROT_RO_armv6n
915 #define	L2_L_PROT_MASK		L2_L_PROT_MASK_armv6n
916 
917 #define	L1_S_CACHE_MASK		L1_S_CACHE_MASK_armv6n
918 #define	L2_L_CACHE_MASK		L2_L_CACHE_MASK_armv6n
919 #define	L2_S_CACHE_MASK		L2_S_CACHE_MASK_armv6n
920 
921 /* These prototypes make writeable mappings, while the other MMU types
922  * make read-only mappings. */
923 #define	L1_SS_PROTO		L1_SS_PROTO_armv6
924 #define	L1_S_PROTO		L1_S_PROTO_armv6
925 #define	L1_C_PROTO		L1_C_PROTO_armv6
926 #define	L2_S_PROTO		L2_S_PROTO_armv6n
927 
928 #define	pmap_copy_page(s, d)	pmap_copy_page_generic((s), (d))
929 #define	pmap_zero_page(d)	pmap_zero_page_generic((d))
930 #elif ARM_MMU_V6C != 0
931 #define	L1_S_PROT_U		L1_S_PROT_U_generic
932 #define	L1_S_PROT_W		L1_S_PROT_W_generic
933 #define	L1_S_PROT_RO		L1_S_PROT_RO_generic
934 #define	L1_S_PROT_MASK		L1_S_PROT_MASK_generic
935 
936 #define	L2_S_PROT_U		L2_S_PROT_U_generic
937 #define	L2_S_PROT_W		L2_S_PROT_W_generic
938 #define	L2_S_PROT_RO		L2_S_PROT_RO_generic
939 #define	L2_S_PROT_MASK		L2_S_PROT_MASK_generic
940 
941 #define	L2_L_PROT_U		L2_L_PROT_U_generic
942 #define	L2_L_PROT_W		L2_L_PROT_W_generic
943 #define	L2_L_PROT_RO		L2_L_PROT_RO_generic
944 #define	L2_L_PROT_MASK		L2_L_PROT_MASK_generic
945 
946 #define	L1_S_CACHE_MASK		L1_S_CACHE_MASK_generic
947 #define	L2_L_CACHE_MASK		L2_L_CACHE_MASK_generic
948 #define	L2_S_CACHE_MASK		L2_S_CACHE_MASK_generic
949 
950 #define	L1_SS_PROTO		L1_SS_PROTO_armv6
951 #define	L1_S_PROTO		L1_S_PROTO_generic
952 #define	L1_C_PROTO		L1_C_PROTO_generic
953 #define	L2_S_PROTO		L2_S_PROTO_generic
954 
955 #define	pmap_copy_page(s, d)	pmap_copy_page_generic((s), (d))
956 #define	pmap_zero_page(d)	pmap_zero_page_generic((d))
957 #elif ARM_MMU_XSCALE == 1
958 #define	L1_S_PROT_U		L1_S_PROT_U_generic
959 #define	L1_S_PROT_W		L1_S_PROT_W_generic
960 #define	L1_S_PROT_RO		L1_S_PROT_RO_generic
961 #define	L1_S_PROT_MASK		L1_S_PROT_MASK_generic
962 
963 #define	L2_S_PROT_U		L2_S_PROT_U_xscale
964 #define	L2_S_PROT_W		L2_S_PROT_W_xscale
965 #define	L2_S_PROT_RO		L2_S_PROT_RO_xscale
966 #define	L2_S_PROT_MASK		L2_S_PROT_MASK_xscale
967 
968 #define	L2_L_PROT_U		L2_L_PROT_U_generic
969 #define	L2_L_PROT_W		L2_L_PROT_W_generic
970 #define	L2_L_PROT_RO		L2_L_PROT_RO_generic
971 #define	L2_L_PROT_MASK		L2_L_PROT_MASK_generic
972 
973 #define	L1_S_CACHE_MASK		L1_S_CACHE_MASK_xscale
974 #define	L2_L_CACHE_MASK		L2_L_CACHE_MASK_xscale
975 #define	L2_S_CACHE_MASK		L2_S_CACHE_MASK_xscale
976 
977 #define	L1_SS_PROTO		L1_SS_PROTO_xscale
978 #define	L1_S_PROTO		L1_S_PROTO_xscale
979 #define	L1_C_PROTO		L1_C_PROTO_xscale
980 #define	L2_S_PROTO		L2_S_PROTO_xscale
981 
982 #define	pmap_copy_page(s, d)	pmap_copy_page_xscale((s), (d))
983 #define	pmap_zero_page(d)	pmap_zero_page_xscale((d))
984 #elif ARM_MMU_V7 == 1
985 #define	L1_S_PROT_U		L1_S_PROT_U_armv7
986 #define	L1_S_PROT_W		L1_S_PROT_W_armv7
987 #define	L1_S_PROT_RO		L1_S_PROT_RO_armv7
988 #define	L1_S_PROT_MASK		L1_S_PROT_MASK_armv7
989 
990 #define	L2_S_PROT_U		L2_S_PROT_U_armv7
991 #define	L2_S_PROT_W		L2_S_PROT_W_armv7
992 #define	L2_S_PROT_RO		L2_S_PROT_RO_armv7
993 #define	L2_S_PROT_MASK		L2_S_PROT_MASK_armv7
994 
995 #define	L2_L_PROT_U		L2_L_PROT_U_armv7
996 #define	L2_L_PROT_W		L2_L_PROT_W_armv7
997 #define	L2_L_PROT_RO		L2_L_PROT_RO_armv7
998 #define	L2_L_PROT_MASK		L2_L_PROT_MASK_armv7
999 
1000 #define	L1_S_CACHE_MASK		L1_S_CACHE_MASK_armv7
1001 #define	L2_L_CACHE_MASK		L2_L_CACHE_MASK_armv7
1002 #define	L2_S_CACHE_MASK		L2_S_CACHE_MASK_armv7
1003 
1004 /* These prototypes make writeable mappings, while the other MMU types
1005  * make read-only mappings. */
1006 #define	L1_SS_PROTO		L1_SS_PROTO_armv7
1007 #define	L1_S_PROTO		L1_S_PROTO_armv7
1008 #define	L1_C_PROTO		L1_C_PROTO_armv7
1009 #define	L2_S_PROTO		L2_S_PROTO_armv7
1010 
1011 #define	pmap_copy_page(s, d)	pmap_copy_page_generic((s), (d))
1012 #define	pmap_zero_page(d)	pmap_zero_page_generic((d))
1013 #endif /* ARM_NMMUS > 1 */
1014 
1015 /*
1016  * Macros to set and query the write permission on page descriptors.
1017  */
1018 #define l1pte_set_writable(pte)	(((pte) & ~L1_S_PROT_RO) | L1_S_PROT_W)
1019 #define l1pte_set_readonly(pte)	(((pte) & ~L1_S_PROT_W) | L1_S_PROT_RO)
1020 #define l2pte_set_writable(pte)	(((pte) & ~L2_S_PROT_RO) | L2_S_PROT_W)
1021 #define l2pte_set_readonly(pte)	(((pte) & ~L2_S_PROT_W) | L2_S_PROT_RO)
1022 
1023 #define l2pte_writable_p(pte)	(((pte) & L2_S_PROT_W) == L2_S_PROT_W && \
1024 				 (L2_S_PROT_RO == 0 || \
1025 				  ((pte) & L2_S_PROT_RO) != L2_S_PROT_RO))
1026 
1027 /*
1028  * These macros return various bits based on kernel/user and protection.
1029  * Note that the compiler will usually fold these at compile time.
1030  */
1031 #define	L1_S_PROT(ku, pr)	((((ku) == PTE_USER) ? L1_S_PROT_U : 0) | \
1032 				 (((pr) & VM_PROT_WRITE) ? L1_S_PROT_W : L1_S_PROT_RO))
1033 
1034 #define	L2_L_PROT(ku, pr)	((((ku) == PTE_USER) ? L2_L_PROT_U : 0) | \
1035 				 (((pr) & VM_PROT_WRITE) ? L2_L_PROT_W : L2_L_PROT_RO))
1036 
1037 #define	L2_S_PROT(ku, pr)	((((ku) == PTE_USER) ? L2_S_PROT_U : 0) | \
1038 				 (((pr) & VM_PROT_WRITE) ? L2_S_PROT_W : L2_S_PROT_RO))
1039 
1040 /*
1041  * Macros to test if a mapping is mappable with an L1 SuperSection,
1042  * L1 Section, or an L2 Large Page mapping.
1043  */
1044 #define	L1_SS_MAPPABLE_P(va, pa, size)					\
1045 	((((va) | (pa)) & L1_SS_OFFSET) == 0 && (size) >= L1_SS_SIZE)
1046 
1047 #define	L1_S_MAPPABLE_P(va, pa, size)					\
1048 	((((va) | (pa)) & L1_S_OFFSET) == 0 && (size) >= L1_S_SIZE)
1049 
1050 #define	L2_L_MAPPABLE_P(va, pa, size)					\
1051 	((((va) | (pa)) & L2_L_OFFSET) == 0 && (size) >= L2_L_SIZE)
1052 
1053 #ifndef _LOCORE
1054 /*
1055  * Hooks for the pool allocator.
1056  */
1057 #define	POOL_VTOPHYS(va)	vtophys((vaddr_t) (va))
1058 extern paddr_t physical_start, physical_end;
1059 #ifdef PMAP_NEED_ALLOC_POOLPAGE
1060 struct vm_page *arm_pmap_alloc_poolpage(int);
1061 #define	PMAP_ALLOC_POOLPAGE	arm_pmap_alloc_poolpage
1062 #endif
1063 #if defined(PMAP_NEED_ALLOC_POOLPAGE) || defined(__HAVE_MM_MD_DIRECT_MAPPED_PHYS)
1064 vaddr_t	pmap_map_poolpage(paddr_t);
1065 paddr_t	pmap_unmap_poolpage(vaddr_t);
1066 #define	PMAP_MAP_POOLPAGE(pa)	pmap_map_poolpage(pa)
1067 #define PMAP_UNMAP_POOLPAGE(va)	pmap_unmap_poolpage(va)
1068 #endif
1069 
1070 #define __HAVE_PMAP_PV_TRACK	1
1071 
1072 void pmap_pv_protect(paddr_t, vm_prot_t);
1073 
1074 struct pmap_page {
1075 	SLIST_HEAD(,pv_entry) pvh_list;		/* pv_entry list */
1076 	int pvh_attrs;				/* page attributes */
1077 	u_int uro_mappings;
1078 	u_int urw_mappings;
1079 	union {
1080 		u_short s_mappings[2];	/* Assume kernel count <= 65535 */
1081 		u_int i_mappings;
1082 	} k_u;
1083 };
1084 
1085 /*
1086  * pmap-specific data store in the vm_page structure.
1087  */
1088 #define	__HAVE_VM_PAGE_MD
1089 struct vm_page_md {
1090 	struct pmap_page pp;
1091 #define	pvh_list	pp.pvh_list
1092 #define	pvh_attrs	pp.pvh_attrs
1093 #define	uro_mappings	pp.uro_mappings
1094 #define	urw_mappings	pp.urw_mappings
1095 #define	kro_mappings	pp.k_u.s_mappings[0]
1096 #define	krw_mappings	pp.k_u.s_mappings[1]
1097 #define	k_mappings	pp.k_u.i_mappings
1098 };
1099 
1100 #define PMAP_PAGE_TO_MD(ppage) container_of((ppage), struct vm_page_md, pp)
1101 
1102 /*
1103  * Set the default color of each page.
1104  */
1105 #if ARM_MMU_V6 > 0
1106 #define	VM_MDPAGE_PVH_ATTRS_INIT(pg) \
1107 	(pg)->mdpage.pvh_attrs = (pg)->phys_addr & arm_cache_prefer_mask
1108 #else
1109 #define	VM_MDPAGE_PVH_ATTRS_INIT(pg) \
1110 	(pg)->mdpage.pvh_attrs = 0
1111 #endif
1112 
1113 #define	VM_MDPAGE_INIT(pg)						\
1114 do {									\
1115 	SLIST_INIT(&(pg)->mdpage.pvh_list);				\
1116 	VM_MDPAGE_PVH_ATTRS_INIT(pg);					\
1117 	(pg)->mdpage.uro_mappings = 0;					\
1118 	(pg)->mdpage.urw_mappings = 0;					\
1119 	(pg)->mdpage.k_mappings = 0;					\
1120 } while (/*CONSTCOND*/0)
1121 
1122 #endif /* !_LOCORE */
1123 
1124 #endif /* _KERNEL */
1125 
1126 #endif	/* _ARM32_PMAP_H_ */
1127