1 2-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc 3 4-- This file is part of VESTs (Vhdl tESTs). 5 6-- VESTs is free software; you can redistribute it and/or modify it 7-- under the terms of the GNU General Public License as published by the 8-- Free Software Foundation; either version 2 of the License, or (at 9-- your option) any later version. 10 11-- VESTs is distributed in the hope that it will be useful, but WITHOUT 12-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 14-- for more details. 15 16-- You should have received a copy of the GNU General Public License 17-- along with VESTs; if not, write to the Free Software Foundation, 18-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 19 20-- --------------------------------------------------------------------- 21-- 22-- $Id: ch_15_regmp.vhd,v 1.3 2001-11-03 23:19:37 paw Exp $ 23-- $Revision: 1.3 $ 24-- 25-- --------------------------------------------------------------------- 26 27library ieee; 28use ieee.std_logic_1164.all; 29 30use work.dlx_types.all; 31 32entity reg_multiple_plus_one_out is 33 generic ( num_outputs : positive; 34 Tpd : delay_length ); 35 port ( d : in dlx_word; 36 q0 : out dlx_word; 37 q : out dlx_word_array(1 to num_outputs); 38 latch_en : in std_logic; 39 out_en : in std_logic_vector(1 to num_outputs) ); 40end entity reg_multiple_plus_one_out; 41