1 /***************************************************************************
2  *   Copyright (C) 2005 by Dominic Rath                                    *
3  *   Dominic.Rath@gmx.de                                                   *
4  *                                                                         *
5  *   Copyright (C) 2006 by Magnus Lundin                                   *
6  *   lundin@mlu.mine.nu                                                    *
7  *                                                                         *
8  *   Copyright (C) 2008 by Spencer Oliver                                  *
9  *   spen@spen-soft.co.uk                                                  *
10  *                                                                         *
11  *   Copyright (C) 2009 by Dirk Behme                                      *
12  *   dirk.behme@gmail.com - copy from cortex_m3                            *
13  *                                                                         *
14  *   This program is free software; you can redistribute it and/or modify  *
15  *   it under the terms of the GNU General Public License as published by  *
16  *   the Free Software Foundation; either version 2 of the License, or     *
17  *   (at your option) any later version.                                   *
18  *                                                                         *
19  *   This program is distributed in the hope that it will be useful,       *
20  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
21  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
22  *   GNU General Public License for more details.                          *
23  *                                                                         *
24  *   You should have received a copy of the GNU General Public License     *
25  *   along with this program.  If not, see <http://www.gnu.org/licenses/>. *
26  ***************************************************************************/
27 
28 #ifndef OPENOCD_TARGET_CORTEX_A_H
29 #define OPENOCD_TARGET_CORTEX_A_H
30 
31 #include "armv7a.h"
32 
33 #define CORTEX_A_COMMON_MAGIC 0x411fc082
34 #define CORTEX_A15_COMMON_MAGIC 0x413fc0f1
35 
36 #define CORTEX_A5_PARTNUM 0xc05
37 #define CORTEX_A7_PARTNUM 0xc07
38 #define CORTEX_A8_PARTNUM 0xc08
39 #define CORTEX_A9_PARTNUM 0xc09
40 #define CORTEX_A15_PARTNUM 0xc0f
41 #define CORTEX_A_MIDR_PARTNUM_MASK 0x0000fff0
42 #define CORTEX_A_MIDR_PARTNUM_SHIFT 4
43 
44 #define CPUDBG_CPUID	0xD00
45 #define CPUDBG_CTYPR	0xD04
46 #define CPUDBG_TTYPR	0xD0C
47 #define CPUDBG_LOCKACCESS 0xFB0
48 #define CPUDBG_LOCKSTATUS 0xFB4
49 #define CPUDBG_OSLAR_LK_MASK (1 << 1)
50 
51 #define BRP_NORMAL 0
52 #define BRP_CONTEXT 1
53 
54 #define CORTEX_A_PADDRDBG_CPU_SHIFT 13
55 
56 enum cortex_a_isrmasking_mode {
57 	CORTEX_A_ISRMASK_OFF,
58 	CORTEX_A_ISRMASK_ON,
59 };
60 
61 enum cortex_a_dacrfixup_mode {
62 	CORTEX_A_DACRFIXUP_OFF,
63 	CORTEX_A_DACRFIXUP_ON
64 };
65 
66 struct cortex_a_brp {
67 	int used;
68 	int type;
69 	uint32_t value;
70 	uint32_t control;
71 	uint8_t BRPn;
72 };
73 
74 struct cortex_a_common {
75 	int common_magic;
76 
77 	/* Context information */
78 	uint32_t cpudbg_dscr;
79 
80 	/* Saved cp15 registers */
81 	uint32_t cp15_control_reg;
82 	/* latest cp15 register value written and cpsr processor mode */
83 	uint32_t cp15_control_reg_curr;
84 	/* auxiliary control reg */
85 	uint32_t cp15_aux_control_reg;
86 	/* DACR */
87 	uint32_t cp15_dacr_reg;
88 	enum arm_mode curr_mode;
89 
90 	/* Breakpoint register pairs */
91 	int brp_num_context;
92 	int brp_num;
93 	int brp_num_available;
94 	struct cortex_a_brp *brp_list;
95 
96 	uint32_t cpuid;
97 	uint32_t didr;
98 
99 	enum cortex_a_isrmasking_mode isrmasking_mode;
100 	enum cortex_a_dacrfixup_mode dacrfixup_mode;
101 
102 	struct armv7a_common armv7a_common;
103 
104 };
105 
106 static inline struct cortex_a_common *
target_to_cortex_a(struct target * target)107 target_to_cortex_a(struct target *target)
108 {
109 	return container_of(target->arch_info, struct cortex_a_common, armv7a_common.arm);
110 }
111 
112 #endif /* OPENOCD_TARGET_CORTEX_A_H */
113