1# powerpc cpu description file 2# this file is read by genmdesc to pruduce a table with all the relevant information 3# about the cpu instructions that may be used by the regsiter allocator, the scheduler 4# and other parts of the arch-dependent part of mini. 5# 6# An opcode name is followed by a colon and optional specifiers. 7# A specifier has a name, a colon and a value. Specifiers are separated by white space. 8# Here is a description of the specifiers valid for this file and their possible values. 9# 10# dest:register describes the destination register of an instruction 11# src1:register describes the first source register of an instruction 12# src2:register describes the second source register of an instruction 13# 14# register may have the following values: 15# i integer register 16# a r3 register (output from calls) 17# b base register (used in address references) 18# f floating point register 19# 20# len:number describe the maximun length in bytes of the instruction 21# number is a positive integer 22# 23# cost:number describe how many cycles are needed to complete the instruction (unused) 24# 25# clob:spec describe if the instruction clobbers registers or has special needs 26# 27# spec can be one of the following characters: 28# c clobbers caller-save registers 29# r 'reserves' the destination register until a later instruction unreserves it 30# used mostly to set output registers in function calls 31# 32# flags:spec describe if the instruction uses or sets the flags (unused) 33# 34# spec can be one of the following chars: 35# s sets the flags 36# u uses the flags 37# m uses and modifies the flags 38# 39# res:spec describe what units are used in the processor (unused) 40# 41# delay: describe delay slots (unused) 42# 43# the required specifiers are: len, clob (if registers are clobbered), the registers 44# specifiers if the registers are actually used, flags (when scheduling is implemented). 45# 46# See the code in mini-x86.c for more details on how the specifiers are used. 47# 48tailcall: len:124 clob:c 49memory_barrier: len:4 50nop: len:4 51relaxed_nop: len:4 52break: len:40 53seq_point: len:48 54il_seq_point: len:0 55jmp: len:96 56call: dest:a clob:c len:36 57br: len:4 58throw: src1:i len:40 59rethrow: src1:i len:40 60ckfinite: dest:f src1:f 61ppc_check_finite: src1:i len:16 62add_ovf_carry: dest:i src1:i src2:i len:16 63sub_ovf_carry: dest:i src1:i src2:i len:16 64add_ovf_un_carry: dest:i src1:i src2:i len:16 65sub_ovf_un_carry: dest:i src1:i src2:i len:16 66start_handler: len:16 67endfinally: len:20 68ceq: dest:i len:12 69cgt: dest:i len:12 70cgt.un: dest:i len:12 71clt: dest:i len:12 72clt.un: dest:i len:12 73localloc: dest:i src1:i len:60 74compare: src1:i src2:i len:4 75compare_imm: src1:i len:12 76fcompare: src1:f src2:f len:12 77oparglist: src1:i len:12 78setlret: src1:i src2:i len:12 79checkthis: src1:b len:4 80voidcall: len:36 clob:c 81voidcall_reg: src1:i len:16 clob:c 82voidcall_membase: src1:b len:16 clob:c 83fcall: dest:g len:36 clob:c 84fcall_reg: dest:g src1:i len:16 clob:c 85fcall_membase: dest:g src1:b len:16 clob:c 86lcall: dest:a len:36 clob:c 87lcall_reg: dest:a src1:i len:16 clob:c 88lcall_membase: dest:a src1:b len:16 clob:c 89vcall: len:16 clob:c 90vcall_reg: src1:i len:16 clob:c 91vcall_membase: src1:b len:12 clob:c 92call_reg: dest:a src1:i len:16 clob:c 93call_membase: dest:a src1:b len:16 clob:c 94iconst: dest:i len:20 95i8const: dest:i len:20 96r4const: dest:f len:12 97r8const: dest:f len:24 98label: len:0 99store_membase_reg: dest:b src1:i len:12 100storei1_membase_reg: dest:b src1:i len:12 101storei2_membase_reg: dest:b src1:i len:12 102storei4_membase_reg: dest:b src1:i len:12 103storei8_membase_reg: dest:b src1:i len:12 104storer4_membase_reg: dest:b src1:f len:16 105storer8_membase_reg: dest:b src1:f len:12 106load_membase: dest:i src1:b len:12 107loadi1_membase: dest:i src1:b len:16 108loadu1_membase: dest:i src1:b len:12 109loadi2_membase: dest:i src1:b len:12 110loadu2_membase: dest:i src1:b len:12 111loadi4_membase: dest:i src1:b len:12 112loadu4_membase: dest:i src1:b len:12 113loadi8_membase: dest:i src1:b len:12 114loadr4_membase: dest:f src1:b len:12 115loadr8_membase: dest:f src1:b len:12 116load_memindex: dest:i src1:b src2:i len:4 117loadi1_memindex: dest:i src1:b src2:i len:8 118loadu1_memindex: dest:i src1:b src2:i len:4 119loadi2_memindex: dest:i src1:b src2:i len:4 120loadu2_memindex: dest:i src1:b src2:i len:4 121loadi4_memindex: dest:i src1:b src2:i len:4 122loadu4_memindex: dest:i src1:b src2:i len:4 123loadi8_memindex: dest:i src1:b src2:i len:4 124loadr4_memindex: dest:f src1:b src2:i len:4 125loadr8_memindex: dest:f src1:b src2:i len:4 126store_memindex: dest:b src1:i src2:i len:4 127storei1_memindex: dest:b src1:i src2:i len:4 128storei2_memindex: dest:b src1:i src2:i len:4 129storei4_memindex: dest:b src1:i src2:i len:4 130storei8_memindex: dest:b src1:i src2:i len:4 131storer4_memindex: dest:b src1:i src2:i len:8 132storer8_memindex: dest:b src1:i src2:i len:4 133loadu4_mem: dest:i len:8 134move: dest:i src1:i len:4 135fmove: dest:f src1:f len:4 136add_imm: dest:i src1:i len:4 137sub_imm: dest:i src1:i len:4 138mul_imm: dest:i src1:i len:4 139# there is no actual support for division or reminder by immediate 140# we simulate them, though (but we need to change the burg rules 141# to allocate a symbolic reg for src2) 142div_imm: dest:i src1:i src2:i len:20 143div_un_imm: dest:i src1:i src2:i len:12 144rem_imm: dest:i src1:i src2:i len:28 145rem_un_imm: dest:i src1:i src2:i len:16 146and_imm: dest:i src1:i len:4 147or_imm: dest:i src1:i len:4 148xor_imm: dest:i src1:i len:4 149shl_imm: dest:i src1:i len:4 150shr_imm: dest:i src1:i len:4 151shr_un_imm: dest:i src1:i len:4 152cond_exc_eq: len:8 153cond_exc_ne_un: len:8 154cond_exc_lt: len:8 155cond_exc_lt_un: len:8 156cond_exc_gt: len:8 157cond_exc_gt_un: len:8 158cond_exc_ge: len:8 159cond_exc_ge_un: len:8 160cond_exc_le: len:8 161cond_exc_le_un: len:8 162cond_exc_ov: len:12 163cond_exc_no: len:8 164cond_exc_c: len:12 165cond_exc_nc: len:8 166long_conv_to_ovf_i: dest:i src1:i src2:i len:32 167#long_mul_ovf: 168long_conv_to_r_un: dest:f src1:i src2:i len:37 169float_beq: len:8 170float_bne_un: len:8 171float_blt: len:8 172float_blt_un: len:8 173float_bgt: len:8 174float_bgt_un: len:8 175float_bge: len:8 176float_bge_un: len:8 177float_ble: len:8 178float_ble_un: len:8 179float_add: dest:f src1:f src2:f len:4 180float_sub: dest:f src1:f src2:f len:4 181float_mul: dest:f src1:f src2:f len:4 182float_div: dest:f src1:f src2:f len:4 183float_div_un: dest:f src1:f src2:f len:4 184float_rem: dest:f src1:f src2:f len:16 185float_rem_un: dest:f src1:f src2:f len:16 186float_neg: dest:f src1:f len:4 187float_not: dest:f src1:f len:4 188float_conv_to_i1: dest:i src1:f len:40 189float_conv_to_i2: dest:i src1:f len:40 190float_conv_to_i4: dest:i src1:f len:40 191float_conv_to_i8: dest:i src1:f len:40 192float_conv_to_r4: dest:f src1:f len:4 193float_conv_to_u4: dest:i src1:f len:40 194float_conv_to_u8: dest:i src1:f len:40 195float_conv_to_u2: dest:i src1:f len:40 196float_conv_to_u1: dest:i src1:f len:40 197float_conv_to_i: dest:i src1:f len:40 198float_ceq: dest:i src1:f src2:f len:16 199float_cgt: dest:i src1:f src2:f len:16 200float_cgt_un: dest:i src1:f src2:f len:20 201float_clt: dest:i src1:f src2:f len:16 202float_clt_un: dest:i src1:f src2:f len:20 203float_conv_to_u: dest:i src1:f len:36 204float_cneq: dest:i src1:f src2:f len:16 205float_cge: dest:i src1:f src2:f len:16 206float_cle: dest:i src1:f src2:f len:16 207call_handler: len:12 clob:c 208endfilter: src1:i len:20 209aot_const: dest:i len:8 210load_gotaddr: dest:i len:32 211got_entry: dest:i src1:b len:32 212sqrt: dest:f src1:f len:4 213adc: dest:i src1:i src2:i len:4 214addcc: dest:i src1:i src2:i len:4 215subcc: dest:i src1:i src2:i len:4 216addcc_imm: dest:i src1:i len:4 217sbb: dest:i src1:i src2:i len:4 218br_reg: src1:i len:8 219ppc_subfic: dest:i src1:i len:4 220ppc_subfze: dest:i src1:i len:4 221bigmul: len:12 dest:i src1:i src2:i 222bigmul_un: len:12 dest:i src1:i src2:i 223 224# Linear IR opcodes 225dummy_use: src1:i len:0 226dummy_store: len:0 227not_reached: len:0 228not_null: src1:i len:0 229 230# 32 bit opcodes 231int_add: dest:i src1:i src2:i len:4 232int_sub: dest:i src1:i src2:i len:4 233int_mul: dest:i src1:i src2:i len:4 234int_div: dest:i src1:i src2:i len:40 235int_div_un: dest:i src1:i src2:i len:16 236int_rem: dest:i src1:i src2:i len:48 237int_rem_un: dest:i src1:i src2:i len:24 238int_and: dest:i src1:i src2:i len:4 239int_or: dest:i src1:i src2:i len:4 240int_xor: dest:i src1:i src2:i len:4 241int_shl: dest:i src1:i src2:i len:4 242int_shr: dest:i src1:i src2:i len:4 243int_shr_un: dest:i src1:i src2:i len:4 244int_neg: dest:i src1:i len:4 245int_not: dest:i src1:i len:4 246int_conv_to_i1: dest:i src1:i len:8 247int_conv_to_i2: dest:i src1:i len:8 248int_conv_to_i4: dest:i src1:i len:4 249sext_i4: dest:i src1:i len:4 250int_conv_to_r4: dest:f src1:i len:20 251int_conv_to_r8: dest:f src1:i len:16 252int_conv_to_u4: dest:i src1:i len:4 253int_conv_to_u2: dest:i src1:i len:8 254int_conv_to_u1: dest:i src1:i len:4 255int_beq: len:8 256int_bge: len:8 257int_bgt: len:8 258int_ble: len:8 259int_blt: len:8 260int_bne_un: len:8 261int_bge_un: len:8 262int_bgt_un: len:8 263int_ble_un: len:8 264int_blt_un: len:8 265int_add_ovf: dest:i src1:i src2:i len:16 266int_add_ovf_un: dest:i src1:i src2:i len:16 267int_mul_ovf: dest:i src1:i src2:i len:16 268int_mul_ovf_un: dest:i src1:i src2:i len:16 269int_sub_ovf: dest:i src1:i src2:i len:16 270int_sub_ovf_un: dest:i src1:i src2:i len:16 271 272int_adc: dest:i src1:i src2:i len:4 273int_addcc: dest:i src1:i src2:i len:4 274int_subcc: dest:i src1:i src2:i len:4 275int_sbb: dest:i src1:i src2:i len:4 276int_adc_imm: dest:i src1:i len:12 277int_sbb_imm: dest:i src1:i len:12 278 279int_add_imm: dest:i src1:i len:4 280int_sub_imm: dest:i src1:i len:12 281int_mul_imm: dest:i src1:i len:12 282int_div_imm: dest:i src1:i len:20 283int_div_un_imm: dest:i src1:i len:12 284int_rem_imm: dest:i src1:i len:28 285int_rem_un_imm: dest:i src1:i len:16 286int_and_imm: dest:i src1:i len:12 287int_or_imm: dest:i src1:i len:12 288int_xor_imm: dest:i src1:i len:12 289int_shl_imm: dest:i src1:i len:8 290int_shr_imm: dest:i src1:i len:8 291int_shr_un_imm: dest:i src1:i len:8 292 293int_ceq: dest:i len:12 294int_cgt: dest:i len:12 295int_cgt_un: dest:i len:12 296int_clt: dest:i len:12 297int_clt_un: dest:i len:12 298 299int_cneq: dest:i len:12 300int_cge: dest:i len:12 301int_cle: dest:i len:12 302int_cge_un: dest:i len:12 303int_cle_un: dest:i len:12 304 305cond_exc_ieq: len:8 306cond_exc_ine_un: len:8 307cond_exc_ilt: len:8 308cond_exc_ilt_un: len:8 309cond_exc_igt: len:8 310cond_exc_igt_un: len:8 311cond_exc_ige: len:8 312cond_exc_ige_un: len:8 313cond_exc_ile: len:8 314cond_exc_ile_un: len:8 315cond_exc_iov: len:12 316cond_exc_ino: len:8 317cond_exc_ic: len:12 318cond_exc_inc: len:8 319 320icompare: src1:i src2:i len:4 321icompare_imm: src1:i len:12 322 323# 64 bit opcodes 324long_add: dest:i src1:i src2:i len:4 325long_sub: dest:i src1:i src2:i len:4 326long_mul: dest:i src1:i src2:i len:4 327long_mul_imm: dest:i src1:i len:4 328long_div: dest:i src1:i src2:i len:40 329long_div_un: dest:i src1:i src2:i len:16 330long_rem: dest:i src1:i src2:i len:48 331long_rem_un: dest:i src1:i src2:i len:24 332long_and: dest:i src1:i src2:i len:4 333long_or: dest:i src1:i src2:i len:4 334long_xor: dest:i src1:i src2:i len:4 335long_shl: dest:i src1:i src2:i len:4 336long_shl_imm: dest:i src1:i len:4 337long_shr: dest:i src1:i src2:i len:4 338long_shr_un: dest:i src1:i src2:i len:4 339long_shr_imm: dest:i src1:i len:4 340long_shr_un_imm: dest:i src1:i len:4 341long_neg: dest:i src1:i len:4 342long_not: dest:i src1:i len:4 343long_conv_to_i1: dest:i src1:i len:4 344long_conv_to_i2: dest:i src1:i len:4 345long_conv_to_i4: dest:i src1:i len:4 346long_conv_to_r4: dest:f src1:i len:16 347long_conv_to_r8: dest:f src1:i len:12 348long_conv_to_u4: dest:i src1:i 349long_conv_to_u2: dest:i src1:i len:4 350long_conv_to_u1: dest:i src1:i len:4 351zext_i4: dest:i src1:i len:4 352 353long_beq: len:8 354long_bge: len:8 355long_bgt: len:8 356long_ble: len:8 357long_blt: len:8 358long_bne_un: len:8 359long_bge_un: len:8 360long_bgt_un: len:8 361long_ble_un: len:8 362long_blt_un: len:8 363long_add_ovf: dest:i src1:i src2:i len:16 364long_add_ovf_un: dest:i src1:i src2:i len:16 365long_mul_ovf: dest:i src1:i src2:i len:16 366long_mul_ovf_un: dest:i src1:i src2:i len:16 367long_sub_ovf: dest:i src1:i src2:i len:16 368long_sub_ovf_un: dest:i src1:i src2:i len:16 369 370long_ceq: dest:i len:12 371long_cgt: dest:i len:12 372long_cgt_un: dest:i len:12 373long_clt: dest:i len:12 374long_clt_un: dest:i len:12 375 376long_add_imm: dest:i src1:i clob:1 len:4 377long_sub_imm: dest:i src1:i clob:1 len:4 378long_and_imm: dest:i src1:i clob:1 len:4 379long_or_imm: dest:i src1:i clob:1 len:4 380long_xor_imm: dest:i src1:i clob:1 len:4 381 382lcompare: src1:i src2:i len:4 383lcompare_imm: src1:i len:12 384 385#long_conv_to_ovf_i4_2: dest:i src1:i src2:i len:30 386 387vcall2: len:36 clob:c 388vcall2_reg: src1:i len:16 clob:c 389vcall2_membase: src1:b len:16 clob:c 390 391jump_table: dest:i len:20 392 393atomic_add_i4: src1:b src2:i dest:i len:28 394atomic_add_i8: src1:b src2:i dest:i len:28 395atomic_cas_i4: src1:b src2:i src3:i dest:i len:38 396atomic_cas_i8: src1:b src2:i src3:i dest:i len:38 397 398gc_safe_point: len:0 399