1 /* $OpenBSD: if_pgt_cardbus.c,v 1.20 2024/05/24 06:26:47 jsg Exp $ */
2
3 /*
4 * Copyright (c) 2006 Marcus Glocker <mglocker@openbsd.org>
5 *
6 * Permission to use, copy, modify, and distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 */
18
19 /*
20 * CardBus front-end for the PrismGT
21 */
22
23 #include "bpfilter.h"
24
25 #include <sys/param.h>
26 #include <sys/systm.h>
27 #include <sys/timeout.h>
28 #include <sys/device.h>
29
30 #include <machine/bus.h>
31
32 #include <net/if.h>
33 #include <net/if_media.h>
34
35 #include <netinet/in.h>
36 #include <netinet/if_ether.h>
37
38 #include <net80211/ieee80211_var.h>
39 #include <net80211/ieee80211_radiotap.h>
40
41 #include <dev/ic/pgtreg.h>
42 #include <dev/ic/pgtvar.h>
43
44 #include <dev/pci/pcireg.h>
45 #include <dev/pci/pcivar.h>
46 #include <dev/pci/pcidevs.h>
47
48 #include <dev/cardbus/cardbusvar.h>
49
50 struct pgt_cardbus_softc {
51 struct pgt_softc sc_pgt;
52 cardbus_devfunc_t sc_ct;
53 pcitag_t sc_tag;
54 int sc_intrline;
55
56 void *sc_ih;
57 bus_size_t sc_mapsize;
58 pcireg_t sc_bar0_val;
59 pci_chipset_tag_t sc_pc;
60 };
61
62 int pgt_cardbus_match(struct device *, void *, void *);
63 void pgt_cardbus_attach(struct device *, struct device *, void *);
64 int pgt_cardbus_detach(struct device *, int);
65 int pgt_cardbus_enable(struct pgt_softc *);
66 void pgt_cardbus_disable(struct pgt_softc *);
67 void pgt_cardbus_power(struct pgt_softc *, int);
68 void pgt_cardbus_setup(struct pgt_cardbus_softc *);
69
70 const struct cfattach pgt_cardbus_ca = {
71 sizeof(struct pgt_cardbus_softc), pgt_cardbus_match, pgt_cardbus_attach,
72 pgt_cardbus_detach
73 };
74
75 const struct pci_matchid pgt_cardbus_devices[] = {
76 { PCI_VENDOR_INTERSIL, PCI_PRODUCT_INTERSIL_ISL3877 },
77 { PCI_VENDOR_INTERSIL, PCI_PRODUCT_INTERSIL_ISL3890 },
78 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CRWE154G72 }
79 };
80
81 int
pgt_cardbus_match(struct device * parent,void * match,void * aux)82 pgt_cardbus_match(struct device *parent, void *match, void *aux)
83 {
84 return (cardbus_matchbyid((struct cardbus_attach_args *)aux,
85 pgt_cardbus_devices,
86 sizeof(pgt_cardbus_devices) / sizeof(pgt_cardbus_devices[0])));
87 }
88
89 void
pgt_cardbus_attach(struct device * parent,struct device * self,void * aux)90 pgt_cardbus_attach(struct device *parent, struct device *self, void *aux)
91 {
92 struct pgt_cardbus_softc *csc = (struct pgt_cardbus_softc *)self;
93 struct pgt_softc *sc = &csc->sc_pgt;
94 struct cardbus_attach_args *ca = aux;
95 cardbus_devfunc_t ct = ca->ca_ct;
96 bus_addr_t base;
97 int error;
98
99 sc->sc_dmat = ca->ca_dmat;
100 csc->sc_ct = ct;
101 csc->sc_tag = ca->ca_tag;
102 csc->sc_intrline = ca->ca_intrline;
103 csc->sc_pc = ca->ca_pc;
104
105 /* power management hooks */
106 sc->sc_enable = pgt_cardbus_enable;
107 sc->sc_disable = pgt_cardbus_disable;
108 sc->sc_power = pgt_cardbus_power;
109
110 /* remember chipset */
111 if (PCI_PRODUCT(ca->ca_id) == PCI_PRODUCT_INTERSIL_ISL3877)
112 sc->sc_flags |= SC_ISL3877;
113
114 /* map control / status registers */
115 error = Cardbus_mapreg_map(ct, CARDBUS_BASE0_REG,
116 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 0,
117 &sc->sc_iotag, &sc->sc_iohandle, &base, &csc->sc_mapsize);
118 if (error != 0) {
119 printf(": can't map mem space\n");
120 return;
121 }
122 csc->sc_bar0_val = base | PCI_MAPREG_TYPE_MEM;
123
124 /* disable all interrupts */
125 bus_space_write_4(sc->sc_iotag, sc->sc_iohandle, PGT_REG_INT_EN, 0);
126 (void)bus_space_read_4(sc->sc_iotag, sc->sc_iohandle, PGT_REG_INT_EN);
127 DELAY(PGT_WRITEIO_DELAY);
128
129 /* set up the PCI configuration registers */
130 pgt_cardbus_setup(csc);
131
132 printf(": irq %d\n", csc->sc_intrline);
133
134 config_mountroot(self, pgt_attach);
135 }
136
137 int
pgt_cardbus_detach(struct device * self,int flags)138 pgt_cardbus_detach(struct device *self, int flags)
139 {
140 struct pgt_cardbus_softc *csc = (struct pgt_cardbus_softc *)self;
141 struct pgt_softc *sc = &csc->sc_pgt;
142 cardbus_devfunc_t ct = csc->sc_ct;
143 cardbus_chipset_tag_t cc = ct->ct_cc;
144 cardbus_function_tag_t cf = ct->ct_cf;
145 int error;
146
147 error = pgt_detach(sc);
148 if (error != 0)
149 return (error);
150
151 /* unhook the interrupt handler */
152 if (csc->sc_ih != NULL) {
153 cardbus_intr_disestablish(cc, cf, csc->sc_ih);
154 csc->sc_ih = NULL;
155 }
156
157 /* release bus space and close window */
158 Cardbus_mapreg_unmap(ct, CARDBUS_BASE0_REG,
159 sc->sc_iotag, sc->sc_iohandle, csc->sc_mapsize);
160
161 return (0);
162 }
163
164 int
pgt_cardbus_enable(struct pgt_softc * sc)165 pgt_cardbus_enable(struct pgt_softc *sc)
166 {
167 struct pgt_cardbus_softc *csc = (struct pgt_cardbus_softc *)sc;
168 cardbus_devfunc_t ct = csc->sc_ct;
169 cardbus_chipset_tag_t cc = ct->ct_cc;
170 cardbus_function_tag_t cf = ct->ct_cf;
171
172 /* power on the socket */
173 Cardbus_function_enable(ct);
174
175 /* setup the PCI configuration registers */
176 pgt_cardbus_setup(csc);
177
178 /* map and establish the interrupt handler */
179 csc->sc_ih = cardbus_intr_establish(cc, cf, csc->sc_intrline, IPL_NET,
180 pgt_intr, sc, sc->sc_dev.dv_xname);
181 if (csc->sc_ih == NULL) {
182 printf("%s: could not establish interrupt at %d\n",
183 sc->sc_dev.dv_xname, csc->sc_intrline);
184 Cardbus_function_disable(ct);
185 return (1);
186 }
187
188 return (0);
189 }
190
191 void
pgt_cardbus_disable(struct pgt_softc * sc)192 pgt_cardbus_disable(struct pgt_softc *sc)
193 {
194 struct pgt_cardbus_softc *csc = (struct pgt_cardbus_softc *)sc;
195 cardbus_devfunc_t ct = csc->sc_ct;
196 cardbus_chipset_tag_t cc = ct->ct_cc;
197 cardbus_function_tag_t cf = ct->ct_cf;
198
199 /* unhook the interrupt handler */
200 cardbus_intr_disestablish(cc, cf, csc->sc_ih);
201 csc->sc_ih = NULL;
202
203 /* power down the socket */
204 Cardbus_function_disable(ct);
205 }
206
207 void
pgt_cardbus_power(struct pgt_softc * sc,int why)208 pgt_cardbus_power(struct pgt_softc *sc, int why)
209 {
210 if (why == DVACT_RESUME)
211 if (sc->sc_enable != NULL)
212 (*sc->sc_enable)(sc);
213 if (why == DVACT_SUSPEND)
214 if (sc->sc_disable != NULL)
215 (*sc->sc_disable)(sc);
216 }
217
218 void
pgt_cardbus_setup(struct pgt_cardbus_softc * csc)219 pgt_cardbus_setup(struct pgt_cardbus_softc *csc)
220 {
221 cardbus_devfunc_t ct = csc->sc_ct;
222 cardbus_chipset_tag_t cc = ct->ct_cc;
223 pci_chipset_tag_t pc = csc->sc_pc;
224 cardbus_function_tag_t cf = ct->ct_cf;
225 pcireg_t reg;
226
227 /* program the BAR */
228 pci_conf_write(pc, csc->sc_tag, CARDBUS_BASE0_REG,
229 csc->sc_bar0_val);
230
231 /* make sure the right access type is on the cardbus bridge */
232 (*cf->cardbus_ctrl)(cc, CARDBUS_MEM_ENABLE);
233 (*cf->cardbus_ctrl)(cc, CARDBUS_BM_ENABLE);
234
235 /* enable the appropriate bits in the PCI CSR */
236 reg = pci_conf_read(pc, csc->sc_tag,
237 PCI_COMMAND_STATUS_REG);
238 reg |= PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_MEM_ENABLE;
239 pci_conf_write(pc, csc->sc_tag, PCI_COMMAND_STATUS_REG,
240 reg);
241 }
242