1 /*
2 * Copyright 2021 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26
27
28 #include "dccg.h"
29 #include "clk_mgr_internal.h"
30
31 // For dce12_get_dp_ref_freq_khz
32 #include "dce100/dce_clk_mgr.h"
33 // For dcn20_update_clocks_update_dpp_dto
34 #include "dcn20/dcn20_clk_mgr.h"
35 #include "dcn31/dcn31_clk_mgr.h"
36 #include "dcn315_clk_mgr.h"
37
38 #include "core_types.h"
39 #include "dcn315_smu.h"
40 #include "dm_helpers.h"
41
42 #include "dc_dmub_srv.h"
43
44 #include "logger_types.h"
45 #undef DC_LOGGER
46 #define DC_LOGGER \
47 clk_mgr->base.base.ctx->logger
48
49 #include "link.h"
50
51 #define TO_CLK_MGR_DCN315(clk_mgr)\
52 container_of(clk_mgr, struct clk_mgr_dcn315, base)
53
54 #define UNSUPPORTED_DCFCLK 10000000
55 #define MIN_DPP_DISP_CLK 100000
56
dcn315_get_active_display_cnt_wa(struct dc * dc,struct dc_state * context)57 static int dcn315_get_active_display_cnt_wa(
58 struct dc *dc,
59 struct dc_state *context)
60 {
61 int i, display_count;
62 bool tmds_present = false;
63
64 display_count = 0;
65 for (i = 0; i < context->stream_count; i++) {
66 const struct dc_stream_state *stream = context->streams[i];
67
68 if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A ||
69 stream->signal == SIGNAL_TYPE_DVI_SINGLE_LINK ||
70 stream->signal == SIGNAL_TYPE_DVI_DUAL_LINK)
71 tmds_present = true;
72 }
73
74 for (i = 0; i < dc->link_count; i++) {
75 const struct dc_link *link = dc->links[i];
76
77 /* abusing the fact that the dig and phy are coupled to see if the phy is enabled */
78 if (link->link_enc && link->link_enc->funcs->is_dig_enabled &&
79 link->link_enc->funcs->is_dig_enabled(link->link_enc))
80 display_count++;
81 }
82
83 /* WA for hang on HDMI after display off back back on*/
84 if (display_count == 0 && tmds_present)
85 display_count = 1;
86
87 return display_count;
88 }
89
should_disable_otg(struct pipe_ctx * pipe)90 static bool should_disable_otg(struct pipe_ctx *pipe)
91 {
92 bool ret = true;
93
94 if (pipe->stream->link->link_enc && pipe->stream->link->link_enc->funcs->is_dig_enabled &&
95 pipe->stream->link->link_enc->funcs->is_dig_enabled(pipe->stream->link->link_enc))
96 ret = false;
97 return ret;
98 }
99
dcn315_disable_otg_wa(struct clk_mgr * clk_mgr_base,struct dc_state * context,bool disable)100 static void dcn315_disable_otg_wa(struct clk_mgr *clk_mgr_base, struct dc_state *context, bool disable)
101 {
102 struct dc *dc = clk_mgr_base->ctx->dc;
103 int i;
104
105 for (i = 0; i < dc->res_pool->pipe_count; ++i) {
106 struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i];
107
108 if (pipe->top_pipe || pipe->prev_odm_pipe)
109 continue;
110 if (pipe->stream && (pipe->stream->dpms_off || pipe->plane_state == NULL ||
111 dc_is_virtual_signal(pipe->stream->signal))) {
112
113 /* This w/a should not trigger when we have a dig active */
114 if (should_disable_otg(pipe)) {
115 if (disable) {
116 pipe->stream_res.tg->funcs->immediate_disable_crtc(pipe->stream_res.tg);
117 reset_sync_context_for_pipe(dc, context, i);
118 } else
119 pipe->stream_res.tg->funcs->enable_crtc(pipe->stream_res.tg);
120 }
121 }
122 }
123 }
124
dcn315_update_clocks(struct clk_mgr * clk_mgr_base,struct dc_state * context,bool safe_to_lower)125 static void dcn315_update_clocks(struct clk_mgr *clk_mgr_base,
126 struct dc_state *context,
127 bool safe_to_lower)
128 {
129 union dmub_rb_cmd cmd;
130 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
131 struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk;
132 struct dc *dc = clk_mgr_base->ctx->dc;
133 int display_count;
134 bool update_dppclk = false;
135 bool update_dispclk = false;
136 bool dpp_clock_lowered = false;
137
138 if (dc->work_arounds.skip_clock_update)
139 return;
140
141 clk_mgr_base->clks.zstate_support = new_clocks->zstate_support;
142 /*
143 * if it is safe to lower, but we are already in the lower state, we don't have to do anything
144 * also if safe to lower is false, we just go in the higher state
145 */
146 clk_mgr_base->clks.zstate_support = new_clocks->zstate_support;
147 if (safe_to_lower) {
148 if (clk_mgr_base->clks.dtbclk_en && !new_clocks->dtbclk_en) {
149 dcn315_smu_set_dtbclk(clk_mgr, false);
150 clk_mgr_base->clks.dtbclk_en = new_clocks->dtbclk_en;
151 }
152 /* check that we're not already in lower */
153 if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_LOW_POWER) {
154 display_count = dcn315_get_active_display_cnt_wa(dc, context);
155 /* if we can go lower, go lower */
156 if (display_count == 0) {
157 union display_idle_optimization_u idle_info = { 0 };
158 idle_info.idle_info.df_request_disabled = 1;
159 idle_info.idle_info.phy_ref_clk_off = 1;
160 idle_info.idle_info.s0i2_rdy = 1;
161 dcn315_smu_set_display_idle_optimization(clk_mgr, idle_info.data);
162 /* update power state */
163 clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_LOW_POWER;
164 }
165 }
166 } else {
167 if (!clk_mgr_base->clks.dtbclk_en && new_clocks->dtbclk_en) {
168 dcn315_smu_set_dtbclk(clk_mgr, true);
169 clk_mgr_base->clks.dtbclk_en = new_clocks->dtbclk_en;
170 }
171 /* check that we're not already in D0 */
172 if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_MISSION_MODE) {
173 union display_idle_optimization_u idle_info = { 0 };
174 dcn315_smu_set_display_idle_optimization(clk_mgr, idle_info.data);
175 /* update power state */
176 clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_MISSION_MODE;
177 }
178 }
179
180 /* Lock pstate by requesting unsupported dcfclk if change is unsupported */
181 if (!new_clocks->p_state_change_support)
182 new_clocks->dcfclk_khz = UNSUPPORTED_DCFCLK;
183 if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz)) {
184 clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz;
185 dcn315_smu_set_hard_min_dcfclk(clk_mgr, clk_mgr_base->clks.dcfclk_khz);
186 }
187
188 if (should_set_clock(safe_to_lower,
189 new_clocks->dcfclk_deep_sleep_khz, clk_mgr_base->clks.dcfclk_deep_sleep_khz)) {
190 clk_mgr_base->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz;
191 dcn315_smu_set_min_deep_sleep_dcfclk(clk_mgr, clk_mgr_base->clks.dcfclk_deep_sleep_khz);
192 }
193
194 // workaround: Limit dppclk to 100Mhz to avoid lower eDP panel switch to plus 4K monitor underflow.
195 if (new_clocks->dppclk_khz < MIN_DPP_DISP_CLK)
196 new_clocks->dppclk_khz = MIN_DPP_DISP_CLK;
197 if (new_clocks->dispclk_khz < MIN_DPP_DISP_CLK)
198 new_clocks->dispclk_khz = MIN_DPP_DISP_CLK;
199
200 if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr->base.clks.dppclk_khz)) {
201 if (clk_mgr->base.clks.dppclk_khz > new_clocks->dppclk_khz)
202 dpp_clock_lowered = true;
203 clk_mgr_base->clks.dppclk_khz = new_clocks->dppclk_khz;
204 update_dppclk = true;
205 }
206
207 if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz)) {
208 /* No need to apply the w/a if we haven't taken over from bios yet */
209 if (clk_mgr_base->clks.dispclk_khz)
210 dcn315_disable_otg_wa(clk_mgr_base, context, true);
211
212 clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz;
213 dcn315_smu_set_dispclk(clk_mgr, clk_mgr_base->clks.dispclk_khz);
214 if (clk_mgr_base->clks.dispclk_khz)
215 dcn315_disable_otg_wa(clk_mgr_base, context, false);
216
217 update_dispclk = true;
218 }
219
220 if (dpp_clock_lowered) {
221 // increase per DPP DTO before lowering global dppclk
222 dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);
223 dcn315_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz);
224 } else {
225 // increase global DPPCLK before lowering per DPP DTO
226 if (update_dppclk || update_dispclk)
227 dcn315_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz);
228 // always update dtos unless clock is lowered and not safe to lower
229 if (new_clocks->dppclk_khz >= dc->current_state->bw_ctx.bw.dcn.clk.dppclk_khz)
230 dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);
231 }
232
233 // notify DMCUB of latest clocks
234 memset(&cmd, 0, sizeof(cmd));
235 cmd.notify_clocks.header.type = DMUB_CMD__CLK_MGR;
236 cmd.notify_clocks.header.sub_type = DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS;
237 cmd.notify_clocks.clocks.dcfclk_khz = clk_mgr_base->clks.dcfclk_khz;
238 cmd.notify_clocks.clocks.dcfclk_deep_sleep_khz =
239 clk_mgr_base->clks.dcfclk_deep_sleep_khz;
240 cmd.notify_clocks.clocks.dispclk_khz = clk_mgr_base->clks.dispclk_khz;
241 cmd.notify_clocks.clocks.dppclk_khz = clk_mgr_base->clks.dppclk_khz;
242
243 dm_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT);
244 }
245
dcn315_dump_clk_registers(struct clk_state_registers_and_bypass * regs_and_bypass,struct clk_mgr * clk_mgr_base,struct clk_log_info * log_info)246 static void dcn315_dump_clk_registers(struct clk_state_registers_and_bypass *regs_and_bypass,
247 struct clk_mgr *clk_mgr_base, struct clk_log_info *log_info)
248 {
249 return;
250 }
251
252 static struct clk_bw_params dcn315_bw_params = {
253 .vram_type = Ddr4MemType,
254 .num_channels = 2,
255 .clk_table = {
256 .entries = {
257 {
258 .voltage = 0,
259 .dispclk_mhz = 640,
260 .dppclk_mhz = 640,
261 .phyclk_mhz = 810,
262 .phyclk_d18_mhz = 667,
263 .dtbclk_mhz = 600,
264 },
265 {
266 .voltage = 1,
267 .dispclk_mhz = 739,
268 .dppclk_mhz = 739,
269 .phyclk_mhz = 810,
270 .phyclk_d18_mhz = 667,
271 .dtbclk_mhz = 600,
272 },
273 {
274 .voltage = 2,
275 .dispclk_mhz = 960,
276 .dppclk_mhz = 960,
277 .phyclk_mhz = 810,
278 .phyclk_d18_mhz = 667,
279 .dtbclk_mhz = 600,
280 },
281 {
282 .voltage = 3,
283 .dispclk_mhz = 1200,
284 .dppclk_mhz = 1200,
285 .phyclk_mhz = 810,
286 .phyclk_d18_mhz = 667,
287 .dtbclk_mhz = 600,
288 },
289 {
290 .voltage = 4,
291 .dispclk_mhz = 1372,
292 .dppclk_mhz = 1372,
293 .phyclk_mhz = 810,
294 .phyclk_d18_mhz = 667,
295 .dtbclk_mhz = 600,
296 },
297 },
298 .num_entries = 5,
299 },
300
301 };
302
303 static struct wm_table ddr5_wm_table = {
304 .entries = {
305 {
306 .wm_inst = WM_A,
307 .wm_type = WM_TYPE_PSTATE_CHG,
308 .pstate_latency_us = 129.0,
309 .sr_exit_time_us = 11.5,
310 .sr_enter_plus_exit_time_us = 14.5,
311 .valid = true,
312 },
313 {
314 .wm_inst = WM_B,
315 .wm_type = WM_TYPE_PSTATE_CHG,
316 .pstate_latency_us = 129.0,
317 .sr_exit_time_us = 11.5,
318 .sr_enter_plus_exit_time_us = 14.5,
319 .valid = true,
320 },
321 {
322 .wm_inst = WM_C,
323 .wm_type = WM_TYPE_PSTATE_CHG,
324 .pstate_latency_us = 129.0,
325 .sr_exit_time_us = 11.5,
326 .sr_enter_plus_exit_time_us = 14.5,
327 .valid = true,
328 },
329 {
330 .wm_inst = WM_D,
331 .wm_type = WM_TYPE_PSTATE_CHG,
332 .pstate_latency_us = 129.0,
333 .sr_exit_time_us = 11.5,
334 .sr_enter_plus_exit_time_us = 14.5,
335 .valid = true,
336 },
337 }
338 };
339
340 static struct wm_table lpddr5_wm_table = {
341 .entries = {
342 {
343 .wm_inst = WM_A,
344 .wm_type = WM_TYPE_PSTATE_CHG,
345 .pstate_latency_us = 129.0,
346 .sr_exit_time_us = 11.5,
347 .sr_enter_plus_exit_time_us = 14.5,
348 .valid = true,
349 },
350 {
351 .wm_inst = WM_B,
352 .wm_type = WM_TYPE_PSTATE_CHG,
353 .pstate_latency_us = 129.0,
354 .sr_exit_time_us = 11.5,
355 .sr_enter_plus_exit_time_us = 14.5,
356 .valid = true,
357 },
358 {
359 .wm_inst = WM_C,
360 .wm_type = WM_TYPE_PSTATE_CHG,
361 .pstate_latency_us = 129.0,
362 .sr_exit_time_us = 11.5,
363 .sr_enter_plus_exit_time_us = 14.5,
364 .valid = true,
365 },
366 {
367 .wm_inst = WM_D,
368 .wm_type = WM_TYPE_PSTATE_CHG,
369 .pstate_latency_us = 129.0,
370 .sr_exit_time_us = 11.5,
371 .sr_enter_plus_exit_time_us = 14.5,
372 .valid = true,
373 },
374 }
375 };
376
377 /* Temporary Place holder until we can get them from fuse */
378 static DpmClocks_315_t dummy_clocks = { 0 };
379 static struct dcn315_watermarks dummy_wms = { 0 };
380
dcn315_build_watermark_ranges(struct clk_bw_params * bw_params,struct dcn315_watermarks * table)381 static void dcn315_build_watermark_ranges(struct clk_bw_params *bw_params, struct dcn315_watermarks *table)
382 {
383 int i, num_valid_sets;
384
385 num_valid_sets = 0;
386
387 for (i = 0; i < WM_SET_COUNT; i++) {
388 /* skip empty entries, the smu array has no holes*/
389 if (!bw_params->wm_table.entries[i].valid)
390 continue;
391
392 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting = bw_params->wm_table.entries[i].wm_inst;
393 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType = bw_params->wm_table.entries[i].wm_type;
394 /* We will not select WM based on fclk, so leave it as unconstrained */
395 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0;
396 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF;
397
398 if (table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType == WM_TYPE_PSTATE_CHG) {
399 if (i == 0)
400 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk = 0;
401 else {
402 /* add 1 to make it non-overlapping with next lvl */
403 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk =
404 bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1;
405 }
406 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxMclk =
407 bw_params->clk_table.entries[i].dcfclk_mhz;
408
409 } else {
410 /* unconstrained for memory retraining */
411 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0;
412 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF;
413
414 /* Modify previous watermark range to cover up to max */
415 table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxClock = 0xFFFF;
416 }
417 num_valid_sets++;
418 }
419
420 ASSERT(num_valid_sets != 0); /* Must have at least one set of valid watermarks */
421
422 /* modify the min and max to make sure we cover the whole range*/
423 table->WatermarkRow[WM_DCFCLK][0].MinMclk = 0;
424 table->WatermarkRow[WM_DCFCLK][0].MinClock = 0;
425 table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxMclk = 0xFFFF;
426 table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxClock = 0xFFFF;
427
428 /* This is for writeback only, does not matter currently as no writeback support*/
429 table->WatermarkRow[WM_SOCCLK][0].WmSetting = WM_A;
430 table->WatermarkRow[WM_SOCCLK][0].MinClock = 0;
431 table->WatermarkRow[WM_SOCCLK][0].MaxClock = 0xFFFF;
432 table->WatermarkRow[WM_SOCCLK][0].MinMclk = 0;
433 table->WatermarkRow[WM_SOCCLK][0].MaxMclk = 0xFFFF;
434 }
435
dcn315_notify_wm_ranges(struct clk_mgr * clk_mgr_base)436 static void dcn315_notify_wm_ranges(struct clk_mgr *clk_mgr_base)
437 {
438 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
439 struct clk_mgr_dcn315 *clk_mgr_dcn315 = TO_CLK_MGR_DCN315(clk_mgr);
440 struct dcn315_watermarks *table = clk_mgr_dcn315->smu_wm_set.wm_set;
441
442 if (!clk_mgr->smu_ver)
443 return;
444
445 if (!table || clk_mgr_dcn315->smu_wm_set.mc_address.quad_part == 0)
446 return;
447
448 memset(table, 0, sizeof(*table));
449
450 dcn315_build_watermark_ranges(clk_mgr_base->bw_params, table);
451
452 dcn315_smu_set_dram_addr_high(clk_mgr,
453 clk_mgr_dcn315->smu_wm_set.mc_address.high_part);
454 dcn315_smu_set_dram_addr_low(clk_mgr,
455 clk_mgr_dcn315->smu_wm_set.mc_address.low_part);
456 dcn315_smu_transfer_wm_table_dram_2_smu(clk_mgr);
457 }
458
dcn315_get_dpm_table_from_smu(struct clk_mgr_internal * clk_mgr,struct dcn315_smu_dpm_clks * smu_dpm_clks)459 static void dcn315_get_dpm_table_from_smu(struct clk_mgr_internal *clk_mgr,
460 struct dcn315_smu_dpm_clks *smu_dpm_clks)
461 {
462 DpmClocks_315_t *table = smu_dpm_clks->dpm_clks;
463
464 if (!clk_mgr->smu_ver)
465 return;
466
467 if (!table || smu_dpm_clks->mc_address.quad_part == 0)
468 return;
469
470 memset(table, 0, sizeof(*table));
471
472 dcn315_smu_set_dram_addr_high(clk_mgr,
473 smu_dpm_clks->mc_address.high_part);
474 dcn315_smu_set_dram_addr_low(clk_mgr,
475 smu_dpm_clks->mc_address.low_part);
476 dcn315_smu_transfer_dpm_table_smu_2_dram(clk_mgr);
477 }
478
dcn315_clk_mgr_helper_populate_bw_params(struct clk_mgr_internal * clk_mgr,struct integrated_info * bios_info,const DpmClocks_315_t * clock_table)479 static void dcn315_clk_mgr_helper_populate_bw_params(
480 struct clk_mgr_internal *clk_mgr,
481 struct integrated_info *bios_info,
482 const DpmClocks_315_t *clock_table)
483 {
484 int i;
485 struct clk_bw_params *bw_params = clk_mgr->base.bw_params;
486 uint32_t max_pstate = clock_table->NumDfPstatesEnabled - 1;
487 struct clk_limit_table_entry def_max = bw_params->clk_table.entries[bw_params->clk_table.num_entries - 1];
488
489 /* For 315 we want to base clock table on dcfclk, need at least one entry regardless of pmfw table */
490 for (i = 0; i < clock_table->NumDcfClkLevelsEnabled; i++) {
491 int j;
492
493 /* DF table is sorted with clocks decreasing */
494 for (j = clock_table->NumDfPstatesEnabled - 2; j >= 0; j--) {
495 if (clock_table->DfPstateTable[j].Voltage <= clock_table->SocVoltage[i])
496 max_pstate = j;
497 }
498 /* Max DCFCLK should match up with max pstate */
499 if (i == clock_table->NumDcfClkLevelsEnabled - 1)
500 max_pstate = 0;
501
502 /* First search defaults for the clocks we don't read using closest lower or equal default dcfclk */
503 for (j = bw_params->clk_table.num_entries - 1; j > 0; j--)
504 if (bw_params->clk_table.entries[j].dcfclk_mhz <= clock_table->DcfClocks[i])
505 break;
506 bw_params->clk_table.entries[i].phyclk_mhz = bw_params->clk_table.entries[j].phyclk_mhz;
507 bw_params->clk_table.entries[i].phyclk_d18_mhz = bw_params->clk_table.entries[j].phyclk_d18_mhz;
508 bw_params->clk_table.entries[i].dtbclk_mhz = bw_params->clk_table.entries[j].dtbclk_mhz;
509
510 /* Now update clocks we do read */
511 bw_params->clk_table.entries[i].fclk_mhz = clock_table->DfPstateTable[max_pstate].FClk;
512 bw_params->clk_table.entries[i].memclk_mhz = clock_table->DfPstateTable[max_pstate].MemClk;
513 bw_params->clk_table.entries[i].voltage = clock_table->SocVoltage[i];
514 bw_params->clk_table.entries[i].dcfclk_mhz = clock_table->DcfClocks[i];
515 bw_params->clk_table.entries[i].socclk_mhz = clock_table->SocClocks[i];
516 bw_params->clk_table.entries[i].dispclk_mhz = clock_table->DispClocks[i];
517 bw_params->clk_table.entries[i].dppclk_mhz = clock_table->DppClocks[i];
518 bw_params->clk_table.entries[i].wck_ratio = 1;
519 }
520
521 /* Make sure to include at least one entry */
522 if (i == 0) {
523 bw_params->clk_table.entries[i].fclk_mhz = clock_table->DfPstateTable[0].FClk;
524 bw_params->clk_table.entries[i].memclk_mhz = clock_table->DfPstateTable[0].MemClk;
525 bw_params->clk_table.entries[i].voltage = clock_table->DfPstateTable[0].Voltage;
526 bw_params->clk_table.entries[i].dcfclk_mhz = clock_table->DcfClocks[0];
527 bw_params->clk_table.entries[i].wck_ratio = 1;
528 i++;
529 } else if (clock_table->NumDcfClkLevelsEnabled != clock_table->NumSocClkLevelsEnabled) {
530 bw_params->clk_table.entries[i-1].voltage = clock_table->SocVoltage[clock_table->NumSocClkLevelsEnabled - 1];
531 bw_params->clk_table.entries[i-1].socclk_mhz = clock_table->SocClocks[clock_table->NumSocClkLevelsEnabled - 1];
532 bw_params->clk_table.entries[i-1].dispclk_mhz = clock_table->DispClocks[clock_table->NumDispClkLevelsEnabled - 1];
533 bw_params->clk_table.entries[i-1].dppclk_mhz = clock_table->DppClocks[clock_table->NumDispClkLevelsEnabled - 1];
534 }
535 bw_params->clk_table.num_entries = i;
536
537 /* Set any 0 clocks to max default setting. Not an issue for
538 * power since we aren't doing switching in such case anyway
539 */
540 for (i = 0; i < bw_params->clk_table.num_entries; i++) {
541 if (!bw_params->clk_table.entries[i].fclk_mhz) {
542 bw_params->clk_table.entries[i].fclk_mhz = def_max.fclk_mhz;
543 bw_params->clk_table.entries[i].memclk_mhz = def_max.memclk_mhz;
544 bw_params->clk_table.entries[i].voltage = def_max.voltage;
545 }
546 if (!bw_params->clk_table.entries[i].dcfclk_mhz)
547 bw_params->clk_table.entries[i].dcfclk_mhz = def_max.dcfclk_mhz;
548 if (!bw_params->clk_table.entries[i].socclk_mhz)
549 bw_params->clk_table.entries[i].socclk_mhz = def_max.socclk_mhz;
550 if (!bw_params->clk_table.entries[i].dispclk_mhz)
551 bw_params->clk_table.entries[i].dispclk_mhz = def_max.dispclk_mhz;
552 if (!bw_params->clk_table.entries[i].dppclk_mhz)
553 bw_params->clk_table.entries[i].dppclk_mhz = def_max.dppclk_mhz;
554 if (!bw_params->clk_table.entries[i].phyclk_mhz)
555 bw_params->clk_table.entries[i].phyclk_mhz = def_max.phyclk_mhz;
556 if (!bw_params->clk_table.entries[i].phyclk_d18_mhz)
557 bw_params->clk_table.entries[i].phyclk_d18_mhz = def_max.phyclk_d18_mhz;
558 if (!bw_params->clk_table.entries[i].dtbclk_mhz)
559 bw_params->clk_table.entries[i].dtbclk_mhz = def_max.dtbclk_mhz;
560 }
561
562 /* Make sure all highest default clocks are included*/
563 ASSERT(bw_params->clk_table.entries[i-1].phyclk_mhz == def_max.phyclk_mhz);
564 ASSERT(bw_params->clk_table.entries[i-1].phyclk_d18_mhz == def_max.phyclk_d18_mhz);
565 ASSERT(bw_params->clk_table.entries[i-1].dtbclk_mhz == def_max.dtbclk_mhz);
566 ASSERT(bw_params->clk_table.entries[i-1].dcfclk_mhz);
567 bw_params->vram_type = bios_info->memory_type;
568 bw_params->num_channels = bios_info->ma_channel_number;
569 bw_params->dram_channel_width_bytes = bios_info->memory_type == 0x22 ? 8 : 4;
570
571 for (i = 0; i < WM_SET_COUNT; i++) {
572 bw_params->wm_table.entries[i].wm_inst = i;
573
574 if (i >= bw_params->clk_table.num_entries) {
575 bw_params->wm_table.entries[i].valid = false;
576 continue;
577 }
578
579 bw_params->wm_table.entries[i].wm_type = WM_TYPE_PSTATE_CHG;
580 bw_params->wm_table.entries[i].valid = true;
581 }
582 }
583
dcn315_enable_pme_wa(struct clk_mgr * clk_mgr_base)584 static void dcn315_enable_pme_wa(struct clk_mgr *clk_mgr_base)
585 {
586 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
587
588 dcn315_smu_enable_pme_wa(clk_mgr);
589 }
590
591 static struct clk_mgr_funcs dcn315_funcs = {
592 .get_dp_ref_clk_frequency = dce12_get_dp_ref_freq_khz,
593 .get_dtb_ref_clk_frequency = dcn31_get_dtb_ref_freq_khz,
594 .update_clocks = dcn315_update_clocks,
595 .init_clocks = dcn31_init_clocks,
596 .enable_pme_wa = dcn315_enable_pme_wa,
597 .are_clock_states_equal = dcn31_are_clock_states_equal,
598 .notify_wm_ranges = dcn315_notify_wm_ranges
599 };
600 extern struct clk_mgr_funcs dcn3_fpga_funcs;
601
dcn315_clk_mgr_construct(struct dc_context * ctx,struct clk_mgr_dcn315 * clk_mgr,struct pp_smu_funcs * pp_smu,struct dccg * dccg)602 void dcn315_clk_mgr_construct(
603 struct dc_context *ctx,
604 struct clk_mgr_dcn315 *clk_mgr,
605 struct pp_smu_funcs *pp_smu,
606 struct dccg *dccg)
607 {
608 struct dcn315_smu_dpm_clks smu_dpm_clks = { 0 };
609 struct clk_log_info log_info = {0};
610
611 clk_mgr->base.base.ctx = ctx;
612 clk_mgr->base.base.funcs = &dcn315_funcs;
613
614 clk_mgr->base.pp_smu = pp_smu;
615
616 clk_mgr->base.dccg = dccg;
617 clk_mgr->base.dfs_bypass_disp_clk = 0;
618
619 clk_mgr->base.dprefclk_ss_percentage = 0;
620 clk_mgr->base.dprefclk_ss_divider = 1000;
621 clk_mgr->base.ss_on_dprefclk = false;
622 clk_mgr->base.dfs_ref_freq_khz = 48000;
623
624 clk_mgr->smu_wm_set.wm_set = (struct dcn315_watermarks *)dm_helpers_allocate_gpu_mem(
625 clk_mgr->base.base.ctx,
626 DC_MEM_ALLOC_TYPE_FRAME_BUFFER,
627 sizeof(struct dcn315_watermarks),
628 &clk_mgr->smu_wm_set.mc_address.quad_part);
629
630 if (!clk_mgr->smu_wm_set.wm_set) {
631 clk_mgr->smu_wm_set.wm_set = &dummy_wms;
632 clk_mgr->smu_wm_set.mc_address.quad_part = 0;
633 }
634 ASSERT(clk_mgr->smu_wm_set.wm_set);
635
636 smu_dpm_clks.dpm_clks = (DpmClocks_315_t *)dm_helpers_allocate_gpu_mem(
637 clk_mgr->base.base.ctx,
638 DC_MEM_ALLOC_TYPE_FRAME_BUFFER,
639 sizeof(DpmClocks_315_t),
640 &smu_dpm_clks.mc_address.quad_part);
641
642 if (smu_dpm_clks.dpm_clks == NULL) {
643 smu_dpm_clks.dpm_clks = &dummy_clocks;
644 smu_dpm_clks.mc_address.quad_part = 0;
645 }
646
647 ASSERT(smu_dpm_clks.dpm_clks);
648
649 clk_mgr->base.smu_ver = dcn315_smu_get_smu_version(&clk_mgr->base);
650
651 if (clk_mgr->base.smu_ver > 0)
652 clk_mgr->base.smu_present = true;
653
654 if (ctx->dc_bios->integrated_info->memory_type == LpDdr5MemType) {
655 dcn315_bw_params.wm_table = lpddr5_wm_table;
656 } else {
657 dcn315_bw_params.wm_table = ddr5_wm_table;
658 }
659 /* Saved clocks configured at boot for debug purposes */
660 dcn315_dump_clk_registers(&clk_mgr->base.base.boot_snapshot,
661 &clk_mgr->base.base, &log_info);
662
663 clk_mgr->base.base.dprefclk_khz = 600000;
664 clk_mgr->base.base.dprefclk_khz = dcn315_smu_get_dpref_clk(&clk_mgr->base);
665 clk_mgr->base.base.clks.ref_dtbclk_khz = clk_mgr->base.base.dprefclk_khz;
666 dce_clock_read_ss_info(&clk_mgr->base);
667 clk_mgr->base.base.clks.ref_dtbclk_khz = dce_adjust_dp_ref_freq_for_ss(&clk_mgr->base, clk_mgr->base.base.dprefclk_khz);
668
669 clk_mgr->base.base.bw_params = &dcn315_bw_params;
670
671 if (clk_mgr->base.base.ctx->dc->debug.pstate_enabled) {
672 int i;
673
674 dcn315_get_dpm_table_from_smu(&clk_mgr->base, &smu_dpm_clks);
675 DC_LOG_SMU("NumDcfClkLevelsEnabled: %d\n"
676 "NumDispClkLevelsEnabled: %d\n"
677 "NumSocClkLevelsEnabled: %d\n"
678 "VcnClkLevelsEnabled: %d\n"
679 "NumDfPst atesEnabled: %d\n"
680 "MinGfxClk: %d\n"
681 "MaxGfxClk: %d\n",
682 smu_dpm_clks.dpm_clks->NumDcfClkLevelsEnabled,
683 smu_dpm_clks.dpm_clks->NumDispClkLevelsEnabled,
684 smu_dpm_clks.dpm_clks->NumSocClkLevelsEnabled,
685 smu_dpm_clks.dpm_clks->VcnClkLevelsEnabled,
686 smu_dpm_clks.dpm_clks->NumDfPstatesEnabled,
687 smu_dpm_clks.dpm_clks->MinGfxClk,
688 smu_dpm_clks.dpm_clks->MaxGfxClk);
689 for (i = 0; i < smu_dpm_clks.dpm_clks->NumDcfClkLevelsEnabled; i++) {
690 DC_LOG_SMU("smu_dpm_clks.dpm_clks->DcfClocks[%d] = %d\n",
691 i,
692 smu_dpm_clks.dpm_clks->DcfClocks[i]);
693 }
694 for (i = 0; i < smu_dpm_clks.dpm_clks->NumDispClkLevelsEnabled; i++) {
695 DC_LOG_SMU("smu_dpm_clks.dpm_clks->DispClocks[%d] = %d\n",
696 i, smu_dpm_clks.dpm_clks->DispClocks[i]);
697 }
698 for (i = 0; i < smu_dpm_clks.dpm_clks->NumSocClkLevelsEnabled; i++) {
699 DC_LOG_SMU("smu_dpm_clks.dpm_clks->SocClocks[%d] = %d\n",
700 i, smu_dpm_clks.dpm_clks->SocClocks[i]);
701 }
702 for (i = 0; i < NUM_SOC_VOLTAGE_LEVELS; i++)
703 DC_LOG_SMU("smu_dpm_clks.dpm_clks->SocVoltage[%d] = %d\n",
704 i, smu_dpm_clks.dpm_clks->SocVoltage[i]);
705
706 for (i = 0; i < NUM_DF_PSTATE_LEVELS; i++) {
707 DC_LOG_SMU("smu_dpm_clks.dpm_clks.DfPstateTable[%d].FClk = %d\n"
708 "smu_dpm_clks.dpm_clks->DfPstateTable[%d].MemClk= %d\n"
709 "smu_dpm_clks.dpm_clks->DfPstateTable[%d].Voltage = %d\n",
710 i, smu_dpm_clks.dpm_clks->DfPstateTable[i].FClk,
711 i, smu_dpm_clks.dpm_clks->DfPstateTable[i].MemClk,
712 i, smu_dpm_clks.dpm_clks->DfPstateTable[i].Voltage);
713 }
714
715 if (ctx->dc_bios && ctx->dc_bios->integrated_info) {
716 dcn315_clk_mgr_helper_populate_bw_params(
717 &clk_mgr->base,
718 ctx->dc_bios->integrated_info,
719 smu_dpm_clks.dpm_clks);
720 }
721 }
722
723 if (smu_dpm_clks.dpm_clks && smu_dpm_clks.mc_address.quad_part != 0)
724 dm_helpers_free_gpu_mem(clk_mgr->base.base.ctx, DC_MEM_ALLOC_TYPE_FRAME_BUFFER,
725 smu_dpm_clks.dpm_clks);
726 }
727
dcn315_clk_mgr_destroy(struct clk_mgr_internal * clk_mgr_int)728 void dcn315_clk_mgr_destroy(struct clk_mgr_internal *clk_mgr_int)
729 {
730 struct clk_mgr_dcn315 *clk_mgr = TO_CLK_MGR_DCN315(clk_mgr_int);
731
732 if (clk_mgr->smu_wm_set.wm_set && clk_mgr->smu_wm_set.mc_address.quad_part != 0)
733 dm_helpers_free_gpu_mem(clk_mgr_int->base.ctx, DC_MEM_ALLOC_TYPE_FRAME_BUFFER,
734 clk_mgr->smu_wm_set.wm_set);
735 }
736