1 // SPDX-License-Identifier: MIT
2 /*
3 * Copyright © 2022 Intel Corporation
4 *
5 * Read out the current hardware modeset state, and sanitize it to the current
6 * state.
7 */
8
9 #include <linux/compiler.h> /* for __must_check */
10 #include <drm/drm_atomic_uapi.h>
11 #include <drm/drm_atomic_state_helper.h>
12
13 #include "i915_drv.h"
14 #include "i915_reg.h"
15 #include "i9xx_wm.h"
16 #include "intel_atomic.h"
17 #include "intel_bw.h"
18 #include "intel_color.h"
19 #include "intel_crtc.h"
20 #include "intel_crtc_state_dump.h"
21 #include "intel_ddi.h"
22 #include "intel_de.h"
23 #include "intel_display.h"
24 #include "intel_display_power.h"
25 #include "intel_display_types.h"
26 #include "intel_dmc.h"
27 #include "intel_fifo_underrun.h"
28 #include "intel_modeset_setup.h"
29 #include "intel_pch_display.h"
30 #include "intel_pmdemand.h"
31 #include "intel_tc.h"
32 #include "intel_vblank.h"
33 #include "intel_wm.h"
34 #include "skl_watermark.h"
35
intel_crtc_disable_noatomic_begin(struct intel_crtc * crtc,struct drm_modeset_acquire_ctx * ctx)36 static void intel_crtc_disable_noatomic_begin(struct intel_crtc *crtc,
37 struct drm_modeset_acquire_ctx *ctx)
38 {
39 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
40 struct intel_crtc_state *crtc_state =
41 to_intel_crtc_state(crtc->base.state);
42 struct intel_plane *plane;
43 struct drm_atomic_state *state;
44 struct intel_crtc *temp_crtc;
45 enum pipe pipe = crtc->pipe;
46
47 if (!crtc_state->hw.active)
48 return;
49
50 for_each_intel_plane_on_crtc(&i915->drm, crtc, plane) {
51 const struct intel_plane_state *plane_state =
52 to_intel_plane_state(plane->base.state);
53
54 if (plane_state->uapi.visible)
55 intel_plane_disable_noatomic(crtc, plane);
56 }
57
58 state = drm_atomic_state_alloc(&i915->drm);
59 if (!state) {
60 drm_dbg_kms(&i915->drm,
61 "failed to disable [CRTC:%d:%s], out of memory",
62 crtc->base.base.id, crtc->base.name);
63 return;
64 }
65
66 state->acquire_ctx = ctx;
67 to_intel_atomic_state(state)->internal = true;
68
69 /* Everything's already locked, -EDEADLK can't happen. */
70 for_each_intel_crtc_in_pipe_mask(&i915->drm, temp_crtc,
71 BIT(pipe) |
72 intel_crtc_bigjoiner_slave_pipes(crtc_state)) {
73 struct intel_crtc_state *temp_crtc_state =
74 intel_atomic_get_crtc_state(state, temp_crtc);
75 int ret;
76
77 ret = drm_atomic_add_affected_connectors(state, &temp_crtc->base);
78
79 drm_WARN_ON(&i915->drm, IS_ERR(temp_crtc_state) || ret);
80 }
81
82 i915->display.funcs.display->crtc_disable(to_intel_atomic_state(state), crtc);
83
84 drm_atomic_state_put(state);
85
86 drm_dbg_kms(&i915->drm,
87 "[CRTC:%d:%s] hw state adjusted, was enabled, now disabled\n",
88 crtc->base.base.id, crtc->base.name);
89
90 crtc->active = false;
91 crtc->base.enabled = false;
92
93 if (crtc_state->shared_dpll)
94 intel_unreference_shared_dpll_crtc(crtc,
95 crtc_state->shared_dpll,
96 &crtc_state->shared_dpll->state);
97 }
98
set_encoder_for_connector(struct intel_connector * connector,struct intel_encoder * encoder)99 static void set_encoder_for_connector(struct intel_connector *connector,
100 struct intel_encoder *encoder)
101 {
102 struct drm_connector_state *conn_state = connector->base.state;
103
104 if (conn_state->crtc)
105 drm_connector_put(&connector->base);
106
107 if (encoder) {
108 conn_state->best_encoder = &encoder->base;
109 conn_state->crtc = encoder->base.crtc;
110 drm_connector_get(&connector->base);
111 } else {
112 conn_state->best_encoder = NULL;
113 conn_state->crtc = NULL;
114 }
115 }
116
reset_encoder_connector_state(struct intel_encoder * encoder)117 static void reset_encoder_connector_state(struct intel_encoder *encoder)
118 {
119 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
120 struct intel_pmdemand_state *pmdemand_state =
121 to_intel_pmdemand_state(i915->display.pmdemand.obj.state);
122 struct intel_connector *connector;
123 struct drm_connector_list_iter conn_iter;
124
125 drm_connector_list_iter_begin(&i915->drm, &conn_iter);
126 for_each_intel_connector_iter(connector, &conn_iter) {
127 if (connector->base.encoder != &encoder->base)
128 continue;
129
130 /* Clear the corresponding bit in pmdemand active phys mask */
131 intel_pmdemand_update_phys_mask(i915, encoder,
132 pmdemand_state, false);
133
134 set_encoder_for_connector(connector, NULL);
135
136 connector->base.dpms = DRM_MODE_DPMS_OFF;
137 connector->base.encoder = NULL;
138 }
139 drm_connector_list_iter_end(&conn_iter);
140 }
141
reset_crtc_encoder_state(struct intel_crtc * crtc)142 static void reset_crtc_encoder_state(struct intel_crtc *crtc)
143 {
144 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
145 struct intel_encoder *encoder;
146
147 for_each_encoder_on_crtc(&i915->drm, &crtc->base, encoder) {
148 reset_encoder_connector_state(encoder);
149 encoder->base.crtc = NULL;
150 }
151 }
152
intel_crtc_disable_noatomic_complete(struct intel_crtc * crtc)153 static void intel_crtc_disable_noatomic_complete(struct intel_crtc *crtc)
154 {
155 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
156 struct intel_bw_state *bw_state =
157 to_intel_bw_state(i915->display.bw.obj.state);
158 struct intel_cdclk_state *cdclk_state =
159 to_intel_cdclk_state(i915->display.cdclk.obj.state);
160 struct intel_dbuf_state *dbuf_state =
161 to_intel_dbuf_state(i915->display.dbuf.obj.state);
162 struct intel_pmdemand_state *pmdemand_state =
163 to_intel_pmdemand_state(i915->display.pmdemand.obj.state);
164 struct intel_crtc_state *crtc_state =
165 to_intel_crtc_state(crtc->base.state);
166 enum pipe pipe = crtc->pipe;
167
168 __drm_atomic_helper_crtc_destroy_state(&crtc_state->uapi);
169 intel_crtc_free_hw_state(crtc_state);
170 intel_crtc_state_reset(crtc_state, crtc);
171
172 reset_crtc_encoder_state(crtc);
173
174 intel_fbc_disable(crtc);
175 intel_update_watermarks(i915);
176
177 intel_display_power_put_all_in_set(i915, &crtc->enabled_power_domains);
178
179 cdclk_state->min_cdclk[pipe] = 0;
180 cdclk_state->min_voltage_level[pipe] = 0;
181 cdclk_state->active_pipes &= ~BIT(pipe);
182
183 dbuf_state->active_pipes &= ~BIT(pipe);
184
185 bw_state->data_rate[pipe] = 0;
186 bw_state->num_active_planes[pipe] = 0;
187
188 intel_pmdemand_update_port_clock(i915, pmdemand_state, pipe, 0);
189 }
190
191 /*
192 * Return all the pipes using a transcoder in @transcoder_mask.
193 * For bigjoiner configs return only the bigjoiner master.
194 */
get_transcoder_pipes(struct drm_i915_private * i915,u8 transcoder_mask)195 static u8 get_transcoder_pipes(struct drm_i915_private *i915,
196 u8 transcoder_mask)
197 {
198 struct intel_crtc *temp_crtc;
199 u8 pipes = 0;
200
201 for_each_intel_crtc(&i915->drm, temp_crtc) {
202 struct intel_crtc_state *temp_crtc_state =
203 to_intel_crtc_state(temp_crtc->base.state);
204
205 if (temp_crtc_state->cpu_transcoder == INVALID_TRANSCODER)
206 continue;
207
208 if (intel_crtc_is_bigjoiner_slave(temp_crtc_state))
209 continue;
210
211 if (transcoder_mask & BIT(temp_crtc_state->cpu_transcoder))
212 pipes |= BIT(temp_crtc->pipe);
213 }
214
215 return pipes;
216 }
217
218 /*
219 * Return the port sync master and slave pipes linked to @crtc.
220 * For bigjoiner configs return only the bigjoiner master pipes.
221 */
get_portsync_pipes(struct intel_crtc * crtc,u8 * master_pipe_mask,u8 * slave_pipes_mask)222 static void get_portsync_pipes(struct intel_crtc *crtc,
223 u8 *master_pipe_mask, u8 *slave_pipes_mask)
224 {
225 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
226 struct intel_crtc_state *crtc_state =
227 to_intel_crtc_state(crtc->base.state);
228 struct intel_crtc *master_crtc;
229 struct intel_crtc_state *master_crtc_state;
230 enum transcoder master_transcoder;
231
232 if (!is_trans_port_sync_mode(crtc_state)) {
233 *master_pipe_mask = BIT(crtc->pipe);
234 *slave_pipes_mask = 0;
235
236 return;
237 }
238
239 if (is_trans_port_sync_master(crtc_state))
240 master_transcoder = crtc_state->cpu_transcoder;
241 else
242 master_transcoder = crtc_state->master_transcoder;
243
244 *master_pipe_mask = get_transcoder_pipes(i915, BIT(master_transcoder));
245 drm_WARN_ON(&i915->drm, !is_power_of_2(*master_pipe_mask));
246
247 master_crtc = intel_crtc_for_pipe(i915, ffs(*master_pipe_mask) - 1);
248 master_crtc_state = to_intel_crtc_state(master_crtc->base.state);
249 *slave_pipes_mask = get_transcoder_pipes(i915, master_crtc_state->sync_mode_slaves_mask);
250 }
251
get_bigjoiner_slave_pipes(struct drm_i915_private * i915,u8 master_pipes_mask)252 static u8 get_bigjoiner_slave_pipes(struct drm_i915_private *i915, u8 master_pipes_mask)
253 {
254 struct intel_crtc *master_crtc;
255 u8 pipes = 0;
256
257 for_each_intel_crtc_in_pipe_mask(&i915->drm, master_crtc, master_pipes_mask) {
258 struct intel_crtc_state *master_crtc_state =
259 to_intel_crtc_state(master_crtc->base.state);
260
261 pipes |= intel_crtc_bigjoiner_slave_pipes(master_crtc_state);
262 }
263
264 return pipes;
265 }
266
intel_crtc_disable_noatomic(struct intel_crtc * crtc,struct drm_modeset_acquire_ctx * ctx)267 static void intel_crtc_disable_noatomic(struct intel_crtc *crtc,
268 struct drm_modeset_acquire_ctx *ctx)
269 {
270 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
271 u8 portsync_master_mask;
272 u8 portsync_slaves_mask;
273 u8 bigjoiner_slaves_mask;
274 struct intel_crtc *temp_crtc;
275
276 /* TODO: Add support for MST */
277 get_portsync_pipes(crtc, &portsync_master_mask, &portsync_slaves_mask);
278 bigjoiner_slaves_mask = get_bigjoiner_slave_pipes(i915,
279 portsync_master_mask |
280 portsync_slaves_mask);
281
282 drm_WARN_ON(&i915->drm,
283 portsync_master_mask & portsync_slaves_mask ||
284 portsync_master_mask & bigjoiner_slaves_mask ||
285 portsync_slaves_mask & bigjoiner_slaves_mask);
286
287 for_each_intel_crtc_in_pipe_mask(&i915->drm, temp_crtc, bigjoiner_slaves_mask)
288 intel_crtc_disable_noatomic_begin(temp_crtc, ctx);
289
290 for_each_intel_crtc_in_pipe_mask(&i915->drm, temp_crtc, portsync_slaves_mask)
291 intel_crtc_disable_noatomic_begin(temp_crtc, ctx);
292
293 for_each_intel_crtc_in_pipe_mask(&i915->drm, temp_crtc, portsync_master_mask)
294 intel_crtc_disable_noatomic_begin(temp_crtc, ctx);
295
296 for_each_intel_crtc_in_pipe_mask(&i915->drm, temp_crtc,
297 bigjoiner_slaves_mask |
298 portsync_slaves_mask |
299 portsync_master_mask)
300 intel_crtc_disable_noatomic_complete(temp_crtc);
301 }
302
intel_modeset_update_connector_atomic_state(struct drm_i915_private * i915)303 static void intel_modeset_update_connector_atomic_state(struct drm_i915_private *i915)
304 {
305 struct intel_connector *connector;
306 struct drm_connector_list_iter conn_iter;
307
308 drm_connector_list_iter_begin(&i915->drm, &conn_iter);
309 for_each_intel_connector_iter(connector, &conn_iter) {
310 struct drm_connector_state *conn_state = connector->base.state;
311 struct intel_encoder *encoder =
312 to_intel_encoder(connector->base.encoder);
313
314 set_encoder_for_connector(connector, encoder);
315
316 if (encoder) {
317 struct intel_crtc *crtc =
318 to_intel_crtc(encoder->base.crtc);
319 const struct intel_crtc_state *crtc_state =
320 to_intel_crtc_state(crtc->base.state);
321
322 conn_state->max_bpc = (crtc_state->pipe_bpp ?: 24) / 3;
323 }
324 }
325 drm_connector_list_iter_end(&conn_iter);
326 }
327
intel_crtc_copy_hw_to_uapi_state(struct intel_crtc_state * crtc_state)328 static void intel_crtc_copy_hw_to_uapi_state(struct intel_crtc_state *crtc_state)
329 {
330 if (intel_crtc_is_bigjoiner_slave(crtc_state))
331 return;
332
333 crtc_state->uapi.enable = crtc_state->hw.enable;
334 crtc_state->uapi.active = crtc_state->hw.active;
335 drm_WARN_ON(crtc_state->uapi.crtc->dev,
336 drm_atomic_set_mode_for_crtc(&crtc_state->uapi, &crtc_state->hw.mode) < 0);
337
338 crtc_state->uapi.adjusted_mode = crtc_state->hw.adjusted_mode;
339 crtc_state->uapi.scaling_filter = crtc_state->hw.scaling_filter;
340
341 /* assume 1:1 mapping */
342 drm_property_replace_blob(&crtc_state->hw.degamma_lut,
343 crtc_state->pre_csc_lut);
344 drm_property_replace_blob(&crtc_state->hw.gamma_lut,
345 crtc_state->post_csc_lut);
346
347 drm_property_replace_blob(&crtc_state->uapi.degamma_lut,
348 crtc_state->hw.degamma_lut);
349 drm_property_replace_blob(&crtc_state->uapi.gamma_lut,
350 crtc_state->hw.gamma_lut);
351 drm_property_replace_blob(&crtc_state->uapi.ctm,
352 crtc_state->hw.ctm);
353 }
354
355 static void
intel_sanitize_plane_mapping(struct drm_i915_private * i915)356 intel_sanitize_plane_mapping(struct drm_i915_private *i915)
357 {
358 struct intel_crtc *crtc;
359
360 if (DISPLAY_VER(i915) >= 4)
361 return;
362
363 for_each_intel_crtc(&i915->drm, crtc) {
364 struct intel_plane *plane =
365 to_intel_plane(crtc->base.primary);
366 struct intel_crtc *plane_crtc;
367 enum pipe pipe;
368
369 if (!plane->get_hw_state(plane, &pipe))
370 continue;
371
372 if (pipe == crtc->pipe)
373 continue;
374
375 drm_dbg_kms(&i915->drm,
376 "[PLANE:%d:%s] attached to the wrong pipe, disabling plane\n",
377 plane->base.base.id, plane->base.name);
378
379 plane_crtc = intel_crtc_for_pipe(i915, pipe);
380 intel_plane_disable_noatomic(plane_crtc, plane);
381 }
382 }
383
intel_crtc_has_encoders(struct intel_crtc * crtc)384 static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
385 {
386 struct drm_device *dev = crtc->base.dev;
387 struct intel_encoder *encoder;
388
389 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
390 return true;
391
392 return false;
393 }
394
intel_crtc_needs_link_reset(struct intel_crtc * crtc)395 static bool intel_crtc_needs_link_reset(struct intel_crtc *crtc)
396 {
397 struct drm_device *dev = crtc->base.dev;
398 struct intel_encoder *encoder;
399
400 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
401 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
402
403 if (dig_port && intel_tc_port_link_needs_reset(dig_port))
404 return true;
405 }
406
407 return false;
408 }
409
intel_encoder_find_connector(struct intel_encoder * encoder)410 static struct intel_connector *intel_encoder_find_connector(struct intel_encoder *encoder)
411 {
412 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
413 struct drm_connector_list_iter conn_iter;
414 struct intel_connector *connector;
415 struct intel_connector *found_connector = NULL;
416
417 drm_connector_list_iter_begin(&i915->drm, &conn_iter);
418 for_each_intel_connector_iter(connector, &conn_iter) {
419 if (&encoder->base == connector->base.encoder) {
420 found_connector = connector;
421 break;
422 }
423 }
424 drm_connector_list_iter_end(&conn_iter);
425
426 return found_connector;
427 }
428
intel_sanitize_fifo_underrun_reporting(const struct intel_crtc_state * crtc_state)429 static void intel_sanitize_fifo_underrun_reporting(const struct intel_crtc_state *crtc_state)
430 {
431 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
432 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
433
434 /*
435 * We start out with underrun reporting disabled on active
436 * pipes to avoid races.
437 *
438 * Also on gmch platforms we dont have any hardware bits to
439 * disable the underrun reporting. Which means we need to start
440 * out with underrun reporting disabled also on inactive pipes,
441 * since otherwise we'll complain about the garbage we read when
442 * e.g. coming up after runtime pm.
443 *
444 * No protection against concurrent access is required - at
445 * worst a fifo underrun happens which also sets this to false.
446 */
447 intel_init_fifo_underrun_reporting(i915, crtc,
448 !crtc_state->hw.active &&
449 !HAS_GMCH(i915));
450 }
451
intel_sanitize_crtc(struct intel_crtc * crtc,struct drm_modeset_acquire_ctx * ctx)452 static bool intel_sanitize_crtc(struct intel_crtc *crtc,
453 struct drm_modeset_acquire_ctx *ctx)
454 {
455 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
456 struct intel_crtc_state *crtc_state = to_intel_crtc_state(crtc->base.state);
457 bool needs_link_reset;
458
459 if (crtc_state->hw.active) {
460 struct intel_plane *plane;
461
462 /* Disable everything but the primary plane */
463 for_each_intel_plane_on_crtc(&i915->drm, crtc, plane) {
464 const struct intel_plane_state *plane_state =
465 to_intel_plane_state(plane->base.state);
466
467 if (plane_state->uapi.visible &&
468 plane->base.type != DRM_PLANE_TYPE_PRIMARY)
469 intel_plane_disable_noatomic(crtc, plane);
470 }
471
472 /* Disable any background color/etc. set by the BIOS */
473 intel_color_commit_noarm(crtc_state);
474 intel_color_commit_arm(crtc_state);
475 }
476
477 if (!crtc_state->hw.active ||
478 intel_crtc_is_bigjoiner_slave(crtc_state))
479 return false;
480
481 needs_link_reset = intel_crtc_needs_link_reset(crtc);
482
483 /*
484 * Adjust the state of the output pipe according to whether we have
485 * active connectors/encoders.
486 */
487 if (!needs_link_reset && intel_crtc_has_encoders(crtc))
488 return false;
489
490 intel_crtc_disable_noatomic(crtc, ctx);
491
492 /*
493 * The HPD state on other active/disconnected TC ports may be stuck in
494 * the connected state until this port is disabled and a ~10ms delay has
495 * passed, wait here for that so that sanitizing other CRTCs will see the
496 * up-to-date HPD state.
497 */
498 if (needs_link_reset)
499 drm_msleep(20);
500
501 return true;
502 }
503
intel_sanitize_all_crtcs(struct drm_i915_private * i915,struct drm_modeset_acquire_ctx * ctx)504 static void intel_sanitize_all_crtcs(struct drm_i915_private *i915,
505 struct drm_modeset_acquire_ctx *ctx)
506 {
507 struct intel_crtc *crtc;
508 u32 crtcs_forced_off = 0;
509
510 /*
511 * An active and disconnected TypeC port prevents the HPD live state
512 * to get updated on other active/disconnected TypeC ports, so after
513 * a port gets disabled the CRTCs using other TypeC ports must be
514 * rechecked wrt. their link status.
515 */
516 for (;;) {
517 u32 old_mask = crtcs_forced_off;
518
519 for_each_intel_crtc(&i915->drm, crtc) {
520 u32 crtc_mask = drm_crtc_mask(&crtc->base);
521
522 if (crtcs_forced_off & crtc_mask)
523 continue;
524
525 if (intel_sanitize_crtc(crtc, ctx))
526 crtcs_forced_off |= crtc_mask;
527 }
528 if (crtcs_forced_off == old_mask)
529 break;
530 }
531
532 for_each_intel_crtc(&i915->drm, crtc) {
533 struct intel_crtc_state *crtc_state =
534 to_intel_crtc_state(crtc->base.state);
535
536 intel_crtc_state_dump(crtc_state, NULL, "setup_hw_state");
537 }
538 }
539
has_bogus_dpll_config(const struct intel_crtc_state * crtc_state)540 static bool has_bogus_dpll_config(const struct intel_crtc_state *crtc_state)
541 {
542 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
543
544 /*
545 * Some SNB BIOSen (eg. ASUS K53SV) are known to misprogram
546 * the hardware when a high res displays plugged in. DPLL P
547 * divider is zero, and the pipe timings are bonkers. We'll
548 * try to disable everything in that case.
549 *
550 * FIXME would be nice to be able to sanitize this state
551 * without several WARNs, but for now let's take the easy
552 * road.
553 */
554 return IS_SANDYBRIDGE(i915) &&
555 crtc_state->hw.active &&
556 crtc_state->shared_dpll &&
557 crtc_state->port_clock == 0;
558 }
559
intel_sanitize_encoder(struct intel_encoder * encoder)560 static void intel_sanitize_encoder(struct intel_encoder *encoder)
561 {
562 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
563 struct intel_connector *connector;
564 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
565 struct intel_crtc_state *crtc_state = crtc ?
566 to_intel_crtc_state(crtc->base.state) : NULL;
567 struct intel_pmdemand_state *pmdemand_state =
568 to_intel_pmdemand_state(i915->display.pmdemand.obj.state);
569
570 /*
571 * We need to check both for a crtc link (meaning that the encoder is
572 * active and trying to read from a pipe) and the pipe itself being
573 * active.
574 */
575 bool has_active_crtc = crtc_state &&
576 crtc_state->hw.active;
577
578 if (crtc_state && has_bogus_dpll_config(crtc_state)) {
579 drm_dbg_kms(&i915->drm,
580 "BIOS has misprogrammed the hardware. Disabling pipe %c\n",
581 pipe_name(crtc->pipe));
582 has_active_crtc = false;
583 }
584
585 connector = intel_encoder_find_connector(encoder);
586 if (connector && !has_active_crtc) {
587 drm_dbg_kms(&i915->drm,
588 "[ENCODER:%d:%s] has active connectors but no active pipe!\n",
589 encoder->base.base.id,
590 encoder->base.name);
591
592 /* Clear the corresponding bit in pmdemand active phys mask */
593 intel_pmdemand_update_phys_mask(i915, encoder,
594 pmdemand_state, false);
595
596 /*
597 * Connector is active, but has no active pipe. This is fallout
598 * from our resume register restoring. Disable the encoder
599 * manually again.
600 */
601 if (crtc_state) {
602 struct drm_encoder *best_encoder;
603
604 drm_dbg_kms(&i915->drm,
605 "[ENCODER:%d:%s] manually disabled\n",
606 encoder->base.base.id,
607 encoder->base.name);
608
609 /* avoid oopsing in case the hooks consult best_encoder */
610 best_encoder = connector->base.state->best_encoder;
611 connector->base.state->best_encoder = &encoder->base;
612
613 /* FIXME NULL atomic state passed! */
614 if (encoder->disable)
615 encoder->disable(NULL, encoder, crtc_state,
616 connector->base.state);
617 if (encoder->post_disable)
618 encoder->post_disable(NULL, encoder, crtc_state,
619 connector->base.state);
620
621 connector->base.state->best_encoder = best_encoder;
622 }
623 encoder->base.crtc = NULL;
624
625 /*
626 * Inconsistent output/port/pipe state happens presumably due to
627 * a bug in one of the get_hw_state functions. Or someplace else
628 * in our code, like the register restore mess on resume. Clamp
629 * things to off as a safer default.
630 */
631 connector->base.dpms = DRM_MODE_DPMS_OFF;
632 connector->base.encoder = NULL;
633 }
634
635 /* notify opregion of the sanitized encoder state */
636 intel_opregion_notify_encoder(encoder, connector && has_active_crtc);
637
638 if (HAS_DDI(i915))
639 intel_ddi_sanitize_encoder_pll_mapping(encoder);
640 }
641
642 /* FIXME read out full plane state for all planes */
readout_plane_state(struct drm_i915_private * i915)643 static void readout_plane_state(struct drm_i915_private *i915)
644 {
645 struct intel_plane *plane;
646 struct intel_crtc *crtc;
647
648 for_each_intel_plane(&i915->drm, plane) {
649 struct intel_plane_state *plane_state =
650 to_intel_plane_state(plane->base.state);
651 struct intel_crtc_state *crtc_state;
652 enum pipe pipe = PIPE_A;
653 bool visible;
654
655 visible = plane->get_hw_state(plane, &pipe);
656
657 crtc = intel_crtc_for_pipe(i915, pipe);
658 crtc_state = to_intel_crtc_state(crtc->base.state);
659
660 intel_set_plane_visible(crtc_state, plane_state, visible);
661
662 drm_dbg_kms(&i915->drm,
663 "[PLANE:%d:%s] hw state readout: %s, pipe %c\n",
664 plane->base.base.id, plane->base.name,
665 str_enabled_disabled(visible), pipe_name(pipe));
666 }
667
668 for_each_intel_crtc(&i915->drm, crtc) {
669 struct intel_crtc_state *crtc_state =
670 to_intel_crtc_state(crtc->base.state);
671
672 intel_plane_fixup_bitmasks(crtc_state);
673 }
674 }
675
intel_modeset_readout_hw_state(struct drm_i915_private * i915)676 static void intel_modeset_readout_hw_state(struct drm_i915_private *i915)
677 {
678 struct intel_cdclk_state *cdclk_state =
679 to_intel_cdclk_state(i915->display.cdclk.obj.state);
680 struct intel_dbuf_state *dbuf_state =
681 to_intel_dbuf_state(i915->display.dbuf.obj.state);
682 struct intel_pmdemand_state *pmdemand_state =
683 to_intel_pmdemand_state(i915->display.pmdemand.obj.state);
684 enum pipe pipe;
685 struct intel_crtc *crtc;
686 struct intel_encoder *encoder;
687 struct intel_connector *connector;
688 struct drm_connector_list_iter conn_iter;
689 u8 active_pipes = 0;
690
691 for_each_intel_crtc(&i915->drm, crtc) {
692 struct intel_crtc_state *crtc_state =
693 to_intel_crtc_state(crtc->base.state);
694
695 __drm_atomic_helper_crtc_destroy_state(&crtc_state->uapi);
696 intel_crtc_free_hw_state(crtc_state);
697 intel_crtc_state_reset(crtc_state, crtc);
698
699 intel_crtc_get_pipe_config(crtc_state);
700
701 crtc_state->hw.enable = crtc_state->hw.active;
702
703 crtc->base.enabled = crtc_state->hw.enable;
704 crtc->active = crtc_state->hw.active;
705
706 if (crtc_state->hw.active)
707 active_pipes |= BIT(crtc->pipe);
708
709 drm_dbg_kms(&i915->drm,
710 "[CRTC:%d:%s] hw state readout: %s\n",
711 crtc->base.base.id, crtc->base.name,
712 str_enabled_disabled(crtc_state->hw.active));
713 }
714
715 cdclk_state->active_pipes = active_pipes;
716 dbuf_state->active_pipes = active_pipes;
717
718 readout_plane_state(i915);
719
720 for_each_intel_encoder(&i915->drm, encoder) {
721 struct intel_crtc_state *crtc_state = NULL;
722
723 pipe = 0;
724
725 if (encoder->get_hw_state(encoder, &pipe)) {
726 crtc = intel_crtc_for_pipe(i915, pipe);
727 crtc_state = to_intel_crtc_state(crtc->base.state);
728
729 encoder->base.crtc = &crtc->base;
730 intel_encoder_get_config(encoder, crtc_state);
731
732 /* read out to slave crtc as well for bigjoiner */
733 if (crtc_state->bigjoiner_pipes) {
734 struct intel_crtc *slave_crtc;
735
736 /* encoder should read be linked to bigjoiner master */
737 WARN_ON(intel_crtc_is_bigjoiner_slave(crtc_state));
738
739 for_each_intel_crtc_in_pipe_mask(&i915->drm, slave_crtc,
740 intel_crtc_bigjoiner_slave_pipes(crtc_state)) {
741 struct intel_crtc_state *slave_crtc_state;
742
743 slave_crtc_state = to_intel_crtc_state(slave_crtc->base.state);
744 intel_encoder_get_config(encoder, slave_crtc_state);
745 }
746 }
747
748 intel_pmdemand_update_phys_mask(i915, encoder,
749 pmdemand_state,
750 true);
751 } else {
752 intel_pmdemand_update_phys_mask(i915, encoder,
753 pmdemand_state,
754 false);
755
756 encoder->base.crtc = NULL;
757 }
758
759 if (encoder->sync_state)
760 encoder->sync_state(encoder, crtc_state);
761
762 drm_dbg_kms(&i915->drm,
763 "[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
764 encoder->base.base.id, encoder->base.name,
765 str_enabled_disabled(encoder->base.crtc),
766 pipe_name(pipe));
767 }
768
769 intel_dpll_readout_hw_state(i915);
770
771 drm_connector_list_iter_begin(&i915->drm, &conn_iter);
772 for_each_intel_connector_iter(connector, &conn_iter) {
773 if (connector->get_hw_state(connector)) {
774 struct intel_crtc_state *crtc_state;
775 struct intel_crtc *crtc;
776
777 connector->base.dpms = DRM_MODE_DPMS_ON;
778
779 encoder = intel_attached_encoder(connector);
780 connector->base.encoder = &encoder->base;
781
782 crtc = to_intel_crtc(encoder->base.crtc);
783 crtc_state = crtc ? to_intel_crtc_state(crtc->base.state) : NULL;
784
785 if (crtc_state && crtc_state->hw.active) {
786 /*
787 * This has to be done during hardware readout
788 * because anything calling .crtc_disable may
789 * rely on the connector_mask being accurate.
790 */
791 crtc_state->uapi.connector_mask |=
792 drm_connector_mask(&connector->base);
793 crtc_state->uapi.encoder_mask |=
794 drm_encoder_mask(&encoder->base);
795 }
796 } else {
797 connector->base.dpms = DRM_MODE_DPMS_OFF;
798 connector->base.encoder = NULL;
799 }
800 drm_dbg_kms(&i915->drm,
801 "[CONNECTOR:%d:%s] hw state readout: %s\n",
802 connector->base.base.id, connector->base.name,
803 str_enabled_disabled(connector->base.encoder));
804 }
805 drm_connector_list_iter_end(&conn_iter);
806
807 for_each_intel_crtc(&i915->drm, crtc) {
808 struct intel_bw_state *bw_state =
809 to_intel_bw_state(i915->display.bw.obj.state);
810 struct intel_crtc_state *crtc_state =
811 to_intel_crtc_state(crtc->base.state);
812 struct intel_plane *plane;
813 int min_cdclk = 0;
814
815 if (crtc_state->hw.active) {
816 /*
817 * The initial mode needs to be set in order to keep
818 * the atomic core happy. It wants a valid mode if the
819 * crtc's enabled, so we do the above call.
820 *
821 * But we don't set all the derived state fully, hence
822 * set a flag to indicate that a full recalculation is
823 * needed on the next commit.
824 */
825 crtc_state->inherited = true;
826
827 intel_crtc_update_active_timings(crtc_state,
828 crtc_state->vrr.enable);
829
830 intel_crtc_copy_hw_to_uapi_state(crtc_state);
831 }
832
833 for_each_intel_plane_on_crtc(&i915->drm, crtc, plane) {
834 const struct intel_plane_state *plane_state =
835 to_intel_plane_state(plane->base.state);
836
837 /*
838 * FIXME don't have the fb yet, so can't
839 * use intel_plane_data_rate() :(
840 */
841 if (plane_state->uapi.visible)
842 crtc_state->data_rate[plane->id] =
843 4 * crtc_state->pixel_rate;
844 /*
845 * FIXME don't have the fb yet, so can't
846 * use plane->min_cdclk() :(
847 */
848 if (plane_state->uapi.visible && plane->min_cdclk) {
849 if (crtc_state->double_wide || DISPLAY_VER(i915) >= 10)
850 crtc_state->min_cdclk[plane->id] =
851 DIV_ROUND_UP(crtc_state->pixel_rate, 2);
852 else
853 crtc_state->min_cdclk[plane->id] =
854 crtc_state->pixel_rate;
855 }
856 drm_dbg_kms(&i915->drm,
857 "[PLANE:%d:%s] min_cdclk %d kHz\n",
858 plane->base.base.id, plane->base.name,
859 crtc_state->min_cdclk[plane->id]);
860 }
861
862 if (crtc_state->hw.active) {
863 min_cdclk = intel_crtc_compute_min_cdclk(crtc_state);
864 if (drm_WARN_ON(&i915->drm, min_cdclk < 0))
865 min_cdclk = 0;
866 }
867
868 cdclk_state->min_cdclk[crtc->pipe] = min_cdclk;
869 cdclk_state->min_voltage_level[crtc->pipe] =
870 crtc_state->min_voltage_level;
871
872 intel_pmdemand_update_port_clock(i915, pmdemand_state, pipe,
873 crtc_state->port_clock);
874
875 intel_bw_crtc_update(bw_state, crtc_state);
876 }
877
878 intel_pmdemand_init_pmdemand_params(i915, pmdemand_state);
879 }
880
881 static void
get_encoder_power_domains(struct drm_i915_private * i915)882 get_encoder_power_domains(struct drm_i915_private *i915)
883 {
884 struct intel_encoder *encoder;
885
886 for_each_intel_encoder(&i915->drm, encoder) {
887 struct intel_crtc_state *crtc_state;
888
889 if (!encoder->get_power_domains)
890 continue;
891
892 /*
893 * MST-primary and inactive encoders don't have a crtc state
894 * and neither of these require any power domain references.
895 */
896 if (!encoder->base.crtc)
897 continue;
898
899 crtc_state = to_intel_crtc_state(encoder->base.crtc->state);
900 encoder->get_power_domains(encoder, crtc_state);
901 }
902 }
903
intel_early_display_was(struct drm_i915_private * i915)904 static void intel_early_display_was(struct drm_i915_private *i915)
905 {
906 /*
907 * Display WA #1185 WaDisableDARBFClkGating:glk,icl,ehl,tgl
908 * Also known as Wa_14010480278.
909 */
910 if (IS_DISPLAY_VER(i915, 10, 12))
911 intel_de_rmw(i915, GEN9_CLKGATE_DIS_0, 0, DARBF_GATING_DIS);
912
913 /*
914 * WaRsPkgCStateDisplayPMReq:hsw
915 * System hang if this isn't done before disabling all planes!
916 */
917 if (IS_HASWELL(i915))
918 intel_de_rmw(i915, CHICKEN_PAR1_1, 0, FORCE_ARB_IDLE_PLANES);
919
920 if (IS_KABYLAKE(i915) || IS_COFFEELAKE(i915) || IS_COMETLAKE(i915)) {
921 /* Display WA #1142:kbl,cfl,cml */
922 intel_de_rmw(i915, CHICKEN_PAR1_1,
923 KBL_ARB_FILL_SPARE_22, KBL_ARB_FILL_SPARE_22);
924 intel_de_rmw(i915, CHICKEN_MISC_2,
925 KBL_ARB_FILL_SPARE_13 | KBL_ARB_FILL_SPARE_14,
926 KBL_ARB_FILL_SPARE_14);
927 }
928 }
929
intel_modeset_setup_hw_state(struct drm_i915_private * i915,struct drm_modeset_acquire_ctx * ctx)930 void intel_modeset_setup_hw_state(struct drm_i915_private *i915,
931 struct drm_modeset_acquire_ctx *ctx)
932 {
933 struct intel_encoder *encoder;
934 struct intel_crtc *crtc;
935 intel_wakeref_t wakeref;
936
937 wakeref = intel_display_power_get(i915, POWER_DOMAIN_INIT);
938
939 intel_early_display_was(i915);
940 intel_modeset_readout_hw_state(i915);
941
942 /* HW state is read out, now we need to sanitize this mess. */
943 get_encoder_power_domains(i915);
944
945 intel_pch_sanitize(i915);
946
947 /*
948 * intel_sanitize_plane_mapping() may need to do vblank
949 * waits, so we need vblank interrupts restored beforehand.
950 */
951 for_each_intel_crtc(&i915->drm, crtc) {
952 struct intel_crtc_state *crtc_state =
953 to_intel_crtc_state(crtc->base.state);
954
955 intel_sanitize_fifo_underrun_reporting(crtc_state);
956
957 drm_crtc_vblank_reset(&crtc->base);
958
959 if (crtc_state->hw.active) {
960 intel_dmc_enable_pipe(i915, crtc->pipe);
961 intel_crtc_vblank_on(crtc_state);
962 }
963 }
964
965 intel_fbc_sanitize(i915);
966
967 intel_sanitize_plane_mapping(i915);
968
969 for_each_intel_encoder(&i915->drm, encoder)
970 intel_sanitize_encoder(encoder);
971
972 /*
973 * Sanitizing CRTCs needs their connector atomic state to be
974 * up-to-date, so ensure that already here.
975 */
976 intel_modeset_update_connector_atomic_state(i915);
977
978 intel_sanitize_all_crtcs(i915, ctx);
979
980 intel_dpll_sanitize_state(i915);
981
982 intel_wm_get_hw_state(i915);
983
984 for_each_intel_crtc(&i915->drm, crtc) {
985 struct intel_crtc_state *crtc_state =
986 to_intel_crtc_state(crtc->base.state);
987 struct intel_power_domain_mask put_domains;
988
989 intel_modeset_get_crtc_power_domains(crtc_state, &put_domains);
990 if (drm_WARN_ON(&i915->drm, !bitmap_empty(put_domains.bits, POWER_DOMAIN_NUM)))
991 intel_modeset_put_crtc_power_domains(crtc, &put_domains);
992 }
993
994 intel_display_power_put(i915, POWER_DOMAIN_INIT, wakeref);
995
996 intel_power_domains_sanitize_state(i915);
997 }
998