1 /* $NetBSD: if_ipw.c,v 1.60 2016/06/10 13:27:14 ozaki-r Exp $ */
2 /* FreeBSD: src/sys/dev/ipw/if_ipw.c,v 1.15 2005/11/13 17:17:40 damien Exp */
3
4 /*-
5 * Copyright (c) 2004, 2005
6 * Damien Bergamini <damien.bergamini@free.fr>. All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice unmodified, this list of conditions, and the following
13 * disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * SUCH DAMAGE.
29 */
30
31 #include <sys/cdefs.h>
32 __KERNEL_RCSID(0, "$NetBSD: if_ipw.c,v 1.60 2016/06/10 13:27:14 ozaki-r Exp $");
33
34 /*-
35 * Intel(R) PRO/Wireless 2100 MiniPCI driver
36 * http://www.intel.com/network/connectivity/products/wireless/prowireless_mobile.htm
37 */
38
39
40 #include <sys/param.h>
41 #include <sys/sockio.h>
42 #include <sys/sysctl.h>
43 #include <sys/mbuf.h>
44 #include <sys/kernel.h>
45 #include <sys/socket.h>
46 #include <sys/systm.h>
47 #include <sys/malloc.h>
48 #include <sys/conf.h>
49 #include <sys/proc.h>
50
51 #include <sys/bus.h>
52 #include <machine/endian.h>
53 #include <sys/intr.h>
54
55 #include <dev/pci/pcireg.h>
56 #include <dev/pci/pcivar.h>
57 #include <dev/pci/pcidevs.h>
58
59 #include <net/bpf.h>
60 #include <net/if.h>
61 #include <net/if_arp.h>
62 #include <net/if_dl.h>
63 #include <net/if_ether.h>
64 #include <net/if_media.h>
65 #include <net/if_types.h>
66
67 #include <net80211/ieee80211_var.h>
68 #include <net80211/ieee80211_radiotap.h>
69
70 #include <netinet/in.h>
71 #include <netinet/in_systm.h>
72 #include <netinet/in_var.h>
73 #include <netinet/ip.h>
74
75 #include <dev/firmload.h>
76
77 #include <dev/pci/if_ipwreg.h>
78 #include <dev/pci/if_ipwvar.h>
79
80 #ifdef IPW_DEBUG
81 #define DPRINTF(x) if (ipw_debug > 0) printf x
82 #define DPRINTFN(n, x) if (ipw_debug >= (n)) printf x
83 int ipw_debug = 0;
84 #else
85 #define DPRINTF(x)
86 #define DPRINTFN(n, x)
87 #endif
88
89 /* Permit loading the Intel firmware */
90 static int ipw_accept_eula;
91
92 static int ipw_dma_alloc(struct ipw_softc *);
93 static void ipw_release(struct ipw_softc *);
94 static int ipw_match(device_t, cfdata_t, void *);
95 static void ipw_attach(device_t, device_t, void *);
96 static int ipw_detach(device_t, int);
97
98 static int ipw_media_change(struct ifnet *);
99 static void ipw_media_status(struct ifnet *, struct ifmediareq *);
100 static int ipw_newstate(struct ieee80211com *, enum ieee80211_state, int);
101 static uint16_t ipw_read_prom_word(struct ipw_softc *, uint8_t);
102 static void ipw_command_intr(struct ipw_softc *, struct ipw_soft_buf *);
103 static void ipw_newstate_intr(struct ipw_softc *, struct ipw_soft_buf *);
104 static void ipw_data_intr(struct ipw_softc *, struct ipw_status *,
105 struct ipw_soft_bd *, struct ipw_soft_buf *);
106 static void ipw_rx_intr(struct ipw_softc *);
107 static void ipw_release_sbd(struct ipw_softc *, struct ipw_soft_bd *);
108 static void ipw_tx_intr(struct ipw_softc *);
109 static int ipw_intr(void *);
110 static int ipw_cmd(struct ipw_softc *, uint32_t, void *, uint32_t);
111 static int ipw_tx_start(struct ifnet *, struct mbuf *,
112 struct ieee80211_node *);
113 static void ipw_start(struct ifnet *);
114 static void ipw_watchdog(struct ifnet *);
115 static int ipw_ioctl(struct ifnet *, u_long, void *);
116 static int ipw_get_table1(struct ipw_softc *, uint32_t *);
117 static int ipw_get_radio(struct ipw_softc *, int *);
118 static void ipw_stop_master(struct ipw_softc *);
119 static int ipw_reset(struct ipw_softc *);
120 static int ipw_load_ucode(struct ipw_softc *, u_char *, int);
121 static int ipw_load_firmware(struct ipw_softc *, u_char *, int);
122 static int ipw_cache_firmware(struct ipw_softc *);
123 static void ipw_free_firmware(struct ipw_softc *);
124 static int ipw_config(struct ipw_softc *);
125 static int ipw_init(struct ifnet *);
126 static void ipw_stop(struct ifnet *, int);
127 static uint32_t ipw_read_table1(struct ipw_softc *, uint32_t);
128 static void ipw_write_table1(struct ipw_softc *, uint32_t, uint32_t);
129 static int ipw_read_table2(struct ipw_softc *, uint32_t, void *, uint32_t *);
130 static void ipw_read_mem_1(struct ipw_softc *, bus_size_t, uint8_t *,
131 bus_size_t);
132 static void ipw_write_mem_1(struct ipw_softc *, bus_size_t, uint8_t *,
133 bus_size_t);
134
135 /*
136 * Supported rates for 802.11b mode (in 500Kbps unit).
137 */
138 static const struct ieee80211_rateset ipw_rateset_11b =
139 { 4, { 2, 4, 11, 22 } };
140
141 static inline uint8_t
MEM_READ_1(struct ipw_softc * sc,uint32_t addr)142 MEM_READ_1(struct ipw_softc *sc, uint32_t addr)
143 {
144 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, addr);
145 return CSR_READ_1(sc, IPW_CSR_INDIRECT_DATA);
146 }
147
148 static inline uint32_t
MEM_READ_4(struct ipw_softc * sc,uint32_t addr)149 MEM_READ_4(struct ipw_softc *sc, uint32_t addr)
150 {
151 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, addr);
152 return CSR_READ_4(sc, IPW_CSR_INDIRECT_DATA);
153 }
154
155 CFATTACH_DECL_NEW(ipw, sizeof (struct ipw_softc), ipw_match, ipw_attach,
156 ipw_detach, NULL);
157
158 static int
ipw_match(device_t parent,cfdata_t match,void * aux)159 ipw_match(device_t parent, cfdata_t match, void *aux)
160 {
161 struct pci_attach_args *pa = aux;
162
163 if (PCI_VENDOR (pa->pa_id) == PCI_VENDOR_INTEL &&
164 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_PRO_WL_2100)
165 return 1;
166
167 return 0;
168 }
169
170 /* Base Address Register */
171 #define IPW_PCI_BAR0 0x10
172
173 static void
ipw_attach(device_t parent,device_t self,void * aux)174 ipw_attach(device_t parent, device_t self, void *aux)
175 {
176 struct ipw_softc *sc = device_private(self);
177 struct ieee80211com *ic = &sc->sc_ic;
178 struct ifnet *ifp = &sc->sc_if;
179 struct pci_attach_args *pa = aux;
180 const char *intrstr;
181 bus_space_tag_t memt;
182 bus_space_handle_t memh;
183 bus_addr_t base;
184 pci_intr_handle_t ih;
185 uint32_t data;
186 uint16_t val;
187 int i, error;
188 char intrbuf[PCI_INTRSTR_LEN];
189
190 sc->sc_dev = self;
191 sc->sc_pct = pa->pa_pc;
192 sc->sc_pcitag = pa->pa_tag;
193
194 pci_aprint_devinfo(pa, NULL);
195
196 /* enable bus-mastering */
197 data = pci_conf_read(sc->sc_pct, pa->pa_tag, PCI_COMMAND_STATUS_REG);
198 data |= PCI_COMMAND_MASTER_ENABLE;
199 pci_conf_write(sc->sc_pct, pa->pa_tag, PCI_COMMAND_STATUS_REG, data);
200
201 /* map the register window */
202 error = pci_mapreg_map(pa, IPW_PCI_BAR0, PCI_MAPREG_TYPE_MEM |
203 PCI_MAPREG_MEM_TYPE_32BIT, 0, &memt, &memh, &base, &sc->sc_sz);
204 if (error != 0) {
205 aprint_error_dev(sc->sc_dev, "could not map memory space\n");
206 return;
207 }
208
209 sc->sc_st = memt;
210 sc->sc_sh = memh;
211 sc->sc_dmat = pa->pa_dmat;
212 sc->sc_fwname = "ipw2100-1.2.fw";
213
214 /* disable interrupts */
215 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, 0);
216
217 if (pci_intr_map(pa, &ih) != 0) {
218 aprint_error_dev(sc->sc_dev, "could not map interrupt\n");
219 return;
220 }
221
222 intrstr = pci_intr_string(sc->sc_pct, ih, intrbuf, sizeof(intrbuf));
223 sc->sc_ih = pci_intr_establish(sc->sc_pct, ih, IPL_NET, ipw_intr, sc);
224 if (sc->sc_ih == NULL) {
225 aprint_error_dev(sc->sc_dev, "could not establish interrupt");
226 if (intrstr != NULL)
227 aprint_error(" at %s", intrstr);
228 aprint_error("\n");
229 return;
230 }
231 aprint_normal_dev(sc->sc_dev, "interrupting at %s\n", intrstr);
232
233 if (ipw_reset(sc) != 0) {
234 aprint_error_dev(sc->sc_dev, "could not reset adapter\n");
235 goto fail;
236 }
237
238 if (ipw_dma_alloc(sc) != 0) {
239 aprint_error_dev(sc->sc_dev, "could not allocate DMA resources\n");
240 goto fail;
241 }
242
243 ifp->if_softc = sc;
244 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
245 ifp->if_init = ipw_init;
246 ifp->if_stop = ipw_stop;
247 ifp->if_ioctl = ipw_ioctl;
248 ifp->if_start = ipw_start;
249 ifp->if_watchdog = ipw_watchdog;
250 IFQ_SET_READY(&ifp->if_snd);
251 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ);
252
253 ic->ic_ifp = ifp;
254 ic->ic_phytype = IEEE80211_T_DS;
255 ic->ic_opmode = IEEE80211_M_STA;
256 ic->ic_state = IEEE80211_S_INIT;
257
258 /* set device capabilities */
259 ic->ic_caps =
260 IEEE80211_C_SHPREAMBLE /* short preamble supported */
261 | IEEE80211_C_TXPMGT /* tx power management */
262 | IEEE80211_C_IBSS /* ibss mode */
263 | IEEE80211_C_MONITOR /* monitor mode */
264 ;
265
266 /* read MAC address from EEPROM */
267 val = ipw_read_prom_word(sc, IPW_EEPROM_MAC + 0);
268 ic->ic_myaddr[0] = val >> 8;
269 ic->ic_myaddr[1] = val & 0xff;
270 val = ipw_read_prom_word(sc, IPW_EEPROM_MAC + 1);
271 ic->ic_myaddr[2] = val >> 8;
272 ic->ic_myaddr[3] = val & 0xff;
273 val = ipw_read_prom_word(sc, IPW_EEPROM_MAC + 2);
274 ic->ic_myaddr[4] = val >> 8;
275 ic->ic_myaddr[5] = val & 0xff;
276
277 /* set supported .11b rates */
278 ic->ic_sup_rates[IEEE80211_MODE_11B] = ipw_rateset_11b;
279
280 /* set supported .11b channels (read from EEPROM) */
281 if ((val = ipw_read_prom_word(sc, IPW_EEPROM_CHANNEL_LIST)) == 0)
282 val = 0x7ff; /* default to channels 1-11 */
283 val <<= 1;
284 for (i = 1; i < 16; i++) {
285 if (val & (1 << i)) {
286 ic->ic_channels[i].ic_freq =
287 ieee80211_ieee2mhz(i, IEEE80211_CHAN_B);
288 ic->ic_channels[i].ic_flags = IEEE80211_CHAN_B;
289 }
290 }
291
292 /* check support for radio transmitter switch in EEPROM */
293 if (!(ipw_read_prom_word(sc, IPW_EEPROM_RADIO) & 8))
294 sc->flags |= IPW_FLAG_HAS_RADIO_SWITCH;
295
296 aprint_normal_dev(sc->sc_dev, "802.11 address %s\n",
297 ether_sprintf(ic->ic_myaddr));
298
299 if_attach(ifp);
300 ieee80211_ifattach(ic);
301
302 /* override state transition machine */
303 sc->sc_newstate = ic->ic_newstate;
304 ic->ic_newstate = ipw_newstate;
305
306 ieee80211_media_init(ic, ipw_media_change, ipw_media_status);
307
308 bpf_attach2(ifp, DLT_IEEE802_11_RADIO,
309 sizeof(struct ieee80211_frame) + 64, &sc->sc_drvbpf);
310
311 sc->sc_rxtap_len = sizeof sc->sc_rxtapu;
312 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len);
313 sc->sc_rxtap.wr_ihdr.it_present = htole32(IPW_RX_RADIOTAP_PRESENT);
314
315 sc->sc_txtap_len = sizeof sc->sc_txtapu;
316 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len);
317 sc->sc_txtap.wt_ihdr.it_present = htole32(IPW_TX_RADIOTAP_PRESENT);
318
319 /*
320 * Add a few sysctl knobs.
321 * XXX: Not yet
322 */
323 sc->dwelltime = 100;
324
325 if (pmf_device_register(self, NULL, NULL))
326 pmf_class_network_register(self, ifp);
327 else
328 aprint_error_dev(self, "couldn't establish power handler\n");
329
330 ieee80211_announce(ic);
331
332 return;
333
334 fail: ipw_detach(self, 0);
335 }
336
337 static int
ipw_detach(device_t self,int flags)338 ipw_detach(device_t self, int flags)
339 {
340 struct ipw_softc *sc = device_private(self);
341 struct ifnet *ifp = &sc->sc_if;
342
343 if (ifp->if_softc) {
344 ipw_stop(ifp, 1);
345 ipw_free_firmware(sc);
346
347 bpf_detach(ifp);
348 ieee80211_ifdetach(&sc->sc_ic);
349 if_detach(ifp);
350
351 ipw_release(sc);
352 }
353
354 if (sc->sc_ih != NULL) {
355 pci_intr_disestablish(sc->sc_pct, sc->sc_ih);
356 sc->sc_ih = NULL;
357 }
358
359 bus_space_unmap(sc->sc_st, sc->sc_sh, sc->sc_sz);
360
361 return 0;
362 }
363
364 static int
ipw_dma_alloc(struct ipw_softc * sc)365 ipw_dma_alloc(struct ipw_softc *sc)
366 {
367 struct ipw_soft_bd *sbd;
368 struct ipw_soft_hdr *shdr;
369 struct ipw_soft_buf *sbuf;
370 int error, i, nsegs;
371
372 /*
373 * Allocate and map tx ring.
374 */
375 error = bus_dmamap_create(sc->sc_dmat, IPW_TBD_SZ, 1, IPW_TBD_SZ, 0,
376 BUS_DMA_NOWAIT, &sc->tbd_map);
377 if (error != 0) {
378 aprint_error_dev(sc->sc_dev, "could not create tbd dma map\n");
379 goto fail;
380 }
381
382 error = bus_dmamem_alloc(sc->sc_dmat, IPW_TBD_SZ, PAGE_SIZE, 0,
383 &sc->tbd_seg, 1, &nsegs, BUS_DMA_NOWAIT);
384 if (error != 0) {
385 aprint_error_dev(sc->sc_dev, "could not allocate tbd dma memory\n");
386 goto fail;
387 }
388
389 error = bus_dmamem_map(sc->sc_dmat, &sc->tbd_seg, nsegs, IPW_TBD_SZ,
390 (void **)&sc->tbd_list, BUS_DMA_NOWAIT);
391 if (error != 0) {
392 aprint_error_dev(sc->sc_dev, "could not map tbd dma memory\n");
393 goto fail;
394 }
395
396 error = bus_dmamap_load(sc->sc_dmat, sc->tbd_map, sc->tbd_list,
397 IPW_TBD_SZ, NULL, BUS_DMA_NOWAIT);
398 if (error != 0) {
399 aprint_error_dev(sc->sc_dev, "could not load tbd dma memory\n");
400 goto fail;
401 }
402
403 (void)memset(sc->tbd_list, 0, IPW_TBD_SZ);
404
405 /*
406 * Allocate and map rx ring.
407 */
408 error = bus_dmamap_create(sc->sc_dmat, IPW_RBD_SZ, 1, IPW_RBD_SZ, 0,
409 BUS_DMA_NOWAIT, &sc->rbd_map);
410 if (error != 0) {
411 aprint_error_dev(sc->sc_dev, "could not create rbd dma map\n");
412 goto fail;
413 }
414
415 error = bus_dmamem_alloc(sc->sc_dmat, IPW_RBD_SZ, PAGE_SIZE, 0,
416 &sc->rbd_seg, 1, &nsegs, BUS_DMA_NOWAIT);
417 if (error != 0) {
418 aprint_error_dev(sc->sc_dev, "could not allocate rbd dma memory\n");
419 goto fail;
420 }
421
422 error = bus_dmamem_map(sc->sc_dmat, &sc->rbd_seg, nsegs, IPW_RBD_SZ,
423 (void **)&sc->rbd_list, BUS_DMA_NOWAIT);
424 if (error != 0) {
425 aprint_error_dev(sc->sc_dev, "could not map rbd dma memory\n");
426 goto fail;
427 }
428
429 error = bus_dmamap_load(sc->sc_dmat, sc->rbd_map, sc->rbd_list,
430 IPW_RBD_SZ, NULL, BUS_DMA_NOWAIT);
431 if (error != 0) {
432 aprint_error_dev(sc->sc_dev, "could not load rbd dma memory\n");
433 goto fail;
434 }
435
436 (void)memset(sc->rbd_list, 0, IPW_RBD_SZ);
437
438 /*
439 * Allocate and map status ring.
440 */
441 error = bus_dmamap_create(sc->sc_dmat, IPW_STATUS_SZ, 1, IPW_STATUS_SZ,
442 0, BUS_DMA_NOWAIT, &sc->status_map);
443 if (error != 0) {
444 aprint_error_dev(sc->sc_dev, "could not create status dma map\n");
445 goto fail;
446 }
447
448 error = bus_dmamem_alloc(sc->sc_dmat, IPW_STATUS_SZ, PAGE_SIZE, 0,
449 &sc->status_seg, 1, &nsegs, BUS_DMA_NOWAIT);
450 if (error != 0) {
451 aprint_error_dev(sc->sc_dev, "could not allocate status dma memory\n");
452 goto fail;
453 }
454
455 error = bus_dmamem_map(sc->sc_dmat, &sc->status_seg, nsegs,
456 IPW_STATUS_SZ, (void **)&sc->status_list, BUS_DMA_NOWAIT);
457 if (error != 0) {
458 aprint_error_dev(sc->sc_dev, "could not map status dma memory\n");
459 goto fail;
460 }
461
462 error = bus_dmamap_load(sc->sc_dmat, sc->status_map, sc->status_list,
463 IPW_STATUS_SZ, NULL, BUS_DMA_NOWAIT);
464 if (error != 0) {
465 aprint_error_dev(sc->sc_dev, "could not load status dma memory\n");
466 goto fail;
467 }
468
469 (void)memset(sc->status_list, 0, IPW_STATUS_SZ);
470
471 /*
472 * Allocate command DMA map.
473 */
474 error = bus_dmamap_create(sc->sc_dmat, sizeof (struct ipw_cmd),
475 1, sizeof (struct ipw_cmd), 0, BUS_DMA_NOWAIT, &sc->cmd_map);
476 if (error != 0) {
477 aprint_error_dev(sc->sc_dev, "could not create cmd dma map\n");
478 goto fail;
479 }
480
481 error = bus_dmamem_alloc(sc->sc_dmat, sizeof (struct ipw_cmd),
482 PAGE_SIZE, 0, &sc->cmd_seg, 1, &nsegs, BUS_DMA_NOWAIT);
483 if (error != 0) {
484 aprint_error_dev(sc->sc_dev, "could not allocate cmd dma memory\n");
485 goto fail;
486 }
487
488 error = bus_dmamem_map(sc->sc_dmat, &sc->cmd_seg, nsegs,
489 sizeof (struct ipw_cmd), (void **)&sc->cmd, BUS_DMA_NOWAIT);
490 if (error != 0) {
491 aprint_error_dev(sc->sc_dev, "could not map cmd dma memory\n");
492 goto fail;
493 }
494
495 error = bus_dmamap_load(sc->sc_dmat, sc->cmd_map, &sc->cmd,
496 sizeof (struct ipw_cmd), NULL, BUS_DMA_NOWAIT);
497 if (error != 0) {
498 aprint_error_dev(sc->sc_dev, "could not map cmd dma memory\n");
499 return error;
500 }
501
502 /*
503 * Allocate and map hdr list.
504 */
505
506 error = bus_dmamap_create(sc->sc_dmat,
507 IPW_NDATA * sizeof(struct ipw_hdr), 1,
508 sizeof(struct ipw_hdr), 0, BUS_DMA_NOWAIT,
509 &sc->hdr_map);
510 if (error != 0) {
511 aprint_error_dev(sc->sc_dev, "could not create hdr dma map\n");
512 goto fail;
513 }
514
515 error = bus_dmamem_alloc(sc->sc_dmat,
516 IPW_NDATA * sizeof(struct ipw_hdr), PAGE_SIZE, 0, &sc->hdr_seg,
517 1, &nsegs, BUS_DMA_NOWAIT);
518 if (error != 0) {
519 aprint_error_dev(sc->sc_dev, "could not allocate hdr memory\n");
520 goto fail;
521 }
522
523 error = bus_dmamem_map(sc->sc_dmat, &sc->hdr_seg, nsegs,
524 IPW_NDATA * sizeof(struct ipw_hdr), (void **)&sc->hdr_list,
525 BUS_DMA_NOWAIT);
526 if (error != 0) {
527 aprint_error_dev(sc->sc_dev, "could not map hdr memory\n");
528 goto fail;
529 }
530
531 error = bus_dmamap_load(sc->sc_dmat, sc->hdr_map, sc->hdr_list,
532 IPW_NDATA * sizeof(struct ipw_hdr), NULL, BUS_DMA_NOWAIT);
533 if (error != 0) {
534 aprint_error_dev(sc->sc_dev, "could not load hdr memory\n");
535 goto fail;
536 }
537
538 (void)memset(sc->hdr_list, 0, IPW_HDR_SZ);
539
540 /*
541 * Create DMA hdrs tailq.
542 */
543 TAILQ_INIT(&sc->sc_free_shdr);
544 for (i = 0; i < IPW_NDATA; i++) {
545 shdr = &sc->shdr_list[i];
546 shdr->hdr = sc->hdr_list + i;
547 shdr->offset = sizeof(struct ipw_hdr) * i;
548 shdr->addr = sc->hdr_map->dm_segs[0].ds_addr + shdr->offset;
549 TAILQ_INSERT_TAIL(&sc->sc_free_shdr, shdr, next);
550 }
551
552 /*
553 * Allocate tx buffers DMA maps.
554 */
555 TAILQ_INIT(&sc->sc_free_sbuf);
556 for (i = 0; i < IPW_NDATA; i++) {
557 sbuf = &sc->tx_sbuf_list[i];
558
559 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES,
560 IPW_MAX_NSEG, MCLBYTES, 0, BUS_DMA_NOWAIT, &sbuf->map);
561 if (error != 0) {
562 aprint_error_dev(sc->sc_dev, "could not create txbuf dma map\n");
563 goto fail;
564 }
565 TAILQ_INSERT_TAIL(&sc->sc_free_sbuf, sbuf, next);
566 }
567
568 /*
569 * Initialize tx ring.
570 */
571 for (i = 0; i < IPW_NTBD; i++) {
572 sbd = &sc->stbd_list[i];
573 sbd->bd = &sc->tbd_list[i];
574 sbd->type = IPW_SBD_TYPE_NOASSOC;
575 }
576
577 /*
578 * Pre-allocate rx buffers and DMA maps
579 */
580 for (i = 0; i < IPW_NRBD; i++) {
581 sbd = &sc->srbd_list[i];
582 sbuf = &sc->rx_sbuf_list[i];
583 sbd->bd = &sc->rbd_list[i];
584
585 MGETHDR(sbuf->m, M_DONTWAIT, MT_DATA);
586 if (sbuf->m == NULL) {
587 aprint_error_dev(sc->sc_dev, "could not allocate rx mbuf\n");
588 error = ENOMEM;
589 goto fail;
590 }
591
592 MCLGET(sbuf->m, M_DONTWAIT);
593 if (!(sbuf->m->m_flags & M_EXT)) {
594 m_freem(sbuf->m);
595 aprint_error_dev(sc->sc_dev, "could not allocate rx mbuf cluster\n");
596 error = ENOMEM;
597 goto fail;
598 }
599
600 sbuf->m->m_pkthdr.len = sbuf->m->m_len = sbuf->m->m_ext.ext_size;
601
602 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES,
603 0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, &sbuf->map);
604 if (error != 0) {
605 aprint_error_dev(sc->sc_dev, "could not create rxbuf dma map\n");
606 m_freem(sbuf->m);
607 goto fail;
608 }
609
610 error = bus_dmamap_load_mbuf(sc->sc_dmat, sbuf->map,
611 sbuf->m, BUS_DMA_READ | BUS_DMA_NOWAIT);
612 if (error != 0) {
613 bus_dmamap_destroy(sc->sc_dmat, sbuf->map);
614 m_freem(sbuf->m);
615 aprint_error_dev(sc->sc_dev, "could not map rxbuf dma memory\n");
616 goto fail;
617 }
618
619 sbd->type = IPW_SBD_TYPE_DATA;
620 sbd->priv = sbuf;
621 sbd->bd->physaddr = htole32(sbuf->map->dm_segs[0].ds_addr);
622 sbd->bd->len = htole32(MCLBYTES);
623
624 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0,
625 sbuf->map->dm_mapsize, BUS_DMASYNC_PREREAD);
626
627 }
628
629 bus_dmamap_sync(sc->sc_dmat, sc->rbd_map, 0, IPW_RBD_SZ,
630 BUS_DMASYNC_PREREAD);
631
632 return 0;
633
634 fail: ipw_release(sc);
635 return error;
636 }
637
638 static void
ipw_release(struct ipw_softc * sc)639 ipw_release(struct ipw_softc *sc)
640 {
641 struct ipw_soft_buf *sbuf;
642 int i;
643
644 if (sc->tbd_map != NULL) {
645 if (sc->tbd_list != NULL) {
646 bus_dmamap_unload(sc->sc_dmat, sc->tbd_map);
647 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->tbd_list,
648 IPW_TBD_SZ);
649 bus_dmamem_free(sc->sc_dmat, &sc->tbd_seg, 1);
650 }
651 bus_dmamap_destroy(sc->sc_dmat, sc->tbd_map);
652 }
653
654 if (sc->rbd_map != NULL) {
655 if (sc->rbd_list != NULL) {
656 bus_dmamap_unload(sc->sc_dmat, sc->rbd_map);
657 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->rbd_list,
658 IPW_RBD_SZ);
659 bus_dmamem_free(sc->sc_dmat, &sc->rbd_seg, 1);
660 }
661 bus_dmamap_destroy(sc->sc_dmat, sc->rbd_map);
662 }
663
664 if (sc->status_map != NULL) {
665 if (sc->status_list != NULL) {
666 bus_dmamap_unload(sc->sc_dmat, sc->status_map);
667 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->status_list,
668 IPW_RBD_SZ);
669 bus_dmamem_free(sc->sc_dmat, &sc->status_seg, 1);
670 }
671 bus_dmamap_destroy(sc->sc_dmat, sc->status_map);
672 }
673
674 for (i = 0; i < IPW_NTBD; i++)
675 ipw_release_sbd(sc, &sc->stbd_list[i]);
676
677 if (sc->cmd_map != NULL)
678 bus_dmamap_destroy(sc->sc_dmat, sc->cmd_map);
679
680 if (sc->hdr_list != NULL) {
681 bus_dmamap_unload(sc->sc_dmat, sc->hdr_map);
682 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->hdr_list,
683 IPW_NDATA * sizeof(struct ipw_hdr));
684 }
685 if (sc->hdr_map != NULL) {
686 bus_dmamem_free(sc->sc_dmat, &sc->hdr_seg, 1);
687 bus_dmamap_destroy(sc->sc_dmat, sc->hdr_map);
688 }
689
690 for (i = 0; i < IPW_NDATA; i++)
691 bus_dmamap_destroy(sc->sc_dmat, sc->tx_sbuf_list[i].map);
692
693 for (i = 0; i < IPW_NRBD; i++) {
694 sbuf = &sc->rx_sbuf_list[i];
695 if (sbuf->map != NULL) {
696 if (sbuf->m != NULL) {
697 bus_dmamap_unload(sc->sc_dmat, sbuf->map);
698 m_freem(sbuf->m);
699 }
700 bus_dmamap_destroy(sc->sc_dmat, sbuf->map);
701 }
702 }
703
704 }
705
706 static int
ipw_media_change(struct ifnet * ifp)707 ipw_media_change(struct ifnet *ifp)
708 {
709 int error;
710
711 error = ieee80211_media_change(ifp);
712 if (error != ENETRESET)
713 return error;
714
715 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == (IFF_UP | IFF_RUNNING))
716 ipw_init(ifp);
717
718 return 0;
719 }
720
721 /*
722 * The firmware automatically adapts the transmit speed. We report the current
723 * transmit speed here.
724 */
725 static void
ipw_media_status(struct ifnet * ifp,struct ifmediareq * imr)726 ipw_media_status(struct ifnet *ifp, struct ifmediareq *imr)
727 {
728 #define N(a) (sizeof (a) / sizeof (a[0]))
729 struct ipw_softc *sc = ifp->if_softc;
730 struct ieee80211com *ic = &sc->sc_ic;
731 static const struct {
732 uint32_t val;
733 int rate;
734 } rates[] = {
735 { IPW_RATE_DS1, 2 },
736 { IPW_RATE_DS2, 4 },
737 { IPW_RATE_DS5, 11 },
738 { IPW_RATE_DS11, 22 },
739 };
740 uint32_t val;
741 int rate, i;
742
743 imr->ifm_status = IFM_AVALID;
744 imr->ifm_active = IFM_IEEE80211;
745 if (ic->ic_state == IEEE80211_S_RUN)
746 imr->ifm_status |= IFM_ACTIVE;
747
748 /* read current transmission rate from adapter */
749 val = ipw_read_table1(sc, IPW_INFO_CURRENT_TX_RATE) & 0xf;
750
751 /* convert ipw rate to 802.11 rate */
752 for (i = 0; i < N(rates) && rates[i].val != val; i++);
753 rate = (i < N(rates)) ? rates[i].rate : 0;
754
755 imr->ifm_active |= IFM_IEEE80211_11B;
756 imr->ifm_active |= ieee80211_rate2media(ic, rate, IEEE80211_MODE_11B);
757 switch (ic->ic_opmode) {
758 case IEEE80211_M_STA:
759 break;
760
761 case IEEE80211_M_IBSS:
762 imr->ifm_active |= IFM_IEEE80211_ADHOC;
763 break;
764
765 case IEEE80211_M_MONITOR:
766 imr->ifm_active |= IFM_IEEE80211_MONITOR;
767 break;
768
769 case IEEE80211_M_AHDEMO:
770 case IEEE80211_M_HOSTAP:
771 /* should not get there */
772 break;
773 }
774 #undef N
775 }
776
777 static int
ipw_newstate(struct ieee80211com * ic,enum ieee80211_state nstate,int arg)778 ipw_newstate(struct ieee80211com *ic, enum ieee80211_state nstate,
779 int arg)
780 {
781 struct ifnet *ifp = ic->ic_ifp;
782 struct ipw_softc *sc = ifp->if_softc;
783 struct ieee80211_node *ni;
784 uint8_t macaddr[IEEE80211_ADDR_LEN];
785 uint32_t len;
786 struct ipw_rx_radiotap_header *wr = &sc->sc_rxtap;
787 struct ipw_tx_radiotap_header *wt = &sc->sc_txtap;
788
789 switch (nstate) {
790 case IEEE80211_S_INIT:
791 break;
792 default:
793 KASSERT(ic->ic_curchan != IEEE80211_CHAN_ANYC);
794 KASSERT(ic->ic_curchan != NULL);
795 wt->wt_chan_freq = htole16(ic->ic_curchan->ic_freq);
796 wt->wt_chan_flags = htole16(ic->ic_curchan->ic_flags);
797 wr->wr_chan_freq = htole16(ic->ic_curchan->ic_freq);
798 wr->wr_chan_flags = htole16(ic->ic_curchan->ic_flags);
799 break;
800 }
801
802 switch (nstate) {
803 case IEEE80211_S_RUN:
804 DELAY(200); /* firmware needs a short delay here */
805
806 len = IEEE80211_ADDR_LEN;
807 ipw_read_table2(sc, IPW_INFO_CURRENT_BSSID, macaddr, &len);
808
809 ni = ieee80211_find_node(&ic->ic_scan, macaddr);
810 if (ni == NULL)
811 break;
812
813 ieee80211_ref_node(ni);
814 ieee80211_sta_join(ic, ni);
815 ieee80211_node_authorize(ni);
816
817 if (ic->ic_opmode == IEEE80211_M_STA)
818 ieee80211_notify_node_join(ic, ni, 1);
819 break;
820
821 case IEEE80211_S_INIT:
822 case IEEE80211_S_SCAN:
823 case IEEE80211_S_AUTH:
824 case IEEE80211_S_ASSOC:
825 break;
826 }
827
828 ic->ic_state = nstate;
829 return 0;
830 }
831
832 /*
833 * Read 16 bits at address 'addr' from the serial EEPROM.
834 */
835 static uint16_t
ipw_read_prom_word(struct ipw_softc * sc,uint8_t addr)836 ipw_read_prom_word(struct ipw_softc *sc, uint8_t addr)
837 {
838 uint32_t tmp;
839 uint16_t val;
840 int n;
841
842 /* clock C once before the first command */
843 IPW_EEPROM_CTL(sc, 0);
844 IPW_EEPROM_CTL(sc, IPW_EEPROM_S);
845 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_C);
846 IPW_EEPROM_CTL(sc, IPW_EEPROM_S);
847
848 /* write start bit (1) */
849 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D);
850 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D | IPW_EEPROM_C);
851
852 /* write READ opcode (10) */
853 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D);
854 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_D | IPW_EEPROM_C);
855 IPW_EEPROM_CTL(sc, IPW_EEPROM_S);
856 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_C);
857
858 /* write address A7-A0 */
859 for (n = 7; n >= 0; n--) {
860 IPW_EEPROM_CTL(sc, IPW_EEPROM_S |
861 (((addr >> n) & 1) << IPW_EEPROM_SHIFT_D));
862 IPW_EEPROM_CTL(sc, IPW_EEPROM_S |
863 (((addr >> n) & 1) << IPW_EEPROM_SHIFT_D) | IPW_EEPROM_C);
864 }
865
866 IPW_EEPROM_CTL(sc, IPW_EEPROM_S);
867
868 /* read data Q15-Q0 */
869 val = 0;
870 for (n = 15; n >= 0; n--) {
871 IPW_EEPROM_CTL(sc, IPW_EEPROM_S | IPW_EEPROM_C);
872 IPW_EEPROM_CTL(sc, IPW_EEPROM_S);
873 tmp = MEM_READ_4(sc, IPW_MEM_EEPROM_CTL);
874 val |= ((tmp & IPW_EEPROM_Q) >> IPW_EEPROM_SHIFT_Q) << n;
875 }
876
877 IPW_EEPROM_CTL(sc, 0);
878
879 /* clear Chip Select and clock C */
880 IPW_EEPROM_CTL(sc, IPW_EEPROM_S);
881 IPW_EEPROM_CTL(sc, 0);
882 IPW_EEPROM_CTL(sc, IPW_EEPROM_C);
883
884 return le16toh(val);
885 }
886
887 static void
ipw_command_intr(struct ipw_softc * sc,struct ipw_soft_buf * sbuf)888 ipw_command_intr(struct ipw_softc *sc, struct ipw_soft_buf *sbuf)
889 {
890
891 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, sizeof (struct ipw_cmd),
892 BUS_DMASYNC_POSTREAD);
893
894 #ifdef IPW_DEBUG
895 struct ipw_cmd *cmd = mtod(sbuf->m, struct ipw_cmd *);
896
897 DPRINTFN(2, ("cmd ack'ed (%u, %u, %u, %u, %u)\n", le32toh(cmd->type),
898 le32toh(cmd->subtype), le32toh(cmd->seq), le32toh(cmd->len),
899 le32toh(cmd->status)));
900 #endif
901
902 wakeup(&sc->cmd);
903 }
904
905 static void
ipw_newstate_intr(struct ipw_softc * sc,struct ipw_soft_buf * sbuf)906 ipw_newstate_intr(struct ipw_softc *sc, struct ipw_soft_buf *sbuf)
907 {
908 struct ieee80211com *ic = &sc->sc_ic;
909 struct ifnet *ifp = sc->sc_ic.ic_ifp;
910 uint32_t state;
911
912 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, sizeof state,
913 BUS_DMASYNC_POSTREAD);
914
915 state = le32toh(*mtod(sbuf->m, uint32_t *));
916
917 DPRINTFN(2, ("entering state %u\n", state));
918
919 switch (state) {
920 case IPW_STATE_ASSOCIATED:
921 ieee80211_new_state(ic, IEEE80211_S_RUN, -1);
922 break;
923
924 case IPW_STATE_SCANNING:
925 /* don't leave run state on background scan */
926 if (ic->ic_state != IEEE80211_S_RUN)
927 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1);
928
929 ic->ic_flags |= IEEE80211_F_SCAN;
930 break;
931
932 case IPW_STATE_SCAN_COMPLETE:
933 ieee80211_notify_scan_done(ic);
934 ic->ic_flags &= ~IEEE80211_F_SCAN;
935 break;
936
937 case IPW_STATE_ASSOCIATION_LOST:
938 ieee80211_new_state(ic, IEEE80211_S_INIT, -1);
939 break;
940
941 case IPW_STATE_RADIO_DISABLED:
942 ic->ic_ifp->if_flags &= ~IFF_UP;
943 ipw_stop(ifp, 1);
944 break;
945 }
946 }
947
948 /*
949 * XXX: Hack to set the current channel to the value advertised in beacons or
950 * probe responses. Only used during AP detection.
951 */
952 static void
ipw_fix_channel(struct ieee80211com * ic,struct mbuf * m)953 ipw_fix_channel(struct ieee80211com *ic, struct mbuf *m)
954 {
955 struct ieee80211_frame *wh;
956 uint8_t subtype;
957 uint8_t *frm, *efrm;
958
959 wh = mtod(m, struct ieee80211_frame *);
960
961 if ((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) != IEEE80211_FC0_TYPE_MGT)
962 return;
963
964 subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK;
965
966 if (subtype != IEEE80211_FC0_SUBTYPE_BEACON &&
967 subtype != IEEE80211_FC0_SUBTYPE_PROBE_RESP)
968 return;
969
970 frm = (uint8_t *)(wh + 1);
971 efrm = mtod(m, uint8_t *) + m->m_len;
972
973 frm += 12; /* skip tstamp, bintval and capinfo fields */
974 while (frm < efrm) {
975 if (*frm == IEEE80211_ELEMID_DSPARMS)
976 #if IEEE80211_CHAN_MAX < 255
977 if (frm[2] <= IEEE80211_CHAN_MAX)
978 #endif
979 ic->ic_curchan = &ic->ic_channels[frm[2]];
980
981 frm += frm[1] + 2;
982 }
983 }
984
985 static void
ipw_data_intr(struct ipw_softc * sc,struct ipw_status * status,struct ipw_soft_bd * sbd,struct ipw_soft_buf * sbuf)986 ipw_data_intr(struct ipw_softc *sc, struct ipw_status *status,
987 struct ipw_soft_bd *sbd, struct ipw_soft_buf *sbuf)
988 {
989 struct ieee80211com *ic = &sc->sc_ic;
990 struct ifnet *ifp = &sc->sc_if;
991 struct mbuf *mnew, *m;
992 struct ieee80211_frame *wh;
993 struct ieee80211_node *ni;
994 int error;
995
996 DPRINTFN(5, ("received frame len=%u, rssi=%u\n", le32toh(status->len),
997 status->rssi));
998
999 if (le32toh(status->len) < sizeof (struct ieee80211_frame_min) ||
1000 le32toh(status->len) > MCLBYTES)
1001 return;
1002
1003 /*
1004 * Try to allocate a new mbuf for this ring element and load it before
1005 * processing the current mbuf. If the ring element cannot be loaded,
1006 * drop the received packet and reuse the old mbuf. In the unlikely
1007 * case that the old mbuf can't be reloaded either, explicitly panic.
1008 */
1009 MGETHDR(mnew, M_DONTWAIT, MT_DATA);
1010 if (mnew == NULL) {
1011 aprint_error_dev(sc->sc_dev, "could not allocate rx mbuf\n");
1012 ifp->if_ierrors++;
1013 return;
1014 }
1015
1016 MCLGET(mnew, M_DONTWAIT);
1017 if (!(mnew->m_flags & M_EXT)) {
1018 aprint_error_dev(sc->sc_dev, "could not allocate rx mbuf cluster\n");
1019 m_freem(mnew);
1020 ifp->if_ierrors++;
1021 return;
1022 }
1023
1024 mnew->m_pkthdr.len = mnew->m_len = mnew->m_ext.ext_size;
1025
1026 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, le32toh(status->len),
1027 BUS_DMASYNC_POSTREAD);
1028 bus_dmamap_unload(sc->sc_dmat, sbuf->map);
1029
1030 error = bus_dmamap_load_mbuf(sc->sc_dmat, sbuf->map, mnew,
1031 BUS_DMA_READ | BUS_DMA_NOWAIT);
1032 if (error != 0) {
1033 aprint_error_dev(sc->sc_dev, "could not load rx buf DMA map\n");
1034 m_freem(mnew);
1035
1036 /* try to reload the old mbuf */
1037 error = bus_dmamap_load_mbuf(sc->sc_dmat, sbuf->map,
1038 sbuf->m, BUS_DMA_READ | BUS_DMA_NOWAIT);
1039 if (error != 0) {
1040 /* very unlikely that it will fail... */
1041 panic("%s: unable to remap rx buf",
1042 device_xname(sc->sc_dev));
1043 }
1044 ifp->if_ierrors++;
1045 return;
1046 }
1047
1048 /*
1049 * New mbuf successfully loaded, update Rx ring and continue
1050 * processing.
1051 */
1052 m = sbuf->m;
1053 sbuf->m = mnew;
1054 sbd->bd->physaddr = htole32(sbuf->map->dm_segs[0].ds_addr);
1055
1056 /* finalize mbuf */
1057 m_set_rcvif(m, ifp);
1058 m->m_pkthdr.len = m->m_len = le32toh(status->len);
1059
1060 if (sc->sc_drvbpf != NULL) {
1061 struct ipw_rx_radiotap_header *tap = &sc->sc_rxtap;
1062
1063 tap->wr_antsignal = status->rssi;
1064
1065 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_rxtap_len, m);
1066 }
1067
1068 if (ic->ic_state == IEEE80211_S_SCAN)
1069 ipw_fix_channel(ic, m);
1070
1071 wh = mtod(m, struct ieee80211_frame *);
1072 ni = ieee80211_find_rxnode(ic, (struct ieee80211_frame_min *)wh);
1073
1074 /* send the frame to the 802.11 layer */
1075 ieee80211_input(ic, m, ni, status->rssi, 0);
1076
1077 /* node is no longer needed */
1078 ieee80211_free_node(ni);
1079
1080 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0,
1081 sbuf->map->dm_mapsize, BUS_DMASYNC_PREREAD);
1082 }
1083
1084 static void
ipw_rx_intr(struct ipw_softc * sc)1085 ipw_rx_intr(struct ipw_softc *sc)
1086 {
1087 struct ipw_status *status;
1088 struct ipw_soft_bd *sbd;
1089 struct ipw_soft_buf *sbuf;
1090 uint32_t r, i;
1091
1092 if (!(sc->flags & IPW_FLAG_FW_INITED))
1093 return;
1094
1095 r = CSR_READ_4(sc, IPW_CSR_RX_READ);
1096
1097 for (i = (sc->rxcur + 1) % IPW_NRBD; i != r; i = (i + 1) % IPW_NRBD) {
1098
1099 /* firmware was killed, stop processing received frames */
1100 if (!(sc->flags & IPW_FLAG_FW_INITED))
1101 return;
1102
1103 bus_dmamap_sync(sc->sc_dmat, sc->rbd_map,
1104 i * sizeof (struct ipw_bd), sizeof (struct ipw_bd),
1105 BUS_DMASYNC_POSTREAD);
1106
1107 bus_dmamap_sync(sc->sc_dmat, sc->status_map,
1108 i * sizeof (struct ipw_status), sizeof (struct ipw_status),
1109 BUS_DMASYNC_POSTREAD);
1110
1111 status = &sc->status_list[i];
1112 sbd = &sc->srbd_list[i];
1113 sbuf = sbd->priv;
1114
1115 switch (le16toh(status->code) & 0xf) {
1116 case IPW_STATUS_CODE_COMMAND:
1117 ipw_command_intr(sc, sbuf);
1118 break;
1119
1120 case IPW_STATUS_CODE_NEWSTATE:
1121 ipw_newstate_intr(sc, sbuf);
1122 break;
1123
1124 case IPW_STATUS_CODE_DATA_802_3:
1125 case IPW_STATUS_CODE_DATA_802_11:
1126 ipw_data_intr(sc, status, sbd, sbuf);
1127 break;
1128
1129 case IPW_STATUS_CODE_NOTIFICATION:
1130 DPRINTFN(2, ("received notification\n"));
1131 break;
1132
1133 default:
1134 aprint_error_dev(sc->sc_dev, "unknown status code %u\n",
1135 le16toh(status->code));
1136 }
1137
1138 sbd->bd->flags = 0;
1139
1140 bus_dmamap_sync(sc->sc_dmat, sc->rbd_map,
1141 i * sizeof (struct ipw_bd), sizeof (struct ipw_bd),
1142 BUS_DMASYNC_PREREAD);
1143
1144 bus_dmamap_sync(sc->sc_dmat, sc->status_map,
1145 i * sizeof (struct ipw_status), sizeof (struct ipw_status),
1146 BUS_DMASYNC_PREREAD);
1147 }
1148
1149 /* Tell the firmware what we have processed */
1150 sc->rxcur = (r == 0) ? IPW_NRBD - 1 : r - 1;
1151 CSR_WRITE_4(sc, IPW_CSR_RX_WRITE, sc->rxcur);
1152 }
1153
1154 static void
ipw_release_sbd(struct ipw_softc * sc,struct ipw_soft_bd * sbd)1155 ipw_release_sbd(struct ipw_softc *sc, struct ipw_soft_bd *sbd)
1156 {
1157 struct ipw_soft_hdr *shdr;
1158 struct ipw_soft_buf *sbuf;
1159
1160 switch (sbd->type) {
1161 case IPW_SBD_TYPE_COMMAND:
1162 bus_dmamap_sync(sc->sc_dmat, sc->cmd_map,
1163 0, sizeof(struct ipw_cmd), BUS_DMASYNC_POSTWRITE);
1164 /* bus_dmamap_unload(sc->sc_dmat, sc->cmd_map); */
1165 break;
1166
1167 case IPW_SBD_TYPE_HEADER:
1168 shdr = sbd->priv;
1169 bus_dmamap_sync(sc->sc_dmat, sc->hdr_map,
1170 shdr->offset, sizeof(struct ipw_hdr), BUS_DMASYNC_POSTWRITE);
1171 TAILQ_INSERT_TAIL(&sc->sc_free_shdr, shdr, next);
1172 break;
1173
1174 case IPW_SBD_TYPE_DATA:
1175 sbuf = sbd->priv;
1176
1177 bus_dmamap_sync(sc->sc_dmat, sbuf->map,
1178 0, MCLBYTES, BUS_DMASYNC_POSTWRITE);
1179 bus_dmamap_unload(sc->sc_dmat, sbuf->map);
1180 m_freem(sbuf->m);
1181 if (sbuf->ni != NULL)
1182 ieee80211_free_node(sbuf->ni);
1183 /* kill watchdog timer */
1184 sc->sc_tx_timer = 0;
1185 TAILQ_INSERT_TAIL(&sc->sc_free_sbuf, sbuf, next);
1186 break;
1187 }
1188 sbd->type = IPW_SBD_TYPE_NOASSOC;
1189 }
1190
1191 static void
ipw_tx_intr(struct ipw_softc * sc)1192 ipw_tx_intr(struct ipw_softc *sc)
1193 {
1194 struct ifnet *ifp = &sc->sc_if;
1195 struct ipw_soft_bd *sbd;
1196 uint32_t r, i;
1197
1198 if (!(sc->flags & IPW_FLAG_FW_INITED))
1199 return;
1200
1201 r = CSR_READ_4(sc, IPW_CSR_TX_READ);
1202
1203 for (i = (sc->txold + 1) % IPW_NTBD; i != r; i = (i + 1) % IPW_NTBD) {
1204 sbd = &sc->stbd_list[i];
1205
1206 if (sbd->type == IPW_SBD_TYPE_DATA)
1207 ifp->if_opackets++;
1208
1209 ipw_release_sbd(sc, sbd);
1210 sc->txfree++;
1211 }
1212
1213 /* remember what the firmware has processed */
1214 sc->txold = (r == 0) ? IPW_NTBD - 1 : r - 1;
1215
1216 /* Call start() since some buffer descriptors have been released */
1217 ifp->if_flags &= ~IFF_OACTIVE;
1218 (*ifp->if_start)(ifp);
1219 }
1220
1221 static int
ipw_intr(void * arg)1222 ipw_intr(void *arg)
1223 {
1224 struct ipw_softc *sc = arg;
1225 uint32_t r;
1226
1227 r = CSR_READ_4(sc, IPW_CSR_INTR);
1228 if (r == 0 || r == 0xffffffff)
1229 return 0;
1230
1231 /* Disable interrupts */
1232 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, 0);
1233
1234 if (r & (IPW_INTR_FATAL_ERROR | IPW_INTR_PARITY_ERROR)) {
1235 aprint_error_dev(sc->sc_dev, "fatal error\n");
1236 sc->sc_ic.ic_ifp->if_flags &= ~IFF_UP;
1237 ipw_stop(&sc->sc_if, 1);
1238 }
1239
1240 if (r & IPW_INTR_FW_INIT_DONE) {
1241 if (!(r & (IPW_INTR_FATAL_ERROR | IPW_INTR_PARITY_ERROR)))
1242 wakeup(sc);
1243 }
1244
1245 if (r & IPW_INTR_RX_TRANSFER)
1246 ipw_rx_intr(sc);
1247
1248 if (r & IPW_INTR_TX_TRANSFER)
1249 ipw_tx_intr(sc);
1250
1251 /* Acknowledge all interrupts */
1252 CSR_WRITE_4(sc, IPW_CSR_INTR, r);
1253
1254 /* Re-enable interrupts */
1255 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, IPW_INTR_MASK);
1256
1257 return 0;
1258 }
1259
1260 /*
1261 * Send a command to the firmware and wait for the acknowledgement.
1262 */
1263 static int
ipw_cmd(struct ipw_softc * sc,uint32_t type,void * data,uint32_t len)1264 ipw_cmd(struct ipw_softc *sc, uint32_t type, void *data, uint32_t len)
1265 {
1266 struct ipw_soft_bd *sbd;
1267
1268 sbd = &sc->stbd_list[sc->txcur];
1269
1270 sc->cmd.type = htole32(type);
1271 sc->cmd.subtype = 0;
1272 sc->cmd.len = htole32(len);
1273 sc->cmd.seq = 0;
1274
1275 (void)memcpy(sc->cmd.data, data, len);
1276
1277 sbd->type = IPW_SBD_TYPE_COMMAND;
1278 sbd->bd->physaddr = htole32(sc->cmd_map->dm_segs[0].ds_addr);
1279 sbd->bd->len = htole32(sizeof (struct ipw_cmd));
1280 sbd->bd->nfrag = 1;
1281 sbd->bd->flags = IPW_BD_FLAG_TX_FRAME_COMMAND |
1282 IPW_BD_FLAG_TX_LAST_FRAGMENT;
1283
1284 bus_dmamap_sync(sc->sc_dmat, sc->cmd_map, 0, sizeof (struct ipw_cmd),
1285 BUS_DMASYNC_PREWRITE);
1286
1287 bus_dmamap_sync(sc->sc_dmat, sc->tbd_map,
1288 sc->txcur * sizeof (struct ipw_bd), sizeof (struct ipw_bd),
1289 BUS_DMASYNC_PREWRITE);
1290
1291 DPRINTFN(2, ("sending command (%u, %u, %u, %u)\n", type, 0, 0, len));
1292
1293 /* kick firmware */
1294 sc->txfree--;
1295 sc->txcur = (sc->txcur + 1) % IPW_NTBD;
1296 CSR_WRITE_4(sc, IPW_CSR_TX_WRITE, sc->txcur);
1297
1298 /* Wait at most one second for command to complete */
1299 return tsleep(&sc->cmd, 0, "ipwcmd", hz);
1300 }
1301
1302 static int
ipw_tx_start(struct ifnet * ifp,struct mbuf * m0,struct ieee80211_node * ni)1303 ipw_tx_start(struct ifnet *ifp, struct mbuf *m0, struct ieee80211_node *ni)
1304 {
1305 struct ipw_softc *sc = ifp->if_softc;
1306 struct ieee80211com *ic = &sc->sc_ic;
1307 struct ieee80211_frame *wh;
1308 struct ipw_soft_bd *sbd;
1309 struct ipw_soft_hdr *shdr;
1310 struct ipw_soft_buf *sbuf;
1311 struct ieee80211_key *k;
1312 struct mbuf *mnew;
1313 int error, i;
1314
1315 wh = mtod(m0, struct ieee80211_frame *);
1316
1317 if (wh->i_fc[1] & IEEE80211_FC1_WEP) {
1318 k = ieee80211_crypto_encap(ic, ni, m0);
1319 if (k == NULL) {
1320 m_freem(m0);
1321 return ENOBUFS;
1322 }
1323
1324 /* packet header may have moved, reset our local pointer */
1325 wh = mtod(m0, struct ieee80211_frame *);
1326 }
1327
1328 if (sc->sc_drvbpf != NULL) {
1329 struct ipw_tx_radiotap_header *tap = &sc->sc_txtap;
1330
1331 bpf_mtap2(sc->sc_drvbpf, tap, sc->sc_txtap_len, m0);
1332 }
1333
1334 shdr = TAILQ_FIRST(&sc->sc_free_shdr);
1335 sbuf = TAILQ_FIRST(&sc->sc_free_sbuf);
1336 KASSERT(shdr != NULL && sbuf != NULL);
1337
1338 shdr->hdr->type = htole32(IPW_HDR_TYPE_SEND);
1339 shdr->hdr->subtype = 0;
1340 shdr->hdr->encrypted = (wh->i_fc[1] & IEEE80211_FC1_WEP) ? 1 : 0;
1341 shdr->hdr->encrypt = 0;
1342 shdr->hdr->keyidx = 0;
1343 shdr->hdr->keysz = 0;
1344 shdr->hdr->fragmentsz = 0;
1345 IEEE80211_ADDR_COPY(shdr->hdr->src_addr, wh->i_addr2);
1346 if (ic->ic_opmode == IEEE80211_M_STA)
1347 IEEE80211_ADDR_COPY(shdr->hdr->dst_addr, wh->i_addr3);
1348 else
1349 IEEE80211_ADDR_COPY(shdr->hdr->dst_addr, wh->i_addr1);
1350
1351 /* trim IEEE802.11 header */
1352 m_adj(m0, sizeof (struct ieee80211_frame));
1353
1354 error = bus_dmamap_load_mbuf(sc->sc_dmat, sbuf->map, m0, BUS_DMA_NOWAIT);
1355 if (error != 0 && error != EFBIG) {
1356 aprint_error_dev(sc->sc_dev, "could not map mbuf (error %d)\n",
1357 error);
1358 m_freem(m0);
1359 return error;
1360 }
1361
1362 if (error != 0) {
1363 /* too many fragments, linearize */
1364
1365 MGETHDR(mnew, M_DONTWAIT, MT_DATA);
1366 if (mnew == NULL) {
1367 m_freem(m0);
1368 return ENOMEM;
1369 }
1370
1371 M_COPY_PKTHDR(mnew, m0);
1372
1373 /* If the data won't fit in the header, get a cluster */
1374 if (m0->m_pkthdr.len > MHLEN) {
1375 MCLGET(mnew, M_DONTWAIT);
1376 if (!(mnew->m_flags & M_EXT)) {
1377 m_freem(m0);
1378 m_freem(mnew);
1379 return ENOMEM;
1380 }
1381 }
1382 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(mnew, void *));
1383 m_freem(m0);
1384 mnew->m_len = mnew->m_pkthdr.len;
1385 m0 = mnew;
1386
1387 error = bus_dmamap_load_mbuf(sc->sc_dmat, sbuf->map, m0,
1388 BUS_DMA_WRITE | BUS_DMA_NOWAIT);
1389 if (error != 0) {
1390 aprint_error_dev(sc->sc_dev, "could not map mbuf (error %d)\n", error);
1391 m_freem(m0);
1392 return error;
1393 }
1394 }
1395
1396 TAILQ_REMOVE(&sc->sc_free_sbuf, sbuf, next);
1397 TAILQ_REMOVE(&sc->sc_free_shdr, shdr, next);
1398
1399 sbd = &sc->stbd_list[sc->txcur];
1400 sbd->type = IPW_SBD_TYPE_HEADER;
1401 sbd->priv = shdr;
1402 sbd->bd->physaddr = htole32(shdr->addr);
1403 sbd->bd->len = htole32(sizeof (struct ipw_hdr));
1404 sbd->bd->nfrag = 1 + sbuf->map->dm_nsegs;
1405 sbd->bd->flags = IPW_BD_FLAG_TX_FRAME_802_3 |
1406 IPW_BD_FLAG_TX_NOT_LAST_FRAGMENT;
1407
1408 DPRINTFN(5, ("sending tx hdr (%u, %u, %u, %u, )\n",
1409 shdr->hdr->type, shdr->hdr->subtype, shdr->hdr->encrypted,
1410 shdr->hdr->encrypt));
1411 DPRINTFN(5, ("%s->", ether_sprintf(shdr->hdr->src_addr)));
1412 DPRINTFN(5, ("%s\n", ether_sprintf(shdr->hdr->dst_addr)));
1413
1414 bus_dmamap_sync(sc->sc_dmat, sc->tbd_map,
1415 sc->txcur * sizeof (struct ipw_bd),
1416 sizeof (struct ipw_bd), BUS_DMASYNC_PREWRITE);
1417
1418 sc->txfree--;
1419 sc->txcur = (sc->txcur + 1) % IPW_NTBD;
1420
1421 sbuf->m = m0;
1422 sbuf->ni = ni;
1423
1424 for (i = 0; i < sbuf->map->dm_nsegs; i++) {
1425 sbd = &sc->stbd_list[sc->txcur];
1426
1427 sbd->bd->physaddr = htole32(sbuf->map->dm_segs[i].ds_addr);
1428 sbd->bd->len = htole32(sbuf->map->dm_segs[i].ds_len);
1429 sbd->bd->nfrag = 0;
1430 sbd->bd->flags = IPW_BD_FLAG_TX_FRAME_802_3;
1431 if (i == sbuf->map->dm_nsegs - 1) {
1432 sbd->type = IPW_SBD_TYPE_DATA;
1433 sbd->priv = sbuf;
1434 sbd->bd->flags |= IPW_BD_FLAG_TX_LAST_FRAGMENT;
1435 } else {
1436 sbd->type = IPW_SBD_TYPE_NOASSOC;
1437 sbd->bd->flags |= IPW_BD_FLAG_TX_NOT_LAST_FRAGMENT;
1438 }
1439
1440 DPRINTFN(5, ("sending fragment (%d, %d)\n", i,
1441 (int)sbuf->map->dm_segs[i].ds_len));
1442
1443 bus_dmamap_sync(sc->sc_dmat, sc->tbd_map,
1444 sc->txcur * sizeof (struct ipw_bd),
1445 sizeof (struct ipw_bd), BUS_DMASYNC_PREWRITE);
1446
1447 sc->txfree--;
1448 sc->txcur = (sc->txcur + 1) % IPW_NTBD;
1449 }
1450
1451 bus_dmamap_sync(sc->sc_dmat, sc->hdr_map, shdr->offset,
1452 sizeof (struct ipw_hdr), BUS_DMASYNC_PREWRITE);
1453
1454 bus_dmamap_sync(sc->sc_dmat, sbuf->map, 0, MCLBYTES,
1455 BUS_DMASYNC_PREWRITE);
1456
1457 /* Inform firmware about this new packet */
1458 CSR_WRITE_4(sc, IPW_CSR_TX_WRITE, sc->txcur);
1459
1460 return 0;
1461 }
1462
1463 static void
ipw_start(struct ifnet * ifp)1464 ipw_start(struct ifnet *ifp)
1465 {
1466 struct ipw_softc *sc = ifp->if_softc;
1467 struct ieee80211com *ic = &sc->sc_ic;
1468 struct mbuf *m0;
1469 struct ether_header *eh;
1470 struct ieee80211_node *ni;
1471
1472
1473 if (ic->ic_state != IEEE80211_S_RUN)
1474 return;
1475
1476 for (;;) {
1477 IF_DEQUEUE(&ifp->if_snd, m0);
1478 if (m0 == NULL)
1479 break;
1480
1481 if (sc->txfree < 1 + IPW_MAX_NSEG) {
1482 IF_PREPEND(&ifp->if_snd, m0);
1483 ifp->if_flags |= IFF_OACTIVE;
1484 break;
1485 }
1486
1487 if (m0->m_len < sizeof (struct ether_header) &&
1488 (m0 = m_pullup(m0, sizeof (struct ether_header))) == NULL)
1489 continue;
1490
1491 eh = mtod(m0, struct ether_header *);
1492 ni = ieee80211_find_txnode(ic, eh->ether_dhost);
1493 if (ni == NULL) {
1494 m_freem(m0);
1495 continue;
1496 }
1497
1498 bpf_mtap(ifp, m0);
1499
1500 m0 = ieee80211_encap(ic, m0, ni);
1501 if (m0 == NULL) {
1502 ieee80211_free_node(ni);
1503 continue;
1504 }
1505
1506 bpf_mtap3(ic->ic_rawbpf, m0);
1507
1508 if (ipw_tx_start(ifp, m0, ni) != 0) {
1509 ieee80211_free_node(ni);
1510 ifp->if_oerrors++;
1511 break;
1512 }
1513
1514 /* start watchdog timer */
1515 sc->sc_tx_timer = 5;
1516 ifp->if_timer = 1;
1517 }
1518 }
1519
1520 static void
ipw_watchdog(struct ifnet * ifp)1521 ipw_watchdog(struct ifnet *ifp)
1522 {
1523 struct ipw_softc *sc = ifp->if_softc;
1524
1525 ifp->if_timer = 0;
1526
1527 if (sc->sc_tx_timer > 0) {
1528 if (--sc->sc_tx_timer == 0) {
1529 aprint_error_dev(sc->sc_dev, "device timeout\n");
1530 ifp->if_oerrors++;
1531 ifp->if_flags &= ~IFF_UP;
1532 ipw_stop(ifp, 1);
1533 return;
1534 }
1535 ifp->if_timer = 1;
1536 }
1537
1538 ieee80211_watchdog(&sc->sc_ic);
1539 }
1540
1541 static int
ipw_get_table1(struct ipw_softc * sc,uint32_t * tbl)1542 ipw_get_table1(struct ipw_softc *sc, uint32_t *tbl)
1543 {
1544 uint32_t addr, size, data, i;
1545 int error;
1546
1547 if (!(sc->flags & IPW_FLAG_FW_INITED))
1548 return ENOTTY;
1549
1550 CSR_WRITE_4(sc, IPW_CSR_AUTOINC_ADDR, sc->table1_base);
1551
1552 size = CSR_READ_4(sc, IPW_CSR_AUTOINC_DATA);
1553 if ((error = copyout(&size, tbl, sizeof(size))) != 0)
1554 return error;
1555
1556 for (i = 1, ++tbl; i < size; i++, tbl++) {
1557 addr = CSR_READ_4(sc, IPW_CSR_AUTOINC_DATA);
1558 data = MEM_READ_4(sc, addr);
1559 if ((error = copyout(&data, tbl, sizeof(data))) != 0)
1560 return error;
1561 }
1562 return 0;
1563 }
1564
1565 static int
ipw_get_radio(struct ipw_softc * sc,int * ret)1566 ipw_get_radio(struct ipw_softc *sc, int *ret)
1567 {
1568 uint32_t addr, data;
1569
1570 if (!(sc->flags & IPW_FLAG_FW_INITED))
1571 return ENOTTY;
1572
1573 addr = ipw_read_table1(sc, IPW_INFO_EEPROM_ADDRESS);
1574 if ((MEM_READ_4(sc, addr + 32) >> 24) & 1)
1575 data = -1;
1576 else if (CSR_READ_4(sc, IPW_CSR_IO) & IPW_IO_RADIO_DISABLED)
1577 data = 0;
1578 else
1579 data = 1;
1580
1581 return copyout(&data, ret, sizeof(data));
1582 }
1583
1584 static int
ipw_ioctl(struct ifnet * ifp,u_long cmd,void * data)1585 ipw_ioctl(struct ifnet *ifp, u_long cmd, void *data)
1586 {
1587 #define IS_RUNNING(ifp) \
1588 ((ifp->if_flags & IFF_UP) && (ifp->if_flags & IFF_RUNNING))
1589
1590 struct ipw_softc *sc = ifp->if_softc;
1591 struct ieee80211com *ic = &sc->sc_ic;
1592 struct ifreq *ifr = (struct ifreq *)data;
1593 int s, error = 0;
1594
1595 s = splnet();
1596
1597 switch (cmd) {
1598 case SIOCSIFFLAGS:
1599 if ((error = ifioctl_common(ifp, cmd, data)) != 0)
1600 break;
1601 if (ifp->if_flags & IFF_UP) {
1602 if (!(ifp->if_flags & IFF_RUNNING))
1603 ipw_init(ifp);
1604 } else {
1605 if (ifp->if_flags & IFF_RUNNING)
1606 ipw_stop(ifp, 1);
1607 }
1608 break;
1609
1610 case SIOCADDMULTI:
1611 case SIOCDELMULTI:
1612 /* XXX no h/w multicast filter? --dyoung */
1613 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) {
1614 /* setup multicast filter, etc */
1615 error = 0;
1616 }
1617 break;
1618
1619 case SIOCGTABLE1:
1620 error = ipw_get_table1(sc, (uint32_t *)ifr->ifr_data);
1621 break;
1622
1623 case SIOCGRADIO:
1624 error = ipw_get_radio(sc, (int *)ifr->ifr_data);
1625 break;
1626
1627 case SIOCSIFMEDIA:
1628 if (ifr->ifr_media & IFM_IEEE80211_ADHOC)
1629 sc->sc_fwname = "ipw2100-1.2-i.fw";
1630 else if (ifr->ifr_media & IFM_IEEE80211_MONITOR)
1631 sc->sc_fwname = "ipw2100-1.2-p.fw";
1632 else
1633 sc->sc_fwname = "ipw2100-1.2.fw";
1634
1635 ipw_free_firmware(sc);
1636 /* FALLTRHOUGH */
1637 default:
1638 error = ieee80211_ioctl(&sc->sc_ic, cmd, data);
1639 if (error != ENETRESET)
1640 break;
1641
1642 if (error == ENETRESET) {
1643 if (IS_RUNNING(ifp) &&
1644 (ic->ic_roaming != IEEE80211_ROAMING_MANUAL))
1645 ipw_init(ifp);
1646 error = 0;
1647 }
1648
1649 }
1650
1651 splx(s);
1652 return error;
1653 #undef IS_RUNNING
1654 }
1655
1656 static uint32_t
ipw_read_table1(struct ipw_softc * sc,uint32_t off)1657 ipw_read_table1(struct ipw_softc *sc, uint32_t off)
1658 {
1659 return MEM_READ_4(sc, MEM_READ_4(sc, sc->table1_base + off));
1660 }
1661
1662 static void
ipw_write_table1(struct ipw_softc * sc,uint32_t off,uint32_t info)1663 ipw_write_table1(struct ipw_softc *sc, uint32_t off, uint32_t info)
1664 {
1665 MEM_WRITE_4(sc, MEM_READ_4(sc, sc->table1_base + off), info);
1666 }
1667
1668 static int
ipw_read_table2(struct ipw_softc * sc,uint32_t off,void * buf,uint32_t * len)1669 ipw_read_table2(struct ipw_softc *sc, uint32_t off, void *buf, uint32_t *len)
1670 {
1671 uint32_t addr, info;
1672 uint16_t count, size;
1673 uint32_t total;
1674
1675 /* addr[4] + count[2] + size[2] */
1676 addr = MEM_READ_4(sc, sc->table2_base + off);
1677 info = MEM_READ_4(sc, sc->table2_base + off + 4);
1678
1679 count = info >> 16;
1680 size = info & 0xffff;
1681 total = count * size;
1682
1683 if (total > *len) {
1684 *len = total;
1685 return EINVAL;
1686 }
1687
1688 *len = total;
1689 ipw_read_mem_1(sc, addr, buf, total);
1690
1691 return 0;
1692 }
1693
1694 static void
ipw_stop_master(struct ipw_softc * sc)1695 ipw_stop_master(struct ipw_softc *sc)
1696 {
1697 int ntries;
1698
1699 /* disable interrupts */
1700 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, 0);
1701
1702 CSR_WRITE_4(sc, IPW_CSR_RST, IPW_RST_STOP_MASTER);
1703 for (ntries = 0; ntries < 50; ntries++) {
1704 if (CSR_READ_4(sc, IPW_CSR_RST) & IPW_RST_MASTER_DISABLED)
1705 break;
1706 DELAY(10);
1707 }
1708 if (ntries == 50)
1709 aprint_error_dev(sc->sc_dev, "timeout waiting for master\n");
1710
1711 CSR_WRITE_4(sc, IPW_CSR_RST, CSR_READ_4(sc, IPW_CSR_RST) |
1712 IPW_RST_PRINCETON_RESET);
1713
1714 sc->flags &= ~IPW_FLAG_FW_INITED;
1715 }
1716
1717 static int
ipw_reset(struct ipw_softc * sc)1718 ipw_reset(struct ipw_softc *sc)
1719 {
1720 int ntries;
1721
1722 ipw_stop_master(sc);
1723
1724 /* move adapter to D0 state */
1725 CSR_WRITE_4(sc, IPW_CSR_CTL, CSR_READ_4(sc, IPW_CSR_CTL) |
1726 IPW_CTL_INIT);
1727
1728 /* wait for clock stabilization */
1729 for (ntries = 0; ntries < 1000; ntries++) {
1730 if (CSR_READ_4(sc, IPW_CSR_CTL) & IPW_CTL_CLOCK_READY)
1731 break;
1732 DELAY(200);
1733 }
1734 if (ntries == 1000)
1735 return EIO;
1736
1737 CSR_WRITE_4(sc, IPW_CSR_RST, CSR_READ_4(sc, IPW_CSR_RST) |
1738 IPW_RST_SW_RESET);
1739
1740 DELAY(10);
1741
1742 CSR_WRITE_4(sc, IPW_CSR_CTL, CSR_READ_4(sc, IPW_CSR_CTL) |
1743 IPW_CTL_INIT);
1744
1745 return 0;
1746 }
1747
1748 /*
1749 * Upload the microcode to the device.
1750 */
1751 static int
ipw_load_ucode(struct ipw_softc * sc,u_char * uc,int size)1752 ipw_load_ucode(struct ipw_softc *sc, u_char *uc, int size)
1753 {
1754 int ntries;
1755
1756 MEM_WRITE_4(sc, 0x3000e0, 0x80000000);
1757 CSR_WRITE_4(sc, IPW_CSR_RST, 0);
1758
1759 MEM_WRITE_2(sc, 0x220000, 0x0703);
1760 MEM_WRITE_2(sc, 0x220000, 0x0707);
1761
1762 MEM_WRITE_1(sc, 0x210014, 0x72);
1763 MEM_WRITE_1(sc, 0x210014, 0x72);
1764
1765 MEM_WRITE_1(sc, 0x210000, 0x40);
1766 MEM_WRITE_1(sc, 0x210000, 0x00);
1767 MEM_WRITE_1(sc, 0x210000, 0x40);
1768
1769 MEM_WRITE_MULTI_1(sc, 0x210010, uc, size);
1770
1771 MEM_WRITE_1(sc, 0x210000, 0x00);
1772 MEM_WRITE_1(sc, 0x210000, 0x00);
1773 MEM_WRITE_1(sc, 0x210000, 0x80);
1774
1775 MEM_WRITE_2(sc, 0x220000, 0x0703);
1776 MEM_WRITE_2(sc, 0x220000, 0x0707);
1777
1778 MEM_WRITE_1(sc, 0x210014, 0x72);
1779 MEM_WRITE_1(sc, 0x210014, 0x72);
1780
1781 MEM_WRITE_1(sc, 0x210000, 0x00);
1782 MEM_WRITE_1(sc, 0x210000, 0x80);
1783
1784 for (ntries = 0; ntries < 10; ntries++) {
1785 if (MEM_READ_1(sc, 0x210000) & 1)
1786 break;
1787 DELAY(10);
1788 }
1789 if (ntries == 10) {
1790 aprint_error_dev(sc->sc_dev, "timeout waiting for ucode to initialize\n");
1791 return EIO;
1792 }
1793
1794 MEM_WRITE_4(sc, 0x3000e0, 0);
1795
1796 return 0;
1797 }
1798
1799 /* set of macros to handle unaligned little endian data in firmware image */
1800 #define GETLE32(p) ((p)[0] | (p)[1] << 8 | (p)[2] << 16 | (p)[3] << 24)
1801 #define GETLE16(p) ((p)[0] | (p)[1] << 8)
1802 static int
ipw_load_firmware(struct ipw_softc * sc,u_char * fw,int size)1803 ipw_load_firmware(struct ipw_softc *sc, u_char *fw, int size)
1804 {
1805 u_char *p, *end;
1806 uint32_t dst;
1807 uint16_t len;
1808 int error;
1809
1810 p = fw;
1811 end = fw + size;
1812 while (p < end) {
1813 dst = GETLE32(p); p += 4;
1814 len = GETLE16(p); p += 2;
1815
1816 ipw_write_mem_1(sc, dst, p, len);
1817 p += len;
1818 }
1819
1820 CSR_WRITE_4(sc, IPW_CSR_IO, IPW_IO_GPIO1_ENABLE | IPW_IO_GPIO3_MASK |
1821 IPW_IO_LED_OFF);
1822
1823 /* enable interrupts */
1824 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, IPW_INTR_MASK);
1825
1826 /* kick the firmware */
1827 CSR_WRITE_4(sc, IPW_CSR_RST, 0);
1828
1829 CSR_WRITE_4(sc, IPW_CSR_CTL, CSR_READ_4(sc, IPW_CSR_CTL) |
1830 IPW_CTL_ALLOW_STANDBY);
1831
1832 /* wait at most one second for firmware initialization to complete */
1833 if ((error = tsleep(sc, 0, "ipwinit", hz)) != 0) {
1834 aprint_error_dev(sc->sc_dev, "timeout waiting for firmware initialization "
1835 "to complete\n");
1836 return error;
1837 }
1838
1839 CSR_WRITE_4(sc, IPW_CSR_IO, CSR_READ_4(sc, IPW_CSR_IO) |
1840 IPW_IO_GPIO1_MASK | IPW_IO_GPIO3_MASK);
1841
1842 return 0;
1843 }
1844
1845 /*
1846 * Store firmware into kernel memory so we can download it when we need to,
1847 * e.g when the adapter wakes up from suspend mode.
1848 */
1849 static int
ipw_cache_firmware(struct ipw_softc * sc)1850 ipw_cache_firmware(struct ipw_softc *sc)
1851 {
1852 struct ipw_firmware *fw = &sc->fw;
1853 struct ipw_firmware_hdr hdr;
1854 firmware_handle_t fwh;
1855 off_t fwsz, p;
1856 int error;
1857
1858 ipw_free_firmware(sc);
1859
1860 if (ipw_accept_eula == 0) {
1861 aprint_error_dev(sc->sc_dev,
1862 "EULA not accepted; please see the ipw(4) man page.\n");
1863 return EPERM;
1864 }
1865
1866 if ((error = firmware_open("if_ipw", sc->sc_fwname, &fwh)) != 0)
1867 goto fail0;
1868
1869 fwsz = firmware_get_size(fwh);
1870
1871 if (fwsz < sizeof(hdr))
1872 goto fail2;
1873
1874 if ((error = firmware_read(fwh, 0, &hdr, sizeof(hdr))) != 0)
1875 goto fail2;
1876
1877 fw->main_size = le32toh(hdr.main_size);
1878 fw->ucode_size = le32toh(hdr.ucode_size);
1879
1880 fw->main = firmware_malloc(fw->main_size);
1881 if (fw->main == NULL) {
1882 error = ENOMEM;
1883 goto fail1;
1884 }
1885
1886 fw->ucode = firmware_malloc(fw->ucode_size);
1887 if (fw->ucode == NULL) {
1888 error = ENOMEM;
1889 goto fail2;
1890 }
1891
1892 p = sizeof(hdr);
1893 if ((error = firmware_read(fwh, p, fw->main, fw->main_size)) != 0)
1894 goto fail3;
1895
1896 p += fw->main_size;
1897 if ((error = firmware_read(fwh, p, fw->ucode, fw->ucode_size)) != 0)
1898 goto fail3;
1899
1900 DPRINTF(("Firmware cached: main %u, ucode %u\n", fw->main_size,
1901 fw->ucode_size));
1902
1903 sc->flags |= IPW_FLAG_FW_CACHED;
1904
1905 firmware_close(fwh);
1906
1907 return 0;
1908
1909 fail3: firmware_free(fw->ucode, fw->ucode_size);
1910 fail2: firmware_free(fw->main, fw->main_size);
1911 fail1: firmware_close(fwh);
1912 fail0:
1913 return error;
1914 }
1915
1916 static void
ipw_free_firmware(struct ipw_softc * sc)1917 ipw_free_firmware(struct ipw_softc *sc)
1918 {
1919 if (!(sc->flags & IPW_FLAG_FW_CACHED))
1920 return;
1921
1922 firmware_free(sc->fw.main, sc->fw.main_size);
1923 firmware_free(sc->fw.ucode, sc->fw.ucode_size);
1924
1925 sc->flags &= ~IPW_FLAG_FW_CACHED;
1926 }
1927
1928 static int
ipw_config(struct ipw_softc * sc)1929 ipw_config(struct ipw_softc *sc)
1930 {
1931 struct ieee80211com *ic = &sc->sc_ic;
1932 struct ifnet *ifp = &sc->sc_if;
1933 struct ipw_security security;
1934 struct ieee80211_key *k;
1935 struct ipw_wep_key wepkey;
1936 struct ipw_scan_options options;
1937 struct ipw_configuration config;
1938 uint32_t data;
1939 int error, i;
1940
1941 switch (ic->ic_opmode) {
1942 case IEEE80211_M_STA:
1943 case IEEE80211_M_HOSTAP:
1944 data = htole32(IPW_MODE_BSS);
1945 break;
1946
1947 case IEEE80211_M_IBSS:
1948 case IEEE80211_M_AHDEMO:
1949 data = htole32(IPW_MODE_IBSS);
1950 break;
1951
1952 case IEEE80211_M_MONITOR:
1953 data = htole32(IPW_MODE_MONITOR);
1954 break;
1955 }
1956 DPRINTF(("Setting mode to %u\n", le32toh(data)));
1957 error = ipw_cmd(sc, IPW_CMD_SET_MODE, &data, sizeof data);
1958 if (error != 0)
1959 return error;
1960
1961 if (ic->ic_opmode == IEEE80211_M_IBSS ||
1962 ic->ic_opmode == IEEE80211_M_MONITOR) {
1963 data = htole32(ieee80211_chan2ieee(ic, ic->ic_ibss_chan));
1964 DPRINTF(("Setting channel to %u\n", le32toh(data)));
1965 error = ipw_cmd(sc, IPW_CMD_SET_CHANNEL, &data, sizeof data);
1966 if (error != 0)
1967 return error;
1968 }
1969
1970 if (ic->ic_opmode == IEEE80211_M_MONITOR) {
1971 DPRINTF(("Enabling adapter\n"));
1972 return ipw_cmd(sc, IPW_CMD_ENABLE, NULL, 0);
1973 }
1974
1975 DPRINTF(("Setting MAC to %s\n", ether_sprintf(ic->ic_myaddr)));
1976 error = ipw_cmd(sc, IPW_CMD_SET_MAC_ADDRESS, ic->ic_myaddr,
1977 IEEE80211_ADDR_LEN);
1978 if (error != 0)
1979 return error;
1980
1981 config.flags = htole32(IPW_CFG_BSS_MASK | IPW_CFG_IBSS_MASK |
1982 IPW_CFG_PREAMBLE_AUTO | IPW_CFG_802_1x_ENABLE);
1983
1984 if (ic->ic_opmode == IEEE80211_M_IBSS)
1985 config.flags |= htole32(IPW_CFG_IBSS_AUTO_START);
1986 if (ifp->if_flags & IFF_PROMISC)
1987 config.flags |= htole32(IPW_CFG_PROMISCUOUS);
1988 config.bss_chan = htole32(0x3fff); /* channels 1-14 */
1989 config.ibss_chan = htole32(0x7ff); /* channels 1-11 */
1990 DPRINTF(("Setting adapter configuration 0x%08x\n", config.flags));
1991 error = ipw_cmd(sc, IPW_CMD_SET_CONFIGURATION, &config, sizeof config);
1992 if (error != 0)
1993 return error;
1994
1995 data = htole32(0x3); /* 1, 2 */
1996 DPRINTF(("Setting basic tx rates to 0x%x\n", le32toh(data)));
1997 error = ipw_cmd(sc, IPW_CMD_SET_BASIC_TX_RATES, &data, sizeof data);
1998 if (error != 0)
1999 return error;
2000
2001 data = htole32(0xf); /* 1, 2, 5.5, 11 */
2002 DPRINTF(("Setting tx rates to 0x%x\n", le32toh(data)));
2003 error = ipw_cmd(sc, IPW_CMD_SET_TX_RATES, &data, sizeof data);
2004 if (error != 0)
2005 return error;
2006
2007 data = htole32(IPW_POWER_MODE_CAM);
2008 DPRINTF(("Setting power mode to %u\n", le32toh(data)));
2009 error = ipw_cmd(sc, IPW_CMD_SET_POWER_MODE, &data, sizeof data);
2010 if (error != 0)
2011 return error;
2012
2013 if (ic->ic_opmode == IEEE80211_M_IBSS) {
2014 data = htole32(32); /* default value */
2015 DPRINTF(("Setting tx power index to %u\n", le32toh(data)));
2016 error = ipw_cmd(sc, IPW_CMD_SET_TX_POWER_INDEX, &data,
2017 sizeof data);
2018 if (error != 0)
2019 return error;
2020 }
2021
2022 data = htole32(ic->ic_rtsthreshold);
2023 DPRINTF(("Setting RTS threshold to %u\n", le32toh(data)));
2024 error = ipw_cmd(sc, IPW_CMD_SET_RTS_THRESHOLD, &data, sizeof data);
2025 if (error != 0)
2026 return error;
2027
2028 data = htole32(ic->ic_fragthreshold);
2029 DPRINTF(("Setting frag threshold to %u\n", le32toh(data)));
2030 error = ipw_cmd(sc, IPW_CMD_SET_FRAG_THRESHOLD, &data, sizeof data);
2031 if (error != 0)
2032 return error;
2033
2034 #ifdef IPW_DEBUG
2035 if (ipw_debug > 0) {
2036 printf("Setting ESSID to ");
2037 ieee80211_print_essid(ic->ic_des_essid, ic->ic_des_esslen);
2038 printf("\n");
2039 }
2040 #endif
2041 error = ipw_cmd(sc, IPW_CMD_SET_ESSID, ic->ic_des_essid,
2042 ic->ic_des_esslen);
2043 if (error != 0)
2044 return error;
2045
2046 /* no mandatory BSSID */
2047 DPRINTF(("Setting mandatory BSSID to null\n"));
2048 error = ipw_cmd(sc, IPW_CMD_SET_MANDATORY_BSSID, NULL, 0);
2049 if (error != 0)
2050 return error;
2051
2052 if (ic->ic_flags & IEEE80211_F_DESBSSID) {
2053 DPRINTF(("Setting desired BSSID to %s\n",
2054 ether_sprintf(ic->ic_des_bssid)));
2055 error = ipw_cmd(sc, IPW_CMD_SET_DESIRED_BSSID,
2056 ic->ic_des_bssid, IEEE80211_ADDR_LEN);
2057 if (error != 0)
2058 return error;
2059 }
2060
2061 (void)memset(&security, 0, sizeof(security));
2062 security.authmode = (ic->ic_bss->ni_authmode == IEEE80211_AUTH_SHARED) ?
2063 IPW_AUTH_SHARED : IPW_AUTH_OPEN;
2064 security.ciphers = htole32(IPW_CIPHER_NONE);
2065 DPRINTF(("Setting authmode to %u\n", security.authmode));
2066 error = ipw_cmd(sc, IPW_CMD_SET_SECURITY_INFORMATION, &security,
2067 sizeof security);
2068 if (error != 0)
2069 return error;
2070
2071 if (ic->ic_flags & IEEE80211_F_PRIVACY) {
2072 k = ic->ic_crypto.cs_nw_keys;
2073 for (i = 0; i < IEEE80211_WEP_NKID; i++, k++) {
2074 if (k->wk_keylen == 0)
2075 continue;
2076
2077 wepkey.idx = i;
2078 wepkey.len = k->wk_keylen;
2079 memset(wepkey.key, 0, sizeof(wepkey.key));
2080 memcpy(wepkey.key, k->wk_key, k->wk_keylen);
2081 DPRINTF(("Setting wep key index %u len %u\n",
2082 wepkey.idx, wepkey.len));
2083 error = ipw_cmd(sc, IPW_CMD_SET_WEP_KEY, &wepkey,
2084 sizeof wepkey);
2085 if (error != 0)
2086 return error;
2087 }
2088
2089 data = htole32(ic->ic_crypto.cs_def_txkey);
2090 DPRINTF(("Setting tx key index to %u\n", le32toh(data)));
2091 error = ipw_cmd(sc, IPW_CMD_SET_WEP_KEY_INDEX, &data,
2092 sizeof data);
2093 if (error != 0)
2094 return error;
2095 }
2096
2097 data = htole32((sc->sc_ic.ic_flags & IEEE80211_F_PRIVACY) ? IPW_WEPON : 0);
2098 DPRINTF(("Setting wep flags to 0x%x\n", le32toh(data)));
2099 error = ipw_cmd(sc, IPW_CMD_SET_WEP_FLAGS, &data, sizeof data);
2100 if (error != 0)
2101 return error;
2102
2103 #if 0
2104 struct ipw_wpa_ie ie;
2105
2106 memset(&ie, 0 sizeof(ie));
2107 ie.len = htole32(sizeof (struct ieee80211_ie_wpa));
2108 DPRINTF(("Setting wpa ie\n"));
2109 error = ipw_cmd(sc, IPW_CMD_SET_WPA_IE, &ie, sizeof ie);
2110 if (error != 0)
2111 return error;
2112 #endif
2113
2114 if (ic->ic_opmode == IEEE80211_M_IBSS) {
2115 data = htole32(ic->ic_bintval);
2116 DPRINTF(("Setting beacon interval to %u\n", le32toh(data)));
2117 error = ipw_cmd(sc, IPW_CMD_SET_BEACON_INTERVAL, &data,
2118 sizeof data);
2119 if (error != 0)
2120 return error;
2121 }
2122
2123 options.flags = 0;
2124 options.channels = htole32(0x3fff); /* scan channels 1-14 */
2125 DPRINTF(("Setting scan options to 0x%x\n", le32toh(options.flags)));
2126 error = ipw_cmd(sc, IPW_CMD_SET_SCAN_OPTIONS, &options, sizeof options);
2127 if (error != 0)
2128 return error;
2129
2130 /* finally, enable adapter (start scanning for an access point) */
2131 DPRINTF(("Enabling adapter\n"));
2132 return ipw_cmd(sc, IPW_CMD_ENABLE, NULL, 0);
2133 }
2134
2135 static int
ipw_init(struct ifnet * ifp)2136 ipw_init(struct ifnet *ifp)
2137 {
2138 struct ipw_softc *sc = ifp->if_softc;
2139 struct ipw_firmware *fw = &sc->fw;
2140
2141 if (!(sc->flags & IPW_FLAG_FW_CACHED)) {
2142 if (ipw_cache_firmware(sc) != 0) {
2143 aprint_error_dev(sc->sc_dev, "could not cache the firmware (%s)\n",
2144 sc->sc_fwname);
2145 goto fail;
2146 }
2147 }
2148
2149 ipw_stop(ifp, 0);
2150
2151 if (ipw_reset(sc) != 0) {
2152 aprint_error_dev(sc->sc_dev, "could not reset adapter\n");
2153 goto fail;
2154 }
2155
2156 if (ipw_load_ucode(sc, fw->ucode, fw->ucode_size) != 0) {
2157 aprint_error_dev(sc->sc_dev, "could not load microcode\n");
2158 goto fail;
2159 }
2160
2161 ipw_stop_master(sc);
2162
2163 /*
2164 * Setup tx, rx and status rings.
2165 */
2166 sc->txold = IPW_NTBD - 1;
2167 sc->txcur = 0;
2168 sc->txfree = IPW_NTBD - 2;
2169 sc->rxcur = IPW_NRBD - 1;
2170
2171 CSR_WRITE_4(sc, IPW_CSR_TX_BASE, sc->tbd_map->dm_segs[0].ds_addr);
2172 CSR_WRITE_4(sc, IPW_CSR_TX_SIZE, IPW_NTBD);
2173 CSR_WRITE_4(sc, IPW_CSR_TX_READ, 0);
2174 CSR_WRITE_4(sc, IPW_CSR_TX_WRITE, sc->txcur);
2175
2176 CSR_WRITE_4(sc, IPW_CSR_RX_BASE, sc->rbd_map->dm_segs[0].ds_addr);
2177 CSR_WRITE_4(sc, IPW_CSR_RX_SIZE, IPW_NRBD);
2178 CSR_WRITE_4(sc, IPW_CSR_RX_READ, 0);
2179 CSR_WRITE_4(sc, IPW_CSR_RX_WRITE, sc->rxcur);
2180
2181 CSR_WRITE_4(sc, IPW_CSR_STATUS_BASE, sc->status_map->dm_segs[0].ds_addr);
2182
2183 if (ipw_load_firmware(sc, fw->main, fw->main_size) != 0) {
2184 aprint_error_dev(sc->sc_dev, "could not load firmware\n");
2185 goto fail;
2186 }
2187
2188 sc->flags |= IPW_FLAG_FW_INITED;
2189
2190 /* retrieve information tables base addresses */
2191 sc->table1_base = CSR_READ_4(sc, IPW_CSR_TABLE1_BASE);
2192 sc->table2_base = CSR_READ_4(sc, IPW_CSR_TABLE2_BASE);
2193
2194 ipw_write_table1(sc, IPW_INFO_LOCK, 0);
2195
2196 if (ipw_config(sc) != 0) {
2197 aprint_error_dev(sc->sc_dev, "device configuration failed\n");
2198 goto fail;
2199 }
2200
2201 ifp->if_flags &= ~IFF_OACTIVE;
2202 ifp->if_flags |= IFF_RUNNING;
2203
2204 return 0;
2205
2206 fail: ifp->if_flags &= ~IFF_UP;
2207 ipw_stop(ifp, 0);
2208
2209 return EIO;
2210 }
2211
2212 static void
ipw_stop(struct ifnet * ifp,int disable)2213 ipw_stop(struct ifnet *ifp, int disable)
2214 {
2215 struct ipw_softc *sc = ifp->if_softc;
2216 struct ieee80211com *ic = &sc->sc_ic;
2217 int i;
2218
2219 ipw_stop_master(sc);
2220
2221 CSR_WRITE_4(sc, IPW_CSR_RST, IPW_RST_SW_RESET);
2222
2223 /*
2224 * Release tx buffers.
2225 */
2226 for (i = 0; i < IPW_NTBD; i++)
2227 ipw_release_sbd(sc, &sc->stbd_list[i]);
2228
2229 sc->sc_tx_timer = 0;
2230 ifp->if_timer = 0;
2231 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
2232
2233 ieee80211_new_state(ic, IEEE80211_S_INIT, -1);
2234 }
2235
2236 static void
ipw_read_mem_1(struct ipw_softc * sc,bus_size_t offset,uint8_t * datap,bus_size_t count)2237 ipw_read_mem_1(struct ipw_softc *sc, bus_size_t offset, uint8_t *datap,
2238 bus_size_t count)
2239 {
2240 for (; count > 0; offset++, datap++, count--) {
2241 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, offset & ~3);
2242 *datap = CSR_READ_1(sc, IPW_CSR_INDIRECT_DATA + (offset & 3));
2243 }
2244 }
2245
2246 static void
ipw_write_mem_1(struct ipw_softc * sc,bus_size_t offset,uint8_t * datap,bus_size_t count)2247 ipw_write_mem_1(struct ipw_softc *sc, bus_size_t offset, uint8_t *datap,
2248 bus_size_t count)
2249 {
2250 for (; count > 0; offset++, datap++, count--) {
2251 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, offset & ~3);
2252 CSR_WRITE_1(sc, IPW_CSR_INDIRECT_DATA + (offset & 3), *datap);
2253 }
2254 }
2255
2256 SYSCTL_SETUP(sysctl_hw_ipw_accept_eula_setup, "sysctl hw.ipw.accept_eula")
2257 {
2258 const struct sysctlnode *rnode;
2259 const struct sysctlnode *cnode;
2260
2261 sysctl_createv(NULL, 0, NULL, &rnode,
2262 CTLFLAG_PERMANENT,
2263 CTLTYPE_NODE, "ipw",
2264 NULL,
2265 NULL, 0,
2266 NULL, 0,
2267 CTL_HW, CTL_CREATE, CTL_EOL);
2268
2269 sysctl_createv(NULL, 0, &rnode, &cnode,
2270 CTLFLAG_PERMANENT | CTLFLAG_READWRITE,
2271 CTLTYPE_INT, "accept_eula",
2272 SYSCTL_DESCR("Accept Intel EULA and permit use of ipw(4) firmware"),
2273 NULL, 0,
2274 &ipw_accept_eula, sizeof(ipw_accept_eula),
2275 CTL_CREATE, CTL_EOL);
2276 }
2277