1 /* $NetBSD: if_stge.c,v 1.60 2016/07/07 06:55:41 msaitoh Exp $ */
2
3 /*-
4 * Copyright (c) 2001 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Jason R. Thorpe.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 */
31
32 /*
33 * Device driver for the Sundance Tech. TC9021 10/100/1000
34 * Ethernet controller.
35 */
36
37 #include <sys/cdefs.h>
38 __KERNEL_RCSID(0, "$NetBSD: if_stge.c,v 1.60 2016/07/07 06:55:41 msaitoh Exp $");
39
40
41 #include <sys/param.h>
42 #include <sys/systm.h>
43 #include <sys/callout.h>
44 #include <sys/mbuf.h>
45 #include <sys/malloc.h>
46 #include <sys/kernel.h>
47 #include <sys/socket.h>
48 #include <sys/ioctl.h>
49 #include <sys/errno.h>
50 #include <sys/device.h>
51 #include <sys/queue.h>
52
53 #include <net/if.h>
54 #include <net/if_dl.h>
55 #include <net/if_media.h>
56 #include <net/if_ether.h>
57
58 #include <net/bpf.h>
59
60 #include <sys/bus.h>
61 #include <sys/intr.h>
62
63 #include <dev/mii/mii.h>
64 #include <dev/mii/miivar.h>
65 #include <dev/mii/mii_bitbang.h>
66
67 #include <dev/pci/pcireg.h>
68 #include <dev/pci/pcivar.h>
69 #include <dev/pci/pcidevs.h>
70
71 #include <dev/pci/if_stgereg.h>
72
73 #include <prop/proplib.h>
74
75 /* #define STGE_CU_BUG 1 */
76 #define STGE_VLAN_UNTAG 1
77 /* #define STGE_VLAN_CFI 1 */
78
79 /*
80 * Transmit descriptor list size.
81 */
82 #define STGE_NTXDESC 256
83 #define STGE_NTXDESC_MASK (STGE_NTXDESC - 1)
84 #define STGE_NEXTTX(x) (((x) + 1) & STGE_NTXDESC_MASK)
85
86 /*
87 * Receive descriptor list size.
88 */
89 #define STGE_NRXDESC 256
90 #define STGE_NRXDESC_MASK (STGE_NRXDESC - 1)
91 #define STGE_NEXTRX(x) (((x) + 1) & STGE_NRXDESC_MASK)
92
93 /*
94 * Only interrupt every N frames. Must be a power-of-two.
95 */
96 #define STGE_TXINTR_SPACING 16
97 #define STGE_TXINTR_SPACING_MASK (STGE_TXINTR_SPACING - 1)
98
99 /*
100 * Control structures are DMA'd to the TC9021 chip. We allocate them in
101 * a single clump that maps to a single DMA segment to make several things
102 * easier.
103 */
104 struct stge_control_data {
105 /*
106 * The transmit descriptors.
107 */
108 struct stge_tfd scd_txdescs[STGE_NTXDESC];
109
110 /*
111 * The receive descriptors.
112 */
113 struct stge_rfd scd_rxdescs[STGE_NRXDESC];
114 };
115
116 #define STGE_CDOFF(x) offsetof(struct stge_control_data, x)
117 #define STGE_CDTXOFF(x) STGE_CDOFF(scd_txdescs[(x)])
118 #define STGE_CDRXOFF(x) STGE_CDOFF(scd_rxdescs[(x)])
119
120 /*
121 * Software state for transmit and receive jobs.
122 */
123 struct stge_descsoft {
124 struct mbuf *ds_mbuf; /* head of our mbuf chain */
125 bus_dmamap_t ds_dmamap; /* our DMA map */
126 };
127
128 /*
129 * Software state per device.
130 */
131 struct stge_softc {
132 device_t sc_dev; /* generic device information */
133 bus_space_tag_t sc_st; /* bus space tag */
134 bus_space_handle_t sc_sh; /* bus space handle */
135 bus_dma_tag_t sc_dmat; /* bus DMA tag */
136 struct ethercom sc_ethercom; /* ethernet common data */
137 int sc_rev; /* silicon revision */
138
139 void *sc_ih; /* interrupt cookie */
140
141 struct mii_data sc_mii; /* MII/media information */
142
143 callout_t sc_tick_ch; /* tick callout */
144
145 bus_dmamap_t sc_cddmamap; /* control data DMA map */
146 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr
147
148 /*
149 * Software state for transmit and receive descriptors.
150 */
151 struct stge_descsoft sc_txsoft[STGE_NTXDESC];
152 struct stge_descsoft sc_rxsoft[STGE_NRXDESC];
153
154 /*
155 * Control data structures.
156 */
157 struct stge_control_data *sc_control_data;
158 #define sc_txdescs sc_control_data->scd_txdescs
159 #define sc_rxdescs sc_control_data->scd_rxdescs
160
161 #ifdef STGE_EVENT_COUNTERS
162 /*
163 * Event counters.
164 */
165 struct evcnt sc_ev_txstall; /* Tx stalled */
166 struct evcnt sc_ev_txdmaintr; /* Tx DMA interrupts */
167 struct evcnt sc_ev_txindintr; /* Tx Indicate interrupts */
168 struct evcnt sc_ev_rxintr; /* Rx interrupts */
169
170 struct evcnt sc_ev_txseg1; /* Tx packets w/ 1 segment */
171 struct evcnt sc_ev_txseg2; /* Tx packets w/ 2 segments */
172 struct evcnt sc_ev_txseg3; /* Tx packets w/ 3 segments */
173 struct evcnt sc_ev_txseg4; /* Tx packets w/ 4 segments */
174 struct evcnt sc_ev_txseg5; /* Tx packets w/ 5 segments */
175 struct evcnt sc_ev_txsegmore; /* Tx packets w/ more than 5 segments */
176 struct evcnt sc_ev_txcopy; /* Tx packets that we had to copy */
177
178 struct evcnt sc_ev_rxipsum; /* IP checksums checked in-bound */
179 struct evcnt sc_ev_rxtcpsum; /* TCP checksums checked in-bound */
180 struct evcnt sc_ev_rxudpsum; /* UDP checksums checked in-bound */
181
182 struct evcnt sc_ev_txipsum; /* IP checksums comp. out-bound */
183 struct evcnt sc_ev_txtcpsum; /* TCP checksums comp. out-bound */
184 struct evcnt sc_ev_txudpsum; /* UDP checksums comp. out-bound */
185 #endif /* STGE_EVENT_COUNTERS */
186
187 int sc_txpending; /* number of Tx requests pending */
188 int sc_txdirty; /* first dirty Tx descriptor */
189 int sc_txlast; /* last used Tx descriptor */
190
191 int sc_rxptr; /* next ready Rx descriptor/descsoft */
192 int sc_rxdiscard;
193 int sc_rxlen;
194 struct mbuf *sc_rxhead;
195 struct mbuf *sc_rxtail;
196 struct mbuf **sc_rxtailp;
197
198 int sc_txthresh; /* Tx threshold */
199 uint32_t sc_usefiber:1; /* if we're fiber */
200 uint32_t sc_stge1023:1; /* are we a 1023 */
201 uint32_t sc_DMACtrl; /* prototype DMACtrl register */
202 uint32_t sc_MACCtrl; /* prototype MacCtrl register */
203 uint16_t sc_IntEnable; /* prototype IntEnable register */
204 uint16_t sc_ReceiveMode; /* prototype ReceiveMode register */
205 uint8_t sc_PhyCtrl; /* prototype PhyCtrl register */
206 };
207
208 #define STGE_RXCHAIN_RESET(sc) \
209 do { \
210 (sc)->sc_rxtailp = &(sc)->sc_rxhead; \
211 *(sc)->sc_rxtailp = NULL; \
212 (sc)->sc_rxlen = 0; \
213 } while (/*CONSTCOND*/0)
214
215 #define STGE_RXCHAIN_LINK(sc, m) \
216 do { \
217 *(sc)->sc_rxtailp = (sc)->sc_rxtail = (m); \
218 (sc)->sc_rxtailp = &(m)->m_next; \
219 } while (/*CONSTCOND*/0)
220
221 #ifdef STGE_EVENT_COUNTERS
222 #define STGE_EVCNT_INCR(ev) (ev)->ev_count++
223 #else
224 #define STGE_EVCNT_INCR(ev) /* nothing */
225 #endif
226
227 #define STGE_CDTXADDR(sc, x) ((sc)->sc_cddma + STGE_CDTXOFF((x)))
228 #define STGE_CDRXADDR(sc, x) ((sc)->sc_cddma + STGE_CDRXOFF((x)))
229
230 #define STGE_CDTXSYNC(sc, x, ops) \
231 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \
232 STGE_CDTXOFF((x)), sizeof(struct stge_tfd), (ops))
233
234 #define STGE_CDRXSYNC(sc, x, ops) \
235 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \
236 STGE_CDRXOFF((x)), sizeof(struct stge_rfd), (ops))
237
238 #define STGE_INIT_RXDESC(sc, x) \
239 do { \
240 struct stge_descsoft *__ds = &(sc)->sc_rxsoft[(x)]; \
241 struct stge_rfd *__rfd = &(sc)->sc_rxdescs[(x)]; \
242 \
243 /* \
244 * Note: We scoot the packet forward 2 bytes in the buffer \
245 * so that the payload after the Ethernet header is aligned \
246 * to a 4-byte boundary. \
247 */ \
248 __rfd->rfd_frag.frag_word0 = \
249 htole64(FRAG_ADDR(__ds->ds_dmamap->dm_segs[0].ds_addr + 2) |\
250 FRAG_LEN(MCLBYTES - 2)); \
251 __rfd->rfd_next = \
252 htole64((uint64_t)STGE_CDRXADDR((sc), STGE_NEXTRX((x)))); \
253 __rfd->rfd_status = 0; \
254 STGE_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \
255 } while (/*CONSTCOND*/0)
256
257 #define STGE_TIMEOUT 1000
258
259 static void stge_start(struct ifnet *);
260 static void stge_watchdog(struct ifnet *);
261 static int stge_ioctl(struct ifnet *, u_long, void *);
262 static int stge_init(struct ifnet *);
263 static void stge_stop(struct ifnet *, int);
264
265 static bool stge_shutdown(device_t, int);
266
267 static void stge_reset(struct stge_softc *);
268 static void stge_rxdrain(struct stge_softc *);
269 static int stge_add_rxbuf(struct stge_softc *, int);
270 static void stge_read_eeprom(struct stge_softc *, int, uint16_t *);
271 static void stge_tick(void *);
272
273 static void stge_stats_update(struct stge_softc *);
274
275 static void stge_set_filter(struct stge_softc *);
276
277 static int stge_intr(void *);
278 static void stge_txintr(struct stge_softc *);
279 static void stge_rxintr(struct stge_softc *);
280
281 static int stge_mii_readreg(device_t, int, int);
282 static void stge_mii_writereg(device_t, int, int, int);
283 static void stge_mii_statchg(struct ifnet *);
284
285 static int stge_match(device_t, cfdata_t, void *);
286 static void stge_attach(device_t, device_t, void *);
287
288 int stge_copy_small = 0;
289
290 CFATTACH_DECL_NEW(stge, sizeof(struct stge_softc),
291 stge_match, stge_attach, NULL, NULL);
292
293 static uint32_t stge_mii_bitbang_read(device_t);
294 static void stge_mii_bitbang_write(device_t, uint32_t);
295
296 static const struct mii_bitbang_ops stge_mii_bitbang_ops = {
297 stge_mii_bitbang_read,
298 stge_mii_bitbang_write,
299 {
300 PC_MgmtData, /* MII_BIT_MDO */
301 PC_MgmtData, /* MII_BIT_MDI */
302 PC_MgmtClk, /* MII_BIT_MDC */
303 PC_MgmtDir, /* MII_BIT_DIR_HOST_PHY */
304 0, /* MII_BIT_DIR_PHY_HOST */
305 }
306 };
307
308 /*
309 * Devices supported by this driver.
310 */
311 static const struct stge_product {
312 pci_vendor_id_t stge_vendor;
313 pci_product_id_t stge_product;
314 const char *stge_name;
315 } stge_products[] = {
316 { PCI_VENDOR_SUNDANCETI, PCI_PRODUCT_SUNDANCETI_ST1023,
317 "Sundance ST-1023 Gigabit Ethernet" },
318
319 { PCI_VENDOR_SUNDANCETI, PCI_PRODUCT_SUNDANCETI_ST2021,
320 "Sundance ST-2021 Gigabit Ethernet" },
321
322 { PCI_VENDOR_TAMARACK, PCI_PRODUCT_TAMARACK_TC9021,
323 "Tamarack TC9021 Gigabit Ethernet" },
324
325 { PCI_VENDOR_TAMARACK, PCI_PRODUCT_TAMARACK_TC9021_ALT,
326 "Tamarack TC9021 Gigabit Ethernet" },
327
328 /*
329 * The Sundance sample boards use the Sundance vendor ID,
330 * but the Tamarack product ID.
331 */
332 { PCI_VENDOR_SUNDANCETI, PCI_PRODUCT_TAMARACK_TC9021,
333 "Sundance TC9021 Gigabit Ethernet" },
334
335 { PCI_VENDOR_SUNDANCETI, PCI_PRODUCT_TAMARACK_TC9021_ALT,
336 "Sundance TC9021 Gigabit Ethernet" },
337
338 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DL4000,
339 "D-Link DL-4000 Gigabit Ethernet" },
340
341 { PCI_VENDOR_ANTARES, PCI_PRODUCT_ANTARES_TC9021,
342 "Antares Gigabit Ethernet" },
343
344 { 0, 0,
345 NULL },
346 };
347
348 static const struct stge_product *
stge_lookup(const struct pci_attach_args * pa)349 stge_lookup(const struct pci_attach_args *pa)
350 {
351 const struct stge_product *sp;
352
353 for (sp = stge_products; sp->stge_name != NULL; sp++) {
354 if (PCI_VENDOR(pa->pa_id) == sp->stge_vendor &&
355 PCI_PRODUCT(pa->pa_id) == sp->stge_product)
356 return (sp);
357 }
358 return (NULL);
359 }
360
361 static int
stge_match(device_t parent,cfdata_t cf,void * aux)362 stge_match(device_t parent, cfdata_t cf, void *aux)
363 {
364 struct pci_attach_args *pa = aux;
365
366 if (stge_lookup(pa) != NULL)
367 return (1);
368
369 return (0);
370 }
371
372 static void
stge_attach(device_t parent,device_t self,void * aux)373 stge_attach(device_t parent, device_t self, void *aux)
374 {
375 struct stge_softc *sc = device_private(self);
376 struct pci_attach_args *pa = aux;
377 struct ifnet *ifp = &sc->sc_ethercom.ec_if;
378 pci_chipset_tag_t pc = pa->pa_pc;
379 pci_intr_handle_t ih;
380 const char *intrstr = NULL;
381 bus_space_tag_t iot, memt;
382 bus_space_handle_t ioh, memh;
383 bus_dma_segment_t seg;
384 prop_data_t data;
385 int ioh_valid, memh_valid;
386 int i, rseg, error;
387 const struct stge_product *sp;
388 uint8_t enaddr[ETHER_ADDR_LEN];
389 char intrbuf[PCI_INTRSTR_LEN];
390
391 callout_init(&sc->sc_tick_ch, 0);
392
393 sp = stge_lookup(pa);
394 if (sp == NULL) {
395 printf("\n");
396 panic("ste_attach: impossible");
397 }
398
399 sc->sc_rev = PCI_REVISION(pa->pa_class);
400
401 pci_aprint_devinfo_fancy(pa, NULL, sp->stge_name, 1);
402
403 /*
404 * Map the device.
405 */
406 ioh_valid = (pci_mapreg_map(pa, STGE_PCI_IOBA,
407 PCI_MAPREG_TYPE_IO, 0,
408 &iot, &ioh, NULL, NULL) == 0);
409 memh_valid = (pci_mapreg_map(pa, STGE_PCI_MMBA,
410 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0,
411 &memt, &memh, NULL, NULL) == 0);
412
413 if (memh_valid) {
414 sc->sc_st = memt;
415 sc->sc_sh = memh;
416 } else if (ioh_valid) {
417 sc->sc_st = iot;
418 sc->sc_sh = ioh;
419 } else {
420 aprint_error_dev(self, "unable to map device registers\n");
421 return;
422 }
423
424 sc->sc_dmat = pa->pa_dmat;
425
426 /* Enable bus mastering. */
427 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG,
428 pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG) |
429 PCI_COMMAND_MASTER_ENABLE);
430
431 /* power up chip */
432 if ((error = pci_activate(pa->pa_pc, pa->pa_tag, self, NULL)) &&
433 error != EOPNOTSUPP) {
434 aprint_error_dev(self, "cannot activate %d\n", error);
435 return;
436 }
437 /*
438 * Map and establish our interrupt.
439 */
440 if (pci_intr_map(pa, &ih)) {
441 aprint_error_dev(self, "unable to map interrupt\n");
442 return;
443 }
444 intrstr = pci_intr_string(pc, ih, intrbuf, sizeof(intrbuf));
445 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, stge_intr, sc);
446 if (sc->sc_ih == NULL) {
447 aprint_error_dev(self, "unable to establish interrupt");
448 if (intrstr != NULL)
449 aprint_error(" at %s", intrstr);
450 aprint_error("\n");
451 return;
452 }
453 aprint_normal_dev(self, "interrupting at %s\n", intrstr);
454
455 /*
456 * Allocate the control data structures, and create and load the
457 * DMA map for it.
458 */
459 if ((error = bus_dmamem_alloc(sc->sc_dmat,
460 sizeof(struct stge_control_data), PAGE_SIZE, 0, &seg, 1, &rseg,
461 0)) != 0) {
462 aprint_error_dev(self,
463 "unable to allocate control data, error = %d\n", error);
464 goto fail_0;
465 }
466
467 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg,
468 sizeof(struct stge_control_data), (void **)&sc->sc_control_data,
469 BUS_DMA_COHERENT)) != 0) {
470 aprint_error_dev(self,
471 "unable to map control data, error = %d\n", error);
472 goto fail_1;
473 }
474
475 if ((error = bus_dmamap_create(sc->sc_dmat,
476 sizeof(struct stge_control_data), 1,
477 sizeof(struct stge_control_data), 0, 0, &sc->sc_cddmamap)) != 0) {
478 aprint_error_dev(self,
479 "unable to create control data DMA map, error = %d\n",
480 error);
481 goto fail_2;
482 }
483
484 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap,
485 sc->sc_control_data, sizeof(struct stge_control_data), NULL,
486 0)) != 0) {
487 aprint_error_dev(self,
488 "unable to load control data DMA map, error = %d\n",
489 error);
490 goto fail_3;
491 }
492
493 /*
494 * Create the transmit buffer DMA maps. Note that rev B.3
495 * and earlier seem to have a bug regarding multi-fragment
496 * packets. We need to limit the number of Tx segments on
497 * such chips to 1.
498 */
499 for (i = 0; i < STGE_NTXDESC; i++) {
500 if ((error = bus_dmamap_create(sc->sc_dmat,
501 ETHER_MAX_LEN_JUMBO, STGE_NTXFRAGS, MCLBYTES, 0, 0,
502 &sc->sc_txsoft[i].ds_dmamap)) != 0) {
503 aprint_error_dev(self,
504 "unable to create tx DMA map %d, error = %d\n",
505 i, error);
506 goto fail_4;
507 }
508 }
509
510 /*
511 * Create the receive buffer DMA maps.
512 */
513 for (i = 0; i < STGE_NRXDESC; i++) {
514 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1,
515 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].ds_dmamap)) != 0) {
516 aprint_error_dev(self,
517 "unable to create rx DMA map %d, error = %d\n",
518 i, error);
519 goto fail_5;
520 }
521 sc->sc_rxsoft[i].ds_mbuf = NULL;
522 }
523
524 /*
525 * Determine if we're copper or fiber. It affects how we
526 * reset the card.
527 */
528 if (bus_space_read_4(sc->sc_st, sc->sc_sh, STGE_AsicCtrl) &
529 AC_PhyMedia)
530 sc->sc_usefiber = 1;
531 else
532 sc->sc_usefiber = 0;
533
534 /*
535 * Reset the chip to a known state.
536 */
537 stge_reset(sc);
538
539 /*
540 * Reading the station address from the EEPROM doesn't seem
541 * to work, at least on my sample boards. Instead, since
542 * the reset sequence does AutoInit, read it from the station
543 * address registers. For Sundance 1023 you can only read it
544 * from EEPROM.
545 */
546 if (sp->stge_product != PCI_PRODUCT_SUNDANCETI_ST1023) {
547 enaddr[0] = bus_space_read_2(sc->sc_st, sc->sc_sh,
548 STGE_StationAddress0) & 0xff;
549 enaddr[1] = bus_space_read_2(sc->sc_st, sc->sc_sh,
550 STGE_StationAddress0) >> 8;
551 enaddr[2] = bus_space_read_2(sc->sc_st, sc->sc_sh,
552 STGE_StationAddress1) & 0xff;
553 enaddr[3] = bus_space_read_2(sc->sc_st, sc->sc_sh,
554 STGE_StationAddress1) >> 8;
555 enaddr[4] = bus_space_read_2(sc->sc_st, sc->sc_sh,
556 STGE_StationAddress2) & 0xff;
557 enaddr[5] = bus_space_read_2(sc->sc_st, sc->sc_sh,
558 STGE_StationAddress2) >> 8;
559 sc->sc_stge1023 = 0;
560 } else {
561 data = prop_dictionary_get(device_properties(self),
562 "mac-address");
563 if (data != NULL) {
564 /*
565 * Try to get the station address from device
566 * properties first, in case the EEPROM is missing.
567 */
568 KASSERT(prop_object_type(data) == PROP_TYPE_DATA);
569 KASSERT(prop_data_size(data) == ETHER_ADDR_LEN);
570 (void)memcpy(enaddr, prop_data_data_nocopy(data),
571 ETHER_ADDR_LEN);
572 } else {
573 uint16_t myaddr[ETHER_ADDR_LEN / 2];
574 for (i = 0; i <ETHER_ADDR_LEN / 2; i++) {
575 stge_read_eeprom(sc,
576 STGE_EEPROM_StationAddress0 + i,
577 &myaddr[i]);
578 myaddr[i] = le16toh(myaddr[i]);
579 }
580 (void)memcpy(enaddr, myaddr, sizeof(enaddr));
581 }
582 sc->sc_stge1023 = 1;
583 }
584
585 aprint_normal_dev(self, "Ethernet address %s\n",
586 ether_sprintf(enaddr));
587
588 /*
589 * Read some important bits from the PhyCtrl register.
590 */
591 sc->sc_PhyCtrl = bus_space_read_1(sc->sc_st, sc->sc_sh,
592 STGE_PhyCtrl) & (PC_PhyDuplexPolarity | PC_PhyLnkPolarity);
593
594 /*
595 * Initialize our media structures and probe the MII.
596 */
597 sc->sc_mii.mii_ifp = ifp;
598 sc->sc_mii.mii_readreg = stge_mii_readreg;
599 sc->sc_mii.mii_writereg = stge_mii_writereg;
600 sc->sc_mii.mii_statchg = stge_mii_statchg;
601 sc->sc_ethercom.ec_mii = &sc->sc_mii;
602 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, ether_mediachange,
603 ether_mediastatus);
604 mii_attach(self, &sc->sc_mii, 0xffffffff, MII_PHY_ANY,
605 MII_OFFSET_ANY, MIIF_DOPAUSE);
606 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) {
607 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL);
608 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE);
609 } else
610 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO);
611
612 ifp = &sc->sc_ethercom.ec_if;
613 strlcpy(ifp->if_xname, device_xname(self), IFNAMSIZ);
614 ifp->if_softc = sc;
615 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
616 ifp->if_ioctl = stge_ioctl;
617 ifp->if_start = stge_start;
618 ifp->if_watchdog = stge_watchdog;
619 ifp->if_init = stge_init;
620 ifp->if_stop = stge_stop;
621 IFQ_SET_READY(&ifp->if_snd);
622
623 /*
624 * The manual recommends disabling early transmit, so we
625 * do. It's disabled anyway, if using IP checksumming,
626 * since the entire packet must be in the FIFO in order
627 * for the chip to perform the checksum.
628 */
629 sc->sc_txthresh = 0x0fff;
630
631 /*
632 * Disable MWI if the PCI layer tells us to.
633 */
634 sc->sc_DMACtrl = 0;
635 if ((pa->pa_flags & PCI_FLAGS_MWI_OKAY) == 0)
636 sc->sc_DMACtrl |= DMAC_MWIDisable;
637
638 /*
639 * We can support 802.1Q VLAN-sized frames and jumbo
640 * Ethernet frames.
641 *
642 * XXX Figure out how to do hw-assisted VLAN tagging in
643 * XXX a reasonable way on this chip.
644 */
645 sc->sc_ethercom.ec_capabilities |=
646 ETHERCAP_VLAN_MTU | /* XXX ETHERCAP_JUMBO_MTU | */
647 ETHERCAP_VLAN_HWTAGGING;
648
649 /*
650 * We can do IPv4/TCPv4/UDPv4 checksums in hardware.
651 */
652 sc->sc_ethercom.ec_if.if_capabilities |=
653 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx |
654 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx |
655 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx;
656
657 /*
658 * Attach the interface.
659 */
660 if_attach(ifp);
661 ether_ifattach(ifp, enaddr);
662
663 #ifdef STGE_EVENT_COUNTERS
664 /*
665 * Attach event counters.
666 */
667 evcnt_attach_dynamic(&sc->sc_ev_txstall, EVCNT_TYPE_MISC,
668 NULL, device_xname(self), "txstall");
669 evcnt_attach_dynamic(&sc->sc_ev_txdmaintr, EVCNT_TYPE_INTR,
670 NULL, device_xname(self), "txdmaintr");
671 evcnt_attach_dynamic(&sc->sc_ev_txindintr, EVCNT_TYPE_INTR,
672 NULL, device_xname(self), "txindintr");
673 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR,
674 NULL, device_xname(self), "rxintr");
675
676 evcnt_attach_dynamic(&sc->sc_ev_txseg1, EVCNT_TYPE_MISC,
677 NULL, device_xname(self), "txseg1");
678 evcnt_attach_dynamic(&sc->sc_ev_txseg2, EVCNT_TYPE_MISC,
679 NULL, device_xname(self), "txseg2");
680 evcnt_attach_dynamic(&sc->sc_ev_txseg3, EVCNT_TYPE_MISC,
681 NULL, device_xname(self), "txseg3");
682 evcnt_attach_dynamic(&sc->sc_ev_txseg4, EVCNT_TYPE_MISC,
683 NULL, device_xname(self), "txseg4");
684 evcnt_attach_dynamic(&sc->sc_ev_txseg5, EVCNT_TYPE_MISC,
685 NULL, device_xname(self), "txseg5");
686 evcnt_attach_dynamic(&sc->sc_ev_txsegmore, EVCNT_TYPE_MISC,
687 NULL, device_xname(self), "txsegmore");
688 evcnt_attach_dynamic(&sc->sc_ev_txcopy, EVCNT_TYPE_MISC,
689 NULL, device_xname(self), "txcopy");
690
691 evcnt_attach_dynamic(&sc->sc_ev_rxipsum, EVCNT_TYPE_MISC,
692 NULL, device_xname(self), "rxipsum");
693 evcnt_attach_dynamic(&sc->sc_ev_rxtcpsum, EVCNT_TYPE_MISC,
694 NULL, device_xname(self), "rxtcpsum");
695 evcnt_attach_dynamic(&sc->sc_ev_rxudpsum, EVCNT_TYPE_MISC,
696 NULL, device_xname(self), "rxudpsum");
697 evcnt_attach_dynamic(&sc->sc_ev_txipsum, EVCNT_TYPE_MISC,
698 NULL, device_xname(self), "txipsum");
699 evcnt_attach_dynamic(&sc->sc_ev_txtcpsum, EVCNT_TYPE_MISC,
700 NULL, device_xname(self), "txtcpsum");
701 evcnt_attach_dynamic(&sc->sc_ev_txudpsum, EVCNT_TYPE_MISC,
702 NULL, device_xname(self), "txudpsum");
703 #endif /* STGE_EVENT_COUNTERS */
704
705 /*
706 * Make sure the interface is shutdown during reboot.
707 */
708 if (pmf_device_register1(self, NULL, NULL, stge_shutdown))
709 pmf_class_network_register(self, ifp);
710 else
711 aprint_error_dev(self, "couldn't establish power handler\n");
712
713 return;
714
715 /*
716 * Free any resources we've allocated during the failed attach
717 * attempt. Do this in reverse order and fall through.
718 */
719 fail_5:
720 for (i = 0; i < STGE_NRXDESC; i++) {
721 if (sc->sc_rxsoft[i].ds_dmamap != NULL)
722 bus_dmamap_destroy(sc->sc_dmat,
723 sc->sc_rxsoft[i].ds_dmamap);
724 }
725 fail_4:
726 for (i = 0; i < STGE_NTXDESC; i++) {
727 if (sc->sc_txsoft[i].ds_dmamap != NULL)
728 bus_dmamap_destroy(sc->sc_dmat,
729 sc->sc_txsoft[i].ds_dmamap);
730 }
731 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap);
732 fail_3:
733 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap);
734 fail_2:
735 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data,
736 sizeof(struct stge_control_data));
737 fail_1:
738 bus_dmamem_free(sc->sc_dmat, &seg, rseg);
739 fail_0:
740 return;
741 }
742
743 /*
744 * stge_shutdown:
745 *
746 * Make sure the interface is stopped at reboot time.
747 */
748 static bool
stge_shutdown(device_t self,int howto)749 stge_shutdown(device_t self, int howto)
750 {
751 struct stge_softc *sc = device_private(self);
752 struct ifnet *ifp = &sc->sc_ethercom.ec_if;
753
754 stge_stop(ifp, 1);
755 stge_reset(sc);
756 return true;
757 }
758
759 static void
stge_dma_wait(struct stge_softc * sc)760 stge_dma_wait(struct stge_softc *sc)
761 {
762 int i;
763
764 for (i = 0; i < STGE_TIMEOUT; i++) {
765 delay(2);
766 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, STGE_DMACtrl) &
767 DMAC_TxDMAInProg) == 0)
768 break;
769 }
770
771 if (i == STGE_TIMEOUT)
772 printf("%s: DMA wait timed out\n", device_xname(sc->sc_dev));
773 }
774
775 /*
776 * stge_start: [ifnet interface function]
777 *
778 * Start packet transmission on the interface.
779 */
780 static void
stge_start(struct ifnet * ifp)781 stge_start(struct ifnet *ifp)
782 {
783 struct stge_softc *sc = ifp->if_softc;
784 struct mbuf *m0;
785 struct stge_descsoft *ds;
786 struct stge_tfd *tfd;
787 bus_dmamap_t dmamap;
788 int error, firsttx, nexttx, opending, seg, totlen;
789 uint64_t csum_flags;
790
791 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING)
792 return;
793
794 /*
795 * Remember the previous number of pending transmissions
796 * and the first descriptor we will use.
797 */
798 opending = sc->sc_txpending;
799 firsttx = STGE_NEXTTX(sc->sc_txlast);
800
801 /*
802 * Loop through the send queue, setting up transmit descriptors
803 * until we drain the queue, or use up all available transmit
804 * descriptors.
805 */
806 for (;;) {
807 struct m_tag *mtag;
808 uint64_t tfc;
809
810 /*
811 * Grab a packet off the queue.
812 */
813 IFQ_POLL(&ifp->if_snd, m0);
814 if (m0 == NULL)
815 break;
816
817 /*
818 * Leave one unused descriptor at the end of the
819 * list to prevent wrapping completely around.
820 */
821 if (sc->sc_txpending == (STGE_NTXDESC - 1)) {
822 STGE_EVCNT_INCR(&sc->sc_ev_txstall);
823 break;
824 }
825
826 /*
827 * See if we have any VLAN stuff.
828 */
829 mtag = VLAN_OUTPUT_TAG(&sc->sc_ethercom, m0);
830
831 /*
832 * Get the last and next available transmit descriptor.
833 */
834 nexttx = STGE_NEXTTX(sc->sc_txlast);
835 tfd = &sc->sc_txdescs[nexttx];
836 ds = &sc->sc_txsoft[nexttx];
837
838 dmamap = ds->ds_dmamap;
839
840 /*
841 * Load the DMA map. If this fails, the packet either
842 * didn't fit in the alloted number of segments, or we
843 * were short on resources. For the too-many-segments
844 * case, we simply report an error and drop the packet,
845 * since we can't sanely copy a jumbo packet to a single
846 * buffer.
847 */
848 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0,
849 BUS_DMA_NOWAIT);
850 if (error) {
851 if (error == EFBIG) {
852 printf("%s: Tx packet consumes too many "
853 "DMA segments, dropping...\n",
854 device_xname(sc->sc_dev));
855 IFQ_DEQUEUE(&ifp->if_snd, m0);
856 m_freem(m0);
857 continue;
858 }
859 /*
860 * Short on resources, just stop for now.
861 */
862 break;
863 }
864
865 IFQ_DEQUEUE(&ifp->if_snd, m0);
866
867 /*
868 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET.
869 */
870
871 /* Sync the DMA map. */
872 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize,
873 BUS_DMASYNC_PREWRITE);
874
875 /* Initialize the fragment list. */
876 for (totlen = 0, seg = 0; seg < dmamap->dm_nsegs; seg++) {
877 tfd->tfd_frags[seg].frag_word0 =
878 htole64(FRAG_ADDR(dmamap->dm_segs[seg].ds_addr) |
879 FRAG_LEN(dmamap->dm_segs[seg].ds_len));
880 totlen += dmamap->dm_segs[seg].ds_len;
881 }
882
883 #ifdef STGE_EVENT_COUNTERS
884 switch (dmamap->dm_nsegs) {
885 case 1:
886 STGE_EVCNT_INCR(&sc->sc_ev_txseg1);
887 break;
888 case 2:
889 STGE_EVCNT_INCR(&sc->sc_ev_txseg2);
890 break;
891 case 3:
892 STGE_EVCNT_INCR(&sc->sc_ev_txseg3);
893 break;
894 case 4:
895 STGE_EVCNT_INCR(&sc->sc_ev_txseg4);
896 break;
897 case 5:
898 STGE_EVCNT_INCR(&sc->sc_ev_txseg5);
899 break;
900 default:
901 STGE_EVCNT_INCR(&sc->sc_ev_txsegmore);
902 break;
903 }
904 #endif /* STGE_EVENT_COUNTERS */
905
906 /*
907 * Initialize checksumming flags in the descriptor.
908 * Byte-swap constants so the compiler can optimize.
909 */
910 csum_flags = 0;
911 if (m0->m_pkthdr.csum_flags & M_CSUM_IPv4) {
912 STGE_EVCNT_INCR(&sc->sc_ev_txipsum);
913 csum_flags |= TFD_IPChecksumEnable;
914 }
915
916 if (m0->m_pkthdr.csum_flags & M_CSUM_TCPv4) {
917 STGE_EVCNT_INCR(&sc->sc_ev_txtcpsum);
918 csum_flags |= TFD_TCPChecksumEnable;
919 } else if (m0->m_pkthdr.csum_flags & M_CSUM_UDPv4) {
920 STGE_EVCNT_INCR(&sc->sc_ev_txudpsum);
921 csum_flags |= TFD_UDPChecksumEnable;
922 }
923
924 /*
925 * Initialize the descriptor and give it to the chip.
926 * Check to see if we have a VLAN tag to insert.
927 */
928
929 tfc = TFD_FrameId(nexttx) | TFD_WordAlign(/*totlen & */3) |
930 TFD_FragCount(seg) | csum_flags |
931 (((nexttx & STGE_TXINTR_SPACING_MASK) == 0) ?
932 TFD_TxDMAIndicate : 0);
933 if (mtag) {
934 #if 0
935 struct ether_header *eh =
936 mtod(m0, struct ether_header *);
937 u_int16_t etype = ntohs(eh->ether_type);
938 printf("%s: xmit (tag %d) etype %x\n",
939 ifp->if_xname, *mtod(n, int *), etype);
940 #endif
941 tfc |= TFD_VLANTagInsert |
942 #ifdef STGE_VLAN_CFI
943 TFD_CFI |
944 #endif
945 TFD_VID(VLAN_TAG_VALUE(mtag));
946 }
947 tfd->tfd_control = htole64(tfc);
948
949 /* Sync the descriptor. */
950 STGE_CDTXSYNC(sc, nexttx,
951 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
952
953 /*
954 * Kick the transmit DMA logic.
955 */
956 bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_DMACtrl,
957 sc->sc_DMACtrl | DMAC_TxDMAPollNow);
958
959 /*
960 * Store a pointer to the packet so we can free it later.
961 */
962 ds->ds_mbuf = m0;
963
964 /* Advance the tx pointer. */
965 sc->sc_txpending++;
966 sc->sc_txlast = nexttx;
967
968 /*
969 * Pass the packet to any BPF listeners.
970 */
971 bpf_mtap(ifp, m0);
972 }
973
974 if (sc->sc_txpending == (STGE_NTXDESC - 1)) {
975 /* No more slots left; notify upper layer. */
976 ifp->if_flags |= IFF_OACTIVE;
977 }
978
979 if (sc->sc_txpending != opending) {
980 /*
981 * We enqueued packets. If the transmitter was idle,
982 * reset the txdirty pointer.
983 */
984 if (opending == 0)
985 sc->sc_txdirty = firsttx;
986
987 /* Set a watchdog timer in case the chip flakes out. */
988 ifp->if_timer = 5;
989 }
990 }
991
992 /*
993 * stge_watchdog: [ifnet interface function]
994 *
995 * Watchdog timer handler.
996 */
997 static void
stge_watchdog(struct ifnet * ifp)998 stge_watchdog(struct ifnet *ifp)
999 {
1000 struct stge_softc *sc = ifp->if_softc;
1001
1002 /*
1003 * Sweep up first, since we don't interrupt every frame.
1004 */
1005 stge_txintr(sc);
1006 if (sc->sc_txpending != 0) {
1007 printf("%s: device timeout\n", device_xname(sc->sc_dev));
1008 ifp->if_oerrors++;
1009
1010 (void) stge_init(ifp);
1011
1012 /* Try to get more packets going. */
1013 stge_start(ifp);
1014 }
1015 }
1016
1017 /*
1018 * stge_ioctl: [ifnet interface function]
1019 *
1020 * Handle control requests from the operator.
1021 */
1022 static int
stge_ioctl(struct ifnet * ifp,u_long cmd,void * data)1023 stge_ioctl(struct ifnet *ifp, u_long cmd, void *data)
1024 {
1025 struct stge_softc *sc = ifp->if_softc;
1026 int s, error;
1027
1028 s = splnet();
1029
1030 error = ether_ioctl(ifp, cmd, data);
1031 if (error == ENETRESET) {
1032 error = 0;
1033
1034 if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI)
1035 ;
1036 else if (ifp->if_flags & IFF_RUNNING) {
1037 /*
1038 * Multicast list has changed; set the hardware filter
1039 * accordingly.
1040 */
1041 stge_set_filter(sc);
1042 }
1043 }
1044
1045 /* Try to get more packets going. */
1046 stge_start(ifp);
1047
1048 splx(s);
1049 return (error);
1050 }
1051
1052 /*
1053 * stge_intr:
1054 *
1055 * Interrupt service routine.
1056 */
1057 static int
stge_intr(void * arg)1058 stge_intr(void *arg)
1059 {
1060 struct stge_softc *sc = arg;
1061 struct ifnet *ifp = &sc->sc_ethercom.ec_if;
1062 uint32_t txstat;
1063 int wantinit;
1064 uint16_t isr;
1065
1066 if ((bus_space_read_2(sc->sc_st, sc->sc_sh, STGE_IntStatus) &
1067 IS_InterruptStatus) == 0)
1068 return (0);
1069
1070 for (wantinit = 0; wantinit == 0;) {
1071 isr = bus_space_read_2(sc->sc_st, sc->sc_sh, STGE_IntStatusAck);
1072 if ((isr & sc->sc_IntEnable) == 0)
1073 break;
1074
1075 /* Host interface errors. */
1076 if (isr & IS_HostError) {
1077 printf("%s: Host interface error\n",
1078 device_xname(sc->sc_dev));
1079 wantinit = 1;
1080 continue;
1081 }
1082
1083 /* Receive interrupts. */
1084 if (isr & (IS_RxDMAComplete|IS_RFDListEnd)) {
1085 STGE_EVCNT_INCR(&sc->sc_ev_rxintr);
1086 stge_rxintr(sc);
1087 if (isr & IS_RFDListEnd) {
1088 printf("%s: receive ring overflow\n",
1089 device_xname(sc->sc_dev));
1090 /*
1091 * XXX Should try to recover from this
1092 * XXX more gracefully.
1093 */
1094 wantinit = 1;
1095 }
1096 }
1097
1098 /* Transmit interrupts. */
1099 if (isr & (IS_TxDMAComplete|IS_TxComplete)) {
1100 #ifdef STGE_EVENT_COUNTERS
1101 if (isr & IS_TxDMAComplete)
1102 STGE_EVCNT_INCR(&sc->sc_ev_txdmaintr);
1103 #endif
1104 stge_txintr(sc);
1105 }
1106
1107 /* Statistics overflow. */
1108 if (isr & IS_UpdateStats)
1109 stge_stats_update(sc);
1110
1111 /* Transmission errors. */
1112 if (isr & IS_TxComplete) {
1113 STGE_EVCNT_INCR(&sc->sc_ev_txindintr);
1114 for (;;) {
1115 txstat = bus_space_read_4(sc->sc_st, sc->sc_sh,
1116 STGE_TxStatus);
1117 if ((txstat & TS_TxComplete) == 0)
1118 break;
1119 if (txstat & TS_TxUnderrun) {
1120 sc->sc_txthresh++;
1121 if (sc->sc_txthresh > 0x0fff)
1122 sc->sc_txthresh = 0x0fff;
1123 printf("%s: transmit underrun, new "
1124 "threshold: %d bytes\n",
1125 device_xname(sc->sc_dev),
1126 sc->sc_txthresh << 5);
1127 }
1128 if (txstat & TS_MaxCollisions)
1129 printf("%s: excessive collisions\n",
1130 device_xname(sc->sc_dev));
1131 }
1132 wantinit = 1;
1133 }
1134
1135 }
1136
1137 if (wantinit)
1138 stge_init(ifp);
1139
1140 bus_space_write_2(sc->sc_st, sc->sc_sh, STGE_IntEnable,
1141 sc->sc_IntEnable);
1142
1143 /* Try to get more packets going. */
1144 stge_start(ifp);
1145
1146 return (1);
1147 }
1148
1149 /*
1150 * stge_txintr:
1151 *
1152 * Helper; handle transmit interrupts.
1153 */
1154 static void
stge_txintr(struct stge_softc * sc)1155 stge_txintr(struct stge_softc *sc)
1156 {
1157 struct ifnet *ifp = &sc->sc_ethercom.ec_if;
1158 struct stge_descsoft *ds;
1159 uint64_t control;
1160 int i;
1161
1162 ifp->if_flags &= ~IFF_OACTIVE;
1163
1164 /*
1165 * Go through our Tx list and free mbufs for those
1166 * frames which have been transmitted.
1167 */
1168 for (i = sc->sc_txdirty; sc->sc_txpending != 0;
1169 i = STGE_NEXTTX(i), sc->sc_txpending--) {
1170 ds = &sc->sc_txsoft[i];
1171
1172 STGE_CDTXSYNC(sc, i,
1173 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
1174
1175 control = le64toh(sc->sc_txdescs[i].tfd_control);
1176 if ((control & TFD_TFDDone) == 0)
1177 break;
1178
1179 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap,
1180 0, ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE);
1181 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap);
1182 m_freem(ds->ds_mbuf);
1183 ds->ds_mbuf = NULL;
1184 }
1185
1186 /* Update the dirty transmit buffer pointer. */
1187 sc->sc_txdirty = i;
1188
1189 /*
1190 * If there are no more pending transmissions, cancel the watchdog
1191 * timer.
1192 */
1193 if (sc->sc_txpending == 0)
1194 ifp->if_timer = 0;
1195 }
1196
1197 /*
1198 * stge_rxintr:
1199 *
1200 * Helper; handle receive interrupts.
1201 */
1202 static void
stge_rxintr(struct stge_softc * sc)1203 stge_rxintr(struct stge_softc *sc)
1204 {
1205 struct ifnet *ifp = &sc->sc_ethercom.ec_if;
1206 struct stge_descsoft *ds;
1207 struct mbuf *m, *tailm;
1208 uint64_t status;
1209 int i, len;
1210
1211 for (i = sc->sc_rxptr;; i = STGE_NEXTRX(i)) {
1212 ds = &sc->sc_rxsoft[i];
1213
1214 STGE_CDRXSYNC(sc, i,
1215 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
1216
1217 status = le64toh(sc->sc_rxdescs[i].rfd_status);
1218
1219 if ((status & RFD_RFDDone) == 0)
1220 break;
1221
1222 if (__predict_false(sc->sc_rxdiscard)) {
1223 STGE_INIT_RXDESC(sc, i);
1224 if (status & RFD_FrameEnd) {
1225 /* Reset our state. */
1226 sc->sc_rxdiscard = 0;
1227 }
1228 continue;
1229 }
1230
1231 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0,
1232 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD);
1233
1234 m = ds->ds_mbuf;
1235
1236 /*
1237 * Add a new receive buffer to the ring.
1238 */
1239 if (stge_add_rxbuf(sc, i) != 0) {
1240 /*
1241 * Failed, throw away what we've done so
1242 * far, and discard the rest of the packet.
1243 */
1244 ifp->if_ierrors++;
1245 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0,
1246 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD);
1247 STGE_INIT_RXDESC(sc, i);
1248 if ((status & RFD_FrameEnd) == 0)
1249 sc->sc_rxdiscard = 1;
1250 if (sc->sc_rxhead != NULL)
1251 m_freem(sc->sc_rxhead);
1252 STGE_RXCHAIN_RESET(sc);
1253 continue;
1254 }
1255
1256 #ifdef DIAGNOSTIC
1257 if (status & RFD_FrameStart) {
1258 KASSERT(sc->sc_rxhead == NULL);
1259 KASSERT(sc->sc_rxtailp == &sc->sc_rxhead);
1260 }
1261 #endif
1262
1263 STGE_RXCHAIN_LINK(sc, m);
1264
1265 /*
1266 * If this is not the end of the packet, keep
1267 * looking.
1268 */
1269 if ((status & RFD_FrameEnd) == 0) {
1270 sc->sc_rxlen += m->m_len;
1271 continue;
1272 }
1273
1274 /*
1275 * Okay, we have the entire packet now...
1276 */
1277 *sc->sc_rxtailp = NULL;
1278 m = sc->sc_rxhead;
1279 tailm = sc->sc_rxtail;
1280
1281 STGE_RXCHAIN_RESET(sc);
1282
1283 /*
1284 * If the packet had an error, drop it. Note we
1285 * count the error later in the periodic stats update.
1286 */
1287 if (status & (RFD_RxFIFOOverrun | RFD_RxRuntFrame |
1288 RFD_RxAlignmentError | RFD_RxFCSError |
1289 RFD_RxLengthError)) {
1290 m_freem(m);
1291 continue;
1292 }
1293
1294 /*
1295 * No errors.
1296 *
1297 * Note we have configured the chip to not include
1298 * the CRC at the end of the packet.
1299 */
1300 len = RFD_RxDMAFrameLen(status);
1301 tailm->m_len = len - sc->sc_rxlen;
1302
1303 /*
1304 * If the packet is small enough to fit in a
1305 * single header mbuf, allocate one and copy
1306 * the data into it. This greatly reduces
1307 * memory consumption when we receive lots
1308 * of small packets.
1309 */
1310 if (stge_copy_small != 0 && len <= (MHLEN - 2)) {
1311 struct mbuf *nm;
1312 MGETHDR(nm, M_DONTWAIT, MT_DATA);
1313 if (nm == NULL) {
1314 ifp->if_ierrors++;
1315 m_freem(m);
1316 continue;
1317 }
1318 nm->m_data += 2;
1319 nm->m_pkthdr.len = nm->m_len = len;
1320 m_copydata(m, 0, len, mtod(nm, void *));
1321 m_freem(m);
1322 m = nm;
1323 }
1324
1325 /*
1326 * Set the incoming checksum information for the packet.
1327 */
1328 if (status & RFD_IPDetected) {
1329 STGE_EVCNT_INCR(&sc->sc_ev_rxipsum);
1330 m->m_pkthdr.csum_flags |= M_CSUM_IPv4;
1331 if (status & RFD_IPError)
1332 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD;
1333 if (status & RFD_TCPDetected) {
1334 STGE_EVCNT_INCR(&sc->sc_ev_rxtcpsum);
1335 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4;
1336 if (status & RFD_TCPError)
1337 m->m_pkthdr.csum_flags |=
1338 M_CSUM_TCP_UDP_BAD;
1339 } else if (status & RFD_UDPDetected) {
1340 STGE_EVCNT_INCR(&sc->sc_ev_rxudpsum);
1341 m->m_pkthdr.csum_flags |= M_CSUM_UDPv4;
1342 if (status & RFD_UDPError)
1343 m->m_pkthdr.csum_flags |=
1344 M_CSUM_TCP_UDP_BAD;
1345 }
1346 }
1347
1348 m_set_rcvif(m, ifp);
1349 m->m_pkthdr.len = len;
1350
1351 /*
1352 * Pass this up to any BPF listeners, but only
1353 * pass if up the stack if it's for us.
1354 */
1355 bpf_mtap(ifp, m);
1356 #ifdef STGE_VLAN_UNTAG
1357 /*
1358 * Check for VLAN tagged packets
1359 */
1360 if (status & RFD_VLANDetected)
1361 VLAN_INPUT_TAG(ifp, m, RFD_TCI(status), continue);
1362
1363 #endif
1364 #if 0
1365 if (status & RFD_VLANDetected) {
1366 struct ether_header *eh;
1367 u_int16_t etype;
1368
1369 eh = mtod(m, struct ether_header *);
1370 etype = ntohs(eh->ether_type);
1371 printf("%s: VLANtag detected (TCI %d) etype %x\n",
1372 ifp->if_xname, (u_int16_t) RFD_TCI(status),
1373 etype);
1374 }
1375 #endif
1376 /* Pass it on. */
1377 if_percpuq_enqueue(ifp->if_percpuq, m);
1378 }
1379
1380 /* Update the receive pointer. */
1381 sc->sc_rxptr = i;
1382 }
1383
1384 /*
1385 * stge_tick:
1386 *
1387 * One second timer, used to tick the MII.
1388 */
1389 static void
stge_tick(void * arg)1390 stge_tick(void *arg)
1391 {
1392 struct stge_softc *sc = arg;
1393 int s;
1394
1395 s = splnet();
1396 mii_tick(&sc->sc_mii);
1397 stge_stats_update(sc);
1398 splx(s);
1399
1400 callout_reset(&sc->sc_tick_ch, hz, stge_tick, sc);
1401 }
1402
1403 /*
1404 * stge_stats_update:
1405 *
1406 * Read the TC9021 statistics counters.
1407 */
1408 static void
stge_stats_update(struct stge_softc * sc)1409 stge_stats_update(struct stge_softc *sc)
1410 {
1411 struct ifnet *ifp = &sc->sc_ethercom.ec_if;
1412 bus_space_tag_t st = sc->sc_st;
1413 bus_space_handle_t sh = sc->sc_sh;
1414
1415 (void) bus_space_read_4(st, sh, STGE_OctetRcvOk);
1416
1417 ifp->if_ipackets +=
1418 bus_space_read_4(st, sh, STGE_FramesRcvdOk);
1419
1420 ifp->if_ierrors +=
1421 (u_int) bus_space_read_2(st, sh, STGE_FramesLostRxErrors);
1422
1423 (void) bus_space_read_4(st, sh, STGE_OctetXmtdOk);
1424
1425 ifp->if_opackets +=
1426 bus_space_read_4(st, sh, STGE_FramesXmtdOk);
1427
1428 ifp->if_collisions +=
1429 bus_space_read_4(st, sh, STGE_LateCollisions) +
1430 bus_space_read_4(st, sh, STGE_MultiColFrames) +
1431 bus_space_read_4(st, sh, STGE_SingleColFrames);
1432
1433 ifp->if_oerrors +=
1434 (u_int) bus_space_read_2(st, sh, STGE_FramesAbortXSColls) +
1435 (u_int) bus_space_read_2(st, sh, STGE_FramesWEXDeferal);
1436 }
1437
1438 /*
1439 * stge_reset:
1440 *
1441 * Perform a soft reset on the TC9021.
1442 */
1443 static void
stge_reset(struct stge_softc * sc)1444 stge_reset(struct stge_softc *sc)
1445 {
1446 uint32_t ac;
1447 int i;
1448
1449 ac = bus_space_read_4(sc->sc_st, sc->sc_sh, STGE_AsicCtrl);
1450
1451 /*
1452 * Only assert RstOut if we're fiber. We need GMII clocks
1453 * to be present in order for the reset to complete on fiber
1454 * cards.
1455 */
1456 bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_AsicCtrl,
1457 ac | AC_GlobalReset | AC_RxReset | AC_TxReset |
1458 AC_DMA | AC_FIFO | AC_Network | AC_Host | AC_AutoInit |
1459 (sc->sc_usefiber ? AC_RstOut : 0));
1460
1461 delay(50000);
1462
1463 for (i = 0; i < STGE_TIMEOUT; i++) {
1464 delay(5000);
1465 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, STGE_AsicCtrl) &
1466 AC_ResetBusy) == 0)
1467 break;
1468 }
1469
1470 if (i == STGE_TIMEOUT)
1471 printf("%s: reset failed to complete\n",
1472 device_xname(sc->sc_dev));
1473
1474 delay(1000);
1475 }
1476
1477 /*
1478 * stge_init: [ ifnet interface function ]
1479 *
1480 * Initialize the interface. Must be called at splnet().
1481 */
1482 static int
stge_init(struct ifnet * ifp)1483 stge_init(struct ifnet *ifp)
1484 {
1485 struct stge_softc *sc = ifp->if_softc;
1486 bus_space_tag_t st = sc->sc_st;
1487 bus_space_handle_t sh = sc->sc_sh;
1488 struct stge_descsoft *ds;
1489 int i, error = 0;
1490
1491 /*
1492 * Cancel any pending I/O.
1493 */
1494 stge_stop(ifp, 0);
1495
1496 /*
1497 * Reset the chip to a known state.
1498 */
1499 stge_reset(sc);
1500
1501 /*
1502 * Initialize the transmit descriptor ring.
1503 */
1504 memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs));
1505 for (i = 0; i < STGE_NTXDESC; i++) {
1506 sc->sc_txdescs[i].tfd_next = htole64(
1507 STGE_CDTXADDR(sc, STGE_NEXTTX(i)));
1508 sc->sc_txdescs[i].tfd_control = htole64(TFD_TFDDone);
1509 }
1510 sc->sc_txpending = 0;
1511 sc->sc_txdirty = 0;
1512 sc->sc_txlast = STGE_NTXDESC - 1;
1513
1514 /*
1515 * Initialize the receive descriptor and receive job
1516 * descriptor rings.
1517 */
1518 for (i = 0; i < STGE_NRXDESC; i++) {
1519 ds = &sc->sc_rxsoft[i];
1520 if (ds->ds_mbuf == NULL) {
1521 if ((error = stge_add_rxbuf(sc, i)) != 0) {
1522 printf("%s: unable to allocate or map rx "
1523 "buffer %d, error = %d\n",
1524 device_xname(sc->sc_dev), i, error);
1525 /*
1526 * XXX Should attempt to run with fewer receive
1527 * XXX buffers instead of just failing.
1528 */
1529 stge_rxdrain(sc);
1530 goto out;
1531 }
1532 } else
1533 STGE_INIT_RXDESC(sc, i);
1534 }
1535 sc->sc_rxptr = 0;
1536 sc->sc_rxdiscard = 0;
1537 STGE_RXCHAIN_RESET(sc);
1538
1539 /* Set the station address. */
1540 for (i = 0; i < 6; i++)
1541 bus_space_write_1(st, sh, STGE_StationAddress0 + i,
1542 CLLADDR(ifp->if_sadl)[i]);
1543
1544 /*
1545 * Set the statistics masks. Disable all the RMON stats,
1546 * and disable selected stats in the non-RMON stats registers.
1547 */
1548 bus_space_write_4(st, sh, STGE_RMONStatisticsMask, 0xffffffff);
1549 bus_space_write_4(st, sh, STGE_StatisticsMask,
1550 (1U << 1) | (1U << 2) | (1U << 3) | (1U << 4) | (1U << 5) |
1551 (1U << 6) | (1U << 7) | (1U << 8) | (1U << 9) | (1U << 10) |
1552 (1U << 13) | (1U << 14) | (1U << 15) | (1U << 19) | (1U << 20) |
1553 (1U << 21));
1554
1555 /* Set up the receive filter. */
1556 stge_set_filter(sc);
1557
1558 /*
1559 * Give the transmit and receive ring to the chip.
1560 */
1561 bus_space_write_4(st, sh, STGE_TFDListPtrHi, 0); /* NOTE: 32-bit DMA */
1562 bus_space_write_4(st, sh, STGE_TFDListPtrLo,
1563 STGE_CDTXADDR(sc, sc->sc_txdirty));
1564
1565 bus_space_write_4(st, sh, STGE_RFDListPtrHi, 0); /* NOTE: 32-bit DMA */
1566 bus_space_write_4(st, sh, STGE_RFDListPtrLo,
1567 STGE_CDRXADDR(sc, sc->sc_rxptr));
1568
1569 /*
1570 * Initialize the Tx auto-poll period. It's OK to make this number
1571 * large (255 is the max, but we use 127) -- we explicitly kick the
1572 * transmit engine when there's actually a packet.
1573 */
1574 bus_space_write_1(st, sh, STGE_TxDMAPollPeriod, 127);
1575
1576 /* ..and the Rx auto-poll period. */
1577 bus_space_write_1(st, sh, STGE_RxDMAPollPeriod, 64);
1578
1579 /* Initialize the Tx start threshold. */
1580 bus_space_write_2(st, sh, STGE_TxStartThresh, sc->sc_txthresh);
1581
1582 /* RX DMA thresholds, from linux */
1583 bus_space_write_1(st, sh, STGE_RxDMABurstThresh, 0x30);
1584 bus_space_write_1(st, sh, STGE_RxDMAUrgentThresh, 0x30);
1585
1586 /*
1587 * Initialize the Rx DMA interrupt control register. We
1588 * request an interrupt after every incoming packet, but
1589 * defer it for 32us (64 * 512 ns). When the number of
1590 * interrupts pending reaches 8, we stop deferring the
1591 * interrupt, and signal it immediately.
1592 */
1593 bus_space_write_4(st, sh, STGE_RxDMAIntCtrl,
1594 RDIC_RxFrameCount(8) | RDIC_RxDMAWaitTime(512));
1595
1596 /*
1597 * Initialize the interrupt mask.
1598 */
1599 sc->sc_IntEnable = IS_HostError | IS_TxComplete | IS_UpdateStats |
1600 IS_TxDMAComplete | IS_RxDMAComplete | IS_RFDListEnd;
1601 bus_space_write_2(st, sh, STGE_IntStatus, 0xffff);
1602 bus_space_write_2(st, sh, STGE_IntEnable, sc->sc_IntEnable);
1603
1604 /*
1605 * Configure the DMA engine.
1606 * XXX Should auto-tune TxBurstLimit.
1607 */
1608 bus_space_write_4(st, sh, STGE_DMACtrl, sc->sc_DMACtrl |
1609 DMAC_TxBurstLimit(3));
1610
1611 /*
1612 * Send a PAUSE frame when we reach 29,696 bytes in the Rx
1613 * FIFO, and send an un-PAUSE frame when the FIFO is totally
1614 * empty again.
1615 */
1616 bus_space_write_2(st, sh, STGE_FlowOnTresh, 29696 / 16);
1617 bus_space_write_2(st, sh, STGE_FlowOffThresh, 0);
1618
1619 /*
1620 * Set the maximum frame size.
1621 */
1622 bus_space_write_2(st, sh, STGE_MaxFrameSize,
1623 ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN +
1624 ((sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) ?
1625 ETHER_VLAN_ENCAP_LEN : 0));
1626
1627 /*
1628 * Initialize MacCtrl -- do it before setting the media,
1629 * as setting the media will actually program the register.
1630 *
1631 * Note: We have to poke the IFS value before poking
1632 * anything else.
1633 */
1634 sc->sc_MACCtrl = MC_IFSSelect(0);
1635 bus_space_write_4(st, sh, STGE_MACCtrl, sc->sc_MACCtrl);
1636 sc->sc_MACCtrl |= MC_StatisticsEnable | MC_TxEnable | MC_RxEnable;
1637 #ifdef STGE_VLAN_UNTAG
1638 sc->sc_MACCtrl |= MC_AutoVLANuntagging;
1639 #endif
1640
1641 if (sc->sc_rev >= 6) { /* >= B.2 */
1642 /* Multi-frag frame bug work-around. */
1643 bus_space_write_2(st, sh, STGE_DebugCtrl,
1644 bus_space_read_2(st, sh, STGE_DebugCtrl) | 0x0200);
1645
1646 /* Tx Poll Now bug work-around. */
1647 bus_space_write_2(st, sh, STGE_DebugCtrl,
1648 bus_space_read_2(st, sh, STGE_DebugCtrl) | 0x0010);
1649 /* XXX ? from linux */
1650 bus_space_write_2(st, sh, STGE_DebugCtrl,
1651 bus_space_read_2(st, sh, STGE_DebugCtrl) | 0x0020);
1652 }
1653
1654 /*
1655 * Set the current media.
1656 */
1657 if ((error = ether_mediachange(ifp)) != 0)
1658 goto out;
1659
1660 /*
1661 * Start the one second MII clock.
1662 */
1663 callout_reset(&sc->sc_tick_ch, hz, stge_tick, sc);
1664
1665 /*
1666 * ...all done!
1667 */
1668 ifp->if_flags |= IFF_RUNNING;
1669 ifp->if_flags &= ~IFF_OACTIVE;
1670
1671 out:
1672 if (error)
1673 printf("%s: interface not running\n", device_xname(sc->sc_dev));
1674 return (error);
1675 }
1676
1677 /*
1678 * stge_drain:
1679 *
1680 * Drain the receive queue.
1681 */
1682 static void
stge_rxdrain(struct stge_softc * sc)1683 stge_rxdrain(struct stge_softc *sc)
1684 {
1685 struct stge_descsoft *ds;
1686 int i;
1687
1688 for (i = 0; i < STGE_NRXDESC; i++) {
1689 ds = &sc->sc_rxsoft[i];
1690 if (ds->ds_mbuf != NULL) {
1691 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap);
1692 ds->ds_mbuf->m_next = NULL;
1693 m_freem(ds->ds_mbuf);
1694 ds->ds_mbuf = NULL;
1695 }
1696 }
1697 }
1698
1699 /*
1700 * stge_stop: [ ifnet interface function ]
1701 *
1702 * Stop transmission on the interface.
1703 */
1704 static void
stge_stop(struct ifnet * ifp,int disable)1705 stge_stop(struct ifnet *ifp, int disable)
1706 {
1707 struct stge_softc *sc = ifp->if_softc;
1708 struct stge_descsoft *ds;
1709 int i;
1710
1711 /*
1712 * Stop the one second clock.
1713 */
1714 callout_stop(&sc->sc_tick_ch);
1715
1716 /* Down the MII. */
1717 mii_down(&sc->sc_mii);
1718
1719 /*
1720 * Disable interrupts.
1721 */
1722 bus_space_write_2(sc->sc_st, sc->sc_sh, STGE_IntEnable, 0);
1723
1724 /*
1725 * Stop receiver, transmitter, and stats update.
1726 */
1727 bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_MACCtrl,
1728 MC_StatisticsDisable | MC_TxDisable | MC_RxDisable);
1729
1730 /*
1731 * Stop the transmit and receive DMA.
1732 */
1733 stge_dma_wait(sc);
1734 bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_TFDListPtrHi, 0);
1735 bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_TFDListPtrLo, 0);
1736 bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_RFDListPtrHi, 0);
1737 bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_RFDListPtrLo, 0);
1738
1739 /*
1740 * Release any queued transmit buffers.
1741 */
1742 for (i = 0; i < STGE_NTXDESC; i++) {
1743 ds = &sc->sc_txsoft[i];
1744 if (ds->ds_mbuf != NULL) {
1745 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap);
1746 m_freem(ds->ds_mbuf);
1747 ds->ds_mbuf = NULL;
1748 }
1749 }
1750
1751 /*
1752 * Mark the interface down and cancel the watchdog timer.
1753 */
1754 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1755 ifp->if_timer = 0;
1756
1757 if (disable)
1758 stge_rxdrain(sc);
1759 }
1760
1761 static int
stge_eeprom_wait(struct stge_softc * sc)1762 stge_eeprom_wait(struct stge_softc *sc)
1763 {
1764 int i;
1765
1766 for (i = 0; i < STGE_TIMEOUT; i++) {
1767 delay(1000);
1768 if ((bus_space_read_2(sc->sc_st, sc->sc_sh, STGE_EepromCtrl) &
1769 EC_EepromBusy) == 0)
1770 return (0);
1771 }
1772 return (1);
1773 }
1774
1775 /*
1776 * stge_read_eeprom:
1777 *
1778 * Read data from the serial EEPROM.
1779 */
1780 static void
stge_read_eeprom(struct stge_softc * sc,int offset,uint16_t * data)1781 stge_read_eeprom(struct stge_softc *sc, int offset, uint16_t *data)
1782 {
1783
1784 if (stge_eeprom_wait(sc))
1785 printf("%s: EEPROM failed to come ready\n",
1786 device_xname(sc->sc_dev));
1787
1788 bus_space_write_2(sc->sc_st, sc->sc_sh, STGE_EepromCtrl,
1789 EC_EepromAddress(offset) | EC_EepromOpcode(EC_OP_RR));
1790 if (stge_eeprom_wait(sc))
1791 printf("%s: EEPROM read timed out\n",
1792 device_xname(sc->sc_dev));
1793 *data = bus_space_read_2(sc->sc_st, sc->sc_sh, STGE_EepromData);
1794 }
1795
1796 /*
1797 * stge_add_rxbuf:
1798 *
1799 * Add a receive buffer to the indicated descriptor.
1800 */
1801 static int
stge_add_rxbuf(struct stge_softc * sc,int idx)1802 stge_add_rxbuf(struct stge_softc *sc, int idx)
1803 {
1804 struct stge_descsoft *ds = &sc->sc_rxsoft[idx];
1805 struct mbuf *m;
1806 int error;
1807
1808 MGETHDR(m, M_DONTWAIT, MT_DATA);
1809 if (m == NULL)
1810 return (ENOBUFS);
1811
1812 MCLGET(m, M_DONTWAIT);
1813 if ((m->m_flags & M_EXT) == 0) {
1814 m_freem(m);
1815 return (ENOBUFS);
1816 }
1817
1818 m->m_data = m->m_ext.ext_buf + 2;
1819 m->m_len = MCLBYTES - 2;
1820
1821 if (ds->ds_mbuf != NULL)
1822 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap);
1823
1824 ds->ds_mbuf = m;
1825
1826 error = bus_dmamap_load(sc->sc_dmat, ds->ds_dmamap,
1827 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, BUS_DMA_NOWAIT);
1828 if (error) {
1829 printf("%s: can't load rx DMA map %d, error = %d\n",
1830 device_xname(sc->sc_dev), idx, error);
1831 panic("stge_add_rxbuf"); /* XXX */
1832 }
1833
1834 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0,
1835 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD);
1836
1837 STGE_INIT_RXDESC(sc, idx);
1838
1839 return (0);
1840 }
1841
1842 /*
1843 * stge_set_filter:
1844 *
1845 * Set up the receive filter.
1846 */
1847 static void
stge_set_filter(struct stge_softc * sc)1848 stge_set_filter(struct stge_softc *sc)
1849 {
1850 struct ethercom *ec = &sc->sc_ethercom;
1851 struct ifnet *ifp = &sc->sc_ethercom.ec_if;
1852 struct ether_multi *enm;
1853 struct ether_multistep step;
1854 uint32_t crc;
1855 uint32_t mchash[2];
1856
1857 sc->sc_ReceiveMode = RM_ReceiveUnicast;
1858 if (ifp->if_flags & IFF_BROADCAST)
1859 sc->sc_ReceiveMode |= RM_ReceiveBroadcast;
1860
1861 /* XXX: ST1023 only works in promiscuous mode */
1862 if (sc->sc_stge1023)
1863 ifp->if_flags |= IFF_PROMISC;
1864
1865 if (ifp->if_flags & IFF_PROMISC) {
1866 sc->sc_ReceiveMode |= RM_ReceiveAllFrames;
1867 goto allmulti;
1868 }
1869
1870 /*
1871 * Set up the multicast address filter by passing all multicast
1872 * addresses through a CRC generator, and then using the low-order
1873 * 6 bits as an index into the 64 bit multicast hash table. The
1874 * high order bits select the register, while the rest of the bits
1875 * select the bit within the register.
1876 */
1877
1878 memset(mchash, 0, sizeof(mchash));
1879
1880 ETHER_FIRST_MULTI(step, ec, enm);
1881 if (enm == NULL)
1882 goto done;
1883
1884 while (enm != NULL) {
1885 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) {
1886 /*
1887 * We must listen to a range of multicast addresses.
1888 * For now, just accept all multicasts, rather than
1889 * trying to set only those filter bits needed to match
1890 * the range. (At this time, the only use of address
1891 * ranges is for IP multicast routing, for which the
1892 * range is big enough to require all bits set.)
1893 */
1894 goto allmulti;
1895 }
1896
1897 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN);
1898
1899 /* Just want the 6 least significant bits. */
1900 crc &= 0x3f;
1901
1902 /* Set the corresponding bit in the hash table. */
1903 mchash[crc >> 5] |= 1 << (crc & 0x1f);
1904
1905 ETHER_NEXT_MULTI(step, enm);
1906 }
1907
1908 sc->sc_ReceiveMode |= RM_ReceiveMulticastHash;
1909
1910 ifp->if_flags &= ~IFF_ALLMULTI;
1911 goto done;
1912
1913 allmulti:
1914 ifp->if_flags |= IFF_ALLMULTI;
1915 sc->sc_ReceiveMode |= RM_ReceiveMulticast;
1916
1917 done:
1918 if ((ifp->if_flags & IFF_ALLMULTI) == 0) {
1919 /*
1920 * Program the multicast hash table.
1921 */
1922 bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_HashTable0,
1923 mchash[0]);
1924 bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_HashTable1,
1925 mchash[1]);
1926 }
1927
1928 bus_space_write_2(sc->sc_st, sc->sc_sh, STGE_ReceiveMode,
1929 sc->sc_ReceiveMode);
1930 }
1931
1932 /*
1933 * stge_mii_readreg: [mii interface function]
1934 *
1935 * Read a PHY register on the MII of the TC9021.
1936 */
1937 static int
stge_mii_readreg(device_t self,int phy,int reg)1938 stge_mii_readreg(device_t self, int phy, int reg)
1939 {
1940
1941 return (mii_bitbang_readreg(self, &stge_mii_bitbang_ops, phy, reg));
1942 }
1943
1944 /*
1945 * stge_mii_writereg: [mii interface function]
1946 *
1947 * Write a PHY register on the MII of the TC9021.
1948 */
1949 static void
stge_mii_writereg(device_t self,int phy,int reg,int val)1950 stge_mii_writereg(device_t self, int phy, int reg, int val)
1951 {
1952
1953 mii_bitbang_writereg(self, &stge_mii_bitbang_ops, phy, reg, val);
1954 }
1955
1956 /*
1957 * stge_mii_statchg: [mii interface function]
1958 *
1959 * Callback from MII layer when media changes.
1960 */
1961 static void
stge_mii_statchg(struct ifnet * ifp)1962 stge_mii_statchg(struct ifnet *ifp)
1963 {
1964 struct stge_softc *sc = ifp->if_softc;
1965
1966 if (sc->sc_mii.mii_media_active & IFM_FDX)
1967 sc->sc_MACCtrl |= MC_DuplexSelect;
1968 else
1969 sc->sc_MACCtrl &= ~MC_DuplexSelect;
1970
1971 /* XXX 802.1x flow-control? */
1972
1973 bus_space_write_4(sc->sc_st, sc->sc_sh, STGE_MACCtrl, sc->sc_MACCtrl);
1974 }
1975
1976 /*
1977 * sste_mii_bitbang_read: [mii bit-bang interface function]
1978 *
1979 * Read the MII serial port for the MII bit-bang module.
1980 */
1981 static uint32_t
stge_mii_bitbang_read(device_t self)1982 stge_mii_bitbang_read(device_t self)
1983 {
1984 struct stge_softc *sc = device_private(self);
1985
1986 return (bus_space_read_1(sc->sc_st, sc->sc_sh, STGE_PhyCtrl));
1987 }
1988
1989 /*
1990 * stge_mii_bitbang_write: [mii big-bang interface function]
1991 *
1992 * Write the MII serial port for the MII bit-bang module.
1993 */
1994 static void
stge_mii_bitbang_write(device_t self,uint32_t val)1995 stge_mii_bitbang_write(device_t self, uint32_t val)
1996 {
1997 struct stge_softc *sc = device_private(self);
1998
1999 bus_space_write_1(sc->sc_st, sc->sc_sh, STGE_PhyCtrl,
2000 val | sc->sc_PhyCtrl);
2001 }
2002