1 /* $NetBSD: ifpci2.c,v 1.22 2014/03/29 19:28:25 christos Exp $ */
2 /*
3 * Copyright (c) 1999 Gary Jennejohn. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. Neither the name of the author nor the names of any co-contributors
15 * may be used to endorse or promote products derived from this software
16 * without specific prior written permission.
17 * 4. Altered versions must be plainly marked as such, and must not be
18 * misrepresented as being the original software and/or documentation.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
24 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 * SUCH DAMAGE.
31 *
32 *---------------------------------------------------------------------------
33 * a lot of code was borrowed from i4b_bchan.c and i4b_hscx.c
34 *---------------------------------------------------------------------------
35 *
36 * Fritz!Card PCI driver
37 * ------------------------------------------------
38 *
39 * $Id: ifpci2.c,v 1.22 2014/03/29 19:28:25 christos Exp $
40 *
41 * last edit-date: [Fri Jan 5 11:38:58 2001]
42 *
43 *---------------------------------------------------------------------------*/
44
45 #include <sys/cdefs.h>
46 __KERNEL_RCSID(0, "$NetBSD: ifpci2.c,v 1.22 2014/03/29 19:28:25 christos Exp $");
47
48
49 #include <sys/param.h>
50 #include <sys/ioctl.h>
51 #include <sys/kernel.h>
52 #include <sys/systm.h>
53 #include <sys/mbuf.h>
54
55 #include <sys/bus.h>
56 #include <sys/device.h>
57
58 #include <sys/socket.h>
59 #include <net/if.h>
60
61 #include <sys/callout.h>
62
63 #include <dev/pci/pcireg.h>
64 #include <dev/pci/pcivar.h>
65 #include <dev/pci/pcidevs.h>
66 #include <netisdn/i4b_debug.h>
67 #include <netisdn/i4b_ioctl.h>
68
69 #include <netisdn/i4b_global.h>
70 #include <netisdn/i4b_l2.h>
71 #include <netisdn/i4b_l1l2.h>
72 #include <netisdn/i4b_trace.h>
73 #include <netisdn/i4b_mbuf.h>
74
75 #include <dev/ic/isic_l1.h>
76 #include <dev/ic/isacsx.h>
77 #include <dev/ic/hscx.h>
78
79 #include <dev/pci/isic_pci.h>
80
81 /* PCI config map to use (only one in this driver) */
82 #define FRITZPCI_PORT0_IO_MAPOFF PCI_MAPREG_START+4
83 #define FRITZPCI_PORT0_MEM_MAPOFF PCI_MAPREG_START
84
85 static isdn_link_t *avma1pp2_ret_linktab(void *token, int channel);
86 static void avma1pp2_set_link(void *token, int channel, const struct isdn_l4_driver_functions *l4_driver, void *l4_driver_softc);
87
88 void n_connect_request(struct call_desc *cd);
89 void n_connect_response(struct call_desc *cd, int response, int cause);
90 void n_disconnect_request(struct call_desc *cd, int cause);
91 void n_alert_request(struct call_desc *cd);
92 void n_mgmt_command(struct isdn_l3_driver *drv, int cmd, void *parm);
93
94 extern const struct isdn_layer1_isdnif_driver isic_std_driver;
95
96 const struct isdn_l3_driver_functions
97 ifpci2_l3_driver = {
98 avma1pp2_ret_linktab,
99 avma1pp2_set_link,
100 n_connect_request,
101 n_connect_response,
102 n_disconnect_request,
103 n_alert_request,
104 NULL,
105 NULL,
106 n_mgmt_command
107 };
108
109 struct ifpci_softc {
110 struct isic_softc sc_isic; /* parent class */
111
112 /* PCI-specific goo */
113 void *sc_ih; /* interrupt handler */
114 bus_addr_t sc_base;
115 bus_size_t sc_size;
116 pci_chipset_tag_t sc_pc;
117 };
118
119 /* prototypes */
120 static void avma1pp2_disable(struct isic_softc *);
121 static int isic_hscx_fifo(l1_bchan_state_t *chan, struct isic_softc *sc);
122
123 static int avma1pp2_intr(void*);
124 static void avma1pp2_read_fifo(struct isic_softc *sc, int what, void *buf, size_t size);
125 static void avma1pp2_write_fifo(struct isic_softc *sc, int what, const void *buf, size_t size);
126 static void avma1pp2_write_reg(struct isic_softc *sc, int what, bus_size_t offs, u_int8_t data);
127 static u_int8_t avma1pp2_read_reg(struct isic_softc *sc, int what, bus_size_t offs);
128 static void hscx_write_fifo(int chan, const void *buf, size_t len, struct isic_softc *sc);
129 static void hscx_read_fifo(int chan, void *buf, size_t len, struct isic_softc *sc);
130 static void hscx_write_reg(int chan, u_int val, struct isic_softc *sc);
131 static u_char hscx_read_reg(int chan, struct isic_softc *sc);
132 static u_int hscx_read_reg_int(int chan, struct isic_softc *sc);
133 static void avma1pp2_bchannel_stat(isdn_layer1token, int h_chan, bchan_statistics_t *bsp);
134 static void avma1pp2_map_int(struct ifpci_softc *sc, struct pci_attach_args *pa);
135 static void avma1pp2_bchannel_setup(isdn_layer1token, int h_chan, int bprot, int activate);
136 static void avma1pp2_init_linktab(struct isic_softc *);
137 static int ifpci2_match(device_t parent, cfdata_t match, void *aux);
138 static void ifpci2_attach(device_t parent, device_t self, void *aux);
139 static int ifpci2_detach(device_t self, int flags);
140 static int ifpci2_activate(device_t self, enum devact act);
141
142 CFATTACH_DECL_NEW(ifritz, sizeof(struct ifpci_softc),
143 ifpci2_match, ifpci2_attach, ifpci2_detach, ifpci2_activate);
144
145 /*---------------------------------------------------------------------------*
146 * AVM PCI Fritz!Card V. 2 special registers
147 *---------------------------------------------------------------------------*/
148
149 /*
150 * AVM PCI Status Latch 0 read only bits
151 */
152 #define ASL_IRQ_ISAC 0x01 /* ISAC interrupt, active high */
153 #define ASL_IRQ_HSCX 0x02 /* HSX interrupt, active high */
154 #define ASL_IRQ_TIMER 0x04 /* Timer interrupt, active high */
155 #define ASL_IRQ_BCHAN ASL_IRQ_HSCX
156 /* actually active high */
157 #define ASL_IRQ_Pending (ASL_IRQ_ISAC | ASL_IRQ_HSCX | ASL_IRQ_TIMER)
158
159 /*
160 * AVM PCI Status Latch 0 read only bits
161 */
162 #define ASL_RESET 0x01
163 #define ASL_TIMERRESET 0x04
164 #define ASL_ENABLE_INT 0x08
165
166 /*
167 * "HSCX" status bits
168 */
169 #define HSCX_STAT_RME 0x01
170 #define HSCX_STAT_RDO 0x10
171 #define HSCX_STAT_CRCVFRRAB 0x0E
172 #define HSCX_STAT_CRCVFR 0x06
173 #define HSCX_STAT_RML_MASK 0x3f00
174
175 /*
176 * "HSCX" interrupt bits
177 */
178 #define HSCX_INT_XPR 0x80
179 #define HSCX_INT_XDU 0x40
180 #define HSCX_INT_RPR 0x20
181 #define HSCX_INT_MASK 0xE0
182
183 /*
184 * "HSCX" command bits
185 */
186 #define HSCX_CMD_XRS 0x80
187 #define HSCX_CMD_XME 0x01
188 #define HSCX_CMD_RRS 0x20
189 #define HSCX_CMD_XML_MASK 0x3f00
190
191 /* "HSCX" mode bits */
192 #define HSCX_MODE_ITF_FLG 0x01
193 #define HSCX_MODE_TRANS 0x02
194
195 /* offsets to various registers in the ASIC, evidently */
196 #define STAT0_OFFSET 0x02
197
198 #define HSCX_FIFO1 0x10
199 #define HSCX_FIFO2 0x18
200
201 #define HSCX_STAT1 0x14
202 #define HSCX_STAT2 0x1c
203
204 #define ISACSX_INDEX 0x04
205 #define ISACSX_DATA 0x08
206
207 /*
208 * Commands and parameters are sent to the "HSCX" as a long, but the
209 * fields are handled as bytes.
210 *
211 * The long contains:
212 * (prot << 16)|(txl << 8)|cmd
213 *
214 * where:
215 * prot = protocol to use
216 * txl = transmit length
217 * cmd = the command to be executed
218 *
219 * The fields are defined as u_char in struct l1_softc.
220 *
221 * Macro to coalesce the byte fields into a u_int
222 */
223 #define AVMA1PPSETCMDLONG(f) (f) = ((sc->avma1pp_cmd) | (sc->avma1pp_txl << 8) \
224 | (sc->avma1pp_prot << 16))
225
226 /*
227 * to prevent deactivating the "HSCX" when both channels are active we
228 * define an HSCX_ACTIVE flag which is or'd into the channel's state
229 * flag in avma1pp2_bchannel_setup upon active and cleared upon deactivation.
230 * It is set high to allow room for new flags.
231 */
232 #define HSCX_AVMA1PP_ACTIVE 0x1000
233
234 static int
ifpci2_match(device_t parent,cfdata_t match,void * aux)235 ifpci2_match(device_t parent, cfdata_t match, void *aux)
236 {
237 struct pci_attach_args *pa = aux;
238
239 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_AVM &&
240 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_AVM_FRITZ_PCI_V2_ISDN)
241 return 1;
242 return 0;
243 }
244
245 static void
ifpci2_attach(device_t parent,device_t self,void * aux)246 ifpci2_attach(device_t parent, device_t self, void *aux)
247 {
248 struct ifpci_softc *psc = device_private(self);
249 struct pci_attach_args *pa = aux;
250 struct isic_softc *sc = &psc->sc_isic;
251 struct isdn_l3_driver *drv;
252
253 sc->sc_dev = self;
254
255 /* announce */
256 printf(": Fritz!PCI V2 card\n");
257
258 /* initialize sc */
259 callout_init(&sc->sc_T3_callout, 0);
260 callout_init(&sc->sc_T4_callout, 0);
261
262 /* setup io mappings */
263 sc->sc_num_mappings = 1;
264 MALLOC_MAPS(sc);
265 sc->sc_maps[0].size = 0;
266 if (pci_mapreg_map(pa, FRITZPCI_PORT0_IO_MAPOFF, PCI_MAPREG_TYPE_IO, 0,
267 &sc->sc_maps[0].t, &sc->sc_maps[0].h, &psc->sc_base, &psc->sc_size) != 0) {
268 aprint_error_dev(sc->sc_dev, "can't map card\n");
269 return;
270 }
271
272 /* setup access routines */
273
274 sc->clearirq = NULL;
275 sc->readreg = avma1pp2_read_reg;
276 sc->writereg = avma1pp2_write_reg;
277
278 sc->readfifo = avma1pp2_read_fifo;
279 sc->writefifo = avma1pp2_write_fifo;
280
281
282 /* setup card type */
283
284 sc->sc_cardtyp = CARD_TYPEP_AVMA1PCIV2;
285
286 /* setup IOM bus type */
287
288 sc->sc_bustyp = BUS_TYPE_IOM2;
289
290 /* this is no IPAC based card */
291 sc->sc_ipac = 0;
292 sc->sc_bfifolen = HSCX_FIFO_LEN;
293
294 /* setup interrupt mapping */
295 avma1pp2_map_int(psc, pa);
296
297 /* init the card */
298
299 bus_space_read_4(sc->sc_maps[0].t, sc->sc_maps[0].h, 0);
300 bus_space_write_1(sc->sc_maps[0].t, sc->sc_maps[0].h, STAT0_OFFSET, 0);
301 DELAY(SEC_DELAY/20); /* 50 ms */
302 bus_space_write_1(sc->sc_maps[0].t, sc->sc_maps[0].h, STAT0_OFFSET, ASL_RESET);
303 DELAY(SEC_DELAY/20); /* 50 ms */
304 bus_space_write_1(sc->sc_maps[0].t, sc->sc_maps[0].h, STAT0_OFFSET, 0);
305 DELAY(SEC_DELAY/20); /* 50 ms */
306
307 bus_space_write_1(sc->sc_maps[0].t, sc->sc_maps[0].h, STAT0_OFFSET, ASL_TIMERRESET);
308 DELAY(SEC_DELAY/100); /* 10 ms */
309 bus_space_write_1(sc->sc_maps[0].t, sc->sc_maps[0].h, STAT0_OFFSET, ASL_ENABLE_INT);
310 DELAY(SEC_DELAY/100); /* 10 ms */
311
312 /* setup i4b infrastructure (have to roll our own here) */
313
314 /* sc->sc_isac_version = ((ISAC_READ(I_RBCH)) >> 5) & 0x03; */
315 printf("%s: ISACSX %s\n", device_xname(sc->sc_dev), "PSB3186");
316
317 /* init the ISAC */
318 isic_isacsx_init(sc);
319
320 ISAC_READ(I_CIR0); /* Leo: reset generates status change */
321
322 /* init the "HSCX" */
323 avma1pp2_bchannel_setup(sc, HSCX_CH_A, BPROT_NONE, 0);
324
325 avma1pp2_bchannel_setup(sc, HSCX_CH_B, BPROT_NONE, 0);
326
327 /* can't use the normal B-Channel stuff */
328 avma1pp2_init_linktab(sc);
329
330 /* set trace level */
331
332 sc->sc_trace = TRACE_OFF;
333
334 sc->sc_state = ISAC_IDLE;
335
336 sc->sc_ibuf = NULL;
337 sc->sc_ib = NULL;
338 sc->sc_ilen = 0;
339
340 sc->sc_obuf = NULL;
341 sc->sc_op = NULL;
342 sc->sc_ol = 0;
343 sc->sc_freeflag = 0;
344
345 sc->sc_obuf2 = NULL;
346 sc->sc_freeflag2 = 0;
347
348 /* init higher protocol layers */
349 drv = isdn_attach_isdnif(device_xname(sc->sc_dev),
350 "AVM Fritz!PCI V2", &sc->sc_l2, &ifpci2_l3_driver, NBCH_BRI);
351 sc->sc_l3token = drv;
352 sc->sc_l2.driver = &isic_std_driver;
353 sc->sc_l2.l1_token = sc;
354 sc->sc_l2.drv = drv;
355 isdn_layer2_status_ind(&sc->sc_l2, drv, STI_ATTACH, 1);
356 isdn_isdnif_ready(drv->isdnif);
357 }
358
359 static int
ifpci2_detach(device_t self,int flags)360 ifpci2_detach(device_t self, int flags)
361 {
362 struct ifpci_softc *psc = device_private(self);
363
364 bus_space_unmap(psc->sc_isic.sc_maps[0].t, psc->sc_isic.sc_maps[0].h, psc->sc_size);
365 bus_space_free(psc->sc_isic.sc_maps[0].t, psc->sc_isic.sc_maps[0].h, psc->sc_size);
366 pci_intr_disestablish(psc->sc_pc, psc->sc_ih);
367
368 return (0);
369 }
370
371 int
ifpci2_activate(device_t self,enum devact act)372 ifpci2_activate(device_t self, enum devact act)
373 {
374 struct ifpci_softc *psc = device_private(self);
375
376 switch (act) {
377 case DVACT_DEACTIVATE:
378 psc->sc_isic.sc_intr_valid = ISIC_INTR_DYING;
379 isdn_layer2_status_ind(&psc->sc_isic.sc_l2, psc->sc_isic.sc_l3token, STI_ATTACH, 0);
380 isdn_detach_isdnif(psc->sc_isic.sc_l3token);
381 psc->sc_isic.sc_l3token = NULL;
382 return 0;
383 default:
384 return EOPNOTSUPP;
385 }
386 }
387
388 /*---------------------------------------------------------------------------*
389 * AVM read fifo routines
390 *---------------------------------------------------------------------------*/
391
392 static void
avma1pp2_read_fifo(struct isic_softc * sc,int what,void * buf,size_t size)393 avma1pp2_read_fifo(struct isic_softc *sc, int what, void *buf, size_t size)
394 {
395 int i;
396
397 switch (what) {
398 case ISIC_WHAT_ISAC:
399 bus_space_write_4(sc->sc_maps[0].t, sc->sc_maps[0].h, ISACSX_INDEX, 0);
400 /* evidently each byte must be read as a long */
401 for (i = 0; i < size; i++)
402 ((u_int8_t *)buf)[i] = (u_int8_t)bus_space_read_4(sc->sc_maps[0].t, sc->sc_maps[0].h, ISACSX_DATA);
403 break;
404 case ISIC_WHAT_HSCXA:
405 hscx_read_fifo(0, buf, size, sc);
406 break;
407 case ISIC_WHAT_HSCXB:
408 hscx_read_fifo(1, buf, size, sc);
409 break;
410 }
411 }
412
413 static void
hscx_read_fifo(int chan,void * buf,size_t len,struct isic_softc * sc)414 hscx_read_fifo(int chan, void *buf, size_t len, struct isic_softc *sc)
415 {
416 int dataoff;
417
418 dataoff = chan ? HSCX_FIFO2 : HSCX_FIFO1;
419 bus_space_read_multi_stream_4(sc->sc_maps[0].t, sc->sc_maps[0].h,
420 dataoff, buf, len/4);
421 if (__predict_false((len&3)>0)) {
422 uint32_t tmp;
423
424 buf = ((unsigned char*)buf) + (len & ~3u);
425 len &= 3u;
426 tmp = bus_space_read_stream_4(sc->sc_maps[0].t,
427 sc->sc_maps[0].h, dataoff);
428 memcpy(buf, &tmp, len);
429 }
430 }
431
432 /*---------------------------------------------------------------------------*
433 * AVM write fifo routines
434 *---------------------------------------------------------------------------*/
435
436 static void
avma1pp2_write_fifo(struct isic_softc * sc,int what,const void * buf,size_t size)437 avma1pp2_write_fifo(struct isic_softc *sc, int what, const void *buf, size_t size)
438 {
439 int i;
440
441 switch (what) {
442 case ISIC_WHAT_ISAC:
443 bus_space_write_4(sc->sc_maps[0].t, sc->sc_maps[0].h, ISACSX_INDEX, 0);
444 /* evidently each byte must be written as a long */
445 for (i = 0; i < size; i++)
446 bus_space_write_4(sc->sc_maps[0].t, sc->sc_maps[0].h, ISACSX_DATA, ((const unsigned char *)buf)[i]);
447 break;
448 case ISIC_WHAT_HSCXA:
449 hscx_write_fifo(0, buf, size, sc);
450 break;
451 case ISIC_WHAT_HSCXB:
452 hscx_write_fifo(1, buf, size, sc);
453 break;
454 }
455 }
456
457 static void
hscx_write_fifo(int chan,const void * buf,size_t len,struct isic_softc * sc)458 hscx_write_fifo(int chan, const void *buf, size_t len, struct isic_softc *sc)
459 {
460 size_t cnt;
461 int dataoff;
462 l1_bchan_state_t *Bchan = &sc->sc_chan[chan];
463
464 dataoff = chan ? HSCX_FIFO2 : HSCX_FIFO1;
465
466 sc->avma1pp_cmd &= ~HSCX_CMD_XME;
467 sc->avma1pp_txl = 0;
468 if (Bchan->out_mbuf_cur == NULL)
469 {
470 if (Bchan->bprot != BPROT_NONE)
471 sc->avma1pp_cmd |= HSCX_CMD_XME;
472 }
473 if (len != sc->sc_bfifolen)
474 sc->avma1pp_txl = len;
475
476 cnt = 0; /* borrow cnt */
477 AVMA1PPSETCMDLONG(cnt);
478 hscx_write_reg(chan, cnt, sc);
479
480 bus_space_write_multi_stream_4(sc->sc_maps[0].t, sc->sc_maps[0].h,
481 dataoff, buf, (len+3)/4);
482 if (__predict_false((len&3)>0)) {
483 uint32_t tmp;
484
485 buf = (const unsigned char*)buf + (len & ~3u);
486 len &= 3u;
487 memset(&tmp, 0, sizeof(tmp));
488 memcpy(&tmp, buf, len);
489 bus_space_write_stream_4(sc->sc_maps[0].t, sc->sc_maps[0].h,
490 dataoff, tmp);
491 }
492 }
493
494 /*---------------------------------------------------------------------------*
495 * AVM write register routines
496 *---------------------------------------------------------------------------*/
497
498 static void
avma1pp2_write_reg(struct isic_softc * sc,int what,bus_size_t offs,u_int8_t data)499 avma1pp2_write_reg(struct isic_softc *sc, int what, bus_size_t offs, u_int8_t data)
500 {
501 switch (what) {
502 case ISIC_WHAT_ISAC:
503 bus_space_write_4(sc->sc_maps[0].t, sc->sc_maps[0].h, ISACSX_INDEX, offs);
504 bus_space_write_4(sc->sc_maps[0].t, sc->sc_maps[0].h, ISACSX_DATA, data);
505 break;
506 case ISIC_WHAT_HSCXA:
507 hscx_write_reg(0, data, sc);
508 break;
509 case ISIC_WHAT_HSCXB:
510 hscx_write_reg(1, data, sc);
511 break;
512 }
513 }
514
515 static void
hscx_write_reg(int chan,u_int val,struct isic_softc * sc)516 hscx_write_reg(int chan, u_int val, struct isic_softc *sc)
517 {
518 u_int off;
519
520 off = (chan == 0 ? HSCX_STAT1 : HSCX_STAT2);
521 bus_space_write_4(sc->sc_maps[0].t, sc->sc_maps[0].h, off, val);
522 }
523
524 /*---------------------------------------------------------------------------*
525 * AVM read register routines
526 *---------------------------------------------------------------------------*/
527
528 static u_int8_t
avma1pp2_read_reg(struct isic_softc * sc,int what,bus_size_t offs)529 avma1pp2_read_reg(struct isic_softc *sc, int what, bus_size_t offs)
530 {
531 u_int8_t val;
532
533 switch (what) {
534 case ISIC_WHAT_ISAC:
535 bus_space_write_4(sc->sc_maps[0].t, sc->sc_maps[0].h, ISACSX_INDEX, offs);
536 val = (u_int8_t)bus_space_read_4(sc->sc_maps[0].t, sc->sc_maps[0].h, ISACSX_DATA);
537 return(val);
538 case ISIC_WHAT_HSCXA:
539 return hscx_read_reg(0, sc);
540 case ISIC_WHAT_HSCXB:
541 return hscx_read_reg(1, sc);
542 }
543 return 0;
544 }
545
546 static u_char
hscx_read_reg(int chan,struct isic_softc * sc)547 hscx_read_reg(int chan, struct isic_softc *sc)
548 {
549 return(hscx_read_reg_int(chan, sc) & 0xff);
550 }
551
552 /*
553 * need to be able to return an int because the RBCH is in the 2nd
554 * byte.
555 */
556 static u_int
hscx_read_reg_int(int chan,struct isic_softc * sc)557 hscx_read_reg_int(int chan, struct isic_softc *sc)
558 {
559 u_int off;
560
561 off = (chan == 0 ? HSCX_STAT1 : HSCX_STAT2);
562 return(bus_space_read_4(sc->sc_maps[0].t, sc->sc_maps[0].h, off));
563 }
564
565 /*
566 * this is the real interrupt routine
567 */
568 static void
avma1pp2_hscx_intr(int h_chan,u_int stat,struct isic_softc * sc)569 avma1pp2_hscx_intr(int h_chan, u_int stat, struct isic_softc *sc)
570 {
571 register l1_bchan_state_t *chan = &sc->sc_chan[h_chan];
572 int activity = -1;
573 u_int param = 0;
574
575 NDBGL1(L1_H_IRQ, "%#x", stat);
576
577 if((stat & HSCX_INT_XDU) && (chan->bprot != BPROT_NONE))/* xmit data underrun */
578 {
579 chan->stat_XDU++;
580 NDBGL1(L1_H_XFRERR, "xmit data underrun");
581 /* abort the transmission */
582 sc->avma1pp_txl = 0;
583 sc->avma1pp_cmd |= HSCX_CMD_XRS;
584 AVMA1PPSETCMDLONG(param);
585 hscx_write_reg(h_chan, param, sc);
586 sc->avma1pp_cmd &= ~HSCX_CMD_XRS;
587 AVMA1PPSETCMDLONG(param);
588 hscx_write_reg(h_chan, param, sc);
589
590 if (chan->out_mbuf_head != NULL) /* don't continue to transmit this buffer */
591 {
592 i4b_Bfreembuf(chan->out_mbuf_head);
593 chan->out_mbuf_cur = chan->out_mbuf_head = NULL;
594 }
595 }
596
597 /*
598 * The following is based on examination of the Linux driver.
599 *
600 * The logic here is different than with a "real" HSCX; all kinds
601 * of information (interrupt/status bits) are in stat.
602 * HSCX_INT_RPR indicates a receive interrupt
603 * HSCX_STAT_RDO indicates an overrun condition, abort -
604 * otherwise read the bytes ((stat & HSCX_STZT_RML_MASK) >> 8)
605 * HSCX_STAT_RME indicates end-of-frame and apparently any
606 * CRC/framing errors are only reported in this state.
607 * if ((stat & HSCX_STAT_CRCVFRRAB) != HSCX_STAT_CRCVFR)
608 * CRC/framing error
609 */
610
611 if(stat & HSCX_INT_RPR)
612 {
613 register int fifo_data_len;
614 int error = 0;
615 /* always have to read the FIFO, so use a scratch buffer */
616 u_char scrbuf[HSCX_FIFO_LEN];
617
618 if(stat & HSCX_STAT_RDO)
619 {
620 chan->stat_RDO++;
621 NDBGL1(L1_H_XFRERR, "receive data overflow");
622 error++;
623 }
624
625 /*
626 * check whether we're receiving data for an inactive B-channel
627 * and discard it. This appears to happen for telephony when
628 * both B-channels are active and one is deactivated. Since
629 * it is not really possible to deactivate the channel in that
630 * case (the ASIC seems to deactivate _both_ channels), the
631 * "deactivated" channel keeps receiving data which can lead
632 * to exhaustion of mbufs and a kernel panic.
633 *
634 * This is a hack, but it's the only solution I can think of
635 * without having the documentation for the ASIC.
636 * GJ - 28 Nov 1999
637 */
638 if (chan->state == HSCX_IDLE)
639 {
640 NDBGL1(L1_H_XFRERR, "toss data from %d", h_chan);
641 error++;
642 }
643
644 fifo_data_len = ((stat & HSCX_STAT_RML_MASK) >> 8);
645
646 if(fifo_data_len == 0)
647 fifo_data_len = sc->sc_bfifolen;
648
649 /* ALWAYS read data from HSCX fifo */
650
651 HSCX_RDFIFO(h_chan, scrbuf, fifo_data_len);
652 chan->rxcount += fifo_data_len;
653
654 /* all error conditions checked, now decide and take action */
655
656 if(error == 0)
657 {
658 if(chan->in_mbuf == NULL)
659 {
660 if((chan->in_mbuf = i4b_Bgetmbuf(BCH_MAX_DATALEN)) == NULL)
661 panic("L1 avma1pp2_hscx_intr: RME, cannot allocate mbuf!");
662 chan->in_cbptr = chan->in_mbuf->m_data;
663 chan->in_len = 0;
664 }
665
666 if((chan->in_len + fifo_data_len) <= BCH_MAX_DATALEN)
667 {
668 /* OK to copy the data */
669 memcpy(chan->in_cbptr, scrbuf, fifo_data_len);
670 chan->in_cbptr += fifo_data_len;
671 chan->in_len += fifo_data_len;
672
673 /* setup mbuf data length */
674
675 chan->in_mbuf->m_len = chan->in_len;
676 chan->in_mbuf->m_pkthdr.len = chan->in_len;
677
678 if(sc->sc_trace & TRACE_B_RX)
679 {
680 struct i4b_trace_hdr hdr;
681 hdr.type = (h_chan == HSCX_CH_A ? TRC_CH_B1 : TRC_CH_B2);
682 hdr.dir = FROM_NT;
683 hdr.count = ++sc->sc_trace_bcount;
684 isdn_layer2_trace_ind(&sc->sc_l2, sc->sc_l3token, &hdr, chan->in_mbuf->m_len, chan->in_mbuf->m_data);
685 }
686
687 if (stat & HSCX_STAT_RME)
688 {
689 if((stat & HSCX_STAT_CRCVFRRAB) == HSCX_STAT_CRCVFR)
690 {
691 (*chan->l4_driver->bch_rx_data_ready)(chan->l4_driver_softc);
692 activity = ACT_RX;
693
694 /* mark buffer ptr as unused */
695
696 chan->in_mbuf = NULL;
697 chan->in_cbptr = NULL;
698 chan->in_len = 0;
699 }
700 else
701 {
702 chan->stat_CRC++;
703 NDBGL1(L1_H_XFRERR, "CRC/RAB");
704 if (chan->in_mbuf != NULL)
705 {
706 i4b_Bfreembuf(chan->in_mbuf);
707 chan->in_mbuf = NULL;
708 chan->in_cbptr = NULL;
709 chan->in_len = 0;
710 }
711 }
712 }
713 } /* END enough space in mbuf */
714 else
715 {
716 if(chan->bprot == BPROT_NONE)
717 {
718 /* setup mbuf data length */
719
720 chan->in_mbuf->m_len = chan->in_len;
721 chan->in_mbuf->m_pkthdr.len = chan->in_len;
722
723 if(sc->sc_trace & TRACE_B_RX)
724 {
725 struct i4b_trace_hdr hdr;
726 hdr.type = (h_chan == HSCX_CH_A ? TRC_CH_B1 : TRC_CH_B2);
727 hdr.dir = FROM_NT;
728 hdr.count = ++sc->sc_trace_bcount;
729 isdn_layer2_trace_ind(&sc->sc_l2, sc->sc_l3token, &hdr, chan->in_mbuf->m_len, chan->in_mbuf->m_data);
730 }
731
732 if(!(isdn_bchan_silence(chan->in_mbuf->m_data, chan->in_mbuf->m_len)))
733 activity = ACT_RX;
734
735 /* move rx'd data to rx queue */
736
737 if (!(IF_QFULL(&chan->rx_queue)))
738 {
739 IF_ENQUEUE(&chan->rx_queue, chan->in_mbuf);
740 }
741 else
742 {
743 i4b_Bfreembuf(chan->in_mbuf);
744 }
745
746 /* signal upper layer that data are available */
747 (*chan->l4_driver->bch_rx_data_ready)(chan->l4_driver_softc);
748
749 /* alloc new buffer */
750
751 if((chan->in_mbuf = i4b_Bgetmbuf(BCH_MAX_DATALEN)) == NULL)
752 panic("L1 avma1pp2_hscx_intr: RPF, cannot allocate new mbuf!");
753
754 /* setup new data ptr */
755
756 chan->in_cbptr = chan->in_mbuf->m_data;
757
758 /* OK to copy the data */
759 memcpy(chan->in_cbptr, scrbuf, fifo_data_len);
760
761 chan->in_cbptr += fifo_data_len;
762 chan->in_len = fifo_data_len;
763
764 chan->rxcount += fifo_data_len;
765 }
766 else
767 {
768 NDBGL1(L1_H_XFRERR, "RAWHDLC rx buffer overflow in RPF, in_len=%d", chan->in_len);
769 chan->in_cbptr = chan->in_mbuf->m_data;
770 chan->in_len = 0;
771 }
772 }
773 } /* if(error == 0) */
774 else
775 {
776 /* land here for RDO */
777 if (chan->in_mbuf != NULL)
778 {
779 i4b_Bfreembuf(chan->in_mbuf);
780 chan->in_mbuf = NULL;
781 chan->in_cbptr = NULL;
782 chan->in_len = 0;
783 }
784 sc->avma1pp_txl = 0;
785 sc->avma1pp_cmd |= HSCX_CMD_RRS;
786 AVMA1PPSETCMDLONG(param);
787 hscx_write_reg(h_chan, param, sc);
788 sc->avma1pp_cmd &= ~HSCX_CMD_RRS;
789 AVMA1PPSETCMDLONG(param);
790 hscx_write_reg(h_chan, param, sc);
791 }
792 }
793
794
795 /* transmit fifo empty, new data can be written to fifo */
796
797 if(stat & HSCX_INT_XPR)
798 {
799 /*
800 * for a description what is going on here, please have
801 * a look at isic_bchannel_start() in i4b_bchan.c !
802 */
803
804 NDBGL1(L1_H_IRQ, "%s: chan %d - XPR, Tx Fifo Empty!", device_xname(sc->sc_dev), h_chan);
805
806 if(chan->out_mbuf_cur == NULL) /* last frame is transmitted */
807 {
808 IF_DEQUEUE(&chan->tx_queue, chan->out_mbuf_head);
809
810 if(chan->out_mbuf_head == NULL)
811 {
812 chan->state &= ~HSCX_TX_ACTIVE;
813 (*chan->l4_driver->bch_tx_queue_empty)(chan->l4_driver_softc);
814 }
815 else
816 {
817 chan->state |= HSCX_TX_ACTIVE;
818 chan->out_mbuf_cur = chan->out_mbuf_head;
819 chan->out_mbuf_cur_ptr = chan->out_mbuf_cur->m_data;
820 chan->out_mbuf_cur_len = chan->out_mbuf_cur->m_len;
821
822 if(sc->sc_trace & TRACE_B_TX)
823 {
824 struct i4b_trace_hdr hdr;
825 hdr.type = (h_chan == HSCX_CH_A ? TRC_CH_B1 : TRC_CH_B2);
826 hdr.dir = FROM_TE;
827 hdr.count = ++sc->sc_trace_bcount;
828 isdn_layer2_trace_ind(&sc->sc_l2, sc->sc_l3token, &hdr, chan->out_mbuf_cur->m_len, chan->out_mbuf_cur->m_data);
829 }
830
831 if(chan->bprot == BPROT_NONE)
832 {
833 if(!(isdn_bchan_silence(chan->out_mbuf_cur->m_data, chan->out_mbuf_cur->m_len)))
834 activity = ACT_TX;
835 }
836 else
837 {
838 activity = ACT_TX;
839 }
840 }
841 }
842
843 isic_hscx_fifo(chan, sc);
844 }
845
846 /* call timeout handling routine */
847
848 if(activity == ACT_RX || activity == ACT_TX)
849 (*chan->l4_driver->bch_activity)(chan->l4_driver_softc, activity);
850 }
851
852 /*
853 * this is the main routine which checks each channel and then calls
854 * the real interrupt routine as appropriate
855 */
856 static void
avma1pp2_hscx_int_handler(struct isic_softc * sc)857 avma1pp2_hscx_int_handler(struct isic_softc *sc)
858 {
859 u_int stat;
860
861 /* has to be a u_int because the byte count is in the 2nd byte */
862 stat = hscx_read_reg_int(0, sc);
863 if (stat & HSCX_INT_MASK)
864 avma1pp2_hscx_intr(0, stat, sc);
865 stat = hscx_read_reg_int(1, sc);
866 if (stat & HSCX_INT_MASK)
867 avma1pp2_hscx_intr(1, stat, sc);
868 }
869
870 static void
avma1pp2_disable(struct isic_softc * sc)871 avma1pp2_disable(struct isic_softc *sc)
872 {
873 /* could be still be wrong, but seems to prevent hangs */
874 bus_space_write_1(sc->sc_maps[0].t, sc->sc_maps[0].h, STAT0_OFFSET, 0x00);
875 }
876
877 static int
avma1pp2_intr(void * parm)878 avma1pp2_intr(void *parm)
879 {
880 struct isic_softc *sc = parm;
881 int ret = 0;
882 #define OURS ret = 1
883 u_char stat;
884
885 if (sc->sc_intr_valid != ISIC_INTR_VALID)
886 return 0;
887
888 stat = bus_space_read_1(sc->sc_maps[0].t, sc->sc_maps[0].h, STAT0_OFFSET);
889 NDBGL1(L1_H_IRQ, "stat %x", stat);
890 /* was there an interrupt from this card ? */
891 if ((stat & ASL_IRQ_Pending) == 0)
892 return 0; /* no */
893 /* For slow machines loop as long as an interrupt is active */
894 for (; ((stat & ASL_IRQ_Pending) != 0) ;)
895 {
896 /* interrupts are high active */
897 if (stat & ASL_IRQ_TIMER)
898 NDBGL1(L1_H_IRQ, "timer interrupt ???");
899 if (stat & ASL_IRQ_HSCX)
900 {
901 NDBGL1(L1_H_IRQ, "HSCX");
902 avma1pp2_hscx_int_handler(sc);
903 }
904 if (stat & ASL_IRQ_ISAC)
905 {
906 u_char isacsx_irq_stat;
907
908 NDBGL1(L1_H_IRQ, "ISAC");
909 for(;;)
910 {
911 /* ISTA tells us whether it was a C/I or HDLC int. */
912 isacsx_irq_stat = ISAC_READ(I_ISTA);
913
914 if(isacsx_irq_stat)
915 isic_isacsx_irq(sc, isacsx_irq_stat); /* isac handler */
916 else
917 break;
918 }
919
920 /*
921 * XXX: Leo: Note that Linux doesn't do this mask
922 * frobbing...
923 */
924 ISAC_WRITE(I_MASKD, 0xff);
925 ISAC_WRITE(I_MASK, 0xff);
926
927 DELAY(100);
928
929 ISAC_WRITE(I_MASKD, isacsx_imaskd);
930 ISAC_WRITE(I_MASK, isacsx_imask);
931
932 }
933 stat = bus_space_read_1(sc->sc_maps[0].t, sc->sc_maps[0].h, STAT0_OFFSET);
934 NDBGL1(L1_H_IRQ, "stat %x", stat);
935 OURS;
936 }
937 return ret;
938 }
939
940 static void
avma1pp2_map_int(struct ifpci_softc * psc,struct pci_attach_args * pa)941 avma1pp2_map_int(struct ifpci_softc *psc, struct pci_attach_args *pa)
942 {
943 struct isic_softc *sc = &psc->sc_isic;
944 pci_chipset_tag_t pc = pa->pa_pc;
945 pci_intr_handle_t ih;
946 const char *intrstr;
947 char intrbuf[PCI_INTRSTR_LEN];
948
949 /* Map and establish the interrupt. */
950 if (pci_intr_map(pa, &ih)) {
951 aprint_error_dev(sc->sc_dev, "couldn't map interrupt\n");
952 avma1pp2_disable(sc);
953 return;
954 }
955 psc->sc_pc = pc;
956 intrstr = pci_intr_string(pc, ih, intrbuf, sizeof(intrbuf));
957 psc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, avma1pp2_intr, sc);
958 if (psc->sc_ih == NULL) {
959 aprint_error_dev(sc->sc_dev, "couldn't establish interrupt");
960 if (intrstr != NULL)
961 aprint_error(" at %s", intrstr);
962 aprint_error("\n");
963 avma1pp2_disable(sc);
964 return;
965 }
966 aprint_normal_dev(sc->sc_dev, "interrupting at %s\n", intrstr);
967 }
968
969 static void
avma1pp2_hscx_init(struct isic_softc * sc,int h_chan,int activate)970 avma1pp2_hscx_init(struct isic_softc *sc, int h_chan, int activate)
971 {
972 l1_bchan_state_t *chan = &sc->sc_chan[h_chan];
973 u_int param = 0;
974
975 NDBGL1(L1_BCHAN, "%s: channel=%d, %s",
976 device_xname(sc->sc_dev), h_chan, activate ? "activate" : "deactivate");
977 sc->avma1pp_cmd = sc->avma1pp_prot = sc->avma1pp_txl = 0;
978
979 if (activate == 0)
980 {
981 /* only deactivate if both channels are idle */
982 if (sc->sc_chan[HSCX_CH_A].state != HSCX_IDLE ||
983 sc->sc_chan[HSCX_CH_B].state != HSCX_IDLE)
984 {
985 return;
986 }
987 sc->avma1pp_cmd = HSCX_CMD_XRS|HSCX_CMD_RRS;
988 sc->avma1pp_prot = HSCX_MODE_TRANS;
989 AVMA1PPSETCMDLONG(param);
990 hscx_write_reg(h_chan, param, sc);
991 return;
992 }
993 if(chan->bprot == BPROT_RHDLC)
994 {
995 NDBGL1(L1_BCHAN, "BPROT_RHDLC");
996
997 /* HDLC Frames, transparent mode 0 */
998 sc->avma1pp_cmd = HSCX_CMD_XRS|HSCX_CMD_RRS;
999 sc->avma1pp_prot = HSCX_MODE_ITF_FLG;
1000 AVMA1PPSETCMDLONG(param);
1001 hscx_write_reg(h_chan, param, sc);
1002 sc->avma1pp_cmd = HSCX_CMD_XRS;
1003 AVMA1PPSETCMDLONG(param);
1004 hscx_write_reg(h_chan, param, sc);
1005 sc->avma1pp_cmd = 0;
1006 }
1007 else
1008 {
1009 NDBGL1(L1_BCHAN, "BPROT_NONE??");
1010
1011 /* Raw Telephony, extended transparent mode 1 */
1012 sc->avma1pp_cmd = HSCX_CMD_XRS|HSCX_CMD_RRS;
1013 sc->avma1pp_prot = HSCX_MODE_TRANS;
1014 AVMA1PPSETCMDLONG(param);
1015 hscx_write_reg(h_chan, param, sc);
1016 sc->avma1pp_cmd = HSCX_CMD_XRS;
1017 AVMA1PPSETCMDLONG(param);
1018 hscx_write_reg(h_chan, param, sc);
1019 sc->avma1pp_cmd = 0;
1020 }
1021 }
1022
1023 static void
avma1pp2_bchannel_setup(isdn_layer1token t,int h_chan,int bprot,int activate)1024 avma1pp2_bchannel_setup(isdn_layer1token t, int h_chan, int bprot, int activate)
1025 {
1026 struct isic_softc *sc = (struct isic_softc*)t;
1027 l1_bchan_state_t *chan = &sc->sc_chan[h_chan];
1028
1029 int s = splnet();
1030
1031 if(activate == 0)
1032 {
1033 /* deactivation */
1034 chan->state = HSCX_IDLE;
1035 avma1pp2_hscx_init(sc, h_chan, activate);
1036 }
1037
1038 NDBGL1(L1_BCHAN, "%s: channel=%d, %s",
1039 device_xname(sc->sc_dev), h_chan, activate ? "activate" : "deactivate");
1040
1041 /* general part */
1042
1043 chan->channel = h_chan; /* B channel */
1044 chan->bprot = bprot; /* B channel protocol */
1045 chan->state = HSCX_IDLE; /* B channel state */
1046
1047 /* receiver part */
1048
1049 i4b_Bcleanifq(&chan->rx_queue); /* clean rx queue */
1050
1051 chan->rx_queue.ifq_maxlen = IFQ_MAXLEN;
1052
1053 chan->rxcount = 0; /* reset rx counter */
1054
1055 i4b_Bfreembuf(chan->in_mbuf); /* clean rx mbuf */
1056
1057 chan->in_mbuf = NULL; /* reset mbuf ptr */
1058 chan->in_cbptr = NULL; /* reset mbuf curr ptr */
1059 chan->in_len = 0; /* reset mbuf data len */
1060
1061 /* transmitter part */
1062
1063 i4b_Bcleanifq(&chan->tx_queue); /* clean tx queue */
1064
1065 chan->tx_queue.ifq_maxlen = IFQ_MAXLEN;
1066
1067 chan->txcount = 0; /* reset tx counter */
1068
1069 i4b_Bfreembuf(chan->out_mbuf_head); /* clean tx mbuf */
1070
1071 chan->out_mbuf_head = NULL; /* reset head mbuf ptr */
1072 chan->out_mbuf_cur = NULL; /* reset current mbuf ptr */
1073 chan->out_mbuf_cur_ptr = NULL; /* reset current mbuf data ptr */
1074 chan->out_mbuf_cur_len = 0; /* reset current mbuf data cnt */
1075
1076 if(activate != 0)
1077 {
1078 /* activation */
1079 avma1pp2_hscx_init(sc, h_chan, activate);
1080 chan->state |= HSCX_AVMA1PP_ACTIVE;
1081 }
1082
1083 splx(s);
1084 }
1085
1086 static void
avma1pp2_bchannel_start(isdn_layer1token t,int h_chan)1087 avma1pp2_bchannel_start(isdn_layer1token t, int h_chan)
1088 {
1089 struct isic_softc *sc = (struct isic_softc*)t;
1090 register l1_bchan_state_t *chan = &sc->sc_chan[h_chan];
1091 int s;
1092 int activity = -1;
1093
1094 s = splnet(); /* enter critical section */
1095 if(chan->state & HSCX_TX_ACTIVE) /* already running ? */
1096 {
1097 splx(s);
1098 return; /* yes, leave */
1099 }
1100
1101 /* get next mbuf from queue */
1102
1103 IF_DEQUEUE(&chan->tx_queue, chan->out_mbuf_head);
1104
1105 if(chan->out_mbuf_head == NULL) /* queue empty ? */
1106 {
1107 splx(s); /* leave critical section */
1108 return; /* yes, exit */
1109 }
1110
1111 /* init current mbuf values */
1112
1113 chan->out_mbuf_cur = chan->out_mbuf_head;
1114 chan->out_mbuf_cur_len = chan->out_mbuf_cur->m_len;
1115 chan->out_mbuf_cur_ptr = chan->out_mbuf_cur->m_data;
1116
1117 /* activity indicator for timeout handling */
1118
1119 if(chan->bprot == BPROT_NONE)
1120 {
1121 if(!(isdn_bchan_silence(chan->out_mbuf_cur->m_data, chan->out_mbuf_cur->m_len)))
1122 activity = ACT_TX;
1123 }
1124 else
1125 {
1126 activity = ACT_TX;
1127 }
1128
1129 chan->state |= HSCX_TX_ACTIVE; /* we start transmitting */
1130
1131 if(sc->sc_trace & TRACE_B_TX) /* if trace, send mbuf to trace dev */
1132 {
1133 struct i4b_trace_hdr hdr;
1134 hdr.type = (h_chan == HSCX_CH_A ? TRC_CH_B1 : TRC_CH_B2);
1135 hdr.dir = FROM_TE;
1136 hdr.count = ++sc->sc_trace_bcount;
1137 isdn_layer2_trace_ind(&sc->sc_l2, sc->sc_l3token, &hdr, chan->out_mbuf_cur->m_len, chan->out_mbuf_cur->m_data);
1138 }
1139
1140 isic_hscx_fifo(chan, sc);
1141
1142 /* call timeout handling routine */
1143
1144 if(activity == ACT_RX || activity == ACT_TX)
1145 (*chan->l4_driver->bch_activity)(chan->l4_driver_softc, activity);
1146
1147 splx(s);
1148 }
1149
1150 /*---------------------------------------------------------------------------*
1151 * return the address of isic drivers linktab
1152 *---------------------------------------------------------------------------*/
1153 static isdn_link_t *
avma1pp2_ret_linktab(void * token,int channel)1154 avma1pp2_ret_linktab(void *token, int channel)
1155 {
1156 struct l2_softc *l2sc = token;
1157 struct isic_softc *sc = l2sc->l1_token;
1158
1159 l1_bchan_state_t *chan = &sc->sc_chan[channel];
1160
1161 return(&chan->isdn_linktab);
1162 }
1163
1164 /*---------------------------------------------------------------------------*
1165 * set the driver linktab in the b channel softc
1166 *---------------------------------------------------------------------------*/
1167 static void
avma1pp2_set_link(void * token,int channel,const struct isdn_l4_driver_functions * l4_driver,void * l4_driver_softc)1168 avma1pp2_set_link(void *token, int channel, const struct isdn_l4_driver_functions *l4_driver, void *l4_driver_softc)
1169 {
1170 struct l2_softc *l2sc = token;
1171 struct isic_softc *sc = l2sc->l1_token;
1172 l1_bchan_state_t *chan = &sc->sc_chan[channel];
1173
1174 chan->l4_driver = l4_driver;
1175 chan->l4_driver_softc = l4_driver_softc;
1176 }
1177
1178 static const struct isdn_l4_bchannel_functions
1179 avma1pp2_l4_bchannel_functions = {
1180 avma1pp2_bchannel_setup,
1181 avma1pp2_bchannel_start,
1182 avma1pp2_bchannel_stat
1183 };
1184
1185 /*---------------------------------------------------------------------------*
1186 * initialize our local linktab
1187 *---------------------------------------------------------------------------*/
1188 static void
avma1pp2_init_linktab(struct isic_softc * sc)1189 avma1pp2_init_linktab(struct isic_softc *sc)
1190 {
1191 l1_bchan_state_t *chan = &sc->sc_chan[HSCX_CH_A];
1192 isdn_link_t *lt = &chan->isdn_linktab;
1193
1194 /* local setup */
1195 lt->l1token = sc;
1196 lt->channel = HSCX_CH_A;
1197 lt->bchannel_driver = &avma1pp2_l4_bchannel_functions;
1198 lt->tx_queue = &chan->tx_queue;
1199
1200 /* used by non-HDLC data transfers, i.e. telephony drivers */
1201 lt->rx_queue = &chan->rx_queue;
1202
1203 /* used by HDLC data transfers, i.e. ipr and isp drivers */
1204 lt->rx_mbuf = &chan->in_mbuf;
1205
1206 chan = &sc->sc_chan[HSCX_CH_B];
1207 lt = &chan->isdn_linktab;
1208
1209 lt->l1token = sc;
1210 lt->channel = HSCX_CH_B;
1211 lt->bchannel_driver = &avma1pp2_l4_bchannel_functions;
1212 lt->tx_queue = &chan->tx_queue;
1213
1214 /* used by non-HDLC data transfers, i.e. telephony drivers */
1215 lt->rx_queue = &chan->rx_queue;
1216
1217 /* used by HDLC data transfers, i.e. ipr and isp drivers */
1218 lt->rx_mbuf = &chan->in_mbuf;
1219 }
1220
1221 /*
1222 * use this instead of isic_bchannel_stat in i4b_bchan.c because it's static
1223 */
1224 static void
avma1pp2_bchannel_stat(isdn_layer1token t,int h_chan,bchan_statistics_t * bsp)1225 avma1pp2_bchannel_stat(isdn_layer1token t, int h_chan, bchan_statistics_t *bsp)
1226 {
1227 struct isic_softc *sc = (struct isic_softc*)t;
1228 l1_bchan_state_t *chan = &sc->sc_chan[h_chan];
1229 int s;
1230
1231 s = splnet();
1232
1233 bsp->outbytes = chan->txcount;
1234 bsp->inbytes = chan->rxcount;
1235
1236 chan->txcount = 0;
1237 chan->rxcount = 0;
1238
1239 splx(s);
1240 }
1241
1242 /*---------------------------------------------------------------------------*
1243 * fill HSCX fifo with data from the current mbuf
1244 * Put this here until it can go into i4b_hscx.c
1245 *---------------------------------------------------------------------------*/
1246 static int
isic_hscx_fifo(l1_bchan_state_t * chan,struct isic_softc * sc)1247 isic_hscx_fifo(l1_bchan_state_t *chan, struct isic_softc *sc)
1248 {
1249 int len;
1250 int nextlen;
1251 int i;
1252 int cmd;
1253 /* using a scratch buffer simplifies writing to the FIFO */
1254 u_char scrbuf[HSCX_FIFO_LEN];
1255
1256 len = 0;
1257 cmd = 0;
1258
1259 /*
1260 * fill the HSCX tx fifo with data from the current mbuf. if
1261 * current mbuf holds less data than HSCX fifo length, try to
1262 * get the next mbuf from (a possible) mbuf chain. if there is
1263 * not enough data in a single mbuf or in a chain, then this
1264 * is the last mbuf and we tell the HSCX that it has to send
1265 * CRC and closing flag
1266 */
1267
1268 while(chan->out_mbuf_cur && len != sc->sc_bfifolen)
1269 {
1270 nextlen = min(chan->out_mbuf_cur_len, sc->sc_bfifolen - len);
1271
1272 #ifdef NOTDEF
1273 printf("i:mh=%p, mc=%p, mcp=%p, mcl=%d l=%d nl=%d # ",
1274 chan->out_mbuf_head,
1275 chan->out_mbuf_cur,
1276 chan->out_mbuf_cur_ptr,
1277 chan->out_mbuf_cur_len,
1278 len,
1279 nextlen);
1280 #endif
1281
1282 cmd |= HSCX_CMDR_XTF;
1283 /* collect the data in the scratch buffer */
1284 for (i = 0; i < nextlen; i++)
1285 scrbuf[i + len] = chan->out_mbuf_cur_ptr[i];
1286
1287 len += nextlen;
1288 chan->txcount += nextlen;
1289
1290 chan->out_mbuf_cur_ptr += nextlen;
1291 chan->out_mbuf_cur_len -= nextlen;
1292
1293 if(chan->out_mbuf_cur_len == 0)
1294 {
1295 if((chan->out_mbuf_cur = chan->out_mbuf_cur->m_next) != NULL)
1296 {
1297 chan->out_mbuf_cur_ptr = chan->out_mbuf_cur->m_data;
1298 chan->out_mbuf_cur_len = chan->out_mbuf_cur->m_len;
1299
1300 if(sc->sc_trace & TRACE_B_TX)
1301 {
1302 struct i4b_trace_hdr hdr;
1303 hdr.type = (chan->channel == HSCX_CH_A ? TRC_CH_B1 : TRC_CH_B2);
1304 hdr.dir = FROM_TE;
1305 hdr.count = ++sc->sc_trace_bcount;
1306 isdn_layer2_trace_ind(&sc->sc_l2, sc->sc_l3token, &hdr, chan->out_mbuf_cur->m_len, chan->out_mbuf_cur->m_data);
1307 }
1308 }
1309 else
1310 {
1311 if (chan->bprot != BPROT_NONE)
1312 cmd |= HSCX_CMDR_XME;
1313 i4b_Bfreembuf(chan->out_mbuf_head);
1314 chan->out_mbuf_head = NULL;
1315 }
1316 }
1317 }
1318 /* write what we have from the scratch buf to the HSCX fifo */
1319 if (len != 0)
1320 HSCX_WRFIFO(chan->channel, scrbuf, len);
1321 return(cmd);
1322 }
1323