1 /*------------------------------------------------------------------------- 2 Register Declarations for the Atmel AT89C513xA Processor Range 3 4 Copyright (C) 2010 - Anirban Brahmachari, a.brahmachari@gmail.com 5 6 This library is free software; you can redistribute it and/or modify it 7 under the terms of the GNU General Public License as published by the 8 Free Software Foundation; either version 2, or (at your option) any 9 later version. 10 11 This library is distributed in the hope that it will be useful, 12 but WITHOUT ANY WARRANTY; without even the implied warranty of 13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 GNU General Public License for more details. 15 16 You should have received a copy of the GNU General Public License 17 along with this library; see the file COPYING. If not, write to the 18 Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston, 19 MA 02110-1301, USA. 20 21 As a special exception, if you link this library with other files, 22 some of which are compiled with SDCC, to produce an executable, 23 this library does not by itself cause the resulting executable to 24 be covered by the GNU General Public License. This exception does 25 not however invalidate any other reasons why the executable file 26 might be covered by the GNU General Public License. 27 -------------------------------------------------------------------------*/ 28 29 #ifndef AT89C5131AUM_H 30 #define AT89C5131AUM_H 31 32 #include <compiler.h> 33 34 SFR(P0, 0x80); // Port 0 35 SBIT(P0_0, 0x80, 0); // Port 0 bit 0 36 SBIT(P0_1, 0x80, 1); // Port 0 bit 1 37 SBIT(P0_2, 0x80, 2); // Port 0 bit 2 38 SBIT(P0_3, 0x80, 3); // Port 0 bit 3 39 SBIT(P0_4, 0x80, 4); // Port 0 bit 4 40 SBIT(P0_5, 0x80, 5); // Port 0 bit 5 41 SBIT(P0_6, 0x80, 6); // Port 0 bit 6 42 SBIT(P0_7, 0x80, 7); // Port 0 bit 7 43 SFR(SP, 0x81); // Stack Pointer ; LSB of SPX 44 SFR(DPL, 0x82); // Data Pointer Low Byte 45 SFR(DPH, 0x83); // Data Pointer High Byte 46 SFR(PCON, 0x87); // Power Mode Control 47 SFR(TCON, 0x88); // Timer Control 48 SBIT(IT0, 0x88, 0); // Ext. Interrupt 0 Type Select 49 SBIT(IE0, 0x88, 1); // Ext. Interrupt 0 Flag 50 SBIT(IT1, 0x88, 2); // Ext. Interrupt 1 Type Select 51 SBIT(IE1, 0x88, 3); // Ext. Interrupt 1 Flag 52 SBIT(TR0, 0x88, 4); // Timer 0 Run Control 53 SBIT(TF0, 0x88, 5); // Timer 0 Overflow Flag 54 SBIT(TR1, 0x88, 6); // Timer 1 Run Control 55 SBIT(TF1, 0x88, 7); // Timer 1 Overflow Flag 56 SFR(TMOD, 0x89); // Timer Mode 57 SFR16E(TMR0, 0x8C8A); // Timer/Counter 0 Word 58 SFR(TL0, 0x8A); // Timer/Counter 0 Low Byte 59 SFR(TH0, 0x8C); // Timer/Counter 0 High Byte 60 SFR16E(TMR1, 0x8D8B); // Timer/Counter 1 Word 61 SFR(TL1, 0x8B); // Timer/Counter 1 Low Byte 62 SFR(TH1, 0x8D); // Timer/Counter 1 High Byte 63 SFR(AUXR, 0x8E); // Auxiliary Register 64 SFR(CKCON0, 0x8F); // Clock Control 0 65 SFR(P1, 0x90); // Port 1 66 SBIT(P1_0, 0x90, 0); // Port 1 bit 0 67 SBIT(P1_1, 0x90, 1); // Port 1 bit 1 68 SBIT(P1_2, 0x90, 2); // Port 1 bit 2 69 SBIT(P1_3, 0x90, 3); // Port 1 bit 3 70 SBIT(P1_4, 0x90, 4); // Port 1 bit 4 71 SBIT(P1_5, 0x90, 5); // Port 1 bit 5 72 SBIT(P1_6, 0x90, 6); // Port 1 bit 6 73 SBIT(P1_7, 0x90, 7); // Port 1 bit 7 74 SFR(SSCON, 0x93); // Synchronous Serial Control 75 SFR(SSCS, 0x94); // Synchronous Serial Control-Status 76 SFR(SSDAT, 0x95); // Synchronous Serial Data 77 SFR(SSADR, 0x96); // Synchronous Serial Address 78 SFR(SCON, 0x98); // Serial Port 0 Control 79 SBIT(RI, 0x98, 0); // Receive Interrupt Flag 80 SBIT(TI, 0x98, 1); // Transmit Interrupt Flag 81 SBIT(RB8, 0x98, 2); // Ninth Receive Bit 82 SBIT(TB8, 0x98, 3); // Ninth Transmission Bit 83 SBIT(REN, 0x98, 4); // Receive Enable 84 SBIT(SM2, 0x98, 5); // Multiprocessor Communication Enable 85 SBIT(SM1, 0x98, 6); // Serial Port Mode 1 86 SBIT(SM0, 0x98, 7); // Serial Port Mode 0 87 SBIT(FE, 0x98, 7); // Framing Error 88 SFR(SBUF, 0x99); // Serial Port Data Buffer 89 SFR(BRL, 0x9A); // Baud Rate Reload 90 SFR(BDRCON, 0x9B); // Baud Rate Control 91 SFR(KBLS, 0x9C); // Keyboard Level Selector Register 92 SFR(KBE, 0x9D); // Keyboard Input Enable Register 93 SFR(KBF, 0x9E); // Keyboard Flag Register 94 SFR(P2, 0xA0); // Port 2 95 SBIT(P2_0, 0xA0, 0); // Port 2 bit 0 96 SBIT(P2_1, 0xA0, 1); // Port 2 bit 1 97 SBIT(P2_2, 0xA0, 2); // Port 2 bit 2 98 SBIT(P2_3, 0xA0, 3); // Port 2 bit 3 99 SBIT(P2_4, 0xA0, 4); // Port 2 bit 4 100 SBIT(P2_5, 0xA0, 5); // Port 2 bit 5 101 SBIT(P2_6, 0xA0, 6); // Port 2 bit 6 102 SBIT(P2_7, 0xA0, 7); // Port 2 bit 7 103 SFR(AUXR1, 0xA2); // Auxiliary Register 1 104 SFR(PLLCON, 0xA3); // PLL Control 105 SFR(PLLDIV, 0xA4); // PLL Divider 106 SFR(WDTRST, 0xA6); // Watchdog Timer Reset 107 SFR(WDTPRG, 0xA7); // Watchdog Timer Program 108 SFR(IE, 0xA8); // Interrupt Enable (traditional 8051 name) 109 SFR(IEN0, 0xA8); // Interrupt Enable Control 0 110 SBIT(EX0, 0xA8, 0); // Enable External Interrupt 0 111 SBIT(ET0, 0xA8, 1); // Enable Timer 0 Interrupt 112 SBIT(EX1, 0xA8, 2); // Enable External Interrupt 1 113 SBIT(ET1, 0xA8, 3); // Enable Timer 1 Interrupt 114 SBIT(ES, 0xA8, 4); // Enable Serial Port Interrupt 115 SBIT(ET2, 0xA8, 5); // Enable Timer 2 Interrupt 116 SBIT(EC, 0xA8, 6); // Enable PCA Interrupt 117 SBIT(EA, 0xA8, 7); // Global Interrupt Enable 118 SFR(SADDR, 0xA9); // Slave Address 119 SFR(CKCON1, 0xAF); // Clock Control 1 120 SFR(P3, 0xB0); // Port 3 121 SBIT(P3_0, 0xB0, 0); // Port 3 bit 0 122 SBIT(P3_1, 0xB0, 1); // Port 3 bit 1 123 SBIT(P3_2, 0xB0, 2); // Port 3 bit 2 124 SBIT(P3_3, 0xB0, 3); // Port 3 bit 3 125 SBIT(P3_4, 0xB0, 4); // Port 3 bit 4 126 SBIT(P3_5, 0xB0, 5); // Port 3 bit 5 127 SBIT(P3_6, 0xB0, 6); // Port 3 bit 6 128 SBIT(P3_7, 0xB0, 7); // Port 3 bit 7 129 SFR(IEN1, 0xB1); // Interrupt Enable Control 1 130 SFR(IPL1, 0xB2); // Interrupt Priority Control Low 1 131 SFR(IPH1, 0xB3); // Interrupt Priority Control High 1 132 SFR(IPH0, 0xB7); // Interrupt Priority Control High 0 133 SFR(IPL0, 0xB8); // Interrupt Priority Control Low 0 134 SBIT(PX0L, 0xB8, 0); // External interrupt 0 Priority bit 135 SBIT(PT0L, 0xB8, 1); // Timer 0 overflow interrupt Priority bit 136 SBIT(PX1L, 0xB8, 2); // External interrupt 1 Priority bit 137 SBIT(PT1L, 0xB8, 3); // Timer 1 overflow interrupt Priority bit 138 SBIT(PSL, 0xB8, 4); // Serial port Priority bit 139 SBIT(PT2L, 0xB8, 5); // Timer 2 overflow interrupt Priority bit 140 SBIT(PPCL, 0xB8, 6); // PCA interrupt Priority bit 141 SFR(SADEN, 0xB9); // Slave Address Mask 142 SFR16E(UFNUM, 0xBBBA); // USB Frame Number Word 143 SFR(UFNUML, 0xBA); // USB Frame Number Low 144 SFR(UFNUMH, 0xBB); // USB Frame Number High 145 SFR(USBCON, 0xBC); // USB Global Control 146 SFR(USBINT, 0xBD); // USB Global Interrupt 147 SFR(USBIEN, 0xBE); // USB Global Interrupt Enable 148 SFR(P4, 0xC0); // Port 4 149 SBIT(P4_0, 0xC0, 0); // Port 4 bit 0 150 SBIT(P4_1, 0xC0, 1); // Port 4 bit 1 151 SFR(UEPIEN, 0xC2); // USB Endpoint Interrupt Enable 152 SFR(SPCON, 0xC3); // Serial Peripheral Control 153 SFR(SPSTA, 0xC4); // Serial Peripheral Status-Control 154 SFR(SPDAT, 0xC5); // Serial Peripheral Data 155 SFR(USBADDR, 0xC6); // USB Address 156 SFR(UEPNUM, 0xC7); // USB Endpoint Number 157 SFR(T2CON, 0xC8); // Timer 2 Control 158 SBIT(CP_RL2, 0xC8, 0); // Timer 2 Capture/Reload bit 159 SBIT(C_T2, 0xC8, 1); // Timer/Counter 2 select bit 160 SBIT(TR2, 0xC8, 2); // Timer 2 Run control bit 161 SBIT(EXEN2, 0xC8, 3); // Timer 2 External Enable bit 162 SBIT(TCLK, 0xC8, 4); // Transmit Clock bit 163 SBIT(RCLK, 0xC8, 5); // Receive Clock bit 164 SBIT(EXF2, 0xC8, 6); // Timer 2 External Flag 165 SBIT(TF2, 0xC8, 7); // Timer 2 overflow Flag 166 SFR(T2MOD, 0xC9); // Timer 2 Mode 167 SFR16E(RCAP2, 0xCBCA); // Timer/Counter 2 Reload/Capture Word 168 SFR(RCAP2L, 0xCA); // Timer/Counter 2 Reload/Capture Low byte 169 SFR(RCAP2H, 0xCB); // Timer/Counter 2 Reload/Capture High byte 170 SFR16E(TMR2, 0xCDCC); // Timer/Counter 2 Word 171 SFR(TL2, 0xCC); // Timer/Counter 2 Low Byte 172 SFR(TH2, 0xCD); // Timer/Counter 2 High Byte 173 SFR(UEPSTAX, 0xCE); // USB Endpoint X Status 174 SFR(UEPDATX, 0xCF); // USB Endpoint X FIFO Data 175 SFR(PSW, 0xD0); // Program Status Word 176 SBIT(P, 0xD0, 0); // Parity Flag 177 SBIT(F1, 0xD0, 1); // User-Defined Flag 178 SBIT(OV, 0xD0, 2); // Overflow Flag 179 SBIT(RS0, 0xD0, 3); // Register Bank Select 0 180 SBIT(RS1, 0xD0, 4); // Register Bank Select 1 181 SBIT(F0, 0xD0, 5); // User-Defined Flag 182 SBIT(AC, 0xD0, 6); // Auxiliary Carry Flag 183 SBIT(CY, 0xD0, 7); // Carry Flag 184 SFR(FCON, 0xD1); // Flash Control 185 SFR(EECON, 0xD2); // EEPROM Contol 186 SFR(UEPCONX, 0xD4); // USB Endpoint X Control 187 SFR(UEPRST, 0xD5); // USB Endpoint Reset 188 SFR(CCON, 0xD8); // PCA Timer/Counter Control 189 SBIT(CCF0, 0xD8,0); // PCA Module 0 interrupt flag 190 SBIT(CCF1, 0xD8,1); // PCA Module 1 interrupt flag 191 SBIT(CCF2, 0xD8,2); // PCA Module 2 interrupt flag 192 SBIT(CCF3, 0xD8,3); // PCA Module 3 interrupt flag 193 SBIT(CCF4, 0xD8,4); // PCA Module 4 interrupt flag 194 SBIT(CR, 0xD8,6); // PCA Counter Run control bit 195 SBIT(CF, 0xD8,7); // PCA Counter Overflow flag 196 SFR(CMOD, 0xD9); // PCA Timer/Counter Mode 197 SFR(CCAPM0, 0xDA); // PCA Timer/Counter 0 Mode 198 SFR(CCAPM1, 0xDB); // PCA Timer/Counter 1 Mode 199 SFR(CCAPM2, 0xDC); // PCA Timer/Counter 2 Mode 200 SFR(CCAPM3, 0xDD); // PCA Timer/Counter 3 Mode 201 SFR(CCAPM4, 0xDE); // PCA Timer/Counter 4 Mode 202 SFR(ACC, 0xE0); // Accumulator 203 SFR16E(UBYCTX, 0xE3E2); // USB Byte Counter Word 204 SFR(UBYCTLX, 0xE2); // USB Byte Counter Low 205 SFR(UBYCTHX, 0xE3); // USB Byte Counter High 206 SFR16E(PCA, 0xF9E9); // PCA Timer/Counter Word 207 SFR(CL, 0xE9); // PCA Timer/Counter Low byte 208 SFR(CH, 0xF9); // PCA Timer/Counter High byte 209 SFR16E(CCAP0, 0xFAEA); // PCA Compare Capture Module 0 Word 210 SFR(CCAP0L, 0xEA); // PCA Compare Capture Module 0 Low byte 211 SFR(CCAP0H, 0xFA); // PCA Compare Capture Module 0 High byte 212 SFR16E(CCAP1, 0xFBEB); // PCA Compare Capture Module 1 Word 213 SFR(CCAP1L, 0xEB); // PCA Compare Capture Module 1 Low byte 214 SFR(CCAP1H, 0xFB); // PCA Compare Capture Module 1 High byte 215 SFR16E(CCAP2, 0xFCEC); // PCA Compare Capture Module 2 Word 216 SFR(CCAP2L, 0xEC); // PCA Compare Capture Module 2 Low byte 217 SFR(CCAP2H, 0xFC); // PCA Compare Capture Module 2 High byte 218 SFR16E(CCAP3, 0xFDED); // PCA Compare Capture Module 3 Word 219 SFR(CCAP3L, 0xED); // PCA Compare Capture Module 3 Low byte 220 SFR(CCAP3H, 0xFD); // PCA Compare Capture Module 3 High byte 221 SFR16E(CCAP4, 0xFEEE); // PCA Compare Capture Module 4 Word 222 SFR(CCAP4L, 0xEE); // PCA Compare Capture Module 4 Low byte 223 SFR(CCAP4H, 0xFE); // PCA Compare Capture Module 4 High byte 224 SFR(B, 0xF0); // B Register 225 SFR(LEDCON, 0xF1); // LED Control 226 SFR(UEPINT, 0xF8); // USB Endpoint Interrupt 227 SBIT(EP0INT, 0xF8,0); // Endpoint 0 Interrupt 228 SBIT(EP1INT, 0xF8,1); // Endpoint 1 Interrupt 229 SBIT(EP2INT, 0xF8,2); // Endpoint 2 Interrupt 230 SBIT(EP3INT, 0xF8,3); // Endpoint 3 Interrupt 231 SBIT(EP4INT, 0xF8,4); // Endpoint 4 Interrupt 232 SBIT(EP5INT, 0xF8,5); // Endpoint 5 Interrupt 233 SBIT(EP6INT, 0xF8,6); // Endpoint 6 Interrupt 234 235 /* Predefined SFR Bit Masks */ 236 237 #define PCON_IDLE 0x01 /* PCON */ 238 #define PCON_STOP 0x02 /* PCON */ 239 240 /* Interrupts */ 241 #define INT_RESET 0 // Reset 242 #define INT_EXT0 1 // External Interrupt 0 243 #define INT_TIMER0 2 // Timer0 Overflow 244 #define INT_EXT1 3 // External Interrupt 1 245 #define INT_TIMER1 4 // Timer1 Overflow 246 #define INT_UART0 5 // Serial Port 0 247 #define INT_TIMER2 6 // Timer2 Overflow 248 #define INT_PCA 7 // Programmable Counter Array 249 #define INT_KEYBOARD 8 // Keyboard on P1 250 #define INT_TWI 9 // Two Wire Interface 251 #define INT_SPI 10 // Serial Peripheral Interface 252 // 11 Reserved 253 // 12 Reserved 254 // 13 Reserved 255 #define INT_USB 14 // USB events 256 // 15 Reserved 257 258 #endif 259