1 /*------------------------------------------------------------------------- 2 C8051T610.h - Register Declarations for the SiLabs C8051T61x Processor 3 Range 4 5 Copyright (C) 2008, Steven Borley, steven.borley@partnerelectronics.com 6 7 This library is free software; you can redistribute it and/or modify it 8 under the terms of the GNU General Public License as published by the 9 Free Software Foundation; either version 2, or (at your option) any 10 later version. 11 12 This library is distributed in the hope that it will be useful, 13 but WITHOUT ANY WARRANTY; without even the implied warranty of 14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 GNU General Public License for more details. 16 17 You should have received a copy of the GNU General Public License 18 along with this library; see the file COPYING. If not, write to the 19 Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston, 20 MA 02110-1301, USA. 21 22 As a special exception, if you link this library with other files, 23 some of which are compiled with SDCC, to produce an executable, 24 this library does not by itself cause the resulting executable to 25 be covered by the GNU General Public License. This exception does 26 not however invalidate any other reasons why the executable file 27 might be covered by the GNU General Public License. 28 -------------------------------------------------------------------------*/ 29 #ifndef C8051T610_H 30 #define C8051T610_H 31 32 #include <compiler.h> 33 34 /* BYTE Registers */ 35 36 SFR( P0, 0x80 ) ; /* PORT 0 */ 37 SFR( SP, 0x81 ) ; /* STACK POINTER */ 38 SFR( DPL, 0x82 ) ; /* DATA POINTER - LOW BYTE */ 39 SFR( DPH, 0x83 ) ; /* DATA POINTER - HIGH BYTE */ 40 SFR( TOFFL, 0x85 ) ; /* TEMPERATURE SENSOR OFFSET - LOW BYTE */ 41 SFR( TOFFH, 0x86 ) ; /* TEMPERATURE SENSOR OFFSET - HIGH BYTE */ 42 SFR( PCON, 0x87 ) ; /* POWER CONTROL */ 43 SFR( TCON, 0x88 ) ; /* TIMER CONTROL */ 44 SFR( TMOD, 0x89 ) ; /* TIMER MODE */ 45 SFR( TL0, 0x8A ) ; /* TIMER 0 - LOW BYTE */ 46 SFR( TL1, 0x8B ) ; /* TIMER 1 - LOW BYTE */ 47 SFR( TH0, 0x8C ) ; /* TIMER 0 - HIGH BYTE */ 48 SFR( TH1, 0x8D ) ; /* TIMER 1 - HIGH BYTE */ 49 SFR( CKCON, 0x8E ) ; /* CLOCK CONTROL */ 50 SFR( P1, 0x90 ) ; /* PORT 1 */ 51 SFR( TMR3CN, 0x91 ) ; /* TIMER 3 CONTROL */ 52 SFR( TMR3RLL, 0x92 ) ; /* TIMER 3 CAPTURE REGISTER - LOW BYTE */ 53 SFR( TMR3RLH, 0x93 ) ; /* TIMER 3 CAPTURE REGISTER - HIGH BYTE */ 54 SFR( TMR3L, 0x94 ) ; /* TIMER 3 - LOW BYTE */ 55 SFR( TMR3H, 0x95 ) ; /* TIMER 3 - HIGH BYTE */ 56 SFR( SCON, 0x98 ) ; /* SERIAL PORT CONTROL */ 57 SFR( SCON0, 0x98 ) ; /* SERIAL PORT CONTROL */ 58 SFR( SBUF, 0x99 ) ; /* SERIAL PORT BUFFER */ 59 SFR( SBUF0, 0x99 ) ; /* SERIAL PORT BUFFER */ 60 SFR( CPT1CN, 0x9A ) ; /* COMPARATOR 1 CONTROL */ 61 SFR( CPT0CN, 0x9B ) ; /* COMPARATOR 0 CONTROL */ 62 SFR( CPT1MD, 0x9C ) ; /* COMPARATOR 1 MODE SELECTION */ 63 SFR( CPT0MD, 0x9D ) ; /* COMPARATOR 0 MODE SELECTION */ 64 SFR( CPT1MX, 0x9E ) ; /* COMPARATOR 1 MUX SELECTION */ 65 SFR( CPT0MX, 0x9F ) ; /* COMPARATOR 0 MUX SELECTION */ 66 SFR( P2, 0xA0 ) ; /* PORT 2 */ 67 SFR( SPI0CFG, 0xA1 ) ; /* SPI0 CONFIGURATION */ 68 SFR( SPI0CKR, 0xA2 ) ; /* SPI0 CLOCK RATE CONTROL */ 69 SFR( SPI0DAT, 0xA3 ) ; /* SPI0 DATA */ 70 SFR( P0MDOUT, 0xA4 ) ; /* PORT 0 OUTPUT MODE CONFIGURATION */ 71 SFR( P1MDOUT, 0xA5 ) ; /* PORT 1 OUTPUT MODE CONFIGURATION */ 72 SFR( P2MDOUT, 0xA6 ) ; /* PORT 2 OUTPUT MODE CONFIGURATION */ 73 SFR( P3MDOUT, 0xA7 ) ; /* PORT 3 OUTPUT MODE CONFIGURATION */ 74 SFR( IE, 0xA8 ) ; /* INTERRUPT ENABLE */ 75 SFR( CLKSEL, 0xA9 ) ; /* SYSTEM CLOCK SELECT */ 76 SFR( EMI0CN, 0xAA ) ; /* EXTERNAL MEMORY INTERFACE CONTROL */ 77 SFR( _XPAGE, 0xAA ) ; /* XDATA/PDATA PAGE */ 78 SFR( P3, 0xB0 ) ; /* PORT 3 */ 79 SFR( OSCXCN, 0xB1 ) ; /* EXTERNAL OSCILLATOR CONTROL */ 80 SFR( OSCICN, 0xB2 ) ; /* INTERNAL OSCILLATOR CONTROL */ 81 SFR( OSCICL, 0xB3 ) ; /* INTERNAL OSCILLATOR CALIBRATION */ 82 SFR( IP, 0xB8 ) ; /* INTERRUPT PRIORITY */ 83 SFR( AMX0P, 0xBB ) ; /* ADC 0 MUX POSITIVE CHANNEL SELECTION */ 84 SFR( ADC0CF, 0xBC ) ; /* ADC 0 CONFIGURATION */ 85 SFR( ADC0L, 0xBD ) ; /* ADC 0 DATA WORD LSB */ 86 SFR( ADC0H, 0xBE ) ; /* ADC 0 DATA WORD MSB */ 87 SFR( SMB0CN, 0xC0 ) ; /* SMBUS CONTROL */ 88 SFR( SMB0CF, 0xC1 ) ; /* SMBUS CONFIGURATION */ 89 SFR( SMB0DAT, 0xC2 ) ; /* SMBUS DATA */ 90 SFR( ADC0GTL, 0xC3 ) ; /* ADC 0 GREATER-THAN LOW BYTE */ 91 SFR( ADC0GTH, 0xC4 ) ; /* ADC 0 GREATER-THAN HIGH BYTE */ 92 SFR( ADC0LTL, 0xC5 ) ; /* ADC 0 LESS-THAN LOW BYTE */ 93 SFR( ADC0LTH, 0xC6 ) ; /* ADC 0 LESS-THAN HIGH BYTE */ 94 SFR( REG0CN, 0xC7 ) ; /* Voltage Regulator Control */ 95 SFR( T2CON, 0xC8 ) ; /* TIMER 2 CONTROL */ 96 SFR( TMR2CN, 0xC8 ) ; /* TIMER 2 CONTROL */ 97 SFR( RCAP2L, 0xCA ) ; /* TIMER 2 CAPTURE REGISTER - LOW BYTE */ 98 SFR( TMR2RLL, 0xCA ) ; /* TIMER 2 CAPTURE REGISTER - LOW BYTE */ 99 SFR( RCAP2H, 0xCB ) ; /* TIMER 2 CAPTURE REGISTER - HIGH BYTE */ 100 SFR( TMR2RLH, 0xCB ) ; /* TIMER 2 CAPTURE REGISTER - HIGH BYTE */ 101 SFR( TL2, 0xCC ) ; /* TIMER 2 - LOW BYTE */ 102 SFR( TMR2L, 0xCC ) ; /* TIMER 2 - LOW BYTE */ 103 SFR( TH2, 0xCD ) ; /* TIMER 2 - HIGH BYTE */ 104 SFR( TMR2H, 0xCD ) ; /* TIMER 2 - HIGH BYTE */ 105 SFR( PSW, 0xD0 ) ; /* PROGRAM STATUS WORD */ 106 SFR( REF0CN, 0xD1 ) ; /* VOLTAGE REFERENCE 0 CONTROL */ 107 SFR( P0SKIP, 0xD4 ) ; /* PORT 0 SKIP */ 108 SFR( P1SKIP, 0xD5 ) ; /* PORT 1 SKIP */ 109 SFR( P2SKIP, 0xD6 ) ; /* PORT 2 SKIP */ 110 SFR( PCA0CN, 0xD8 ) ; /* PCA CONTROL */ 111 SFR( PCA0MD, 0xD9 ) ; /* PCA MODE */ 112 SFR( PCA0CPM0, 0xDA ) ; /* PCA MODULE 0 MODE REGISTER */ 113 SFR( PCA0CPM1, 0xDB ) ; /* PCA MODULE 1 MODE REGISTER */ 114 SFR( PCA0CPM2, 0xDC ) ; /* PCA MODULE 2 MODE REGISTER */ 115 SFR( PCA0CPM3, 0xDD ) ; /* PCA MODULE 3 MODE REGISTER */ 116 SFR( PCA0CPM4, 0xDE ) ; /* PCA MODULE 4 MODE REGISTER */ 117 SFR( ACC, 0xE0 ) ; /* ACCUMULATOR */ 118 SFR( XBR0, 0xE1 ) ; /* PORT MUX CONFIGURATION REGISTER 0 */ 119 SFR( XBR1, 0xE2 ) ; /* PORT MUX CONFIGURATION REGISTER 1 */ 120 SFR( IT01CF, 0xE4 ) ; /* INT0/INT1 CONFIGURATION REGISTER */ 121 SFR( INT01CF, 0xE4 ) ; /* INT0/INT1 CONFIGURATION REGISTER */ 122 SFR( EIE1, 0xE6 ) ; /* EXTERNAL INTERRUPT ENABLE 1 */ 123 SFR( ADC0CN, 0xE8 ) ; /* ADC 0 CONTROL */ 124 SFR( PCA0CPL1, 0xE9 ) ; /* PCA CAPTURE 1 LOW */ 125 SFR( PCA0CPH1, 0xEA ) ; /* PCA CAPTURE 1 HIGH */ 126 SFR( PCA0CPL2, 0xEB ) ; /* PCA CAPTURE 2 LOW */ 127 SFR( PCA0CPH2, 0xEC ) ; /* PCA CAPTURE 2 HIGH */ 128 SFR( PCA0CPL3, 0xED ) ; /* PCA CAPTURE 3 LOW */ 129 SFR( PCA0CPH3, 0xEE ) ; /* PCA CAPTURE 3 HIGH */ 130 SFR( RSTSRC, 0xEF ) ; /* RESET SOURCE */ 131 SFR( B, 0xF0 ) ; /* B REGISTER */ 132 SFR( P0MODE, 0xF1 ) ; /* PORT 0 INPUT MODE CONFIGURATION */ 133 SFR( P0MDIN, 0xF1 ) ; /* PORT 0 INPUT MODE CONFIGURATION */ 134 SFR( P1MODE, 0xF2 ) ; /* PORT 1 INPUT MODE CONFIGURATION */ 135 SFR( P1MDIN, 0xF2 ) ; /* PORT 1 INPUT MODE CONFIGURATION */ 136 SFR( P2MODE, 0xF3 ) ; /* PORT 2 INPUT MODE CONFIGURATION */ 137 SFR( P2MDIN, 0xF3 ) ; /* PORT 2 INPUT MODE CONFIGURATION */ 138 SFR( P3MODE, 0xF4 ) ; /* PORT 3 INPUT MODE CONFIGURATION */ 139 SFR( P3MDIN, 0xF4 ) ; /* PORT 3 INPUT MODE CONFIGURATION */ 140 SFR( EIP1, 0xF6 ) ; /* EXTERNAL INTERRUPT PRIORITY REGISTER 1 */ 141 SFR( SPI0CN, 0xF8 ) ; /* SPI0 CONTROL */ 142 SFR( PCA0L, 0xF9 ) ; /* PCA COUNTER LOW */ 143 SFR( PCA0H, 0xFA ) ; /* PCA COUNTER HIGH */ 144 SFR( PCA0CPL0, 0xFB ) ; /* PCA CAPTURE 0 LOW */ 145 SFR( PCA0CPH0, 0xFC ) ; /* PCA CAPTURE 0 HIGH */ 146 SFR( PCA0CPL4, 0xFD ) ; /* PCA CAPTURE 4 LOW */ 147 SFR( PCA0CPH4, 0xFE ) ; /* PCA CAPTURE 4 HIGH */ 148 SFR( VDM0CN, 0xFF ) ; /* VDD MONITOR CONTROL */ 149 150 151 /* WORD/DWORD Registers */ 152 153 SFR16E( TOFF, 0x8685 ) ; /* TEMPERATURE SENSOR OFFSET WORD */ 154 SFR16E( TMR0, 0x8C8A ) ; /* TIMER 0 COUNTER */ 155 SFR16E( TMR1, 0x8D8B ) ; /* TIMER 1 COUNTER */ 156 SFR16E( TMR2, 0xCDCC ) ; /* TIMER 2 COUNTER */ 157 SFR16E( RCAP2, 0xCBCA ) ; /* TIMER 2 CAPTURE REGISTER WORD */ 158 SFR16E( TMR2RL, 0xCBCA ) ; /* TIMER 2 CAPTURE REGISTER WORD */ 159 SFR16E( TMR3, 0x9594 ) ; /* TIMER 3 COUNTER */ 160 SFR16E( TMR3RL, 0x9392 ) ; /* TIMER 3 CAPTURE REGISTER WORD */ 161 SFR16E( ADC0, 0xBEBD ) ; /* ADC 0 DATA WORD */ 162 SFR16E( ADC0GT, 0xC4C3 ) ; /* ADC 0 GREATER-THAN REGISTER WORD */ 163 SFR16E( ADC0LT, 0xC6C5 ) ; /* ADC 0 LESS-THAN REGISTER WORD */ 164 SFR16E( PCA0, 0xFAF9 ) ; /* PCA COUNTER */ 165 SFR16E( PCA0CP0, 0xFCFB ) ; /* PCA CAPTURE 0 WORD */ 166 SFR16E( PCA0CP1, 0xEAE9 ) ; /* PCA CAPTURE 1 WORD */ 167 SFR16E( PCA0CP2, 0xECEB ) ; /* PCA CAPTURE 2 WORD */ 168 SFR16E( PCA0CP3, 0xEEED ) ; /* PCA CAPTURE 3 WORD */ 169 SFR16E( PCA0CP4, 0xFEFD ) ; /* PCA CAPTURE 4 WORD */ 170 171 172 /* BIT Registers */ 173 174 /* P0 0x80 */ 175 SBIT( P0_0, 0x80, 0 ) ; 176 SBIT( P0_1, 0x80, 1 ) ; 177 SBIT( P0_2, 0x80, 2 ) ; 178 SBIT( P0_3, 0x80, 3 ) ; 179 SBIT( P0_4, 0x80, 4 ) ; 180 SBIT( P0_5, 0x80, 5 ) ; 181 SBIT( P0_6, 0x80, 6 ) ; 182 SBIT( P0_7, 0x80, 7 ) ; 183 184 /* TCON 0x88 */ 185 SBIT( IT0, 0x88, 0 ) ; /* TCON.0 - EXT. INTERRUPT 0 TYPE */ 186 SBIT( IE0, 0x88, 1 ) ; /* TCON.1 - EXT. INTERRUPT 0 EDGE FLAG */ 187 SBIT( IT1, 0x88, 2 ) ; /* TCON.2 - EXT. INTERRUPT 1 TYPE */ 188 SBIT( IE1, 0x88, 3 ) ; /* TCON.3 - EXT. INTERRUPT 1 EDGE FLAG */ 189 SBIT( TR0, 0x88, 4 ) ; /* TCON.4 - TIMER 0 ON/OFF CONTROL */ 190 SBIT( TF0, 0x88, 5 ) ; /* TCON.5 - TIMER 0 OVERFLOW FLAG */ 191 SBIT( TR1, 0x88, 6 ) ; /* TCON.6 - TIMER 1 ON/OFF CONTROL */ 192 SBIT( TF1, 0x88, 7 ) ; /* TCON.7 - TIMER 1 OVERFLOW FLAG */ 193 194 /* P1 0x90 */ 195 SBIT( P1_0, 0x90, 0 ) ; 196 SBIT( P1_1, 0x90, 1 ) ; 197 SBIT( P1_2, 0x90, 2 ) ; 198 SBIT( P1_3, 0x90, 3 ) ; 199 SBIT( P1_4, 0x90, 4 ) ; 200 SBIT( P1_5, 0x90, 5 ) ; 201 SBIT( P1_6, 0x90, 6 ) ; 202 SBIT( P1_7, 0x90, 7 ) ; 203 204 /* SCON 0x98 */ 205 SBIT( RI, 0x98, 0 ) ; /* SCON.0 - RECEIVE INTERRUPT FLAG */ 206 SBIT( RI0, 0x98, 0 ) ; /* SCON.0 - RECEIVE INTERRUPT FLAG */ 207 SBIT( TI, 0x98, 1 ) ; /* SCON.1 - TRANSMIT INTERRUPT FLAG */ 208 SBIT( TI0, 0x98, 1 ) ; /* SCON.1 - TRANSMIT INTERRUPT FLAG */ 209 SBIT( RB8, 0x98, 2 ) ; /* SCON.2 - RECEIVE BIT 8 */ 210 SBIT( RB80, 0x98, 2 ) ; /* SCON.2 - RECEIVE BIT 8 */ 211 SBIT( TB8, 0x98, 3 ) ; /* SCON.3 - TRANSMIT BIT 8 */ 212 SBIT( TB80, 0x98, 3 ) ; /* SCON.3 - TRANSMIT BIT 8 */ 213 SBIT( REN, 0x98, 4 ) ; /* SCON.4 - RECEIVE ENABLE */ 214 SBIT( REN0, 0x98, 4 ) ; /* SCON.4 - RECEIVE ENABLE */ 215 SBIT( SM2, 0x98, 5 ) ; /* SCON.5 - MULTIPROCESSOR COMMUNICATION ENABLE */ 216 SBIT( MCE0, 0x98, 5 ) ; /* SCON.5 - MULTIPROCESSOR COMMUNICATION ENABLE */ 217 SBIT( SM0, 0x98, 7 ) ; /* SCON.7 - SERIAL MODE CONTROL BIT 0 */ 218 SBIT( S0MODE, 0x98, 7 ) ; /* SCON.7 - SERIAL MODE CONTROL BIT 0 */ 219 220 /* P2 0xA0 */ 221 SBIT( P2_0, 0xA0, 0 ) ; 222 SBIT( P2_1, 0xA0, 1 ) ; 223 SBIT( P2_2, 0xA0, 2 ) ; 224 SBIT( P2_3, 0xA0, 3 ) ; 225 SBIT( P2_4, 0xA0, 4 ) ; 226 SBIT( P2_5, 0xA0, 5 ) ; 227 SBIT( P2_6, 0xA0, 6 ) ; 228 SBIT( P2_7, 0xA0, 7 ) ; 229 230 /* IE 0xA8 */ 231 SBIT( EX0, 0xA8, 0 ) ; /* IE.0 - EXTERNAL INTERRUPT 0 ENABLE */ 232 SBIT( ET0, 0xA8, 1 ) ; /* IE.1 - TIMER 0 INTERRUPT ENABLE */ 233 SBIT( EX1, 0xA8, 2 ) ; /* IE.2 - EXTERNAL INTERRUPT 1 ENABLE */ 234 SBIT( ET1, 0xA8, 3 ) ; /* IE.3 - TIMER 1 INTERRUPT ENABLE */ 235 SBIT( ES, 0xA8, 4 ) ; /* IE.4 - SERIAL PORT INTERRUPT ENABLE */ 236 SBIT( ES0, 0xA8, 4 ) ; /* IE.4 - SERIAL PORT INTERRUPT ENABLE */ 237 SBIT( ET2, 0xA8, 5 ) ; /* IE.5 - TIMER 2 INTERRUPT ENABLE */ 238 SBIT( ESPI0, 0xA8, 6 ) ; /* IE.6 - SPI0 INTERRUPT ENABLE */ 239 SBIT( EA, 0xA8, 7 ) ; /* IE.7 - GLOBAL INTERRUPT ENABLE */ 240 241 /* P3 0xB0 */ 242 SBIT( P3_0, 0xB0, 0 ) ; 243 SBIT( P3_1, 0xB0, 1 ) ; 244 SBIT( P3_2, 0xB0, 2 ) ; 245 SBIT( P3_3, 0xB0, 3 ) ; 246 SBIT( P3_4, 0xB0, 4 ) ; 247 SBIT( P3_5, 0xB0, 5 ) ; 248 SBIT( P3_6, 0xB0, 6 ) ; 249 SBIT( P3_7, 0xB0, 7 ) ; 250 251 /* IP 0xB8 */ 252 SBIT( PX0, 0xB8, 0 ) ; /* IP.0 - EXTERNAL INTERRUPT 0 PRIORITY */ 253 SBIT( PT0, 0xB8, 1 ) ; /* IP.1 - TIMER 0 PRIORITY */ 254 SBIT( PX1, 0xB8, 2 ) ; /* IP.2 - EXTERNAL INTERRUPT 1 PRIORITY */ 255 SBIT( PT1, 0xB8, 3 ) ; /* IP.3 - TIMER 1 PRIORITY */ 256 SBIT( PS, 0xB8, 4 ) ; /* IP.4 - SERIAL PORT PRIORITY */ 257 SBIT( PS0, 0xB8, 4 ) ; /* IP.4 - SERIAL PORT PRIORITY */ 258 SBIT( PT2, 0xB8, 5 ) ; /* IP.5 - TIMER 2 PRIORITY */ 259 SBIT( PSPI0, 0xB8, 6 ) ; /* IP.6 - SPI0 PRIORITY */ 260 261 /* SMB0CN 0xC0 */ 262 SBIT( SI, 0xC0, 0 ) ; /* SMB0CN.0 - SMBUS 0 INTERRUPT PENDING FLAG */ 263 SBIT( ACK, 0xC0, 1 ) ; /* SMB0CN.1 - SMBUS 0 ACKNOWLEDGE FLAG */ 264 SBIT( ARBLOST, 0xC0, 2 ) ; /* SMB0CN.2 - SMBUS 0 ARBITRATION LOST INDICATOR */ 265 SBIT( ACKRQ, 0xC0, 3 ) ; /* SMB0CN.3 - SMBUS 0 ACKNOWLEDGE REQUEST */ 266 SBIT( STO, 0xC0, 4 ) ; /* SMB0CN.4 - SMBUS 0 STOP FLAG */ 267 SBIT( STA, 0xC0, 5 ) ; /* SMB0CN.5 - SMBUS 0 START FLAG */ 268 SBIT( TXMODE, 0xC0, 6 ) ; /* SMB0CN.6 - SMBUS 0 TRANSMIT MODE INDICATOR */ 269 SBIT( MASTER, 0xC0, 7 ) ; /* SMB0CN.7 - SMBUS 0 MASTER/SLAVE INDICATOR */ 270 271 /* TMR2CN 0xC8 */ 272 SBIT( T2XCLK, 0xC8, 0 ) ; /* TMR2CN.0 - TIMER 2 EXTERNAL CLOCK SELECT */ 273 SBIT( TR2, 0xC8, 2 ) ; /* TMR2CN.2 - TIMER 2 ON/OFF CONTROL */ 274 SBIT( T2SPLIT, 0xC8, 3 ) ; /* TMR2CN.3 - TIMER 2 SPLIT MODE ENABLE */ 275 SBIT( TF2LEN, 0xC8, 5 ) ; /* TMR2CN.5 - TIMER 2 LOW BYTE INTERRUPT ENABLE */ 276 SBIT( TF2L, 0xC8, 6 ) ; /* TMR2CN.6 - TIMER 2 LOW BYTE OVERFLOW FLAG */ 277 SBIT( TF2, 0xC8, 7 ) ; /* TMR2CN.7 - TIMER 2 OVERFLOW FLAG */ 278 SBIT( TF2H, 0xC8, 7 ) ; /* TMR2CN.7 - TIMER 2 HIGH BYTE OVERFLOW FLAG */ 279 280 /* PSW 0xD0 */ 281 SBIT( PARITY, 0xD0, 0 ) ; /* PSW.0 - ACCUMULATOR PARITY FLAG */ 282 SBIT( F1, 0xD0, 1 ) ; /* PSW.1 - FLAG 1 */ 283 SBIT( OV, 0xD0, 2 ) ; /* PSW.2 - OVERFLOW FLAG */ 284 SBIT( RS0, 0xD0, 3 ) ; /* PSW.3 - REGISTER BANK SELECT 0 */ 285 SBIT( RS1, 0xD0, 4 ) ; /* PSW.4 - REGISTER BANK SELECT 1 */ 286 SBIT( F0, 0xD0, 5 ) ; /* PSW.5 - FLAG 0 */ 287 SBIT( AC, 0xD0, 6 ) ; /* PSW.6 - AUXILIARY CARRY FLAG */ 288 SBIT( CY, 0xD0, 7 ) ; /* PSW.7 - CARRY FLAG */ 289 290 /* PCA0CN 0xD8 */ 291 SBIT( CCF0, 0xD8, 0 ) ; /* PCA0CN.0 - PCA MODULE 0 CAPTURE/COMPARE FLAG */ 292 SBIT( CCF1, 0xD8, 1 ) ; /* PCA0CN.1 - PCA MODULE 1 CAPTURE/COMPARE FLAG */ 293 SBIT( CCF2, 0xD8, 2 ) ; /* PCA0CN.2 - PCA MODULE 2 CAPTURE/COMPARE FLAG */ 294 SBIT( CCF3, 0xD8, 3 ) ; /* PCA0CN.3 - PCA MODULE 3 CAPTURE/COMPARE FLAG */ 295 SBIT( CCF4, 0xD8, 4 ) ; /* PCA0CN.4 - PCA MODULE 4 CAPTURE/COMPARE FLAG */ 296 SBIT( CR, 0xD8, 6 ) ; /* PCA0CN.6 - PCA COUNTER/TIMER RUN CONTROL */ 297 SBIT( CF, 0xD8, 7 ) ; /* PCA0CN.7 - PCA COUNTER/TIMER OVERFLOW FLAG */ 298 299 /* ADC0CN 0xE8 */ 300 SBIT( AD0CM0, 0xE8, 0 ) ; /* ADC0CN.0 - ADC 0 START OF CONV. MODE BIT 0 */ 301 SBIT( AD0CM1, 0xE8, 1 ) ; /* ADC0CN.1 - ADC 0 START OF CONV. MODE BIT 1 */ 302 SBIT( AD0CM2, 0xE8, 2 ) ; /* ADC0CN.2 - ADC 0 START OF CONV. MODE BIT 2 */ 303 SBIT( AD0WINT, 0xE8, 3 ) ; /* ADC0CN.3 - ADC 0 WINDOW COMPARE INT. FLAG */ 304 SBIT( AD0BUSY, 0xE8, 4 ) ; /* ADC0CN.4 - ADC 0 BUSY FLAG */ 305 SBIT( AD0INT, 0xE8, 5 ) ; /* ADC0CN.5 - ADC 0 CONV. COMPLETE INT. FLAG */ 306 SBIT( AD0TM, 0xE8, 6 ) ; /* ADC0CN.6 - ADC 0 TRACK MODE */ 307 SBIT( AD0EN, 0xE8, 7 ) ; /* ADC0CN.7 - ADC 0 ENABLE */ 308 309 /* SPI0CN 0xF8 */ 310 SBIT( SPIEN, 0xF8, 0 ) ; /* SPI0CN.0 - SPI0 ENABLE */ 311 SBIT( TXBMT, 0xF8, 1 ) ; /* SPI0CN.1 - TRANSMIT BUFFER EMPTY */ 312 SBIT( NSSMD0, 0xF8, 2 ) ; /* SPI0CN.2 - SLAVE SELECT MODE BIT 0 */ 313 SBIT( NSSMD1, 0xF8, 3 ) ; /* SPI0CN.3 - SLAVE SELECT MODE BIT 1 */ 314 SBIT( RXOVRN, 0xF8, 4 ) ; /* SPI0CN.4 - RECEIVE OVERRUN FLAG */ 315 SBIT( MODF, 0xF8, 5 ) ; /* SPI0CN.5 - MODE FAULT FLAG */ 316 SBIT( WCOL, 0xF8, 6 ) ; /* SPI0CN.6 - WRITE COLLISION FLAG */ 317 SBIT( SPIF, 0xF8, 7 ) ; /* SPI0CN.7 - SPI0 INTERRUPT FLAG */ 318 319 320 /* Predefined SFR Bit Masks */ 321 322 #define PCON_IDLE 0x01 /* PCON */ 323 #define PCON_STOP 0x02 /* PCON */ 324 #define T1M 0x08 /* CKCON */ 325 #define PSWE 0x01 /* PSCTL */ 326 #define PSEE 0x02 /* PSCTL */ 327 #define ECP0 0x20 /* EIE1 */ 328 #define ECP1 0x40 /* EIE1 */ 329 #define PORSF 0x02 /* RSTSRC */ 330 #define SWRSF 0x10 /* RSTSRC */ 331 #define ECCF 0x01 /* PCA0CPMn */ 332 #define PWM 0x02 /* PCA0CPMn */ 333 #define TOG 0x04 /* PCA0CPMn */ 334 #define MAT 0x08 /* PCA0CPMn */ 335 #define CAPN 0x10 /* PCA0CPMn */ 336 #define CAPP 0x20 /* PCA0CPMn */ 337 #define ECOM 0x40 /* PCA0CPMn */ 338 #define PWM16 0x80 /* PCA0CPMn */ 339 #define CP0E 0x10 /* XBR0 */ 340 #define CP0OEN 0x10 /* XBR0 */ 341 #define CP0AE 0x20 /* XBR0 */ 342 #define CP0AOEN 0x20 /* XBR0 */ 343 #define CP1E 0x40 /* XBR0 */ 344 #define CP1AE 0x80 /* XBR0 */ 345 346 /* Interrupts */ 347 348 #define INT_EXT0 0 /* External Interrupt 0 */ 349 #define INT_TIMER0 1 /* Timer0 Overflow */ 350 #define INT_EXT1 2 /* External Interrupt 1 */ 351 #define INT_TIMER1 3 /* Timer1 Overflow */ 352 #define INT_UART0 4 /* Serial Port 0 */ 353 #define INT_TIMER2 5 /* Timer2 Overflow */ 354 #define INT_SPI0 6 /* Serial Peripheral Interface 0 */ 355 #define INT_SMBUS0 7 /* SMBus0 Interface */ 356 /* 8 Reserved */ 357 #define INT_ADC0_WINDOW 9 /* ADC0 Window Comparison */ 358 #define INT_ADC0_EOC 10 /* ADC0 End Of Conversion */ 359 #define INT_PCA0 11 /* PCA0 Peripheral */ 360 #define INT_COMPARATOR0 12 /* Comparator0 */ 361 #define INT_COMPARATOR1 13 /* Comparator1 */ 362 #define INT_TIMER3 14 /* Timer3 Overflow */ 363 364 #endif 365