1 /*------------------------------------------------------------------------- 2 reg764 - register Declarations for 87C764 3 4 Copyright (C) 2005, Robert Lacoste <robert_lacoste AT yahoo.fr> 5 based upon reg51.h written by Sandeep Dutta 6 Registers are taken from the Phillips Semiconductor 7 8 This library is free software; you can redistribute it and/or modify it 9 under the terms of the GNU General Public License as published by the 10 Free Software Foundation; either version 2, or (at your option) any 11 later version. 12 13 This library is distributed in the hope that it will be useful, 14 but WITHOUT ANY WARRANTY; without even the implied warranty of 15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 GNU General Public License for more details. 17 18 You should have received a copy of the GNU General Public License 19 along with this library; see the file COPYING. If not, write to the 20 Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston, 21 MA 02110-1301, USA. 22 23 As a special exception, if you link this library with other files, 24 some of which are compiled with SDCC, to produce an executable, 25 this library does not by itself cause the resulting executable to 26 be covered by the GNU General Public License. This exception does 27 not however invalidate any other reasons why the executable file 28 might be covered by the GNU General Public License. 29 -------------------------------------------------------------------------*/ 30 31 #ifndef REGC764_H 32 #define REGC764_H 33 34 /* Special Function Registers */ 35 36 __sfr __at 0x80 P0 ; // Port 0 37 __sfr __at 0x81 SP ; // Stack Pointer 38 __sfr __at 0x82 DPL ; // Data Pointer Low 39 __sfr __at 0x83 DPH ; // Data Pointer High 40 __sfr __at 0x84 P0M1 ; // Port 0 output mode 1 41 __sfr __at 0x85 P0M2 ; // Port 0 output mode 2 42 __sfr __at 0x86 KBI ; // Keyboard interrupt 43 __sfr __at 0x87 PCON ; // Power Control 44 __sfr __at 0x88 TCON ; // Timer Control 45 __sfr __at 0x89 TMOD ; // Timer Mode 46 __sfr __at 0x8A TL0 ; // Timer Low 0 47 __sfr __at 0x8B TL1 ; // Timer Low 1 48 __sfr __at 0x8C TH0 ; // Timer High 0 49 __sfr __at 0x8D TH1 ; // Timer High 1 50 51 __sfr __at 0x90 P1 ; // Port 1 52 __sfr __at 0x91 P1M1 ; // Port 1 output mode 1 53 __sfr __at 0x92 P1M2 ; // Port 1 output mode 2 54 __sfr __at 0x95 DIVM ; // CPU clock divide by N control 55 __sfr __at 0x98 SCON ; // Serial Control 56 __sfr __at 0x99 SBUF ; // Serial Data Buffer 57 58 __sfr __at 0xA0 P2 ; // Port 2 59 __sfr __at 0xA2 AUXR1 ; // Auxilliary 1 (not available on 80C51FA/87C51Fx) 60 __sfr __at 0xA4 P2M1 ; // Port 2 output mode 1 61 __sfr __at 0xA5 P2M2 ; // Port 2 output mode 2 62 __sfr __at 0xA6 WDRST ; // Watchdog reset register 63 __sfr __at 0xA7 WDCON ; // Watchdog control register 64 __sfr __at 0xA8 IEN0 ; // Interrupt Enable 0 65 __sfr __at 0xA9 SADDR ; // Serial slave Address 66 __sfr __at 0xAC CMP1 ; // Comparator 1 control register 67 __sfr __at 0xAD CMP2 ; // Comparator 2 control register 68 69 __sfr __at 0xB7 IP0H ; // Interrupt Priority 0 High 70 __sfr __at 0xB8 IP0 ; // Interrupt Priority 0 71 __sfr __at 0xB9 SADEN ; // Serial slave Address Mask 72 73 __sfr __at 0xC8 I2CFG ; // I2C configuration register 74 75 __sfr __at 0xD0 PSW ; // Program Status Word 76 __sfr __at 0xD8 I2CON ; // I2C control register 77 __sfr __at 0xD9 I2DAT ; // I2C data register 78 79 __sfr __at 0xE0 ACC ; // Accumulator 80 __sfr __at 0xE8 IEN1 ; // Interrupt enable 1 81 82 __sfr __at 0xF0 B ; // B Register 83 __sfr __at 0xF6 PT0AD ; // Port 0 digital input disable 84 __sfr __at 0xF7 IP1H ; // Interrupt Priority 1 High 85 __sfr __at 0xF8 IP1 ; // Interrupt Priority 1 86 87 88 /* Bit Addressable Registers */ 89 90 /* P0 */ 91 __sbit __at 0x80 P0_0 ; // Also CMP2 92 __sbit __at 0x81 P0_1 ; // Also CIN2B 93 __sbit __at 0x82 P0_2 ; // Also CIN2A 94 __sbit __at 0x83 P0_3 ; // Also CIN1B 95 __sbit __at 0x84 P0_4 ; // Also CIN1A 96 __sbit __at 0x85 P0_5 ; // Also CMPREF 97 __sbit __at 0x86 P0_6 ; // Also CMP1 98 __sbit __at 0x87 P0_7 ; // Also T1 99 100 /* TCON */ 101 __sbit __at 0x88 IT0 ; // External Interrupt 0 Type 102 __sbit __at 0x89 IE0 ; // External Interrupt 0 Edge Flag 103 __sbit __at 0x8A IT1 ; // External Interrupt 1 Type 104 __sbit __at 0x8B IE1 ; // External Interrupt 1 Edge Flag 105 __sbit __at 0x8C TR0 ; // Timer 0 Run Control 106 __sbit __at 0x8D TF0 ; // Timer 0 Overflow Flag 107 __sbit __at 0x8E TR1 ; // Timer 1 Run Control 108 __sbit __at 0x8F TF1 ; // Timer 1 Overflow Flag 109 110 /* P1 */ 111 __sbit __at 0x90 P1_0 ; // Also TxD 112 __sbit __at 0x91 P1_1 ; // Also RxD 113 __sbit __at 0x92 P1_2 ; // Also T0 114 __sbit __at 0x93 P1_3 ; // Also INT0 115 __sbit __at 0x94 P1_4 ; // Also INT1 116 __sbit __at 0x95 P1_5 ; // Also RST 117 __sbit __at 0x96 P1_6 ; 118 __sbit __at 0x97 P1_7 ; 119 120 /* SCON */ 121 __sbit __at 0x98 RI ; // Receive Interrupt Flag 122 __sbit __at 0x99 TI ; // Transmit Interrupt Flag 123 __sbit __at 0x9A RB8 ; // Receive Bit 8 124 __sbit __at 0x9B TB8 ; // Transmit Bit 8 125 __sbit __at 0x9C REN ; // Receiver Enable 126 __sbit __at 0x9D SM2 ; // Serial Mode Control Bit 2 127 __sbit __at 0x9E SM1 ; // Serial Mode Control Bit 1 128 __sbit __at 0x9F SM0 ; // Serial Mode Control Bit 0 129 130 /* P2 */ 131 __sbit __at 0xA0 P2_0 ; // Also X2 132 __sbit __at 0xA1 P2_1 ; // Also X1 133 134 /* IEN0 */ 135 __sbit __at 0xA8 EX0 ; // External Interrupt 0 Enable 136 __sbit __at 0xA9 ET0 ; // Timer 0 Interrupt Enable 137 __sbit __at 0xAA EX1 ; // External Interrupt 1 Enable 138 __sbit __at 0xAB ET1 ; // Timer 1 Interrupt Enable 139 __sbit __at 0xAC ES ; // Serial Port Interrupt Enable 140 __sbit __at 0xAD EBO ; // Brownout Interrupt Enable 141 __sbit __at 0xAE EWD ; // Watchdog Interrupt Enable 142 __sbit __at 0xAF EA ; // Global Interrupt Enable 143 144 /* IP0 */ 145 __sbit __at 0xB8 PX0 ; // External Interrupt 0 Priority 146 __sbit __at 0xB9 PT0 ; // Timer 0 Interrupt Priority 147 __sbit __at 0xBA PX1 ; // External Interrupt 1 Priority 148 __sbit __at 0xBB PT1 ; // Timer 1 Interrupt Priority 149 __sbit __at 0xBC PS ; // Serial Port Interrupt Priority 150 __sbit __at 0xBD PBO ; // Brownout Interrupt Priority 151 __sbit __at 0xBE PWD ; // Watchdog Interrupt Priority 152 153 /* I2CFG */ 154 __sbit __at 0xC8 CT0 ; // Clock Time Select 0 155 __sbit __at 0xC9 CT1 ; // Clock Time Select 1 156 __sbit __at 0xCC TIRUN ; // Timer I Run Enable 157 __sbit __at 0xCD CLRTI ; // Clear Timer I 158 __sbit __at 0xCE MASTRQ; // Master Request 159 __sbit __at 0xCF SLAVEN; // Slave Enable 160 161 /* PSW */ 162 __sbit __at 0xD0 P ; // Accumulator Parity Flag 163 __sbit __at 0xD1 F1 ; // Flag 1 164 __sbit __at 0xD2 OV ; // Overflow Flag 165 __sbit __at 0xD3 RS0 ; // Register Bank Select 0 166 __sbit __at 0xD4 RS1 ; // Register Bank Select 1 167 __sbit __at 0xD5 F0 ; // Flag 0 168 __sbit __at 0xD6 AC ; // Auxiliary Carry Flag 169 __sbit __at 0xD7 CY ; // Carry Flag 170 171 /* I2CON */ 172 __sbit __at 0xD8 XSTP ; 173 __sbit __at 0xD9 MASTER;// Master Status 174 __sbit __at 0xDA STP ; // Stop Detect Flag 175 __sbit __at 0xDB STR ; // Start Detect Flag 176 __sbit __at 0xDC ARL ; // Arbitration Loss Flag 177 __sbit __at 0xDD DRDY ; // Data Ready Flag 178 __sbit __at 0xDE ATN ; // Attention: I2C Interrupt Flag 179 __sbit __at 0xDF RDAT ; // I2C Read Data 180 181 /* ACC */ 182 __sbit __at 0xE0 ACC_0; 183 __sbit __at 0xE1 ACC_1; 184 __sbit __at 0xE2 ACC_2; 185 __sbit __at 0xE3 ACC_3; 186 __sbit __at 0xE4 ACC_4; 187 __sbit __at 0xE5 ACC_5; 188 __sbit __at 0xE6 ACC_6; 189 __sbit __at 0xE7 ACC_7; 190 191 /* IEN1 */ 192 __sbit __at 0xE8 EI2 ; // I2C Interrupt Enable 193 __sbit __at 0xE9 EKB ; // Keyboard Interrupt Enable 194 __sbit __at 0xEA EC2 ; // Comparator 2 Interrupt Enable 195 __sbit __at 0xED EC1 ; // Comparator 1 Interrupt Enable 196 __sbit __at 0xEF ETI ; // Timer I Interrupt Enable 197 198 /* B */ 199 __sbit __at 0xF0 B_0; 200 __sbit __at 0xF1 B_1; 201 __sbit __at 0xF2 B_2; 202 __sbit __at 0xF3 B_3; 203 __sbit __at 0xF4 B_4; 204 __sbit __at 0xF5 B_5; 205 __sbit __at 0xF6 B_6; 206 __sbit __at 0xF7 B_7; 207 208 /* IP1 */ 209 __sbit __at 0xF8 PI2; // I2C Interrupt Priority 210 __sbit __at 0xF9 PKB; // Keyboard Interrupt Priority 211 __sbit __at 0xFA PC2; // Comparator 2 Interrupt Priority 212 __sbit __at 0xFD PC1; // Comparator 1 Interrupt Priority 213 __sbit __at 0xFF PTI; // Timer I Interrupt Priority 214 215 /* Bitmasks for SFRs */ 216 217 /* AUXR1 bits */ 218 #define DPS 0x01 219 #define SRST 0x08 220 #define LPEP 0x10 221 #define BOI 0x20 222 #define BOD 0x40 223 #define KBF 0x80 224 225 /* CMP1 bits */ 226 #define CMF1 0x01 227 #define CO1 0x02 228 #define OE1 0x04 229 #define CN1 0x08 230 #define CP1 0x10 231 #define CE1 0x20 232 233 /* CMP2 bits */ 234 #define CMF2 0x01 235 #define CO2 0x02 236 #define OE2 0x04 237 #define CN2 0x08 238 #define CP2 0x10 239 #define CE2 0x20 240 241 /* I2DAT bits */ 242 #define RDAT 0x80 243 #define XDAT 0x80 244 245 /* IP1H bits */ 246 #define PI2H 0x01 247 #define PKBH 0x02 248 #define PC2H 0x04 249 #define PC1H 0x20 250 #define PTIH 0x80 251 252 /* PCON bits */ 253 #define IDL 0x01 254 #define PD 0x02 255 #define GF0 0x04 256 #define GF1 0x08 257 #define POF 0x10 258 #define BOF 0x20 259 #define SMOD0 0x40 260 #define SMOD1 0x80 261 262 /* P2M1 bits */ 263 #define ENT0 0x04 264 #define ENT1 0x08 265 #define ENTCLK 0x10 266 #define P0S 0x20 267 #define P1S 0x40 268 #define P2S 0x80 269 270 /* TMOD bits */ 271 #define M0_0 0x01 272 #define M1_0 0x02 273 #define C_T0 0x04 274 #define GATE0 0x08 275 #define M0_1 0x10 276 #define M1_1 0x20 277 #define C_T1 0x40 278 #define GATE1 0x80 279 280 /* WDCON bits */ 281 #define WDS0 0x01 282 #define WDS1 0x02 283 #define WDS2 0x04 284 #define WDCLK 0x08 285 #define WDRUN 0x10 286 #define WDOVF 0x20 287 288 289 /* Masks for I2CFG bits */ 290 #define BTIR 0x10 // Mask for TIRUN bit. 291 #define BMRQ 0x40 // Mask for MASTRQ bit. 292 #define BSLV 0x80 // Mask for SLAVEN bit. 293 294 295 /* Masks for I2CON bits */ 296 #define BCXA 0x80 // Mask for CXA bit. 297 #define BIDLE 0x40 // Mask for IDLE bit. 298 #define BCDR 0x20 // Mask for CDR bit. 299 #define BCARL 0x10 // Mask for CARL bit. 300 #define BCSTR 0x08 // Mask for CSTR bit. 301 #define BCSTP 0x04 // Mask for CSTP bit. 302 #define BXSTR 0x02 // Mask for XSTR bit. 303 #define BXSTP 0x01 // Mask for XSTP bit. 304 305 306 #endif 307