1 /* 2 * This definitions of the PIC18F1230 MCU. 3 * 4 * This file is part of the GNU PIC library for SDCC, originally 5 * created by Molnar Karoly <molnarkaroly@users.sf.net> 2016. 6 * 7 * This file is generated automatically by the cinc2h.pl, 2016-04-13 17:23:42 UTC. 8 * 9 * SDCC is licensed under the GNU Public license (GPL) v2. Note that 10 * this license covers the code to the compiler and other executables, 11 * but explicitly does not cover any code or objects generated by sdcc. 12 * 13 * For pic device libraries and header files which are derived from 14 * Microchip header (.inc) and linker script (.lkr) files Microchip 15 * requires that "The header files should state that they are only to be 16 * used with authentic Microchip devices" which makes them incompatible 17 * with the GPL. Pic device libraries and header files are located at 18 * non-free/lib and non-free/include directories respectively. 19 * Sdcc should be run with the --use-non-free command line option in 20 * order to include non-free header files and libraries. 21 * 22 * See http://sdcc.sourceforge.net/ for the latest information on sdcc. 23 */ 24 25 #include <pic18f1230.h> 26 27 //============================================================================== 28 29 __at(0x0F80) __sfr PORTA; 30 __at(0x0F80) volatile __PORTAbits_t PORTAbits; 31 32 __at(0x0F81) __sfr PORTB; 33 __at(0x0F81) volatile __PORTBbits_t PORTBbits; 34 35 __at(0x0F82) __sfr OVDCONS; 36 __at(0x0F82) volatile __OVDCONSbits_t OVDCONSbits; 37 38 __at(0x0F83) __sfr OVDCOND; 39 __at(0x0F83) volatile __OVDCONDbits_t OVDCONDbits; 40 41 __at(0x0F84) __sfr DTCON; 42 __at(0x0F84) volatile __DTCONbits_t DTCONbits; 43 44 __at(0x0F85) __sfr PWMCON1; 45 __at(0x0F85) volatile __PWMCON1bits_t PWMCON1bits; 46 47 __at(0x0F86) __sfr PWMCON0; 48 __at(0x0F86) volatile __PWMCON0bits_t PWMCON0bits; 49 50 __at(0x0F87) __sfr SEVTCMPH; 51 52 __at(0x0F88) __sfr SEVTCMPL; 53 54 __at(0x0F89) __sfr LATA; 55 __at(0x0F89) volatile __LATAbits_t LATAbits; 56 57 __at(0x0F8A) __sfr LATB; 58 __at(0x0F8A) volatile __LATBbits_t LATBbits; 59 60 __at(0x0F8B) __sfr FLTCONFIG; 61 __at(0x0F8B) volatile __FLTCONFIGbits_t FLTCONFIGbits; 62 63 __at(0x0F8C) __sfr PDC2H; 64 65 __at(0x0F8D) __sfr PDC2L; 66 67 __at(0x0F8E) __sfr PDC1H; 68 69 __at(0x0F8F) __sfr PDC1L; 70 71 __at(0x0F90) __sfr PDC0H; 72 73 __at(0x0F91) __sfr PDC0L; 74 75 __at(0x0F92) __sfr DDRA; 76 __at(0x0F92) volatile __DDRAbits_t DDRAbits; 77 78 __at(0x0F92) __sfr TRISA; 79 __at(0x0F92) volatile __TRISAbits_t TRISAbits; 80 81 __at(0x0F93) __sfr DDRB; 82 __at(0x0F93) volatile __DDRBbits_t DDRBbits; 83 84 __at(0x0F93) __sfr TRISB; 85 __at(0x0F93) volatile __TRISBbits_t TRISBbits; 86 87 __at(0x0F95) __sfr PTPERH; 88 89 __at(0x0F96) __sfr PTPERL; 90 91 __at(0x0F97) __sfr PTMRH; 92 93 __at(0x0F98) __sfr PTMRL; 94 95 __at(0x0F99) __sfr PTCON1; 96 __at(0x0F99) volatile __PTCON1bits_t PTCON1bits; 97 98 __at(0x0F9A) __sfr PTCON0; 99 __at(0x0F9A) volatile __PTCON0bits_t PTCON0bits; 100 101 __at(0x0F9B) __sfr OSCTUNE; 102 __at(0x0F9B) volatile __OSCTUNEbits_t OSCTUNEbits; 103 104 __at(0x0F9D) __sfr PIE1; 105 __at(0x0F9D) volatile __PIE1bits_t PIE1bits; 106 107 __at(0x0F9E) __sfr PIR1; 108 __at(0x0F9E) volatile __PIR1bits_t PIR1bits; 109 110 __at(0x0F9F) __sfr IPR1; 111 __at(0x0F9F) volatile __IPR1bits_t IPR1bits; 112 113 __at(0x0FA0) __sfr PIE2; 114 __at(0x0FA0) volatile __PIE2bits_t PIE2bits; 115 116 __at(0x0FA1) __sfr PIR2; 117 __at(0x0FA1) volatile __PIR2bits_t PIR2bits; 118 119 __at(0x0FA2) __sfr IPR2; 120 __at(0x0FA2) volatile __IPR2bits_t IPR2bits; 121 122 __at(0x0FA3) __sfr PIE3; 123 __at(0x0FA3) volatile __PIE3bits_t PIE3bits; 124 125 __at(0x0FA4) __sfr PIR3; 126 __at(0x0FA4) volatile __PIR3bits_t PIR3bits; 127 128 __at(0x0FA5) __sfr IPR3; 129 __at(0x0FA5) volatile __IPR3bits_t IPR3bits; 130 131 __at(0x0FA6) __sfr EECON1; 132 __at(0x0FA6) volatile __EECON1bits_t EECON1bits; 133 134 __at(0x0FA7) __sfr EECON2; 135 136 __at(0x0FA8) __sfr EEDATA; 137 138 __at(0x0FA9) __sfr EEADR; 139 140 __at(0x0FAB) __sfr RCSTA; 141 __at(0x0FAB) volatile __RCSTAbits_t RCSTAbits; 142 143 __at(0x0FAC) __sfr TXSTA; 144 __at(0x0FAC) volatile __TXSTAbits_t TXSTAbits; 145 146 __at(0x0FAD) __sfr TXREG; 147 148 __at(0x0FAE) __sfr RCREG; 149 150 __at(0x0FAF) __sfr SPBRG; 151 152 __at(0x0FB0) __sfr SPBRGH; 153 154 __at(0x0FB4) __sfr CMCON; 155 __at(0x0FB4) volatile __CMCONbits_t CMCONbits; 156 157 __at(0x0FB5) __sfr CVRCON; 158 __at(0x0FB5) volatile __CVRCONbits_t CVRCONbits; 159 160 __at(0x0FB8) __sfr BAUDCON; 161 __at(0x0FB8) volatile __BAUDCONbits_t BAUDCONbits; 162 163 __at(0x0FB8) __sfr BAUDCTL; 164 __at(0x0FB8) volatile __BAUDCTLbits_t BAUDCTLbits; 165 166 __at(0x0FC0) __sfr ADCON2; 167 __at(0x0FC0) volatile __ADCON2bits_t ADCON2bits; 168 169 __at(0x0FC1) __sfr ADCON1; 170 __at(0x0FC1) volatile __ADCON1bits_t ADCON1bits; 171 172 __at(0x0FC2) __sfr ADCON0; 173 __at(0x0FC2) volatile __ADCON0bits_t ADCON0bits; 174 175 __at(0x0FC3) __sfr ADRES; 176 177 __at(0x0FC3) __sfr ADRESL; 178 179 __at(0x0FC4) __sfr ADRESH; 180 181 __at(0x0FCD) __sfr T1CON; 182 __at(0x0FCD) volatile __T1CONbits_t T1CONbits; 183 184 __at(0x0FCE) __sfr TMR1; 185 186 __at(0x0FCE) __sfr TMR1L; 187 188 __at(0x0FCF) __sfr TMR1H; 189 190 __at(0x0FD0) __sfr RCON; 191 __at(0x0FD0) volatile __RCONbits_t RCONbits; 192 193 __at(0x0FD1) __sfr WDTCON; 194 __at(0x0FD1) volatile __WDTCONbits_t WDTCONbits; 195 196 __at(0x0FD2) __sfr LVDCON; 197 __at(0x0FD2) volatile __LVDCONbits_t LVDCONbits; 198 199 __at(0x0FD3) __sfr OSCCON; 200 __at(0x0FD3) volatile __OSCCONbits_t OSCCONbits; 201 202 __at(0x0FD5) __sfr T0CON; 203 __at(0x0FD5) volatile __T0CONbits_t T0CONbits; 204 205 __at(0x0FD6) __sfr TMR0; 206 207 __at(0x0FD6) __sfr TMR0L; 208 209 __at(0x0FD7) __sfr TMR0H; 210 211 __at(0x0FD8) __sfr STATUS; 212 __at(0x0FD8) volatile __STATUSbits_t STATUSbits; 213 214 __at(0x0FD9) __sfr FSR2L; 215 216 __at(0x0FDA) __sfr FSR2H; 217 218 __at(0x0FDB) __sfr PLUSW2; 219 220 __at(0x0FDC) __sfr PREINC2; 221 222 __at(0x0FDD) __sfr POSTDEC2; 223 224 __at(0x0FDE) __sfr POSTINC2; 225 226 __at(0x0FDF) __sfr INDF2; 227 228 __at(0x0FE0) __sfr BSR; 229 230 __at(0x0FE1) __sfr FSR1L; 231 232 __at(0x0FE2) __sfr FSR1H; 233 234 __at(0x0FE3) __sfr PLUSW1; 235 236 __at(0x0FE4) __sfr PREINC1; 237 238 __at(0x0FE5) __sfr POSTDEC1; 239 240 __at(0x0FE6) __sfr POSTINC1; 241 242 __at(0x0FE7) __sfr INDF1; 243 244 __at(0x0FE8) __sfr WREG; 245 246 __at(0x0FE9) __sfr FSR0L; 247 248 __at(0x0FEA) __sfr FSR0H; 249 250 __at(0x0FEB) __sfr PLUSW0; 251 252 __at(0x0FEC) __sfr PREINC0; 253 254 __at(0x0FED) __sfr POSTDEC0; 255 256 __at(0x0FEE) __sfr POSTINC0; 257 258 __at(0x0FEF) __sfr INDF0; 259 260 __at(0x0FF0) __sfr INTCON3; 261 __at(0x0FF0) volatile __INTCON3bits_t INTCON3bits; 262 263 __at(0x0FF1) __sfr INTCON2; 264 __at(0x0FF1) volatile __INTCON2bits_t INTCON2bits; 265 266 __at(0x0FF2) __sfr INTCON; 267 __at(0x0FF2) volatile __INTCONbits_t INTCONbits; 268 269 __at(0x0FF3) __sfr PROD; 270 271 __at(0x0FF3) __sfr PRODL; 272 273 __at(0x0FF4) __sfr PRODH; 274 275 __at(0x0FF5) __sfr TABLAT; 276 277 __at(0x0FF6) __sfr TBLPTR; 278 279 __at(0x0FF6) __sfr TBLPTRL; 280 281 __at(0x0FF7) __sfr TBLPTRH; 282 283 __at(0x0FF8) __sfr TBLPTRU; 284 285 __at(0x0FF9) __sfr PC; 286 287 __at(0x0FF9) __sfr PCL; 288 289 __at(0x0FFA) __sfr PCLATH; 290 291 __at(0x0FFB) __sfr PCLATU; 292 293 __at(0x0FFC) __sfr STKPTR; 294 __at(0x0FFC) volatile __STKPTRbits_t STKPTRbits; 295 296 __at(0x0FFD) __sfr TOS; 297 298 __at(0x0FFD) __sfr TOSL; 299 300 __at(0x0FFE) __sfr TOSH; 301 302 __at(0x0FFF) __sfr TOSU; 303