1 /* 2 * This definitions of the PIC18F45K22 MCU. 3 * 4 * This file is part of the GNU PIC library for SDCC, originally 5 * created by Molnar Karoly <molnarkaroly@users.sf.net> 2016. 6 * 7 * This file is generated automatically by the cinc2h.pl, 2016-04-13 17:23:30 UTC. 8 * 9 * SDCC is licensed under the GNU Public license (GPL) v2. Note that 10 * this license covers the code to the compiler and other executables, 11 * but explicitly does not cover any code or objects generated by sdcc. 12 * 13 * For pic device libraries and header files which are derived from 14 * Microchip header (.inc) and linker script (.lkr) files Microchip 15 * requires that "The header files should state that they are only to be 16 * used with authentic Microchip devices" which makes them incompatible 17 * with the GPL. Pic device libraries and header files are located at 18 * non-free/lib and non-free/include directories respectively. 19 * Sdcc should be run with the --use-non-free command line option in 20 * order to include non-free header files and libraries. 21 * 22 * See http://sdcc.sourceforge.net/ for the latest information on sdcc. 23 */ 24 25 #include <pic18f45k22.h> 26 27 //============================================================================== 28 29 __at(0x0F38) __sfr ANSELA; 30 __at(0x0F38) volatile __ANSELAbits_t ANSELAbits; 31 32 __at(0x0F39) __sfr ANSELB; 33 __at(0x0F39) volatile __ANSELBbits_t ANSELBbits; 34 35 __at(0x0F3A) __sfr ANSELC; 36 __at(0x0F3A) volatile __ANSELCbits_t ANSELCbits; 37 38 __at(0x0F3B) __sfr ANSELD; 39 __at(0x0F3B) volatile __ANSELDbits_t ANSELDbits; 40 41 __at(0x0F3C) __sfr ANSELE; 42 __at(0x0F3C) volatile __ANSELEbits_t ANSELEbits; 43 44 __at(0x0F3D) __sfr PMD2; 45 __at(0x0F3D) volatile __PMD2bits_t PMD2bits; 46 47 __at(0x0F3E) __sfr PMD1; 48 __at(0x0F3E) volatile __PMD1bits_t PMD1bits; 49 50 __at(0x0F3F) __sfr PMD0; 51 __at(0x0F3F) volatile __PMD0bits_t PMD0bits; 52 53 __at(0x0F40) __sfr DACCON1; 54 __at(0x0F40) volatile __DACCON1bits_t DACCON1bits; 55 56 __at(0x0F40) __sfr VREFCON2; 57 __at(0x0F40) volatile __VREFCON2bits_t VREFCON2bits; 58 59 __at(0x0F41) __sfr DACCON0; 60 __at(0x0F41) volatile __DACCON0bits_t DACCON0bits; 61 62 __at(0x0F41) __sfr VREFCON1; 63 __at(0x0F41) volatile __VREFCON1bits_t VREFCON1bits; 64 65 __at(0x0F42) __sfr FVRCON; 66 __at(0x0F42) volatile __FVRCONbits_t FVRCONbits; 67 68 __at(0x0F42) __sfr VREFCON0; 69 __at(0x0F42) volatile __VREFCON0bits_t VREFCON0bits; 70 71 __at(0x0F43) __sfr CTMUICON; 72 __at(0x0F43) volatile __CTMUICONbits_t CTMUICONbits; 73 74 __at(0x0F43) __sfr CTMUICONH; 75 __at(0x0F43) volatile __CTMUICONHbits_t CTMUICONHbits; 76 77 __at(0x0F44) __sfr CTMUCON1; 78 __at(0x0F44) volatile __CTMUCON1bits_t CTMUCON1bits; 79 80 __at(0x0F44) __sfr CTMUCONL; 81 __at(0x0F44) volatile __CTMUCONLbits_t CTMUCONLbits; 82 83 __at(0x0F45) __sfr CTMUCON0; 84 __at(0x0F45) volatile __CTMUCON0bits_t CTMUCON0bits; 85 86 __at(0x0F45) __sfr CTMUCONH; 87 __at(0x0F45) volatile __CTMUCONHbits_t CTMUCONHbits; 88 89 __at(0x0F46) __sfr SRCON1; 90 __at(0x0F46) volatile __SRCON1bits_t SRCON1bits; 91 92 __at(0x0F47) __sfr SRCON0; 93 __at(0x0F47) volatile __SRCON0bits_t SRCON0bits; 94 95 __at(0x0F48) __sfr CCPTMRS1; 96 __at(0x0F48) volatile __CCPTMRS1bits_t CCPTMRS1bits; 97 98 __at(0x0F49) __sfr CCPTMRS0; 99 __at(0x0F49) volatile __CCPTMRS0bits_t CCPTMRS0bits; 100 101 __at(0x0F4A) __sfr T6CON; 102 __at(0x0F4A) volatile __T6CONbits_t T6CONbits; 103 104 __at(0x0F4B) __sfr PR6; 105 106 __at(0x0F4C) __sfr TMR6; 107 108 __at(0x0F4D) __sfr T5GCON; 109 __at(0x0F4D) volatile __T5GCONbits_t T5GCONbits; 110 111 __at(0x0F4E) __sfr T5CON; 112 __at(0x0F4E) volatile __T5CONbits_t T5CONbits; 113 114 __at(0x0F4F) __sfr TMR5; 115 116 __at(0x0F4F) __sfr TMR5L; 117 118 __at(0x0F50) __sfr TMR5H; 119 120 __at(0x0F51) __sfr T4CON; 121 __at(0x0F51) volatile __T4CONbits_t T4CONbits; 122 123 __at(0x0F52) __sfr PR4; 124 125 __at(0x0F53) __sfr TMR4; 126 127 __at(0x0F54) __sfr CCP5CON; 128 __at(0x0F54) volatile __CCP5CONbits_t CCP5CONbits; 129 130 __at(0x0F55) __sfr CCPR5; 131 132 __at(0x0F55) __sfr CCPR5L; 133 134 __at(0x0F56) __sfr CCPR5H; 135 136 __at(0x0F57) __sfr CCP4CON; 137 __at(0x0F57) volatile __CCP4CONbits_t CCP4CONbits; 138 139 __at(0x0F58) __sfr CCPR4; 140 141 __at(0x0F58) __sfr CCPR4L; 142 143 __at(0x0F59) __sfr CCPR4H; 144 145 __at(0x0F5A) __sfr PSTR3CON; 146 __at(0x0F5A) volatile __PSTR3CONbits_t PSTR3CONbits; 147 148 __at(0x0F5B) __sfr CCP3AS; 149 __at(0x0F5B) volatile __CCP3ASbits_t CCP3ASbits; 150 151 __at(0x0F5B) __sfr ECCP3AS; 152 __at(0x0F5B) volatile __ECCP3ASbits_t ECCP3ASbits; 153 154 __at(0x0F5C) __sfr PWM3CON; 155 __at(0x0F5C) volatile __PWM3CONbits_t PWM3CONbits; 156 157 __at(0x0F5D) __sfr CCP3CON; 158 __at(0x0F5D) volatile __CCP3CONbits_t CCP3CONbits; 159 160 __at(0x0F5E) __sfr CCPR3; 161 162 __at(0x0F5E) __sfr CCPR3L; 163 164 __at(0x0F5F) __sfr CCPR3H; 165 166 __at(0x0F60) __sfr SLRCON; 167 __at(0x0F60) volatile __SLRCONbits_t SLRCONbits; 168 169 __at(0x0F61) __sfr WPUB; 170 __at(0x0F61) volatile __WPUBbits_t WPUBbits; 171 172 __at(0x0F62) __sfr IOCB; 173 __at(0x0F62) volatile __IOCBbits_t IOCBbits; 174 175 __at(0x0F63) __sfr PSTR2CON; 176 __at(0x0F63) volatile __PSTR2CONbits_t PSTR2CONbits; 177 178 __at(0x0F64) __sfr CCP2AS; 179 __at(0x0F64) volatile __CCP2ASbits_t CCP2ASbits; 180 181 __at(0x0F64) __sfr ECCP2AS; 182 __at(0x0F64) volatile __ECCP2ASbits_t ECCP2ASbits; 183 184 __at(0x0F65) __sfr PWM2CON; 185 __at(0x0F65) volatile __PWM2CONbits_t PWM2CONbits; 186 187 __at(0x0F66) __sfr CCP2CON; 188 __at(0x0F66) volatile __CCP2CONbits_t CCP2CONbits; 189 190 __at(0x0F67) __sfr CCPR2; 191 192 __at(0x0F67) __sfr CCPR2L; 193 194 __at(0x0F68) __sfr CCPR2H; 195 196 __at(0x0F69) __sfr SSP2CON3; 197 __at(0x0F69) volatile __SSP2CON3bits_t SSP2CON3bits; 198 199 __at(0x0F6A) __sfr SSP2MSK; 200 __at(0x0F6A) volatile __SSP2MSKbits_t SSP2MSKbits; 201 202 __at(0x0F6B) __sfr SSP2CON2; 203 __at(0x0F6B) volatile __SSP2CON2bits_t SSP2CON2bits; 204 205 __at(0x0F6C) __sfr SSP2CON1; 206 __at(0x0F6C) volatile __SSP2CON1bits_t SSP2CON1bits; 207 208 __at(0x0F6D) __sfr SSP2STAT; 209 __at(0x0F6D) volatile __SSP2STATbits_t SSP2STATbits; 210 211 __at(0x0F6E) __sfr SSP2ADD; 212 213 __at(0x0F6F) __sfr SSP2BUF; 214 215 __at(0x0F70) __sfr BAUD2CON; 216 __at(0x0F70) volatile __BAUD2CONbits_t BAUD2CONbits; 217 218 __at(0x0F70) __sfr BAUDCON2; 219 __at(0x0F70) volatile __BAUDCON2bits_t BAUDCON2bits; 220 221 __at(0x0F71) __sfr RC2STA; 222 __at(0x0F71) volatile __RC2STAbits_t RC2STAbits; 223 224 __at(0x0F71) __sfr RCSTA2; 225 __at(0x0F71) volatile __RCSTA2bits_t RCSTA2bits; 226 227 __at(0x0F72) __sfr TX2STA; 228 __at(0x0F72) volatile __TX2STAbits_t TX2STAbits; 229 230 __at(0x0F72) __sfr TXSTA2; 231 __at(0x0F72) volatile __TXSTA2bits_t TXSTA2bits; 232 233 __at(0x0F73) __sfr TX2REG; 234 235 __at(0x0F73) __sfr TXREG2; 236 237 __at(0x0F74) __sfr RC2REG; 238 239 __at(0x0F74) __sfr RCREG2; 240 241 __at(0x0F75) __sfr SP2BRG; 242 243 __at(0x0F75) __sfr SPBRG2; 244 245 __at(0x0F76) __sfr SP2BRGH; 246 247 __at(0x0F76) __sfr SPBRGH2; 248 249 __at(0x0F77) __sfr CM12CON; 250 __at(0x0F77) volatile __CM12CONbits_t CM12CONbits; 251 252 __at(0x0F77) __sfr CM2CON1; 253 __at(0x0F77) volatile __CM2CON1bits_t CM2CON1bits; 254 255 __at(0x0F78) __sfr CM2CON; 256 __at(0x0F78) volatile __CM2CONbits_t CM2CONbits; 257 258 __at(0x0F78) __sfr CM2CON0; 259 __at(0x0F78) volatile __CM2CON0bits_t CM2CON0bits; 260 261 __at(0x0F79) __sfr CM1CON; 262 __at(0x0F79) volatile __CM1CONbits_t CM1CONbits; 263 264 __at(0x0F79) __sfr CM1CON0; 265 __at(0x0F79) volatile __CM1CON0bits_t CM1CON0bits; 266 267 __at(0x0F7A) __sfr PIE4; 268 __at(0x0F7A) volatile __PIE4bits_t PIE4bits; 269 270 __at(0x0F7B) __sfr PIR4; 271 __at(0x0F7B) volatile __PIR4bits_t PIR4bits; 272 273 __at(0x0F7C) __sfr IPR4; 274 __at(0x0F7C) volatile __IPR4bits_t IPR4bits; 275 276 __at(0x0F7D) __sfr PIE5; 277 __at(0x0F7D) volatile __PIE5bits_t PIE5bits; 278 279 __at(0x0F7E) __sfr PIR5; 280 __at(0x0F7E) volatile __PIR5bits_t PIR5bits; 281 282 __at(0x0F7F) __sfr IPR5; 283 __at(0x0F7F) volatile __IPR5bits_t IPR5bits; 284 285 __at(0x0F80) __sfr PORTA; 286 __at(0x0F80) volatile __PORTAbits_t PORTAbits; 287 288 __at(0x0F81) __sfr PORTB; 289 __at(0x0F81) volatile __PORTBbits_t PORTBbits; 290 291 __at(0x0F82) __sfr PORTC; 292 __at(0x0F82) volatile __PORTCbits_t PORTCbits; 293 294 __at(0x0F83) __sfr PORTD; 295 __at(0x0F83) volatile __PORTDbits_t PORTDbits; 296 297 __at(0x0F84) __sfr PORTE; 298 __at(0x0F84) volatile __PORTEbits_t PORTEbits; 299 300 __at(0x0F89) __sfr LATA; 301 __at(0x0F89) volatile __LATAbits_t LATAbits; 302 303 __at(0x0F8A) __sfr LATB; 304 __at(0x0F8A) volatile __LATBbits_t LATBbits; 305 306 __at(0x0F8B) __sfr LATC; 307 __at(0x0F8B) volatile __LATCbits_t LATCbits; 308 309 __at(0x0F8C) __sfr LATD; 310 __at(0x0F8C) volatile __LATDbits_t LATDbits; 311 312 __at(0x0F8D) __sfr LATE; 313 __at(0x0F8D) volatile __LATEbits_t LATEbits; 314 315 __at(0x0F92) __sfr DDRA; 316 __at(0x0F92) volatile __DDRAbits_t DDRAbits; 317 318 __at(0x0F92) __sfr TRISA; 319 __at(0x0F92) volatile __TRISAbits_t TRISAbits; 320 321 __at(0x0F93) __sfr DDRB; 322 __at(0x0F93) volatile __DDRBbits_t DDRBbits; 323 324 __at(0x0F93) __sfr TRISB; 325 __at(0x0F93) volatile __TRISBbits_t TRISBbits; 326 327 __at(0x0F94) __sfr DDRC; 328 __at(0x0F94) volatile __DDRCbits_t DDRCbits; 329 330 __at(0x0F94) __sfr TRISC; 331 __at(0x0F94) volatile __TRISCbits_t TRISCbits; 332 333 __at(0x0F95) __sfr DDRD; 334 __at(0x0F95) volatile __DDRDbits_t DDRDbits; 335 336 __at(0x0F95) __sfr TRISD; 337 __at(0x0F95) volatile __TRISDbits_t TRISDbits; 338 339 __at(0x0F96) __sfr DDRE; 340 __at(0x0F96) volatile __DDREbits_t DDREbits; 341 342 __at(0x0F96) __sfr TRISE; 343 __at(0x0F96) volatile __TRISEbits_t TRISEbits; 344 345 __at(0x0F9B) __sfr OSCTUNE; 346 __at(0x0F9B) volatile __OSCTUNEbits_t OSCTUNEbits; 347 348 __at(0x0F9C) __sfr HLVDCON; 349 __at(0x0F9C) volatile __HLVDCONbits_t HLVDCONbits; 350 351 __at(0x0F9C) __sfr LVDCON; 352 __at(0x0F9C) volatile __LVDCONbits_t LVDCONbits; 353 354 __at(0x0F9D) __sfr PIE1; 355 __at(0x0F9D) volatile __PIE1bits_t PIE1bits; 356 357 __at(0x0F9E) __sfr PIR1; 358 __at(0x0F9E) volatile __PIR1bits_t PIR1bits; 359 360 __at(0x0F9F) __sfr IPR1; 361 __at(0x0F9F) volatile __IPR1bits_t IPR1bits; 362 363 __at(0x0FA0) __sfr PIE2; 364 __at(0x0FA0) volatile __PIE2bits_t PIE2bits; 365 366 __at(0x0FA1) __sfr PIR2; 367 __at(0x0FA1) volatile __PIR2bits_t PIR2bits; 368 369 __at(0x0FA2) __sfr IPR2; 370 __at(0x0FA2) volatile __IPR2bits_t IPR2bits; 371 372 __at(0x0FA3) __sfr PIE3; 373 __at(0x0FA3) volatile __PIE3bits_t PIE3bits; 374 375 __at(0x0FA4) __sfr PIR3; 376 __at(0x0FA4) volatile __PIR3bits_t PIR3bits; 377 378 __at(0x0FA5) __sfr IPR3; 379 __at(0x0FA5) volatile __IPR3bits_t IPR3bits; 380 381 __at(0x0FA6) __sfr EECON1; 382 __at(0x0FA6) volatile __EECON1bits_t EECON1bits; 383 384 __at(0x0FA7) __sfr EECON2; 385 386 __at(0x0FA8) __sfr EEDATA; 387 388 __at(0x0FA9) __sfr EEADR; 389 __at(0x0FA9) volatile __EEADRbits_t EEADRbits; 390 391 __at(0x0FAB) __sfr RC1STA; 392 __at(0x0FAB) volatile __RC1STAbits_t RC1STAbits; 393 394 __at(0x0FAB) __sfr RCSTA; 395 __at(0x0FAB) volatile __RCSTAbits_t RCSTAbits; 396 397 __at(0x0FAB) __sfr RCSTA1; 398 __at(0x0FAB) volatile __RCSTA1bits_t RCSTA1bits; 399 400 __at(0x0FAC) __sfr TX1STA; 401 __at(0x0FAC) volatile __TX1STAbits_t TX1STAbits; 402 403 __at(0x0FAC) __sfr TXSTA; 404 __at(0x0FAC) volatile __TXSTAbits_t TXSTAbits; 405 406 __at(0x0FAC) __sfr TXSTA1; 407 __at(0x0FAC) volatile __TXSTA1bits_t TXSTA1bits; 408 409 __at(0x0FAD) __sfr TX1REG; 410 411 __at(0x0FAD) __sfr TXREG; 412 413 __at(0x0FAD) __sfr TXREG1; 414 415 __at(0x0FAE) __sfr RC1REG; 416 417 __at(0x0FAE) __sfr RCREG; 418 419 __at(0x0FAE) __sfr RCREG1; 420 421 __at(0x0FAF) __sfr SP1BRG; 422 423 __at(0x0FAF) __sfr SPBRG; 424 425 __at(0x0FAF) __sfr SPBRG1; 426 427 __at(0x0FB0) __sfr SP1BRGH; 428 429 __at(0x0FB0) __sfr SPBRGH; 430 431 __at(0x0FB0) __sfr SPBRGH1; 432 433 __at(0x0FB1) __sfr T3CON; 434 __at(0x0FB1) volatile __T3CONbits_t T3CONbits; 435 436 __at(0x0FB2) __sfr TMR3; 437 438 __at(0x0FB2) __sfr TMR3L; 439 440 __at(0x0FB3) __sfr TMR3H; 441 442 __at(0x0FB4) __sfr T3GCON; 443 __at(0x0FB4) volatile __T3GCONbits_t T3GCONbits; 444 445 __at(0x0FB6) __sfr ECCP1AS; 446 __at(0x0FB6) volatile __ECCP1ASbits_t ECCP1ASbits; 447 448 __at(0x0FB6) __sfr ECCPAS; 449 __at(0x0FB6) volatile __ECCPASbits_t ECCPASbits; 450 451 __at(0x0FB7) __sfr PWM1CON; 452 __at(0x0FB7) volatile __PWM1CONbits_t PWM1CONbits; 453 454 __at(0x0FB7) __sfr PWMCON; 455 __at(0x0FB7) volatile __PWMCONbits_t PWMCONbits; 456 457 __at(0x0FB8) __sfr BAUD1CON; 458 __at(0x0FB8) volatile __BAUD1CONbits_t BAUD1CONbits; 459 460 __at(0x0FB8) __sfr BAUDCON; 461 __at(0x0FB8) volatile __BAUDCONbits_t BAUDCONbits; 462 463 __at(0x0FB8) __sfr BAUDCON1; 464 __at(0x0FB8) volatile __BAUDCON1bits_t BAUDCON1bits; 465 466 __at(0x0FB8) __sfr BAUDCTL; 467 __at(0x0FB8) volatile __BAUDCTLbits_t BAUDCTLbits; 468 469 __at(0x0FB9) __sfr PSTR1CON; 470 __at(0x0FB9) volatile __PSTR1CONbits_t PSTR1CONbits; 471 472 __at(0x0FB9) __sfr PSTRCON; 473 __at(0x0FB9) volatile __PSTRCONbits_t PSTRCONbits; 474 475 __at(0x0FBA) __sfr T2CON; 476 __at(0x0FBA) volatile __T2CONbits_t T2CONbits; 477 478 __at(0x0FBB) __sfr PR2; 479 480 __at(0x0FBC) __sfr TMR2; 481 482 __at(0x0FBD) __sfr CCP1CON; 483 __at(0x0FBD) volatile __CCP1CONbits_t CCP1CONbits; 484 485 __at(0x0FBE) __sfr CCPR1; 486 487 __at(0x0FBE) __sfr CCPR1L; 488 489 __at(0x0FBF) __sfr CCPR1H; 490 491 __at(0x0FC0) __sfr ADCON2; 492 __at(0x0FC0) volatile __ADCON2bits_t ADCON2bits; 493 494 __at(0x0FC1) __sfr ADCON1; 495 __at(0x0FC1) volatile __ADCON1bits_t ADCON1bits; 496 497 __at(0x0FC2) __sfr ADCON0; 498 __at(0x0FC2) volatile __ADCON0bits_t ADCON0bits; 499 500 __at(0x0FC3) __sfr ADRES; 501 502 __at(0x0FC3) __sfr ADRESL; 503 504 __at(0x0FC4) __sfr ADRESH; 505 506 __at(0x0FC5) __sfr SSP1CON2; 507 __at(0x0FC5) volatile __SSP1CON2bits_t SSP1CON2bits; 508 509 __at(0x0FC5) __sfr SSPCON2; 510 __at(0x0FC5) volatile __SSPCON2bits_t SSPCON2bits; 511 512 __at(0x0FC6) __sfr SSP1CON1; 513 __at(0x0FC6) volatile __SSP1CON1bits_t SSP1CON1bits; 514 515 __at(0x0FC6) __sfr SSPCON1; 516 __at(0x0FC6) volatile __SSPCON1bits_t SSPCON1bits; 517 518 __at(0x0FC7) __sfr SSP1STAT; 519 __at(0x0FC7) volatile __SSP1STATbits_t SSP1STATbits; 520 521 __at(0x0FC7) __sfr SSPSTAT; 522 __at(0x0FC7) volatile __SSPSTATbits_t SSPSTATbits; 523 524 __at(0x0FC8) __sfr SSP1ADD; 525 526 __at(0x0FC8) __sfr SSPADD; 527 528 __at(0x0FC9) __sfr SSP1BUF; 529 530 __at(0x0FC9) __sfr SSPBUF; 531 532 __at(0x0FCA) __sfr SSP1MSK; 533 __at(0x0FCA) volatile __SSP1MSKbits_t SSP1MSKbits; 534 535 __at(0x0FCA) __sfr SSPMSK; 536 __at(0x0FCA) volatile __SSPMSKbits_t SSPMSKbits; 537 538 __at(0x0FCB) __sfr SSP1CON3; 539 __at(0x0FCB) volatile __SSP1CON3bits_t SSP1CON3bits; 540 541 __at(0x0FCB) __sfr SSPCON3; 542 __at(0x0FCB) volatile __SSPCON3bits_t SSPCON3bits; 543 544 __at(0x0FCC) __sfr T1GCON; 545 __at(0x0FCC) volatile __T1GCONbits_t T1GCONbits; 546 547 __at(0x0FCD) __sfr T1CON; 548 __at(0x0FCD) volatile __T1CONbits_t T1CONbits; 549 550 __at(0x0FCE) __sfr TMR1; 551 552 __at(0x0FCE) __sfr TMR1L; 553 554 __at(0x0FCF) __sfr TMR1H; 555 556 __at(0x0FD0) __sfr RCON; 557 __at(0x0FD0) volatile __RCONbits_t RCONbits; 558 559 __at(0x0FD1) __sfr WDTCON; 560 __at(0x0FD1) volatile __WDTCONbits_t WDTCONbits; 561 562 __at(0x0FD2) __sfr OSCCON2; 563 __at(0x0FD2) volatile __OSCCON2bits_t OSCCON2bits; 564 565 __at(0x0FD3) __sfr OSCCON; 566 __at(0x0FD3) volatile __OSCCONbits_t OSCCONbits; 567 568 __at(0x0FD5) __sfr T0CON; 569 __at(0x0FD5) volatile __T0CONbits_t T0CONbits; 570 571 __at(0x0FD6) __sfr TMR0; 572 573 __at(0x0FD6) __sfr TMR0L; 574 575 __at(0x0FD7) __sfr TMR0H; 576 577 __at(0x0FD8) __sfr STATUS; 578 __at(0x0FD8) volatile __STATUSbits_t STATUSbits; 579 580 __at(0x0FD9) __sfr FSR2L; 581 582 __at(0x0FDA) __sfr FSR2H; 583 584 __at(0x0FDB) __sfr PLUSW2; 585 586 __at(0x0FDC) __sfr PREINC2; 587 588 __at(0x0FDD) __sfr POSTDEC2; 589 590 __at(0x0FDE) __sfr POSTINC2; 591 592 __at(0x0FDF) __sfr INDF2; 593 594 __at(0x0FE0) __sfr BSR; 595 596 __at(0x0FE1) __sfr FSR1L; 597 598 __at(0x0FE2) __sfr FSR1H; 599 600 __at(0x0FE3) __sfr PLUSW1; 601 602 __at(0x0FE4) __sfr PREINC1; 603 604 __at(0x0FE5) __sfr POSTDEC1; 605 606 __at(0x0FE6) __sfr POSTINC1; 607 608 __at(0x0FE7) __sfr INDF1; 609 610 __at(0x0FE8) __sfr WREG; 611 612 __at(0x0FE9) __sfr FSR0L; 613 614 __at(0x0FEA) __sfr FSR0H; 615 616 __at(0x0FEB) __sfr PLUSW0; 617 618 __at(0x0FEC) __sfr PREINC0; 619 620 __at(0x0FED) __sfr POSTDEC0; 621 622 __at(0x0FEE) __sfr POSTINC0; 623 624 __at(0x0FEF) __sfr INDF0; 625 626 __at(0x0FF0) __sfr INTCON3; 627 __at(0x0FF0) volatile __INTCON3bits_t INTCON3bits; 628 629 __at(0x0FF1) __sfr INTCON2; 630 __at(0x0FF1) volatile __INTCON2bits_t INTCON2bits; 631 632 __at(0x0FF2) __sfr INTCON; 633 __at(0x0FF2) volatile __INTCONbits_t INTCONbits; 634 635 __at(0x0FF3) __sfr PROD; 636 637 __at(0x0FF3) __sfr PRODL; 638 639 __at(0x0FF4) __sfr PRODH; 640 641 __at(0x0FF5) __sfr TABLAT; 642 643 __at(0x0FF6) __sfr TBLPTR; 644 645 __at(0x0FF6) __sfr TBLPTRL; 646 647 __at(0x0FF7) __sfr TBLPTRH; 648 649 __at(0x0FF8) __sfr TBLPTRU; 650 651 __at(0x0FF9) __sfr PC; 652 653 __at(0x0FF9) __sfr PCL; 654 655 __at(0x0FFA) __sfr PCLATH; 656 657 __at(0x0FFB) __sfr PCLATU; 658 659 __at(0x0FFC) __sfr STKPTR; 660 __at(0x0FFC) volatile __STKPTRbits_t STKPTRbits; 661 662 __at(0x0FFD) __sfr TOS; 663 664 __at(0x0FFD) __sfr TOSL; 665 666 __at(0x0FFE) __sfr TOSH; 667 668 __at(0x0FFF) __sfr TOSU; 669