1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright © 2022 Intel Corporation 4 */ 5 6 #ifndef __INTEL_DISPLAY_CORE_H__ 7 #define __INTEL_DISPLAY_CORE_H__ 8 9 #include <linux/list.h> 10 #include <linux/llist.h> 11 #include <linux/mutex.h> 12 #include <linux/types.h> 13 #include <linux/wait.h> 14 #include <linux/workqueue.h> 15 16 #include <drm/drm_connector.h> 17 #include <drm/drm_modeset_lock.h> 18 19 #include "intel_cdclk.h" 20 #include "intel_display_device.h" 21 #include "intel_display_limits.h" 22 #include "intel_display_power.h" 23 #include "intel_dpll_mgr.h" 24 #include "intel_fbc.h" 25 #include "intel_global_state.h" 26 #include "intel_gmbus.h" 27 #include "intel_opregion.h" 28 #include "intel_wm_types.h" 29 30 struct drm_i915_private; 31 struct drm_property; 32 struct drm_property_blob; 33 struct i915_audio_component; 34 struct i915_hdcp_arbiter; 35 struct intel_atomic_state; 36 struct intel_audio_funcs; 37 struct intel_cdclk_funcs; 38 struct intel_cdclk_vals; 39 struct intel_color_funcs; 40 struct intel_crtc; 41 struct intel_crtc_state; 42 struct intel_dmc; 43 struct intel_dpll_funcs; 44 struct intel_dpll_mgr; 45 struct intel_fbdev; 46 struct intel_fdi_funcs; 47 struct intel_hotplug_funcs; 48 struct intel_initial_plane_config; 49 struct intel_overlay; 50 51 /* Amount of SAGV/QGV points, BSpec precisely defines this */ 52 #define I915_NUM_QGV_POINTS 8 53 54 /* Amount of PSF GV points, BSpec precisely defines this */ 55 #define I915_NUM_PSF_GV_POINTS 3 56 57 struct intel_display_funcs { 58 /* 59 * Returns the active state of the crtc, and if the crtc is active, 60 * fills out the pipe-config with the hw state. 61 */ 62 bool (*get_pipe_config)(struct intel_crtc *, 63 struct intel_crtc_state *); 64 void (*get_initial_plane_config)(struct intel_crtc *, 65 struct intel_initial_plane_config *); 66 bool (*fixup_initial_plane_config)(struct intel_crtc *crtc, 67 const struct intel_initial_plane_config *plane_config); 68 void (*crtc_enable)(struct intel_atomic_state *state, 69 struct intel_crtc *crtc); 70 void (*crtc_disable)(struct intel_atomic_state *state, 71 struct intel_crtc *crtc); 72 void (*commit_modeset_enables)(struct intel_atomic_state *state); 73 }; 74 75 /* functions used for watermark calcs for display. */ 76 struct intel_wm_funcs { 77 /* update_wm is for legacy wm management */ 78 void (*update_wm)(struct drm_i915_private *dev_priv); 79 int (*compute_pipe_wm)(struct intel_atomic_state *state, 80 struct intel_crtc *crtc); 81 int (*compute_intermediate_wm)(struct intel_atomic_state *state, 82 struct intel_crtc *crtc); 83 void (*initial_watermarks)(struct intel_atomic_state *state, 84 struct intel_crtc *crtc); 85 void (*atomic_update_watermarks)(struct intel_atomic_state *state, 86 struct intel_crtc *crtc); 87 void (*optimize_watermarks)(struct intel_atomic_state *state, 88 struct intel_crtc *crtc); 89 int (*compute_global_watermarks)(struct intel_atomic_state *state); 90 void (*get_hw_state)(struct drm_i915_private *i915); 91 }; 92 93 struct intel_audio_state { 94 struct intel_encoder *encoder; 95 u8 eld[MAX_ELD_BYTES]; 96 }; 97 98 struct intel_audio { 99 /* hda/i915 audio component */ 100 struct i915_audio_component *component; 101 bool component_registered; 102 /* mutex for audio/video sync */ 103 struct rwlock mutex; 104 int power_refcount; 105 u32 freq_cntrl; 106 107 /* current audio state for the audio component hooks */ 108 struct intel_audio_state state[I915_MAX_TRANSCODERS]; 109 110 /* necessary resource sharing with HDMI LPE audio driver. */ 111 struct { 112 struct platform_device *platdev; 113 int irq; 114 } lpe; 115 }; 116 117 /* 118 * dpll and cdclk state is protected by connection_mutex dpll.lock serializes 119 * intel_{prepare,enable,disable}_shared_dpll. Must be global rather than per 120 * dpll, because on some platforms plls share registers. 121 */ 122 struct intel_dpll { 123 struct rwlock lock; 124 125 int num_shared_dpll; 126 struct intel_shared_dpll shared_dplls[I915_NUM_PLLS]; 127 const struct intel_dpll_mgr *mgr; 128 129 struct { 130 int nssc; 131 int ssc; 132 } ref_clks; 133 134 /* 135 * Bitmask of PLLs using the PCH SSC, indexed using enum intel_dpll_id. 136 */ 137 u8 pch_ssc_use; 138 }; 139 140 struct intel_frontbuffer_tracking { 141 spinlock_t lock; 142 143 /* 144 * Tracking bits for delayed frontbuffer flushing du to gpu activity or 145 * scheduled flips. 146 */ 147 unsigned busy_bits; 148 unsigned flip_bits; 149 }; 150 151 struct intel_hotplug { 152 struct delayed_work hotplug_work; 153 154 const u32 *hpd, *pch_hpd; 155 156 struct { 157 unsigned long last_jiffies; 158 int count; 159 enum { 160 HPD_ENABLED = 0, 161 HPD_DISABLED = 1, 162 HPD_MARK_DISABLED = 2 163 } state; 164 } stats[HPD_NUM_PINS]; 165 u32 event_bits; 166 u32 retry_bits; 167 struct delayed_work reenable_work; 168 169 u32 long_port_mask; 170 u32 short_port_mask; 171 struct work_struct dig_port_work; 172 173 struct work_struct poll_init_work; 174 bool poll_enabled; 175 176 unsigned int hpd_storm_threshold; 177 /* Whether or not to count short HPD IRQs in HPD storms */ 178 u8 hpd_short_storm_enabled; 179 180 /* 181 * if we get a HPD irq from DP and a HPD irq from non-DP 182 * the non-DP HPD could block the workqueue on a mode config 183 * mutex getting, that userspace may have taken. However 184 * userspace is waiting on the DP workqueue to run which is 185 * blocked behind the non-DP one. 186 */ 187 struct workqueue_struct *dp_wq; 188 189 /* 190 * Flag to track if long HPDs need not to be processed 191 * 192 * Some panels generate long HPDs while keep connected to the port. 193 * This can cause issues with CI tests results. In CI systems we 194 * don't expect to disconnect the panels and could ignore the long 195 * HPDs generated from the faulty panels. This flag can be used as 196 * cue to ignore the long HPDs and can be set / unset using debugfs. 197 */ 198 bool ignore_long_hpd; 199 }; 200 201 struct intel_vbt_data { 202 /* bdb version */ 203 u16 version; 204 205 /* Feature bits */ 206 unsigned int int_tv_support:1; 207 unsigned int int_crt_support:1; 208 unsigned int lvds_use_ssc:1; 209 unsigned int int_lvds_support:1; 210 unsigned int display_clock_mode:1; 211 unsigned int fdi_rx_polarity_inverted:1; 212 int lvds_ssc_freq; 213 enum drm_panel_orientation orientation; 214 215 bool override_afc_startup; 216 u8 override_afc_startup_val; 217 218 int crt_ddc_pin; 219 220 struct list_head display_devices; 221 struct list_head bdb_blocks; 222 223 struct sdvo_device_mapping { 224 u8 initialized; 225 u8 dvo_port; 226 u8 slave_addr; 227 u8 dvo_wiring; 228 u8 i2c_pin; 229 u8 ddc_pin; 230 } sdvo_mappings[2]; 231 }; 232 233 struct intel_wm { 234 /* 235 * Raw watermark latency values: 236 * in 0.1us units for WM0, 237 * in 0.5us units for WM1+. 238 */ 239 /* primary */ 240 u16 pri_latency[5]; 241 /* sprite */ 242 u16 spr_latency[5]; 243 /* cursor */ 244 u16 cur_latency[5]; 245 /* 246 * Raw watermark memory latency values 247 * for SKL for all 8 levels 248 * in 1us units. 249 */ 250 u16 skl_latency[8]; 251 252 /* current hardware state */ 253 union { 254 struct ilk_wm_values hw; 255 struct vlv_wm_values vlv; 256 struct g4x_wm_values g4x; 257 }; 258 259 u8 num_levels; 260 261 /* 262 * Should be held around atomic WM register writing; also 263 * protects * intel_crtc->wm.active and 264 * crtc_state->wm.need_postvbl_update. 265 */ 266 struct rwlock wm_mutex; 267 268 bool ipc_enabled; 269 }; 270 271 struct intel_display { 272 /* Display functions */ 273 struct { 274 /* Top level crtc-ish functions */ 275 const struct intel_display_funcs *display; 276 277 /* Display CDCLK functions */ 278 const struct intel_cdclk_funcs *cdclk; 279 280 /* Display pll funcs */ 281 const struct intel_dpll_funcs *dpll; 282 283 /* irq display functions */ 284 const struct intel_hotplug_funcs *hotplug; 285 286 /* pm display functions */ 287 const struct intel_wm_funcs *wm; 288 289 /* fdi display functions */ 290 const struct intel_fdi_funcs *fdi; 291 292 /* Display internal color functions */ 293 const struct intel_color_funcs *color; 294 295 /* Display internal audio functions */ 296 const struct intel_audio_funcs *audio; 297 } funcs; 298 299 /* Grouping using anonymous structs. Keep sorted. */ 300 struct intel_atomic_helper { 301 struct llist_head free_list; 302 struct work_struct free_work; 303 } atomic_helper; 304 305 struct { 306 /* backlight registers and fields in struct intel_panel */ 307 struct rwlock lock; 308 } backlight; 309 310 struct { 311 struct intel_global_obj obj; 312 313 struct intel_bw_info { 314 /* for each QGV point */ 315 unsigned int deratedbw[I915_NUM_QGV_POINTS]; 316 /* for each PSF GV point */ 317 unsigned int psf_bw[I915_NUM_PSF_GV_POINTS]; 318 /* Peak BW for each QGV point */ 319 unsigned int peakbw[I915_NUM_QGV_POINTS]; 320 u8 num_qgv_points; 321 u8 num_psf_gv_points; 322 u8 num_planes; 323 } max[6]; 324 } bw; 325 326 struct { 327 /* The current hardware cdclk configuration */ 328 struct intel_cdclk_config hw; 329 330 /* cdclk, divider, and ratio table from bspec */ 331 const struct intel_cdclk_vals *table; 332 333 struct intel_global_obj obj; 334 335 unsigned int max_cdclk_freq; 336 } cdclk; 337 338 struct { 339 struct drm_property_blob *glk_linear_degamma_lut; 340 } color; 341 342 struct { 343 /* The current hardware dbuf configuration */ 344 u8 enabled_slices; 345 346 struct intel_global_obj obj; 347 } dbuf; 348 349 struct { 350 wait_queue_head_t waitqueue; 351 352 /* mutex to protect pmdemand programming sequence */ 353 struct rwlock lock; 354 355 struct intel_global_obj obj; 356 } pmdemand; 357 358 struct { 359 /* 360 * dkl.phy_lock protects against concurrent access of the 361 * Dekel TypeC PHYs. 362 */ 363 spinlock_t phy_lock; 364 } dkl; 365 366 struct { 367 struct intel_dmc *dmc; 368 intel_wakeref_t wakeref; 369 } dmc; 370 371 struct { 372 /* VLV/CHV/BXT/GLK DSI MMIO register base address */ 373 u32 mmio_base; 374 } dsi; 375 376 struct { 377 /* list of fbdev register on this device */ 378 struct intel_fbdev *fbdev; 379 struct work_struct suspend_work; 380 } fbdev; 381 382 struct { 383 unsigned int pll_freq; 384 u32 rx_config; 385 } fdi; 386 387 struct { 388 struct list_head obj_list; 389 } global; 390 391 struct { 392 /* 393 * Base address of where the gmbus and gpio blocks are located 394 * (either on PCH or on SoC for platforms without PCH). 395 */ 396 u32 mmio_base; 397 398 /* 399 * gmbus.mutex protects against concurrent usage of the single 400 * hw gmbus controller on different i2c buses. 401 */ 402 struct rwlock mutex; 403 404 struct intel_gmbus *bus[GMBUS_NUM_PINS]; 405 406 wait_queue_head_t wait_queue; 407 } gmbus; 408 409 struct { 410 struct i915_hdcp_arbiter *arbiter; 411 bool comp_added; 412 413 /* 414 * HDCP message struct for allocation of memory which can be 415 * reused when sending message to gsc cs. 416 * this is only populated post Meteorlake 417 */ 418 struct intel_hdcp_gsc_message *hdcp_message; 419 /* Mutex to protect the above hdcp related values. */ 420 struct rwlock hdcp_mutex; 421 } hdcp; 422 423 struct { 424 /* 425 * HTI (aka HDPORT) state read during initial hw readout. Most 426 * platforms don't have HTI, so this will just stay 0. Those 427 * that do will use this later to figure out which PLLs and PHYs 428 * are unavailable for driver usage. 429 */ 430 u32 state; 431 } hti; 432 433 struct { 434 /* Access with DISPLAY_INFO() */ 435 const struct intel_display_device_info *__device_info; 436 437 /* Access with DISPLAY_RUNTIME_INFO() */ 438 struct intel_display_runtime_info __runtime_info; 439 } info; 440 441 struct { 442 bool false_color; 443 } ips; 444 445 struct { 446 struct i915_power_domains domains; 447 448 /* Shadow for DISPLAY_PHY_CONTROL which can't be safely read */ 449 u32 chv_phy_control; 450 451 /* perform PHY state sanity checks? */ 452 bool chv_phy_assert[2]; 453 } power; 454 455 struct { 456 u32 mmio_base; 457 458 /* protects panel power sequencer state */ 459 struct rwlock mutex; 460 } pps; 461 462 struct { 463 struct drm_property *broadcast_rgb; 464 struct drm_property *force_audio; 465 } properties; 466 467 struct { 468 unsigned long mask; 469 } quirks; 470 471 struct { 472 /* restore state for suspend/resume and display reset */ 473 struct drm_atomic_state *modeset_state; 474 struct drm_modeset_acquire_ctx reset_ctx; 475 } restore; 476 477 struct { 478 enum { 479 I915_SAGV_UNKNOWN = 0, 480 I915_SAGV_DISABLED, 481 I915_SAGV_ENABLED, 482 I915_SAGV_NOT_CONTROLLED 483 } status; 484 485 u32 block_time_us; 486 } sagv; 487 488 struct { 489 /* 490 * DG2: Mask of PHYs that were not calibrated by the firmware 491 * and should not be used. 492 */ 493 u8 phy_failed_calibration; 494 } snps; 495 496 struct { 497 /* 498 * Shadows for CHV DPLL_MD regs to keep the state 499 * checker somewhat working in the presence hardware 500 * crappiness (can't read out DPLL_MD for pipes B & C). 501 */ 502 u32 chv_dpll_md[I915_MAX_PIPES]; 503 u32 bxt_phy_grc; 504 } state; 505 506 struct { 507 /* ordered wq for modesets */ 508 struct workqueue_struct *modeset; 509 510 /* unbound hipri wq for page flips/plane updates */ 511 struct workqueue_struct *flip; 512 } wq; 513 514 /* Grouping using named structs. Keep sorted. */ 515 struct intel_audio audio; 516 struct intel_dpll dpll; 517 struct intel_fbc *fbc[I915_MAX_FBCS]; 518 struct intel_frontbuffer_tracking fb_tracking; 519 struct intel_hotplug hotplug; 520 struct intel_opregion opregion; 521 struct intel_overlay *overlay; 522 struct intel_vbt_data vbt; 523 struct intel_wm wm; 524 }; 525 526 #endif /* __INTEL_DISPLAY_CORE_H__ */ 527