1 /*
2 * Copyright 2019 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26 #ifndef DMUB_CMD_H
27 #define DMUB_CMD_H
28
29 #if defined(_TEST_HARNESS) || defined(FPGA_USB4)
30 #include "dmub_fw_types.h"
31 #include "include_legacy/atomfirmware.h"
32
33 #if defined(_TEST_HARNESS)
34 #include <string.h>
35 #endif
36 #else
37
38 #include <asm/byteorder.h>
39 #include <linux/types.h>
40 #include <linux/string.h>
41 #include <linux/delay.h>
42
43 #include "atomfirmware.h"
44
45 #endif // defined(_TEST_HARNESS) || defined(FPGA_USB4)
46
47 //<DMUB_TYPES>==================================================================
48 /* Basic type definitions. */
49
50 #define __forceinline inline
51
52 /**
53 * Flag from driver to indicate that ABM should be disabled gradually
54 * by slowly reversing all backlight programming and pixel compensation.
55 */
56 #define SET_ABM_PIPE_GRADUALLY_DISABLE 0
57
58 /**
59 * Flag from driver to indicate that ABM should be disabled immediately
60 * and undo all backlight programming and pixel compensation.
61 */
62 #define SET_ABM_PIPE_IMMEDIATELY_DISABLE 255
63
64 /**
65 * Flag from driver to indicate that ABM should be disabled immediately
66 * and keep the current backlight programming and pixel compensation.
67 */
68 #define SET_ABM_PIPE_IMMEDIATE_KEEP_GAIN_DISABLE 254
69
70 /**
71 * Flag from driver to set the current ABM pipe index or ABM operating level.
72 */
73 #define SET_ABM_PIPE_NORMAL 1
74
75 /**
76 * Number of ambient light levels in ABM algorithm.
77 */
78 #define NUM_AMBI_LEVEL 5
79
80 /**
81 * Number of operating/aggression levels in ABM algorithm.
82 */
83 #define NUM_AGGR_LEVEL 4
84
85 /**
86 * Number of segments in the gamma curve.
87 */
88 #define NUM_POWER_FN_SEGS 8
89
90 /**
91 * Number of segments in the backlight curve.
92 */
93 #define NUM_BL_CURVE_SEGS 16
94
95 /* Maximum number of SubVP streams */
96 #define DMUB_MAX_SUBVP_STREAMS 2
97
98 /* Define max FPO streams as 4 for now. Current implementation today
99 * only supports 1, but could be more in the future. Reduce array
100 * size to ensure the command size remains less than 64 bytes if
101 * adding new fields.
102 */
103 #define DMUB_MAX_FPO_STREAMS 4
104
105 /* Maximum number of streams on any ASIC. */
106 #define DMUB_MAX_STREAMS 6
107
108 /* Maximum number of planes on any ASIC. */
109 #define DMUB_MAX_PLANES 6
110
111 /* Trace buffer offset for entry */
112 #define TRACE_BUFFER_ENTRY_OFFSET 16
113
114 /**
115 * Maximum number of dirty rects supported by FW.
116 */
117 #define DMUB_MAX_DIRTY_RECTS 3
118
119 /**
120 *
121 * PSR control version legacy
122 */
123 #define DMUB_CMD_PSR_CONTROL_VERSION_UNKNOWN 0x0
124 /**
125 * PSR control version with multi edp support
126 */
127 #define DMUB_CMD_PSR_CONTROL_VERSION_1 0x1
128
129
130 /**
131 * ABM control version legacy
132 */
133 #define DMUB_CMD_ABM_CONTROL_VERSION_UNKNOWN 0x0
134
135 /**
136 * ABM control version with multi edp support
137 */
138 #define DMUB_CMD_ABM_CONTROL_VERSION_1 0x1
139
140 /**
141 * Physical framebuffer address location, 64-bit.
142 */
143 #ifndef PHYSICAL_ADDRESS_LOC
144 #define PHYSICAL_ADDRESS_LOC union large_integer
145 #endif
146
147 /**
148 * OS/FW agnostic memcpy
149 */
150 #ifndef dmub_memcpy
151 #define dmub_memcpy(dest, source, bytes) memcpy((dest), (source), (bytes))
152 #endif
153
154 /**
155 * OS/FW agnostic memset
156 */
157 #ifndef dmub_memset
158 #define dmub_memset(dest, val, bytes) memset((dest), (val), (bytes))
159 #endif
160
161 #if defined(__cplusplus)
162 extern "C" {
163 #endif
164
165 #pragma pack(push, 1)
166 /**
167 * OS/FW agnostic udelay
168 */
169 #ifndef dmub_udelay
170 #define dmub_udelay(microseconds) udelay(microseconds)
171 #endif
172
173 #pragma pack(push, 1)
174 #define ABM_NUM_OF_ACE_SEGMENTS 5
175
176 union abm_flags {
177 struct {
178 /**
179 * @abm_enabled: Indicates if ABM is enabled.
180 */
181 unsigned int abm_enabled : 1;
182
183 /**
184 * @disable_abm_requested: Indicates if driver has requested ABM to be disabled.
185 */
186 unsigned int disable_abm_requested : 1;
187
188 /**
189 * @disable_abm_immediately: Indicates if driver has requested ABM to be disabled
190 * immediately.
191 */
192 unsigned int disable_abm_immediately : 1;
193
194 /**
195 * @disable_abm_immediate_keep_gain: Indicates if driver has requested ABM
196 * to be disabled immediately and keep gain.
197 */
198 unsigned int disable_abm_immediate_keep_gain : 1;
199
200 /**
201 * @fractional_pwm: Indicates if fractional duty cycle for backlight PWM is enabled.
202 */
203 unsigned int fractional_pwm : 1;
204
205 /**
206 * @abm_gradual_bl_change: Indicates if algorithm has completed gradual adjustment
207 * of user backlight level.
208 */
209 unsigned int abm_gradual_bl_change : 1;
210 } bitfields;
211
212 unsigned int u32All;
213 };
214 #pragma pack(pop)
215
216 struct abm_save_restore {
217 /**
218 * @flags: Misc. ABM flags.
219 */
220 union abm_flags flags;
221
222 /**
223 * @pause: true: pause ABM and get state
224 * false: unpause ABM after setting state
225 */
226 uint32_t pause;
227
228 /**
229 * @next_ace_slope: Next ACE slopes to be programmed in HW (u3.13)
230 */
231 uint32_t next_ace_slope[ABM_NUM_OF_ACE_SEGMENTS];
232
233 /**
234 * @next_ace_thresh: Next ACE thresholds to be programmed in HW (u10.6)
235 */
236 uint32_t next_ace_thresh[ABM_NUM_OF_ACE_SEGMENTS];
237
238 /**
239 * @next_ace_offset: Next ACE offsets to be programmed in HW (u10.6)
240 */
241 uint32_t next_ace_offset[ABM_NUM_OF_ACE_SEGMENTS];
242
243
244 /**
245 * @knee_threshold: Current x-position of ACE knee (u0.16).
246 */
247 uint32_t knee_threshold;
248 /**
249 * @current_gain: Current backlight reduction (u16.16).
250 */
251 uint32_t current_gain;
252 /**
253 * @curr_bl_level: Current actual backlight level converging to target backlight level.
254 */
255 uint16_t curr_bl_level;
256
257 /**
258 * @curr_user_bl_level: Current nominal backlight level converging to level requested by user.
259 */
260 uint16_t curr_user_bl_level;
261
262 };
263
264 /**
265 * union dmub_addr - DMUB physical/virtual 64-bit address.
266 */
267 union dmub_addr {
268 struct {
269 uint32_t low_part; /**< Lower 32 bits */
270 uint32_t high_part; /**< Upper 32 bits */
271 } u; /*<< Low/high bit access */
272 uint64_t quad_part; /*<< 64 bit address */
273 };
274 #pragma pack(pop)
275
276 /**
277 * Dirty rect definition.
278 */
279 struct dmub_rect {
280 /**
281 * Dirty rect x offset.
282 */
283 uint32_t x;
284
285 /**
286 * Dirty rect y offset.
287 */
288 uint32_t y;
289
290 /**
291 * Dirty rect width.
292 */
293 uint32_t width;
294
295 /**
296 * Dirty rect height.
297 */
298 uint32_t height;
299 };
300
301 /**
302 * Flags that can be set by driver to change some PSR behaviour.
303 */
304 union dmub_psr_debug_flags {
305 /**
306 * Debug flags.
307 */
308 struct {
309 /**
310 * Enable visual confirm in FW.
311 */
312 uint32_t visual_confirm : 1;
313
314 /**
315 * Force all selective updates to bw full frame updates.
316 */
317 uint32_t force_full_frame_update : 1;
318
319 /**
320 * Use HW Lock Mgr object to do HW locking in FW.
321 */
322 uint32_t use_hw_lock_mgr : 1;
323
324 /**
325 * Use TPS3 signal when restore main link.
326 */
327 uint32_t force_wakeup_by_tps3 : 1;
328
329 /**
330 * Back to back flip, therefore cannot power down PHY
331 */
332 uint32_t back_to_back_flip : 1;
333
334 } bitfields;
335
336 /**
337 * Union for debug flags.
338 */
339 uint32_t u32All;
340 };
341
342 /**
343 * Flags that can be set by driver to change some Replay behaviour.
344 */
345 union replay_debug_flags {
346 struct {
347 /**
348 * Enable visual confirm in FW.
349 */
350 uint32_t visual_confirm : 1;
351
352 /**
353 * @skip_crc: Set if need to skip CRC.
354 */
355 uint32_t skip_crc : 1;
356
357 /**
358 * @force_link_power_on: Force disable ALPM control
359 */
360 uint32_t force_link_power_on : 1;
361
362 /**
363 * @force_phy_power_on: Force phy power on
364 */
365 uint32_t force_phy_power_on : 1;
366
367 /**
368 * @timing_resync_disabled: Disabled Replay normal sleep mode timing resync
369 */
370 uint32_t timing_resync_disabled : 1;
371
372 /**
373 * @skip_crtc_disabled: CRTC disable skipped
374 */
375 uint32_t skip_crtc_disabled : 1;
376
377 /**
378 * @force_defer_one_frame_update: Force defer one frame update in ultra sleep mode
379 */
380 uint32_t force_defer_one_frame_update : 1;
381 /**
382 * @disable_delay_alpm_on: Force disable delay alpm on
383 */
384 uint32_t disable_delay_alpm_on : 1;
385 /**
386 * @disable_desync_error_check: Force disable desync error check
387 */
388 uint32_t disable_desync_error_check : 1;
389 /**
390 * @disable_desync_error_check: Force disable desync error check
391 */
392 uint32_t disable_dmub_save_restore : 1;
393
394 uint32_t reserved : 22;
395 } bitfields;
396
397 uint32_t u32All;
398 };
399
400 union replay_hw_flags {
401 struct {
402 /**
403 * @allow_alpm_fw_standby_mode: To indicate whether the
404 * ALPM FW standby mode is allowed
405 */
406 uint32_t allow_alpm_fw_standby_mode : 1;
407
408 /*
409 * @dsc_enable_status: DSC enable status in driver
410 */
411 uint32_t dsc_enable_status : 1;
412
413 /**
414 * @fec_enable_status: receive fec enable/disable status from driver
415 */
416 uint32_t fec_enable_status : 1;
417
418 /*
419 * @smu_optimizations_en: SMU power optimization.
420 * Only when active display is Replay capable and display enters Replay.
421 * Trigger interrupt to SMU to powerup/down.
422 */
423 uint32_t smu_optimizations_en : 1;
424
425 /**
426 * @otg_powered_down: Flag to keep track of OTG power state.
427 */
428 uint32_t otg_powered_down : 1;
429
430 /**
431 * @phy_power_state: Indicates current phy power state
432 */
433 uint32_t phy_power_state : 1;
434
435 /**
436 * @link_power_state: Indicates current link power state
437 */
438 uint32_t link_power_state : 1;
439 /**
440 * Use TPS3 signal when restore main link.
441 */
442 uint32_t force_wakeup_by_tps3 : 1;
443 } bitfields;
444
445 uint32_t u32All;
446 };
447
448 /**
449 * DMUB visual confirm color
450 */
451 struct dmub_feature_caps {
452 /**
453 * Max PSR version supported by FW.
454 */
455 uint8_t psr;
456 uint8_t fw_assisted_mclk_switch;
457 uint8_t reserved[4];
458 uint8_t subvp_psr_support;
459 uint8_t gecc_enable;
460 };
461
462 struct dmub_visual_confirm_color {
463 /**
464 * Maximum 10 bits color value
465 */
466 uint16_t color_r_cr;
467 uint16_t color_g_y;
468 uint16_t color_b_cb;
469 uint16_t panel_inst;
470 };
471
472 #if defined(__cplusplus)
473 }
474 #endif
475
476 //==============================================================================
477 //</DMUB_TYPES>=================================================================
478 //==============================================================================
479 //< DMUB_META>==================================================================
480 //==============================================================================
481 #pragma pack(push, 1)
482
483 /* Magic value for identifying dmub_fw_meta_info */
484 #define DMUB_FW_META_MAGIC 0x444D5542
485
486 /* Offset from the end of the file to the dmub_fw_meta_info */
487 #define DMUB_FW_META_OFFSET 0x24
488
489 /**
490 * struct dmub_fw_meta_info - metadata associated with fw binary
491 *
492 * NOTE: This should be considered a stable API. Fields should
493 * not be repurposed or reordered. New fields should be
494 * added instead to extend the structure.
495 *
496 * @magic_value: magic value identifying DMUB firmware meta info
497 * @fw_region_size: size of the firmware state region
498 * @trace_buffer_size: size of the tracebuffer region
499 * @fw_version: the firmware version information
500 * @dal_fw: 1 if the firmware is DAL
501 */
502 struct dmub_fw_meta_info {
503 uint32_t magic_value; /**< magic value identifying DMUB firmware meta info */
504 uint32_t fw_region_size; /**< size of the firmware state region */
505 uint32_t trace_buffer_size; /**< size of the tracebuffer region */
506 uint32_t fw_version; /**< the firmware version information */
507 uint8_t dal_fw; /**< 1 if the firmware is DAL */
508 uint8_t reserved[3]; /**< padding bits */
509 };
510
511 /**
512 * union dmub_fw_meta - ensures that dmub_fw_meta_info remains 64 bytes
513 */
514 union dmub_fw_meta {
515 struct dmub_fw_meta_info info; /**< metadata info */
516 uint8_t reserved[64]; /**< padding bits */
517 };
518
519 #pragma pack(pop)
520
521 //==============================================================================
522 //< DMUB Trace Buffer>================================================================
523 //==============================================================================
524 /**
525 * dmub_trace_code_t - firmware trace code, 32-bits
526 */
527 typedef uint32_t dmub_trace_code_t;
528
529 /**
530 * struct dmcub_trace_buf_entry - Firmware trace entry
531 */
532 struct dmcub_trace_buf_entry {
533 dmub_trace_code_t trace_code; /**< trace code for the event */
534 uint32_t tick_count; /**< the tick count at time of trace */
535 uint32_t param0; /**< trace defined parameter 0 */
536 uint32_t param1; /**< trace defined parameter 1 */
537 };
538
539 //==============================================================================
540 //< DMUB_STATUS>================================================================
541 //==============================================================================
542
543 /**
544 * DMCUB scratch registers can be used to determine firmware status.
545 * Current scratch register usage is as follows:
546 *
547 * SCRATCH0: FW Boot Status register
548 * SCRATCH5: LVTMA Status Register
549 * SCRATCH15: FW Boot Options register
550 */
551
552 /**
553 * union dmub_fw_boot_status - Status bit definitions for SCRATCH0.
554 */
555 union dmub_fw_boot_status {
556 struct {
557 uint32_t dal_fw : 1; /**< 1 if DAL FW */
558 uint32_t mailbox_rdy : 1; /**< 1 if mailbox ready */
559 uint32_t optimized_init_done : 1; /**< 1 if optimized init done */
560 uint32_t restore_required : 1; /**< 1 if driver should call restore */
561 uint32_t defer_load : 1; /**< 1 if VBIOS data is deferred programmed */
562 uint32_t fams_enabled : 1; /**< 1 if VBIOS data is deferred programmed */
563 uint32_t detection_required: 1; /**< if detection need to be triggered by driver */
564 uint32_t hw_power_init_done: 1; /**< 1 if hw power init is completed */
565 } bits; /**< status bits */
566 uint32_t all; /**< 32-bit access to status bits */
567 };
568
569 /**
570 * enum dmub_fw_boot_status_bit - Enum bit definitions for SCRATCH0.
571 */
572 enum dmub_fw_boot_status_bit {
573 DMUB_FW_BOOT_STATUS_BIT_DAL_FIRMWARE = (1 << 0), /**< 1 if DAL FW */
574 DMUB_FW_BOOT_STATUS_BIT_MAILBOX_READY = (1 << 1), /**< 1 if mailbox ready */
575 DMUB_FW_BOOT_STATUS_BIT_OPTIMIZED_INIT_DONE = (1 << 2), /**< 1 if init done */
576 DMUB_FW_BOOT_STATUS_BIT_RESTORE_REQUIRED = (1 << 3), /**< 1 if driver should call restore */
577 DMUB_FW_BOOT_STATUS_BIT_DEFERRED_LOADED = (1 << 4), /**< 1 if VBIOS data is deferred programmed */
578 DMUB_FW_BOOT_STATUS_BIT_FAMS_ENABLED = (1 << 5), /**< 1 if FAMS is enabled*/
579 DMUB_FW_BOOT_STATUS_BIT_DETECTION_REQUIRED = (1 << 6), /**< 1 if detection need to be triggered by driver*/
580 DMUB_FW_BOOT_STATUS_BIT_HW_POWER_INIT_DONE = (1 << 7), /**< 1 if hw power init is completed */
581 };
582
583 /* Register bit definition for SCRATCH5 */
584 union dmub_lvtma_status {
585 struct {
586 uint32_t psp_ok : 1;
587 uint32_t edp_on : 1;
588 uint32_t reserved : 30;
589 } bits;
590 uint32_t all;
591 };
592
593 enum dmub_lvtma_status_bit {
594 DMUB_LVTMA_STATUS_BIT_PSP_OK = (1 << 0),
595 DMUB_LVTMA_STATUS_BIT_EDP_ON = (1 << 1),
596 };
597
598 enum dmub_ips_disable_type {
599 DMUB_IPS_DISABLE_IPS1 = 1,
600 DMUB_IPS_DISABLE_IPS2 = 2,
601 DMUB_IPS_DISABLE_IPS2_Z10 = 3,
602 };
603
604 /**
605 * union dmub_fw_boot_options - Boot option definitions for SCRATCH14
606 */
607 union dmub_fw_boot_options {
608 struct {
609 uint32_t pemu_env : 1; /**< 1 if PEMU */
610 uint32_t fpga_env : 1; /**< 1 if FPGA */
611 uint32_t optimized_init : 1; /**< 1 if optimized init */
612 uint32_t skip_phy_access : 1; /**< 1 if PHY access should be skipped */
613 uint32_t disable_clk_gate: 1; /**< 1 if clock gating should be disabled */
614 uint32_t skip_phy_init_panel_sequence: 1; /**< 1 to skip panel init seq */
615 uint32_t z10_disable: 1; /**< 1 to disable z10 */
616 uint32_t enable_dpia: 1; /**< 1 if DPIA should be enabled */
617 uint32_t invalid_vbios_data: 1; /**< 1 if VBIOS data table is invalid */
618 uint32_t dpia_supported: 1; /**< 1 if DPIA is supported on this platform */
619 uint32_t sel_mux_phy_c_d_phy_f_g: 1; /**< 1 if PHYF/PHYG should be enabled */
620 /**< 1 if all root clock gating is enabled and low power memory is enabled*/
621 uint32_t power_optimization: 1;
622 uint32_t diag_env: 1; /* 1 if diagnostic environment */
623 uint32_t gpint_scratch8: 1; /* 1 if GPINT is in scratch8*/
624 uint32_t usb4_cm_version: 1; /**< 1 CM support */
625 uint32_t dpia_hpd_int_enable_supported: 1; /* 1 if dpia hpd int enable supported */
626 uint32_t usb4_dpia_bw_alloc_supported: 1; /* 1 if USB4 dpia BW allocation supported */
627 uint32_t disable_clk_ds: 1; /* 1 if disallow dispclk_ds and dppclk_ds*/
628 uint32_t disable_timeout_recovery : 1; /* 1 if timeout recovery should be disabled */
629 uint32_t ips_pg_disable: 1; /* 1 to disable ONO domains power gating*/
630 uint32_t ips_disable: 2; /* options to disable ips support*/
631 uint32_t reserved : 10; /**< reserved */
632 } bits; /**< boot bits */
633 uint32_t all; /**< 32-bit access to bits */
634 };
635
636 enum dmub_fw_boot_options_bit {
637 DMUB_FW_BOOT_OPTION_BIT_PEMU_ENV = (1 << 0), /**< 1 if PEMU */
638 DMUB_FW_BOOT_OPTION_BIT_FPGA_ENV = (1 << 1), /**< 1 if FPGA */
639 DMUB_FW_BOOT_OPTION_BIT_OPTIMIZED_INIT_DONE = (1 << 2), /**< 1 if optimized init done */
640 };
641
642 //==============================================================================
643 //</DMUB_STATUS>================================================================
644 //==============================================================================
645 //< DMUB_VBIOS>=================================================================
646 //==============================================================================
647
648 /*
649 * enum dmub_cmd_vbios_type - VBIOS commands.
650 *
651 * Command IDs should be treated as stable ABI.
652 * Do not reuse or modify IDs.
653 */
654 enum dmub_cmd_vbios_type {
655 /**
656 * Configures the DIG encoder.
657 */
658 DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL = 0,
659 /**
660 * Controls the PHY.
661 */
662 DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL = 1,
663 /**
664 * Sets the pixel clock/symbol clock.
665 */
666 DMUB_CMD__VBIOS_SET_PIXEL_CLOCK = 2,
667 /**
668 * Enables or disables power gating.
669 */
670 DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING = 3,
671 /**
672 * Controls embedded panels.
673 */
674 DMUB_CMD__VBIOS_LVTMA_CONTROL = 15,
675 /**
676 * Query DP alt status on a transmitter.
677 */
678 DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT = 26,
679 /**
680 * Controls domain power gating
681 */
682 DMUB_CMD__VBIOS_DOMAIN_CONTROL = 28,
683 };
684
685 //==============================================================================
686 //</DMUB_VBIOS>=================================================================
687 //==============================================================================
688 //< DMUB_GPINT>=================================================================
689 //==============================================================================
690
691 /**
692 * The shifts and masks below may alternatively be used to format and read
693 * the command register bits.
694 */
695
696 #define DMUB_GPINT_DATA_PARAM_MASK 0xFFFF
697 #define DMUB_GPINT_DATA_PARAM_SHIFT 0
698
699 #define DMUB_GPINT_DATA_COMMAND_CODE_MASK 0xFFF
700 #define DMUB_GPINT_DATA_COMMAND_CODE_SHIFT 16
701
702 #define DMUB_GPINT_DATA_STATUS_MASK 0xF
703 #define DMUB_GPINT_DATA_STATUS_SHIFT 28
704
705 /**
706 * Command responses.
707 */
708
709 /**
710 * Return response for DMUB_GPINT__STOP_FW command.
711 */
712 #define DMUB_GPINT__STOP_FW_RESPONSE 0xDEADDEAD
713
714 /**
715 * union dmub_gpint_data_register - Format for sending a command via the GPINT.
716 */
717 union dmub_gpint_data_register {
718 struct {
719 uint32_t param : 16; /**< 16-bit parameter */
720 uint32_t command_code : 12; /**< GPINT command */
721 uint32_t status : 4; /**< Command status bit */
722 } bits; /**< GPINT bit access */
723 uint32_t all; /**< GPINT 32-bit access */
724 };
725
726 /*
727 * enum dmub_gpint_command - GPINT command to DMCUB FW
728 *
729 * Command IDs should be treated as stable ABI.
730 * Do not reuse or modify IDs.
731 */
732 enum dmub_gpint_command {
733 /**
734 * Invalid command, ignored.
735 */
736 DMUB_GPINT__INVALID_COMMAND = 0,
737 /**
738 * DESC: Queries the firmware version.
739 * RETURN: Firmware version.
740 */
741 DMUB_GPINT__GET_FW_VERSION = 1,
742 /**
743 * DESC: Halts the firmware.
744 * RETURN: DMUB_GPINT__STOP_FW_RESPONSE (0xDEADDEAD) when halted
745 */
746 DMUB_GPINT__STOP_FW = 2,
747 /**
748 * DESC: Get PSR state from FW.
749 * RETURN: PSR state enum. This enum may need to be converted to the legacy PSR state value.
750 */
751 DMUB_GPINT__GET_PSR_STATE = 7,
752 /**
753 * DESC: Notifies DMCUB of the currently active streams.
754 * ARGS: Stream mask, 1 bit per active stream index.
755 */
756 DMUB_GPINT__IDLE_OPT_NOTIFY_STREAM_MASK = 8,
757 /**
758 * DESC: Start PSR residency counter. Stop PSR resdiency counter and get value.
759 * ARGS: We can measure residency from various points. The argument will specify the residency mode.
760 * By default, it is measured from after we powerdown the PHY, to just before we powerup the PHY.
761 * RETURN: PSR residency in milli-percent.
762 */
763 DMUB_GPINT__PSR_RESIDENCY = 9,
764
765 /**
766 * DESC: Get REPLAY state from FW.
767 * RETURN: REPLAY state enum. This enum may need to be converted to the legacy REPLAY state value.
768 */
769 DMUB_GPINT__GET_REPLAY_STATE = 13,
770
771 /**
772 * DESC: Start REPLAY residency counter. Stop REPLAY resdiency counter and get value.
773 * ARGS: We can measure residency from various points. The argument will specify the residency mode.
774 * By default, it is measured from after we powerdown the PHY, to just before we powerup the PHY.
775 * RETURN: REPLAY residency in milli-percent.
776 */
777 DMUB_GPINT__REPLAY_RESIDENCY = 14,
778
779
780 /**
781 * DESC: Notifies DMCUB detection is done so detection required can be cleared.
782 */
783 DMUB_GPINT__NOTIFY_DETECTION_DONE = 12,
784 /**
785 * DESC: Updates the trace buffer lower 32-bit mask.
786 * ARGS: The new mask
787 * RETURN: Lower 32-bit mask.
788 */
789 DMUB_GPINT__UPDATE_TRACE_BUFFER_MASK = 101,
790 /**
791 * DESC: Updates the trace buffer lower 32-bit mask.
792 * ARGS: The new mask
793 * RETURN: Lower 32-bit mask.
794 */
795 DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD0 = 102,
796 /**
797 * DESC: Updates the trace buffer mask bi0~bit15.
798 * ARGS: The new mask
799 * RETURN: Lower 32-bit mask.
800 */
801 DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD1 = 103,
802 };
803
804 /**
805 * INBOX0 generic command definition
806 */
807 union dmub_inbox0_cmd_common {
808 struct {
809 uint32_t command_code: 8; /**< INBOX0 command code */
810 uint32_t param: 24; /**< 24-bit parameter */
811 } bits;
812 uint32_t all;
813 };
814
815 /**
816 * INBOX0 hw_lock command definition
817 */
818 union dmub_inbox0_cmd_lock_hw {
819 struct {
820 uint32_t command_code: 8;
821
822 /* NOTE: Must be have enough bits to match: enum hw_lock_client */
823 uint32_t hw_lock_client: 2;
824
825 /* NOTE: Below fields must match with: struct dmub_hw_lock_inst_flags */
826 uint32_t otg_inst: 3;
827 uint32_t opp_inst: 3;
828 uint32_t dig_inst: 3;
829
830 /* NOTE: Below fields must match with: union dmub_hw_lock_flags */
831 uint32_t lock_pipe: 1;
832 uint32_t lock_cursor: 1;
833 uint32_t lock_dig: 1;
834 uint32_t triple_buffer_lock: 1;
835
836 uint32_t lock: 1; /**< Lock */
837 uint32_t should_release: 1; /**< Release */
838 uint32_t reserved: 7; /**< Reserved for extending more clients, HW, etc. */
839 } bits;
840 uint32_t all;
841 };
842
843 union dmub_inbox0_data_register {
844 union dmub_inbox0_cmd_common inbox0_cmd_common;
845 union dmub_inbox0_cmd_lock_hw inbox0_cmd_lock_hw;
846 };
847
848 enum dmub_inbox0_command {
849 /**
850 * DESC: Invalid command, ignored.
851 */
852 DMUB_INBOX0_CMD__INVALID_COMMAND = 0,
853 /**
854 * DESC: Notification to acquire/release HW lock
855 * ARGS:
856 */
857 DMUB_INBOX0_CMD__HW_LOCK = 1,
858 };
859 //==============================================================================
860 //</DMUB_GPINT>=================================================================
861 //==============================================================================
862 //< DMUB_CMD>===================================================================
863 //==============================================================================
864
865 /**
866 * Size in bytes of each DMUB command.
867 */
868 #define DMUB_RB_CMD_SIZE 64
869
870 /**
871 * Maximum number of items in the DMUB ringbuffer.
872 */
873 #define DMUB_RB_MAX_ENTRY 128
874
875 /**
876 * Ringbuffer size in bytes.
877 */
878 #define DMUB_RB_SIZE (DMUB_RB_CMD_SIZE * DMUB_RB_MAX_ENTRY)
879
880 /**
881 * REG_SET mask for reg offload.
882 */
883 #define REG_SET_MASK 0xFFFF
884
885 /*
886 * enum dmub_cmd_type - DMUB inbox command.
887 *
888 * Command IDs should be treated as stable ABI.
889 * Do not reuse or modify IDs.
890 */
891 enum dmub_cmd_type {
892 /**
893 * Invalid command.
894 */
895 DMUB_CMD__NULL = 0,
896 /**
897 * Read modify write register sequence offload.
898 */
899 DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE = 1,
900 /**
901 * Field update register sequence offload.
902 */
903 DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ = 2,
904 /**
905 * Burst write sequence offload.
906 */
907 DMUB_CMD__REG_SEQ_BURST_WRITE = 3,
908 /**
909 * Reg wait sequence offload.
910 */
911 DMUB_CMD__REG_REG_WAIT = 4,
912 /**
913 * Workaround to avoid HUBP underflow during NV12 playback.
914 */
915 DMUB_CMD__PLAT_54186_WA = 5,
916 /**
917 * Command type used to query FW feature caps.
918 */
919 DMUB_CMD__QUERY_FEATURE_CAPS = 6,
920 /**
921 * Command type used to get visual confirm color.
922 */
923 DMUB_CMD__GET_VISUAL_CONFIRM_COLOR = 8,
924 /**
925 * Command type used for all PSR commands.
926 */
927 DMUB_CMD__PSR = 64,
928 /**
929 * Command type used for all MALL commands.
930 */
931 DMUB_CMD__MALL = 65,
932 /**
933 * Command type used for all ABM commands.
934 */
935 DMUB_CMD__ABM = 66,
936 /**
937 * Command type used to update dirty rects in FW.
938 */
939 DMUB_CMD__UPDATE_DIRTY_RECT = 67,
940 /**
941 * Command type used to update cursor info in FW.
942 */
943 DMUB_CMD__UPDATE_CURSOR_INFO = 68,
944 /**
945 * Command type used for HW locking in FW.
946 */
947 DMUB_CMD__HW_LOCK = 69,
948 /**
949 * Command type used to access DP AUX.
950 */
951 DMUB_CMD__DP_AUX_ACCESS = 70,
952 /**
953 * Command type used for OUTBOX1 notification enable
954 */
955 DMUB_CMD__OUTBOX1_ENABLE = 71,
956
957 /**
958 * Command type used for all idle optimization commands.
959 */
960 DMUB_CMD__IDLE_OPT = 72,
961 /**
962 * Command type used for all clock manager commands.
963 */
964 DMUB_CMD__CLK_MGR = 73,
965 /**
966 * Command type used for all panel control commands.
967 */
968 DMUB_CMD__PANEL_CNTL = 74,
969 /**
970 * Command type used for <TODO:description>
971 */
972 DMUB_CMD__CAB_FOR_SS = 75,
973
974 DMUB_CMD__FW_ASSISTED_MCLK_SWITCH = 76,
975
976 /**
977 * Command type used for interfacing with DPIA.
978 */
979 DMUB_CMD__DPIA = 77,
980 /**
981 * Command type used for EDID CEA parsing
982 */
983 DMUB_CMD__EDID_CEA = 79,
984 /**
985 * Command type used for getting usbc cable ID
986 */
987 DMUB_CMD_GET_USBC_CABLE_ID = 81,
988 /**
989 * Command type used to query HPD state.
990 */
991 DMUB_CMD__QUERY_HPD_STATE = 82,
992 /**
993 * Command type used for all VBIOS interface commands.
994 */
995
996 /**
997 * Command type used for all REPLAY commands.
998 */
999 DMUB_CMD__REPLAY = 83,
1000
1001 /**
1002 * Command type used for all SECURE_DISPLAY commands.
1003 */
1004 DMUB_CMD__SECURE_DISPLAY = 85,
1005
1006 /**
1007 * Command type used to set DPIA HPD interrupt state
1008 */
1009 DMUB_CMD__DPIA_HPD_INT_ENABLE = 86,
1010
1011 DMUB_CMD__VBIOS = 128,
1012 };
1013
1014 /**
1015 * enum dmub_out_cmd_type - DMUB outbox commands.
1016 */
1017 enum dmub_out_cmd_type {
1018 /**
1019 * Invalid outbox command, ignored.
1020 */
1021 DMUB_OUT_CMD__NULL = 0,
1022 /**
1023 * Command type used for DP AUX Reply data notification
1024 */
1025 DMUB_OUT_CMD__DP_AUX_REPLY = 1,
1026 /**
1027 * Command type used for DP HPD event notification
1028 */
1029 DMUB_OUT_CMD__DP_HPD_NOTIFY = 2,
1030 /**
1031 * Command type used for SET_CONFIG Reply notification
1032 */
1033 DMUB_OUT_CMD__SET_CONFIG_REPLY = 3,
1034 /**
1035 * Command type used for USB4 DPIA notification
1036 */
1037 DMUB_OUT_CMD__DPIA_NOTIFICATION = 5,
1038 };
1039
1040 /* DMUB_CMD__DPIA command sub-types. */
1041 enum dmub_cmd_dpia_type {
1042 DMUB_CMD__DPIA_DIG1_DPIA_CONTROL = 0,
1043 DMUB_CMD__DPIA_SET_CONFIG_ACCESS = 1,
1044 DMUB_CMD__DPIA_MST_ALLOC_SLOTS = 2,
1045 };
1046
1047 /* DMUB_OUT_CMD__DPIA_NOTIFICATION command types. */
1048 enum dmub_cmd_dpia_notification_type {
1049 DPIA_NOTIFY__BW_ALLOCATION = 0,
1050 };
1051
1052 #pragma pack(push, 1)
1053
1054 /**
1055 * struct dmub_cmd_header - Common command header fields.
1056 */
1057 struct dmub_cmd_header {
1058 unsigned int type : 8; /**< command type */
1059 unsigned int sub_type : 8; /**< command sub type */
1060 unsigned int ret_status : 1; /**< 1 if returned data, 0 otherwise */
1061 unsigned int multi_cmd_pending : 1; /**< 1 if multiple commands chained together */
1062 unsigned int reserved0 : 6; /**< reserved bits */
1063 unsigned int payload_bytes : 6; /* payload excluding header - up to 60 bytes */
1064 unsigned int reserved1 : 2; /**< reserved bits */
1065 };
1066
1067 /*
1068 * struct dmub_cmd_read_modify_write_sequence - Read modify write
1069 *
1070 * 60 payload bytes can hold up to 5 sets of read modify writes,
1071 * each take 3 dwords.
1072 *
1073 * number of sequences = header.payload_bytes / sizeof(struct dmub_cmd_read_modify_write_sequence)
1074 *
1075 * modify_mask = 0xffff'ffff means all fields are going to be updated. in this case
1076 * command parser will skip the read and we can use modify_mask = 0xffff'ffff as reg write
1077 */
1078 struct dmub_cmd_read_modify_write_sequence {
1079 uint32_t addr; /**< register address */
1080 uint32_t modify_mask; /**< modify mask */
1081 uint32_t modify_value; /**< modify value */
1082 };
1083
1084 /**
1085 * Maximum number of ops in read modify write sequence.
1086 */
1087 #define DMUB_READ_MODIFY_WRITE_SEQ__MAX 5
1088
1089 /**
1090 * struct dmub_cmd_read_modify_write_sequence - Read modify write command.
1091 */
1092 struct dmub_rb_cmd_read_modify_write {
1093 struct dmub_cmd_header header; /**< command header */
1094 /**
1095 * Read modify write sequence.
1096 */
1097 struct dmub_cmd_read_modify_write_sequence seq[DMUB_READ_MODIFY_WRITE_SEQ__MAX];
1098 };
1099
1100 /*
1101 * Update a register with specified masks and values sequeunce
1102 *
1103 * 60 payload bytes can hold address + up to 7 sets of mask/value combo, each take 2 dword
1104 *
1105 * number of field update sequence = (header.payload_bytes - sizeof(addr)) / sizeof(struct read_modify_write_sequence)
1106 *
1107 *
1108 * USE CASE:
1109 * 1. auto-increment register where additional read would update pointer and produce wrong result
1110 * 2. toggle a bit without read in the middle
1111 */
1112
1113 struct dmub_cmd_reg_field_update_sequence {
1114 uint32_t modify_mask; /**< 0xffff'ffff to skip initial read */
1115 uint32_t modify_value; /**< value to update with */
1116 };
1117
1118 /**
1119 * Maximum number of ops in field update sequence.
1120 */
1121 #define DMUB_REG_FIELD_UPDATE_SEQ__MAX 7
1122
1123 /**
1124 * struct dmub_rb_cmd_reg_field_update_sequence - Field update command.
1125 */
1126 struct dmub_rb_cmd_reg_field_update_sequence {
1127 struct dmub_cmd_header header; /**< command header */
1128 uint32_t addr; /**< register address */
1129 /**
1130 * Field update sequence.
1131 */
1132 struct dmub_cmd_reg_field_update_sequence seq[DMUB_REG_FIELD_UPDATE_SEQ__MAX];
1133 };
1134
1135
1136 /**
1137 * Maximum number of burst write values.
1138 */
1139 #define DMUB_BURST_WRITE_VALUES__MAX 14
1140
1141 /*
1142 * struct dmub_rb_cmd_burst_write - Burst write
1143 *
1144 * support use case such as writing out LUTs.
1145 *
1146 * 60 payload bytes can hold up to 14 values to write to given address
1147 *
1148 * number of payload = header.payload_bytes / sizeof(struct read_modify_write_sequence)
1149 */
1150 struct dmub_rb_cmd_burst_write {
1151 struct dmub_cmd_header header; /**< command header */
1152 uint32_t addr; /**< register start address */
1153 /**
1154 * Burst write register values.
1155 */
1156 uint32_t write_values[DMUB_BURST_WRITE_VALUES__MAX];
1157 };
1158
1159 /**
1160 * struct dmub_rb_cmd_common - Common command header
1161 */
1162 struct dmub_rb_cmd_common {
1163 struct dmub_cmd_header header; /**< command header */
1164 /**
1165 * Padding to RB_CMD_SIZE
1166 */
1167 uint8_t cmd_buffer[DMUB_RB_CMD_SIZE - sizeof(struct dmub_cmd_header)];
1168 };
1169
1170 /**
1171 * struct dmub_cmd_reg_wait_data - Register wait data
1172 */
1173 struct dmub_cmd_reg_wait_data {
1174 uint32_t addr; /**< Register address */
1175 uint32_t mask; /**< Mask for register bits */
1176 uint32_t condition_field_value; /**< Value to wait for */
1177 uint32_t time_out_us; /**< Time out for reg wait in microseconds */
1178 };
1179
1180 /**
1181 * struct dmub_rb_cmd_reg_wait - Register wait command
1182 */
1183 struct dmub_rb_cmd_reg_wait {
1184 struct dmub_cmd_header header; /**< Command header */
1185 struct dmub_cmd_reg_wait_data reg_wait; /**< Register wait data */
1186 };
1187
1188 /**
1189 * struct dmub_cmd_PLAT_54186_wa - Underflow workaround
1190 *
1191 * Reprograms surface parameters to avoid underflow.
1192 */
1193 struct dmub_cmd_PLAT_54186_wa {
1194 uint32_t DCSURF_SURFACE_CONTROL; /**< reg value */
1195 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH; /**< reg value */
1196 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS; /**< reg value */
1197 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C; /**< reg value */
1198 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_C; /**< reg value */
1199 struct {
1200 uint8_t hubp_inst : 4; /**< HUBP instance */
1201 uint8_t tmz_surface : 1; /**< TMZ enable or disable */
1202 uint8_t immediate :1; /**< Immediate flip */
1203 uint8_t vmid : 4; /**< VMID */
1204 uint8_t grph_stereo : 1; /**< 1 if stereo */
1205 uint32_t reserved : 21; /**< Reserved */
1206 } flip_params; /**< Pageflip parameters */
1207 uint32_t reserved[9]; /**< Reserved bits */
1208 };
1209
1210 /**
1211 * struct dmub_rb_cmd_PLAT_54186_wa - Underflow workaround command
1212 */
1213 struct dmub_rb_cmd_PLAT_54186_wa {
1214 struct dmub_cmd_header header; /**< Command header */
1215 struct dmub_cmd_PLAT_54186_wa flip; /**< Flip data */
1216 };
1217
1218 /**
1219 * struct dmub_rb_cmd_mall - MALL command data.
1220 */
1221 struct dmub_rb_cmd_mall {
1222 struct dmub_cmd_header header; /**< Common command header */
1223 union dmub_addr cursor_copy_src; /**< Cursor copy address */
1224 union dmub_addr cursor_copy_dst; /**< Cursor copy destination */
1225 uint32_t tmr_delay; /**< Timer delay */
1226 uint32_t tmr_scale; /**< Timer scale */
1227 uint16_t cursor_width; /**< Cursor width in pixels */
1228 uint16_t cursor_pitch; /**< Cursor pitch in pixels */
1229 uint16_t cursor_height; /**< Cursor height in pixels */
1230 uint8_t cursor_bpp; /**< Cursor bits per pixel */
1231 uint8_t debug_bits; /**< Debug bits */
1232
1233 uint8_t reserved1; /**< Reserved bits */
1234 uint8_t reserved2; /**< Reserved bits */
1235 };
1236
1237 /**
1238 * enum dmub_cmd_cab_type - CAB command data.
1239 */
1240 enum dmub_cmd_cab_type {
1241 /**
1242 * No idle optimizations (i.e. no CAB)
1243 */
1244 DMUB_CMD__CAB_NO_IDLE_OPTIMIZATION = 0,
1245 /**
1246 * No DCN requests for memory
1247 */
1248 DMUB_CMD__CAB_NO_DCN_REQ = 1,
1249 /**
1250 * Fit surfaces in CAB (i.e. CAB enable)
1251 */
1252 DMUB_CMD__CAB_DCN_SS_FIT_IN_CAB = 2,
1253 };
1254
1255 /**
1256 * struct dmub_rb_cmd_cab - CAB command data.
1257 */
1258 struct dmub_rb_cmd_cab_for_ss {
1259 struct dmub_cmd_header header;
1260 uint8_t cab_alloc_ways; /* total number of ways */
1261 uint8_t debug_bits; /* debug bits */
1262 };
1263
1264 /**
1265 * Enum for indicating which MCLK switch mode per pipe
1266 */
1267 enum mclk_switch_mode {
1268 NONE = 0,
1269 FPO = 1,
1270 SUBVP = 2,
1271 VBLANK = 3,
1272 };
1273
1274 /* Per pipe struct which stores the MCLK switch mode
1275 * data to be sent to DMUB.
1276 * Named "v2" for now -- once FPO and SUBVP are fully merged
1277 * the type name can be updated
1278 */
1279 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 {
1280 union {
1281 struct {
1282 uint32_t pix_clk_100hz;
1283 uint16_t main_vblank_start;
1284 uint16_t main_vblank_end;
1285 uint16_t mall_region_lines;
1286 uint16_t prefetch_lines;
1287 uint16_t prefetch_to_mall_start_lines;
1288 uint16_t processing_delay_lines;
1289 uint16_t htotal; // required to calculate line time for multi-display cases
1290 uint16_t vtotal;
1291 uint8_t main_pipe_index;
1292 uint8_t phantom_pipe_index;
1293 /* Since the microschedule is calculated in terms of OTG lines,
1294 * include any scaling factors to make sure when we get accurate
1295 * conversion when programming MALL_START_LINE (which is in terms
1296 * of HUBP lines). If 4K is being downscaled to 1080p, scale factor
1297 * is 1/2 (numerator = 1, denominator = 2).
1298 */
1299 uint8_t scale_factor_numerator;
1300 uint8_t scale_factor_denominator;
1301 uint8_t is_drr;
1302 uint8_t main_split_pipe_index;
1303 uint8_t phantom_split_pipe_index;
1304 } subvp_data;
1305
1306 struct {
1307 uint32_t pix_clk_100hz;
1308 uint16_t vblank_start;
1309 uint16_t vblank_end;
1310 uint16_t vstartup_start;
1311 uint16_t vtotal;
1312 uint16_t htotal;
1313 uint8_t vblank_pipe_index;
1314 uint8_t padding[1];
1315 struct {
1316 uint8_t drr_in_use;
1317 uint8_t drr_window_size_ms; // Indicates largest VMIN/VMAX adjustment per frame
1318 uint16_t min_vtotal_supported; // Min VTOTAL that supports switching in VBLANK
1319 uint16_t max_vtotal_supported; // Max VTOTAL that can support SubVP static scheduling
1320 uint8_t use_ramping; // Use ramping or not
1321 uint8_t drr_vblank_start_margin;
1322 } drr_info; // DRR considered as part of SubVP + VBLANK case
1323 } vblank_data;
1324 } pipe_config;
1325
1326 /* - subvp_data in the union (pipe_config) takes up 27 bytes.
1327 * - Make the "mode" field a uint8_t instead of enum so we only use 1 byte (only
1328 * for the DMCUB command, cast to enum once we populate the DMCUB subvp state).
1329 */
1330 uint8_t mode; // enum mclk_switch_mode
1331 };
1332
1333 /**
1334 * Config data for Sub-VP and FPO
1335 * Named "v2" for now -- once FPO and SUBVP are fully merged
1336 * the type name can be updated
1337 */
1338 struct dmub_cmd_fw_assisted_mclk_switch_config_v2 {
1339 uint16_t watermark_a_cache;
1340 uint8_t vertical_int_margin_us;
1341 uint8_t pstate_allow_width_us;
1342 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 pipe_data[DMUB_MAX_SUBVP_STREAMS];
1343 };
1344
1345 /**
1346 * DMUB rb command definition for Sub-VP and FPO
1347 * Named "v2" for now -- once FPO and SUBVP are fully merged
1348 * the type name can be updated
1349 */
1350 struct dmub_rb_cmd_fw_assisted_mclk_switch_v2 {
1351 struct dmub_cmd_header header;
1352 struct dmub_cmd_fw_assisted_mclk_switch_config_v2 config_data;
1353 };
1354
1355 /**
1356 * enum dmub_cmd_idle_opt_type - Idle optimization command type.
1357 */
1358 enum dmub_cmd_idle_opt_type {
1359 /**
1360 * DCN hardware restore.
1361 */
1362 DMUB_CMD__IDLE_OPT_DCN_RESTORE = 0,
1363
1364 /**
1365 * DCN hardware save.
1366 */
1367 DMUB_CMD__IDLE_OPT_DCN_SAVE_INIT = 1,
1368
1369 /**
1370 * DCN hardware notify idle.
1371 */
1372 DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE = 2
1373 };
1374
1375 /**
1376 * struct dmub_rb_cmd_idle_opt_dcn_restore - DCN restore command data.
1377 */
1378 struct dmub_rb_cmd_idle_opt_dcn_restore {
1379 struct dmub_cmd_header header; /**< header */
1380 };
1381
1382 /**
1383 * struct dmub_dcn_notify_idle_cntl_data - Data passed to FW in a DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE command.
1384 */
1385 struct dmub_dcn_notify_idle_cntl_data {
1386 uint8_t driver_idle;
1387 uint8_t pad[1];
1388 };
1389
1390 /**
1391 * struct dmub_rb_cmd_idle_opt_dcn_notify_idle - Data passed to FW in a DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE command.
1392 */
1393 struct dmub_rb_cmd_idle_opt_dcn_notify_idle {
1394 struct dmub_cmd_header header; /**< header */
1395 struct dmub_dcn_notify_idle_cntl_data cntl_data;
1396 };
1397
1398 /**
1399 * struct dmub_clocks - Clock update notification.
1400 */
1401 struct dmub_clocks {
1402 uint32_t dispclk_khz; /**< dispclk kHz */
1403 uint32_t dppclk_khz; /**< dppclk kHz */
1404 uint32_t dcfclk_khz; /**< dcfclk kHz */
1405 uint32_t dcfclk_deep_sleep_khz; /**< dcfclk deep sleep kHz */
1406 };
1407
1408 /**
1409 * enum dmub_cmd_clk_mgr_type - Clock manager commands.
1410 */
1411 enum dmub_cmd_clk_mgr_type {
1412 /**
1413 * Notify DMCUB of clock update.
1414 */
1415 DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS = 0,
1416 };
1417
1418 /**
1419 * struct dmub_rb_cmd_clk_mgr_notify_clocks - Clock update notification.
1420 */
1421 struct dmub_rb_cmd_clk_mgr_notify_clocks {
1422 struct dmub_cmd_header header; /**< header */
1423 struct dmub_clocks clocks; /**< clock data */
1424 };
1425
1426 /**
1427 * struct dmub_cmd_digx_encoder_control_data - Encoder control data.
1428 */
1429 struct dmub_cmd_digx_encoder_control_data {
1430 union dig_encoder_control_parameters_v1_5 dig; /**< payload */
1431 };
1432
1433 /**
1434 * struct dmub_rb_cmd_digx_encoder_control - Encoder control command.
1435 */
1436 struct dmub_rb_cmd_digx_encoder_control {
1437 struct dmub_cmd_header header; /**< header */
1438 struct dmub_cmd_digx_encoder_control_data encoder_control; /**< payload */
1439 };
1440
1441 /**
1442 * struct dmub_cmd_set_pixel_clock_data - Set pixel clock data.
1443 */
1444 struct dmub_cmd_set_pixel_clock_data {
1445 struct set_pixel_clock_parameter_v1_7 clk; /**< payload */
1446 };
1447
1448 /**
1449 * struct dmub_cmd_set_pixel_clock_data - Set pixel clock command.
1450 */
1451 struct dmub_rb_cmd_set_pixel_clock {
1452 struct dmub_cmd_header header; /**< header */
1453 struct dmub_cmd_set_pixel_clock_data pixel_clock; /**< payload */
1454 };
1455
1456 /**
1457 * struct dmub_cmd_enable_disp_power_gating_data - Display power gating.
1458 */
1459 struct dmub_cmd_enable_disp_power_gating_data {
1460 struct enable_disp_power_gating_parameters_v2_1 pwr; /**< payload */
1461 };
1462
1463 /**
1464 * struct dmub_rb_cmd_enable_disp_power_gating - Display power command.
1465 */
1466 struct dmub_rb_cmd_enable_disp_power_gating {
1467 struct dmub_cmd_header header; /**< header */
1468 struct dmub_cmd_enable_disp_power_gating_data power_gating; /**< payload */
1469 };
1470
1471 /**
1472 * struct dmub_dig_transmitter_control_data_v1_7 - Transmitter control.
1473 */
1474 struct dmub_dig_transmitter_control_data_v1_7 {
1475 uint8_t phyid; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */
1476 uint8_t action; /**< Defined as ATOM_TRANSMITER_ACTION_xxx */
1477 union {
1478 uint8_t digmode; /**< enum atom_encode_mode_def */
1479 uint8_t dplaneset; /**< DP voltage swing and pre-emphasis value, "DP_LANE_SET__xDB_y_zV" */
1480 } mode_laneset;
1481 uint8_t lanenum; /**< Number of lanes */
1482 union {
1483 uint32_t symclk_10khz; /**< Symbol Clock in 10Khz */
1484 } symclk_units;
1485 uint8_t hpdsel; /**< =1: HPD1, =2: HPD2, ..., =6: HPD6, =0: HPD is not assigned */
1486 uint8_t digfe_sel; /**< DIG front-end selection, bit0 means DIG0 FE is enabled */
1487 uint8_t connobj_id; /**< Connector Object Id defined in ObjectId.h */
1488 uint8_t HPO_instance; /**< HPO instance (0: inst0, 1: inst1) */
1489 uint8_t reserved1; /**< For future use */
1490 uint8_t reserved2[3]; /**< For future use */
1491 uint32_t reserved3[11]; /**< For future use */
1492 };
1493
1494 /**
1495 * union dmub_cmd_dig1_transmitter_control_data - Transmitter control data.
1496 */
1497 union dmub_cmd_dig1_transmitter_control_data {
1498 struct dig_transmitter_control_parameters_v1_6 dig; /**< payload */
1499 struct dmub_dig_transmitter_control_data_v1_7 dig_v1_7; /**< payload 1.7 */
1500 };
1501
1502 /**
1503 * struct dmub_rb_cmd_dig1_transmitter_control - Transmitter control command.
1504 */
1505 struct dmub_rb_cmd_dig1_transmitter_control {
1506 struct dmub_cmd_header header; /**< header */
1507 union dmub_cmd_dig1_transmitter_control_data transmitter_control; /**< payload */
1508 };
1509
1510 /**
1511 * struct dmub_rb_cmd_domain_control_data - Data for DOMAIN power control
1512 */
1513 struct dmub_rb_cmd_domain_control_data {
1514 uint8_t inst : 6; /**< DOMAIN instance to control */
1515 uint8_t power_gate : 1; /**< 1=power gate, 0=power up */
1516 uint8_t reserved[3]; /**< Reserved for future use */
1517 };
1518
1519 /**
1520 * struct dmub_rb_cmd_domain_control - Controls DOMAIN power gating
1521 */
1522 struct dmub_rb_cmd_domain_control {
1523 struct dmub_cmd_header header; /**< header */
1524 struct dmub_rb_cmd_domain_control_data data; /**< payload */
1525 };
1526
1527 /**
1528 * DPIA tunnel command parameters.
1529 */
1530 struct dmub_cmd_dig_dpia_control_data {
1531 uint8_t enc_id; /** 0 = ENGINE_ID_DIGA, ... */
1532 uint8_t action; /** ATOM_TRANSMITER_ACTION_DISABLE/ENABLE/SETUP_VSEMPH */
1533 union {
1534 uint8_t digmode; /** enum atom_encode_mode_def */
1535 uint8_t dplaneset; /** DP voltage swing and pre-emphasis value */
1536 } mode_laneset;
1537 uint8_t lanenum; /** Lane number 1, 2, 4, 8 */
1538 uint32_t symclk_10khz; /** Symbol Clock in 10Khz */
1539 uint8_t hpdsel; /** =0: HPD is not assigned */
1540 uint8_t digfe_sel; /** DIG stream( front-end ) selection, bit0 - DIG0 FE */
1541 uint8_t dpia_id; /** Index of DPIA */
1542 uint8_t fec_rdy : 1;
1543 uint8_t reserved : 7;
1544 uint32_t reserved1;
1545 };
1546
1547 /**
1548 * DMUB command for DPIA tunnel control.
1549 */
1550 struct dmub_rb_cmd_dig1_dpia_control {
1551 struct dmub_cmd_header header;
1552 struct dmub_cmd_dig_dpia_control_data dpia_control;
1553 };
1554
1555 /**
1556 * SET_CONFIG Command Payload
1557 */
1558 struct set_config_cmd_payload {
1559 uint8_t msg_type; /* set config message type */
1560 uint8_t msg_data; /* set config message data */
1561 };
1562
1563 /**
1564 * Data passed from driver to FW in a DMUB_CMD__DPIA_SET_CONFIG_ACCESS command.
1565 */
1566 struct dmub_cmd_set_config_control_data {
1567 struct set_config_cmd_payload cmd_pkt;
1568 uint8_t instance; /* DPIA instance */
1569 uint8_t immed_status; /* Immediate status returned in case of error */
1570 };
1571
1572 /**
1573 * DMUB command structure for SET_CONFIG command.
1574 */
1575 struct dmub_rb_cmd_set_config_access {
1576 struct dmub_cmd_header header; /* header */
1577 struct dmub_cmd_set_config_control_data set_config_control; /* set config data */
1578 };
1579
1580 /**
1581 * Data passed from driver to FW in a DMUB_CMD__DPIA_MST_ALLOC_SLOTS command.
1582 */
1583 struct dmub_cmd_mst_alloc_slots_control_data {
1584 uint8_t mst_alloc_slots; /* mst slots to be allotted */
1585 uint8_t instance; /* DPIA instance */
1586 uint8_t immed_status; /* Immediate status returned as there is no outbox msg posted */
1587 uint8_t mst_slots_in_use; /* returns slots in use for error cases */
1588 };
1589
1590 /**
1591 * DMUB command structure for SET_ command.
1592 */
1593 struct dmub_rb_cmd_set_mst_alloc_slots {
1594 struct dmub_cmd_header header; /* header */
1595 struct dmub_cmd_mst_alloc_slots_control_data mst_slots_control; /* mst slots control */
1596 };
1597
1598 /**
1599 * DMUB command structure for DPIA HPD int enable control.
1600 */
1601 struct dmub_rb_cmd_dpia_hpd_int_enable {
1602 struct dmub_cmd_header header; /* header */
1603 uint32_t enable; /* dpia hpd interrupt enable */
1604 };
1605
1606 /**
1607 * struct dmub_rb_cmd_dpphy_init - DPPHY init.
1608 */
1609 struct dmub_rb_cmd_dpphy_init {
1610 struct dmub_cmd_header header; /**< header */
1611 uint8_t reserved[60]; /**< reserved bits */
1612 };
1613
1614 /**
1615 * enum dp_aux_request_action - DP AUX request command listing.
1616 *
1617 * 4 AUX request command bits are shifted to high nibble.
1618 */
1619 enum dp_aux_request_action {
1620 /** I2C-over-AUX write request */
1621 DP_AUX_REQ_ACTION_I2C_WRITE = 0x00,
1622 /** I2C-over-AUX read request */
1623 DP_AUX_REQ_ACTION_I2C_READ = 0x10,
1624 /** I2C-over-AUX write status request */
1625 DP_AUX_REQ_ACTION_I2C_STATUS_REQ = 0x20,
1626 /** I2C-over-AUX write request with MOT=1 */
1627 DP_AUX_REQ_ACTION_I2C_WRITE_MOT = 0x40,
1628 /** I2C-over-AUX read request with MOT=1 */
1629 DP_AUX_REQ_ACTION_I2C_READ_MOT = 0x50,
1630 /** I2C-over-AUX write status request with MOT=1 */
1631 DP_AUX_REQ_ACTION_I2C_STATUS_REQ_MOT = 0x60,
1632 /** Native AUX write request */
1633 DP_AUX_REQ_ACTION_DPCD_WRITE = 0x80,
1634 /** Native AUX read request */
1635 DP_AUX_REQ_ACTION_DPCD_READ = 0x90
1636 };
1637
1638 /**
1639 * enum aux_return_code_type - DP AUX process return code listing.
1640 */
1641 enum aux_return_code_type {
1642 /** AUX process succeeded */
1643 AUX_RET_SUCCESS = 0,
1644 /** AUX process failed with unknown reason */
1645 AUX_RET_ERROR_UNKNOWN,
1646 /** AUX process completed with invalid reply */
1647 AUX_RET_ERROR_INVALID_REPLY,
1648 /** AUX process timed out */
1649 AUX_RET_ERROR_TIMEOUT,
1650 /** HPD was low during AUX process */
1651 AUX_RET_ERROR_HPD_DISCON,
1652 /** Failed to acquire AUX engine */
1653 AUX_RET_ERROR_ENGINE_ACQUIRE,
1654 /** AUX request not supported */
1655 AUX_RET_ERROR_INVALID_OPERATION,
1656 /** AUX process not available */
1657 AUX_RET_ERROR_PROTOCOL_ERROR,
1658 };
1659
1660 /**
1661 * enum aux_channel_type - DP AUX channel type listing.
1662 */
1663 enum aux_channel_type {
1664 /** AUX thru Legacy DP AUX */
1665 AUX_CHANNEL_LEGACY_DDC,
1666 /** AUX thru DPIA DP tunneling */
1667 AUX_CHANNEL_DPIA
1668 };
1669
1670 /**
1671 * struct aux_transaction_parameters - DP AUX request transaction data
1672 */
1673 struct aux_transaction_parameters {
1674 uint8_t is_i2c_over_aux; /**< 0=native AUX, 1=I2C-over-AUX */
1675 uint8_t action; /**< enum dp_aux_request_action */
1676 uint8_t length; /**< DP AUX request data length */
1677 uint8_t reserved; /**< For future use */
1678 uint32_t address; /**< DP AUX address */
1679 uint8_t data[16]; /**< DP AUX write data */
1680 };
1681
1682 /**
1683 * Data passed from driver to FW in a DMUB_CMD__DP_AUX_ACCESS command.
1684 */
1685 struct dmub_cmd_dp_aux_control_data {
1686 uint8_t instance; /**< AUX instance or DPIA instance */
1687 uint8_t manual_acq_rel_enable; /**< manual control for acquiring or releasing AUX channel */
1688 uint8_t sw_crc_enabled; /**< Use software CRC for tunneling packet instead of hardware CRC */
1689 uint8_t reserved0; /**< For future use */
1690 uint16_t timeout; /**< timeout time in us */
1691 uint16_t reserved1; /**< For future use */
1692 enum aux_channel_type type; /**< enum aux_channel_type */
1693 struct aux_transaction_parameters dpaux; /**< struct aux_transaction_parameters */
1694 };
1695
1696 /**
1697 * Definition of a DMUB_CMD__DP_AUX_ACCESS command.
1698 */
1699 struct dmub_rb_cmd_dp_aux_access {
1700 /**
1701 * Command header.
1702 */
1703 struct dmub_cmd_header header;
1704 /**
1705 * Data passed from driver to FW in a DMUB_CMD__DP_AUX_ACCESS command.
1706 */
1707 struct dmub_cmd_dp_aux_control_data aux_control;
1708 };
1709
1710 /**
1711 * Definition of a DMUB_CMD__OUTBOX1_ENABLE command.
1712 */
1713 struct dmub_rb_cmd_outbox1_enable {
1714 /**
1715 * Command header.
1716 */
1717 struct dmub_cmd_header header;
1718 /**
1719 * enable: 0x0 -> disable outbox1 notification (default value)
1720 * 0x1 -> enable outbox1 notification
1721 */
1722 uint32_t enable;
1723 };
1724
1725 /* DP AUX Reply command - OutBox Cmd */
1726 /**
1727 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command.
1728 */
1729 struct aux_reply_data {
1730 /**
1731 * Aux cmd
1732 */
1733 uint8_t command;
1734 /**
1735 * Aux reply data length (max: 16 bytes)
1736 */
1737 uint8_t length;
1738 /**
1739 * Alignment only
1740 */
1741 uint8_t pad[2];
1742 /**
1743 * Aux reply data
1744 */
1745 uint8_t data[16];
1746 };
1747
1748 /**
1749 * Control Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command.
1750 */
1751 struct aux_reply_control_data {
1752 /**
1753 * Reserved for future use
1754 */
1755 uint32_t handle;
1756 /**
1757 * Aux Instance
1758 */
1759 uint8_t instance;
1760 /**
1761 * Aux transaction result: definition in enum aux_return_code_type
1762 */
1763 uint8_t result;
1764 /**
1765 * Alignment only
1766 */
1767 uint16_t pad;
1768 };
1769
1770 /**
1771 * Definition of a DMUB_OUT_CMD__DP_AUX_REPLY command.
1772 */
1773 struct dmub_rb_cmd_dp_aux_reply {
1774 /**
1775 * Command header.
1776 */
1777 struct dmub_cmd_header header;
1778 /**
1779 * Control Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command.
1780 */
1781 struct aux_reply_control_data control;
1782 /**
1783 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command.
1784 */
1785 struct aux_reply_data reply_data;
1786 };
1787
1788 /* DP HPD Notify command - OutBox Cmd */
1789 /**
1790 * DP HPD Type
1791 */
1792 enum dp_hpd_type {
1793 /**
1794 * Normal DP HPD
1795 */
1796 DP_HPD = 0,
1797 /**
1798 * DP HPD short pulse
1799 */
1800 DP_IRQ
1801 };
1802
1803 /**
1804 * DP HPD Status
1805 */
1806 enum dp_hpd_status {
1807 /**
1808 * DP_HPD status low
1809 */
1810 DP_HPD_UNPLUG = 0,
1811 /**
1812 * DP_HPD status high
1813 */
1814 DP_HPD_PLUG
1815 };
1816
1817 /**
1818 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_HPD_NOTIFY command.
1819 */
1820 struct dp_hpd_data {
1821 /**
1822 * DP HPD instance
1823 */
1824 uint8_t instance;
1825 /**
1826 * HPD type
1827 */
1828 uint8_t hpd_type;
1829 /**
1830 * HPD status: only for type: DP_HPD to indicate status
1831 */
1832 uint8_t hpd_status;
1833 /**
1834 * Alignment only
1835 */
1836 uint8_t pad;
1837 };
1838
1839 /**
1840 * Definition of a DMUB_OUT_CMD__DP_HPD_NOTIFY command.
1841 */
1842 struct dmub_rb_cmd_dp_hpd_notify {
1843 /**
1844 * Command header.
1845 */
1846 struct dmub_cmd_header header;
1847 /**
1848 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_HPD_NOTIFY command.
1849 */
1850 struct dp_hpd_data hpd_data;
1851 };
1852
1853 /**
1854 * Definition of a SET_CONFIG reply from DPOA.
1855 */
1856 enum set_config_status {
1857 SET_CONFIG_PENDING = 0,
1858 SET_CONFIG_ACK_RECEIVED,
1859 SET_CONFIG_RX_TIMEOUT,
1860 SET_CONFIG_UNKNOWN_ERROR,
1861 };
1862
1863 /**
1864 * Definition of a set_config reply
1865 */
1866 struct set_config_reply_control_data {
1867 uint8_t instance; /* DPIA Instance */
1868 uint8_t status; /* Set Config reply */
1869 uint16_t pad; /* Alignment */
1870 };
1871
1872 /**
1873 * Definition of a DMUB_OUT_CMD__SET_CONFIG_REPLY command.
1874 */
1875 struct dmub_rb_cmd_dp_set_config_reply {
1876 struct dmub_cmd_header header;
1877 struct set_config_reply_control_data set_config_reply_control;
1878 };
1879
1880 /**
1881 * Definition of a DPIA notification header
1882 */
1883 struct dpia_notification_header {
1884 uint8_t instance; /**< DPIA Instance */
1885 uint8_t reserved[3];
1886 enum dmub_cmd_dpia_notification_type type; /**< DPIA notification type */
1887 };
1888
1889 /**
1890 * Definition of the common data struct of DPIA notification
1891 */
1892 struct dpia_notification_common {
1893 uint8_t cmd_buffer[DMUB_RB_CMD_SIZE - sizeof(struct dmub_cmd_header)
1894 - sizeof(struct dpia_notification_header)];
1895 };
1896
1897 /**
1898 * Definition of a DPIA notification data
1899 */
1900 struct dpia_bw_allocation_notify_data {
1901 union {
1902 struct {
1903 uint16_t cm_bw_alloc_support: 1; /**< USB4 CM BW Allocation mode support */
1904 uint16_t bw_request_failed: 1; /**< BW_Request_Failed */
1905 uint16_t bw_request_succeeded: 1; /**< BW_Request_Succeeded */
1906 uint16_t est_bw_changed: 1; /**< Estimated_BW changed */
1907 uint16_t bw_alloc_cap_changed: 1; /**< BW_Allocation_Capabiity_Changed */
1908 uint16_t reserved: 11; /**< Reserved */
1909 } bits;
1910
1911 uint16_t flags;
1912 };
1913
1914 uint8_t cm_id; /**< CM ID */
1915 uint8_t group_id; /**< Group ID */
1916 uint8_t granularity; /**< BW Allocation Granularity */
1917 uint8_t estimated_bw; /**< Estimated_BW */
1918 uint8_t allocated_bw; /**< Allocated_BW */
1919 uint8_t reserved;
1920 };
1921
1922 /**
1923 * union dpia_notify_data_type - DPIA Notification in Outbox command
1924 */
1925 union dpia_notification_data {
1926 /**
1927 * DPIA Notification for common data struct
1928 */
1929 struct dpia_notification_common common_data;
1930
1931 /**
1932 * DPIA Notification for DP BW Allocation support
1933 */
1934 struct dpia_bw_allocation_notify_data dpia_bw_alloc;
1935 };
1936
1937 /**
1938 * Definition of a DPIA notification payload
1939 */
1940 struct dpia_notification_payload {
1941 struct dpia_notification_header header;
1942 union dpia_notification_data data; /**< DPIA notification payload data */
1943 };
1944
1945 /**
1946 * Definition of a DMUB_OUT_CMD__DPIA_NOTIFICATION command.
1947 */
1948 struct dmub_rb_cmd_dpia_notification {
1949 struct dmub_cmd_header header; /**< DPIA notification header */
1950 struct dpia_notification_payload payload; /**< DPIA notification payload */
1951 };
1952
1953 /**
1954 * Data passed from driver to FW in a DMUB_CMD__QUERY_HPD_STATE command.
1955 */
1956 struct dmub_cmd_hpd_state_query_data {
1957 uint8_t instance; /**< HPD instance or DPIA instance */
1958 uint8_t result; /**< For returning HPD state */
1959 uint16_t pad; /** < Alignment */
1960 enum aux_channel_type ch_type; /**< enum aux_channel_type */
1961 enum aux_return_code_type status; /**< for returning the status of command */
1962 };
1963
1964 /**
1965 * Definition of a DMUB_CMD__QUERY_HPD_STATE command.
1966 */
1967 struct dmub_rb_cmd_query_hpd_state {
1968 /**
1969 * Command header.
1970 */
1971 struct dmub_cmd_header header;
1972 /**
1973 * Data passed from driver to FW in a DMUB_CMD__QUERY_HPD_STATE command.
1974 */
1975 struct dmub_cmd_hpd_state_query_data data;
1976 };
1977
1978 /*
1979 * Command IDs should be treated as stable ABI.
1980 * Do not reuse or modify IDs.
1981 */
1982
1983 /**
1984 * PSR command sub-types.
1985 */
1986 enum dmub_cmd_psr_type {
1987 /**
1988 * Set PSR version support.
1989 */
1990 DMUB_CMD__PSR_SET_VERSION = 0,
1991 /**
1992 * Copy driver-calculated parameters to PSR state.
1993 */
1994 DMUB_CMD__PSR_COPY_SETTINGS = 1,
1995 /**
1996 * Enable PSR.
1997 */
1998 DMUB_CMD__PSR_ENABLE = 2,
1999
2000 /**
2001 * Disable PSR.
2002 */
2003 DMUB_CMD__PSR_DISABLE = 3,
2004
2005 /**
2006 * Set PSR level.
2007 * PSR level is a 16-bit value dicated by driver that
2008 * will enable/disable different functionality.
2009 */
2010 DMUB_CMD__PSR_SET_LEVEL = 4,
2011
2012 /**
2013 * Forces PSR enabled until an explicit PSR disable call.
2014 */
2015 DMUB_CMD__PSR_FORCE_STATIC = 5,
2016 /**
2017 * Set vtotal in psr active for FreeSync PSR.
2018 */
2019 DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE = 6,
2020 /**
2021 * Set PSR power option
2022 */
2023 DMUB_CMD__SET_PSR_POWER_OPT = 7,
2024 };
2025
2026 enum dmub_cmd_fams_type {
2027 DMUB_CMD__FAMS_SETUP_FW_CTRL = 0,
2028 DMUB_CMD__FAMS_DRR_UPDATE = 1,
2029 DMUB_CMD__HANDLE_SUBVP_CMD = 2, // specifically for SubVP cmd
2030 /**
2031 * For SubVP set manual trigger in FW because it
2032 * triggers DRR_UPDATE_PENDING which SubVP relies
2033 * on (for any SubVP cases that use a DRR display)
2034 */
2035 DMUB_CMD__FAMS_SET_MANUAL_TRIGGER = 3,
2036 };
2037
2038 /**
2039 * PSR versions.
2040 */
2041 enum psr_version {
2042 /**
2043 * PSR version 1.
2044 */
2045 PSR_VERSION_1 = 0,
2046 /**
2047 * Freesync PSR SU.
2048 */
2049 PSR_VERSION_SU_1 = 1,
2050 /**
2051 * PSR not supported.
2052 */
2053 PSR_VERSION_UNSUPPORTED = 0xFFFFFFFF,
2054 };
2055
2056 /**
2057 * enum dmub_cmd_mall_type - MALL commands
2058 */
2059 enum dmub_cmd_mall_type {
2060 /**
2061 * Allows display refresh from MALL.
2062 */
2063 DMUB_CMD__MALL_ACTION_ALLOW = 0,
2064 /**
2065 * Disallows display refresh from MALL.
2066 */
2067 DMUB_CMD__MALL_ACTION_DISALLOW = 1,
2068 /**
2069 * Cursor copy for MALL.
2070 */
2071 DMUB_CMD__MALL_ACTION_COPY_CURSOR = 2,
2072 /**
2073 * Controls DF requests.
2074 */
2075 DMUB_CMD__MALL_ACTION_NO_DF_REQ = 3,
2076 };
2077
2078 /**
2079 * PHY Link rate for DP.
2080 */
2081 enum phy_link_rate {
2082 /**
2083 * not supported.
2084 */
2085 PHY_RATE_UNKNOWN = 0,
2086 /**
2087 * Rate_1 (RBR) - 1.62 Gbps/Lane
2088 */
2089 PHY_RATE_162 = 1,
2090 /**
2091 * Rate_2 - 2.16 Gbps/Lane
2092 */
2093 PHY_RATE_216 = 2,
2094 /**
2095 * Rate_3 - 2.43 Gbps/Lane
2096 */
2097 PHY_RATE_243 = 3,
2098 /**
2099 * Rate_4 (HBR) - 2.70 Gbps/Lane
2100 */
2101 PHY_RATE_270 = 4,
2102 /**
2103 * Rate_5 (RBR2)- 3.24 Gbps/Lane
2104 */
2105 PHY_RATE_324 = 5,
2106 /**
2107 * Rate_6 - 4.32 Gbps/Lane
2108 */
2109 PHY_RATE_432 = 6,
2110 /**
2111 * Rate_7 (HBR2)- 5.40 Gbps/Lane
2112 */
2113 PHY_RATE_540 = 7,
2114 /**
2115 * Rate_8 (HBR3)- 8.10 Gbps/Lane
2116 */
2117 PHY_RATE_810 = 8,
2118 /**
2119 * UHBR10 - 10.0 Gbps/Lane
2120 */
2121 PHY_RATE_1000 = 9,
2122 /**
2123 * UHBR13.5 - 13.5 Gbps/Lane
2124 */
2125 PHY_RATE_1350 = 10,
2126 /**
2127 * UHBR10 - 20.0 Gbps/Lane
2128 */
2129 PHY_RATE_2000 = 11,
2130 };
2131
2132 /**
2133 * enum dmub_phy_fsm_state - PHY FSM states.
2134 * PHY FSM state to transit to during PSR enable/disable.
2135 */
2136 enum dmub_phy_fsm_state {
2137 DMUB_PHY_FSM_POWER_UP_DEFAULT = 0,
2138 DMUB_PHY_FSM_RESET,
2139 DMUB_PHY_FSM_RESET_RELEASED,
2140 DMUB_PHY_FSM_SRAM_LOAD_DONE,
2141 DMUB_PHY_FSM_INITIALIZED,
2142 DMUB_PHY_FSM_CALIBRATED,
2143 DMUB_PHY_FSM_CALIBRATED_LP,
2144 DMUB_PHY_FSM_CALIBRATED_PG,
2145 DMUB_PHY_FSM_POWER_DOWN,
2146 DMUB_PHY_FSM_PLL_EN,
2147 DMUB_PHY_FSM_TX_EN,
2148 DMUB_PHY_FSM_FAST_LP,
2149 DMUB_PHY_FSM_P2_PLL_OFF_CPM,
2150 DMUB_PHY_FSM_P2_PLL_OFF_PG,
2151 DMUB_PHY_FSM_P2_PLL_OFF,
2152 DMUB_PHY_FSM_P2_PLL_ON,
2153 };
2154
2155 /**
2156 * Data passed from driver to FW in a DMUB_CMD__PSR_COPY_SETTINGS command.
2157 */
2158 struct dmub_cmd_psr_copy_settings_data {
2159 /**
2160 * Flags that can be set by driver to change some PSR behaviour.
2161 */
2162 union dmub_psr_debug_flags debug;
2163 /**
2164 * 16-bit value dicated by driver that will enable/disable different functionality.
2165 */
2166 uint16_t psr_level;
2167 /**
2168 * DPP HW instance.
2169 */
2170 uint8_t dpp_inst;
2171 /**
2172 * MPCC HW instance.
2173 * Not used in dmub fw,
2174 * dmub fw will get active opp by reading odm registers.
2175 */
2176 uint8_t mpcc_inst;
2177 /**
2178 * OPP HW instance.
2179 * Not used in dmub fw,
2180 * dmub fw will get active opp by reading odm registers.
2181 */
2182 uint8_t opp_inst;
2183 /**
2184 * OTG HW instance.
2185 */
2186 uint8_t otg_inst;
2187 /**
2188 * DIG FE HW instance.
2189 */
2190 uint8_t digfe_inst;
2191 /**
2192 * DIG BE HW instance.
2193 */
2194 uint8_t digbe_inst;
2195 /**
2196 * DP PHY HW instance.
2197 */
2198 uint8_t dpphy_inst;
2199 /**
2200 * AUX HW instance.
2201 */
2202 uint8_t aux_inst;
2203 /**
2204 * Determines if SMU optimzations are enabled/disabled.
2205 */
2206 uint8_t smu_optimizations_en;
2207 /**
2208 * Unused.
2209 * TODO: Remove.
2210 */
2211 uint8_t frame_delay;
2212 /**
2213 * If RFB setup time is greater than the total VBLANK time,
2214 * it is not possible for the sink to capture the video frame
2215 * in the same frame the SDP is sent. In this case,
2216 * the frame capture indication bit should be set and an extra
2217 * static frame should be transmitted to the sink.
2218 */
2219 uint8_t frame_cap_ind;
2220 /**
2221 * Granularity of Y offset supported by sink.
2222 */
2223 uint8_t su_y_granularity;
2224 /**
2225 * Indicates whether sink should start capturing
2226 * immediately following active scan line,
2227 * or starting with the 2nd active scan line.
2228 */
2229 uint8_t line_capture_indication;
2230 /**
2231 * Multi-display optimizations are implemented on certain ASICs.
2232 */
2233 uint8_t multi_disp_optimizations_en;
2234 /**
2235 * The last possible line SDP may be transmitted without violating
2236 * the RFB setup time or entering the active video frame.
2237 */
2238 uint16_t init_sdp_deadline;
2239 /**
2240 * @ rate_control_caps : Indicate FreeSync PSR Sink Capabilities
2241 */
2242 uint8_t rate_control_caps ;
2243 /*
2244 * Force PSRSU always doing full frame update
2245 */
2246 uint8_t force_ffu_mode;
2247 /**
2248 * Length of each horizontal line in us.
2249 */
2250 uint32_t line_time_in_us;
2251 /**
2252 * FEC enable status in driver
2253 */
2254 uint8_t fec_enable_status;
2255 /**
2256 * FEC re-enable delay when PSR exit.
2257 * unit is 100us, range form 0~255(0xFF).
2258 */
2259 uint8_t fec_enable_delay_in100us;
2260 /**
2261 * PSR control version.
2262 */
2263 uint8_t cmd_version;
2264 /**
2265 * Panel Instance.
2266 * Panel instance to identify which psr_state to use
2267 * Currently the support is only for 0 or 1
2268 */
2269 uint8_t panel_inst;
2270 /*
2271 * DSC enable status in driver
2272 */
2273 uint8_t dsc_enable_status;
2274 /*
2275 * Use FSM state for PSR power up/down
2276 */
2277 uint8_t use_phy_fsm;
2278 /**
2279 * frame delay for frame re-lock
2280 */
2281 uint8_t relock_delay_frame_cnt;
2282 /**
2283 * Explicit padding to 2 byte boundary.
2284 */
2285 uint8_t pad3;
2286 /**
2287 * DSC Slice height.
2288 */
2289 uint16_t dsc_slice_height;
2290 /**
2291 * Explicit padding to 4 byte boundary.
2292 */
2293 uint16_t pad;
2294 };
2295
2296 /**
2297 * Definition of a DMUB_CMD__PSR_COPY_SETTINGS command.
2298 */
2299 struct dmub_rb_cmd_psr_copy_settings {
2300 /**
2301 * Command header.
2302 */
2303 struct dmub_cmd_header header;
2304 /**
2305 * Data passed from driver to FW in a DMUB_CMD__PSR_COPY_SETTINGS command.
2306 */
2307 struct dmub_cmd_psr_copy_settings_data psr_copy_settings_data;
2308 };
2309
2310 /**
2311 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_LEVEL command.
2312 */
2313 struct dmub_cmd_psr_set_level_data {
2314 /**
2315 * 16-bit value dicated by driver that will enable/disable different functionality.
2316 */
2317 uint16_t psr_level;
2318 /**
2319 * PSR control version.
2320 */
2321 uint8_t cmd_version;
2322 /**
2323 * Panel Instance.
2324 * Panel instance to identify which psr_state to use
2325 * Currently the support is only for 0 or 1
2326 */
2327 uint8_t panel_inst;
2328 };
2329
2330 /**
2331 * Definition of a DMUB_CMD__PSR_SET_LEVEL command.
2332 */
2333 struct dmub_rb_cmd_psr_set_level {
2334 /**
2335 * Command header.
2336 */
2337 struct dmub_cmd_header header;
2338 /**
2339 * Definition of a DMUB_CMD__PSR_SET_LEVEL command.
2340 */
2341 struct dmub_cmd_psr_set_level_data psr_set_level_data;
2342 };
2343
2344 struct dmub_rb_cmd_psr_enable_data {
2345 /**
2346 * PSR control version.
2347 */
2348 uint8_t cmd_version;
2349 /**
2350 * Panel Instance.
2351 * Panel instance to identify which psr_state to use
2352 * Currently the support is only for 0 or 1
2353 */
2354 uint8_t panel_inst;
2355 /**
2356 * Phy state to enter.
2357 * Values to use are defined in dmub_phy_fsm_state
2358 */
2359 uint8_t phy_fsm_state;
2360 /**
2361 * Phy rate for DP - RBR/HBR/HBR2/HBR3.
2362 * Set this using enum phy_link_rate.
2363 * This does not support HDMI/DP2 for now.
2364 */
2365 uint8_t phy_rate;
2366 };
2367
2368 /**
2369 * Definition of a DMUB_CMD__PSR_ENABLE command.
2370 * PSR enable/disable is controlled using the sub_type.
2371 */
2372 struct dmub_rb_cmd_psr_enable {
2373 /**
2374 * Command header.
2375 */
2376 struct dmub_cmd_header header;
2377
2378 struct dmub_rb_cmd_psr_enable_data data;
2379 };
2380
2381 /**
2382 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_VERSION command.
2383 */
2384 struct dmub_cmd_psr_set_version_data {
2385 /**
2386 * PSR version that FW should implement.
2387 */
2388 enum psr_version version;
2389 /**
2390 * PSR control version.
2391 */
2392 uint8_t cmd_version;
2393 /**
2394 * Panel Instance.
2395 * Panel instance to identify which psr_state to use
2396 * Currently the support is only for 0 or 1
2397 */
2398 uint8_t panel_inst;
2399 /**
2400 * Explicit padding to 4 byte boundary.
2401 */
2402 uint8_t pad[2];
2403 };
2404
2405 /**
2406 * Definition of a DMUB_CMD__PSR_SET_VERSION command.
2407 */
2408 struct dmub_rb_cmd_psr_set_version {
2409 /**
2410 * Command header.
2411 */
2412 struct dmub_cmd_header header;
2413 /**
2414 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_VERSION command.
2415 */
2416 struct dmub_cmd_psr_set_version_data psr_set_version_data;
2417 };
2418
2419 struct dmub_cmd_psr_force_static_data {
2420 /**
2421 * PSR control version.
2422 */
2423 uint8_t cmd_version;
2424 /**
2425 * Panel Instance.
2426 * Panel instance to identify which psr_state to use
2427 * Currently the support is only for 0 or 1
2428 */
2429 uint8_t panel_inst;
2430 /**
2431 * Explicit padding to 4 byte boundary.
2432 */
2433 uint8_t pad[2];
2434 };
2435
2436 /**
2437 * Definition of a DMUB_CMD__PSR_FORCE_STATIC command.
2438 */
2439 struct dmub_rb_cmd_psr_force_static {
2440 /**
2441 * Command header.
2442 */
2443 struct dmub_cmd_header header;
2444 /**
2445 * Data passed from driver to FW in a DMUB_CMD__PSR_FORCE_STATIC command.
2446 */
2447 struct dmub_cmd_psr_force_static_data psr_force_static_data;
2448 };
2449
2450 /**
2451 * PSR SU debug flags.
2452 */
2453 union dmub_psr_su_debug_flags {
2454 /**
2455 * PSR SU debug flags.
2456 */
2457 struct {
2458 /**
2459 * Update dirty rect in SW only.
2460 */
2461 uint8_t update_dirty_rect_only : 1;
2462 /**
2463 * Reset the cursor/plane state before processing the call.
2464 */
2465 uint8_t reset_state : 1;
2466 } bitfields;
2467
2468 /**
2469 * Union for debug flags.
2470 */
2471 uint32_t u32All;
2472 };
2473
2474 /**
2475 * Data passed from driver to FW in a DMUB_CMD__UPDATE_DIRTY_RECT command.
2476 * This triggers a selective update for PSR SU.
2477 */
2478 struct dmub_cmd_update_dirty_rect_data {
2479 /**
2480 * Dirty rects from OS.
2481 */
2482 struct dmub_rect src_dirty_rects[DMUB_MAX_DIRTY_RECTS];
2483 /**
2484 * PSR SU debug flags.
2485 */
2486 union dmub_psr_su_debug_flags debug_flags;
2487 /**
2488 * OTG HW instance.
2489 */
2490 uint8_t pipe_idx;
2491 /**
2492 * Number of dirty rects.
2493 */
2494 uint8_t dirty_rect_count;
2495 /**
2496 * PSR control version.
2497 */
2498 uint8_t cmd_version;
2499 /**
2500 * Panel Instance.
2501 * Panel instance to identify which psr_state to use
2502 * Currently the support is only for 0 or 1
2503 */
2504 uint8_t panel_inst;
2505 };
2506
2507 /**
2508 * Definition of a DMUB_CMD__UPDATE_DIRTY_RECT command.
2509 */
2510 struct dmub_rb_cmd_update_dirty_rect {
2511 /**
2512 * Command header.
2513 */
2514 struct dmub_cmd_header header;
2515 /**
2516 * Data passed from driver to FW in a DMUB_CMD__UPDATE_DIRTY_RECT command.
2517 */
2518 struct dmub_cmd_update_dirty_rect_data update_dirty_rect_data;
2519 };
2520
2521 /**
2522 * Data passed from driver to FW in a DMUB_CMD__UPDATE_CURSOR_INFO command.
2523 */
2524 union dmub_reg_cursor_control_cfg {
2525 struct {
2526 uint32_t cur_enable: 1;
2527 uint32_t reser0: 3;
2528 uint32_t cur_2x_magnify: 1;
2529 uint32_t reser1: 3;
2530 uint32_t mode: 3;
2531 uint32_t reser2: 5;
2532 uint32_t pitch: 2;
2533 uint32_t reser3: 6;
2534 uint32_t line_per_chunk: 5;
2535 uint32_t reser4: 3;
2536 } bits;
2537 uint32_t raw;
2538 };
2539 struct dmub_cursor_position_cache_hubp {
2540 union dmub_reg_cursor_control_cfg cur_ctl;
2541 union dmub_reg_position_cfg {
2542 struct {
2543 uint32_t cur_x_pos: 16;
2544 uint32_t cur_y_pos: 16;
2545 } bits;
2546 uint32_t raw;
2547 } position;
2548 union dmub_reg_hot_spot_cfg {
2549 struct {
2550 uint32_t hot_x: 16;
2551 uint32_t hot_y: 16;
2552 } bits;
2553 uint32_t raw;
2554 } hot_spot;
2555 union dmub_reg_dst_offset_cfg {
2556 struct {
2557 uint32_t dst_x_offset: 13;
2558 uint32_t reserved: 19;
2559 } bits;
2560 uint32_t raw;
2561 } dst_offset;
2562 };
2563
2564 union dmub_reg_cur0_control_cfg {
2565 struct {
2566 uint32_t cur0_enable: 1;
2567 uint32_t expansion_mode: 1;
2568 uint32_t reser0: 1;
2569 uint32_t cur0_rom_en: 1;
2570 uint32_t mode: 3;
2571 uint32_t reserved: 25;
2572 } bits;
2573 uint32_t raw;
2574 };
2575 struct dmub_cursor_position_cache_dpp {
2576 union dmub_reg_cur0_control_cfg cur0_ctl;
2577 };
2578 struct dmub_cursor_position_cfg {
2579 struct dmub_cursor_position_cache_hubp pHubp;
2580 struct dmub_cursor_position_cache_dpp pDpp;
2581 uint8_t pipe_idx;
2582 /*
2583 * Padding is required. To be 4 Bytes Aligned.
2584 */
2585 uint8_t padding[3];
2586 };
2587
2588 struct dmub_cursor_attribute_cache_hubp {
2589 uint32_t SURFACE_ADDR_HIGH;
2590 uint32_t SURFACE_ADDR;
2591 union dmub_reg_cursor_control_cfg cur_ctl;
2592 union dmub_reg_cursor_size_cfg {
2593 struct {
2594 uint32_t width: 16;
2595 uint32_t height: 16;
2596 } bits;
2597 uint32_t raw;
2598 } size;
2599 union dmub_reg_cursor_settings_cfg {
2600 struct {
2601 uint32_t dst_y_offset: 8;
2602 uint32_t chunk_hdl_adjust: 2;
2603 uint32_t reserved: 22;
2604 } bits;
2605 uint32_t raw;
2606 } settings;
2607 };
2608 struct dmub_cursor_attribute_cache_dpp {
2609 union dmub_reg_cur0_control_cfg cur0_ctl;
2610 };
2611 struct dmub_cursor_attributes_cfg {
2612 struct dmub_cursor_attribute_cache_hubp aHubp;
2613 struct dmub_cursor_attribute_cache_dpp aDpp;
2614 };
2615
2616 struct dmub_cmd_update_cursor_payload0 {
2617 /**
2618 * Cursor dirty rects.
2619 */
2620 struct dmub_rect cursor_rect;
2621 /**
2622 * PSR SU debug flags.
2623 */
2624 union dmub_psr_su_debug_flags debug_flags;
2625 /**
2626 * Cursor enable/disable.
2627 */
2628 uint8_t enable;
2629 /**
2630 * OTG HW instance.
2631 */
2632 uint8_t pipe_idx;
2633 /**
2634 * PSR control version.
2635 */
2636 uint8_t cmd_version;
2637 /**
2638 * Panel Instance.
2639 * Panel instance to identify which psr_state to use
2640 * Currently the support is only for 0 or 1
2641 */
2642 uint8_t panel_inst;
2643 /**
2644 * Cursor Position Register.
2645 * Registers contains Hubp & Dpp modules
2646 */
2647 struct dmub_cursor_position_cfg position_cfg;
2648 };
2649
2650 struct dmub_cmd_update_cursor_payload1 {
2651 struct dmub_cursor_attributes_cfg attribute_cfg;
2652 };
2653
2654 union dmub_cmd_update_cursor_info_data {
2655 struct dmub_cmd_update_cursor_payload0 payload0;
2656 struct dmub_cmd_update_cursor_payload1 payload1;
2657 };
2658 /**
2659 * Definition of a DMUB_CMD__UPDATE_CURSOR_INFO command.
2660 */
2661 struct dmub_rb_cmd_update_cursor_info {
2662 /**
2663 * Command header.
2664 */
2665 struct dmub_cmd_header header;
2666 /**
2667 * Data passed from driver to FW in a DMUB_CMD__UPDATE_CURSOR_INFO command.
2668 */
2669 union dmub_cmd_update_cursor_info_data update_cursor_info_data;
2670 };
2671
2672 /**
2673 * Data passed from driver to FW in a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command.
2674 */
2675 struct dmub_cmd_psr_set_vtotal_data {
2676 /**
2677 * 16-bit value dicated by driver that indicates the vtotal in PSR active requirement when screen idle..
2678 */
2679 uint16_t psr_vtotal_idle;
2680 /**
2681 * PSR control version.
2682 */
2683 uint8_t cmd_version;
2684 /**
2685 * Panel Instance.
2686 * Panel instance to identify which psr_state to use
2687 * Currently the support is only for 0 or 1
2688 */
2689 uint8_t panel_inst;
2690 /*
2691 * 16-bit value dicated by driver that indicates the vtotal in PSR active requirement when doing SU/FFU.
2692 */
2693 uint16_t psr_vtotal_su;
2694 /**
2695 * Explicit padding to 4 byte boundary.
2696 */
2697 uint8_t pad2[2];
2698 };
2699
2700 /**
2701 * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command.
2702 */
2703 struct dmub_rb_cmd_psr_set_vtotal {
2704 /**
2705 * Command header.
2706 */
2707 struct dmub_cmd_header header;
2708 /**
2709 * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command.
2710 */
2711 struct dmub_cmd_psr_set_vtotal_data psr_set_vtotal_data;
2712 };
2713
2714 /**
2715 * Data passed from driver to FW in a DMUB_CMD__SET_PSR_POWER_OPT command.
2716 */
2717 struct dmub_cmd_psr_set_power_opt_data {
2718 /**
2719 * PSR control version.
2720 */
2721 uint8_t cmd_version;
2722 /**
2723 * Panel Instance.
2724 * Panel instance to identify which psr_state to use
2725 * Currently the support is only for 0 or 1
2726 */
2727 uint8_t panel_inst;
2728 /**
2729 * Explicit padding to 4 byte boundary.
2730 */
2731 uint8_t pad[2];
2732 /**
2733 * PSR power option
2734 */
2735 uint32_t power_opt;
2736 };
2737
2738 #define REPLAY_RESIDENCY_MODE_SHIFT (0)
2739 #define REPLAY_RESIDENCY_ENABLE_SHIFT (1)
2740
2741 #define REPLAY_RESIDENCY_MODE_MASK (0x1 << REPLAY_RESIDENCY_MODE_SHIFT)
2742 # define REPLAY_RESIDENCY_MODE_PHY (0x0 << REPLAY_RESIDENCY_MODE_SHIFT)
2743 # define REPLAY_RESIDENCY_MODE_ALPM (0x1 << REPLAY_RESIDENCY_MODE_SHIFT)
2744
2745 #define REPLAY_RESIDENCY_ENABLE_MASK (0x1 << REPLAY_RESIDENCY_ENABLE_SHIFT)
2746 # define REPLAY_RESIDENCY_DISABLE (0x0 << REPLAY_RESIDENCY_ENABLE_SHIFT)
2747 # define REPLAY_RESIDENCY_ENABLE (0x1 << REPLAY_RESIDENCY_ENABLE_SHIFT)
2748
2749 enum replay_state {
2750 REPLAY_STATE_0 = 0x0,
2751 REPLAY_STATE_1 = 0x10,
2752 REPLAY_STATE_1A = 0x11,
2753 REPLAY_STATE_2 = 0x20,
2754 REPLAY_STATE_3 = 0x30,
2755 REPLAY_STATE_3INIT = 0x31,
2756 REPLAY_STATE_4 = 0x40,
2757 REPLAY_STATE_4A = 0x41,
2758 REPLAY_STATE_4B = 0x42,
2759 REPLAY_STATE_4C = 0x43,
2760 REPLAY_STATE_4D = 0x44,
2761 REPLAY_STATE_4B_LOCKED = 0x4A,
2762 REPLAY_STATE_4C_UNLOCKED = 0x4B,
2763 REPLAY_STATE_5 = 0x50,
2764 REPLAY_STATE_5A = 0x51,
2765 REPLAY_STATE_5B = 0x52,
2766 REPLAY_STATE_5A_LOCKED = 0x5A,
2767 REPLAY_STATE_5B_UNLOCKED = 0x5B,
2768 REPLAY_STATE_6 = 0x60,
2769 REPLAY_STATE_6A = 0x61,
2770 REPLAY_STATE_6B = 0x62,
2771 REPLAY_STATE_INVALID = 0xFF,
2772 };
2773
2774 /**
2775 * Replay command sub-types.
2776 */
2777 enum dmub_cmd_replay_type {
2778 /**
2779 * Copy driver-calculated parameters to REPLAY state.
2780 */
2781 DMUB_CMD__REPLAY_COPY_SETTINGS = 0,
2782 /**
2783 * Enable REPLAY.
2784 */
2785 DMUB_CMD__REPLAY_ENABLE = 1,
2786 /**
2787 * Set Replay power option.
2788 */
2789 DMUB_CMD__SET_REPLAY_POWER_OPT = 2,
2790 /**
2791 * Set coasting vtotal.
2792 */
2793 DMUB_CMD__REPLAY_SET_COASTING_VTOTAL = 3,
2794 };
2795
2796 /**
2797 * Data passed from driver to FW in a DMUB_CMD__REPLAY_COPY_SETTINGS command.
2798 */
2799 struct dmub_cmd_replay_copy_settings_data {
2800 /**
2801 * Flags that can be set by driver to change some replay behaviour.
2802 */
2803 union replay_debug_flags debug;
2804
2805 /**
2806 * @flags: Flags used to determine feature functionality.
2807 */
2808 union replay_hw_flags flags;
2809
2810 /**
2811 * DPP HW instance.
2812 */
2813 uint8_t dpp_inst;
2814 /**
2815 * OTG HW instance.
2816 */
2817 uint8_t otg_inst;
2818 /**
2819 * DIG FE HW instance.
2820 */
2821 uint8_t digfe_inst;
2822 /**
2823 * DIG BE HW instance.
2824 */
2825 uint8_t digbe_inst;
2826 /**
2827 * AUX HW instance.
2828 */
2829 uint8_t aux_inst;
2830 /**
2831 * Panel Instance.
2832 * Panel isntance to identify which psr_state to use
2833 * Currently the support is only for 0 or 1
2834 */
2835 uint8_t panel_inst;
2836 /**
2837 * @pixel_deviation_per_line: Indicate the maximum pixel deviation per line compare
2838 * to Source timing when Sink maintains coasting vtotal during the Replay normal sleep mode
2839 */
2840 uint8_t pixel_deviation_per_line;
2841 /**
2842 * @max_deviation_line: The max number of deviation line that can keep the timing
2843 * synchronized between the Source and Sink during Replay normal sleep mode.
2844 */
2845 uint8_t max_deviation_line;
2846 /**
2847 * Length of each horizontal line in ns.
2848 */
2849 uint32_t line_time_in_ns;
2850 /**
2851 * PHY instance.
2852 */
2853 uint8_t dpphy_inst;
2854 /**
2855 * Determines if SMU optimzations are enabled/disabled.
2856 */
2857 uint8_t smu_optimizations_en;
2858 /**
2859 * Determines if timing sync are enabled/disabled.
2860 */
2861 uint8_t replay_timing_sync_supported;
2862 /*
2863 * Use FSM state for Replay power up/down
2864 */
2865 uint8_t use_phy_fsm;
2866 };
2867
2868 /**
2869 * Definition of a DMUB_CMD__REPLAY_COPY_SETTINGS command.
2870 */
2871 struct dmub_rb_cmd_replay_copy_settings {
2872 /**
2873 * Command header.
2874 */
2875 struct dmub_cmd_header header;
2876 /**
2877 * Data passed from driver to FW in a DMUB_CMD__REPLAY_COPY_SETTINGS command.
2878 */
2879 struct dmub_cmd_replay_copy_settings_data replay_copy_settings_data;
2880 };
2881
2882 /**
2883 * Replay disable / enable state for dmub_rb_cmd_replay_enable_data.enable
2884 */
2885 enum replay_enable {
2886 /**
2887 * Disable REPLAY.
2888 */
2889 REPLAY_DISABLE = 0,
2890 /**
2891 * Enable REPLAY.
2892 */
2893 REPLAY_ENABLE = 1,
2894 };
2895
2896 /**
2897 * Data passed from driver to FW in a DMUB_CMD__REPLAY_ENABLE command.
2898 */
2899 struct dmub_rb_cmd_replay_enable_data {
2900 /**
2901 * Replay enable or disable.
2902 */
2903 uint8_t enable;
2904 /**
2905 * Panel Instance.
2906 * Panel isntance to identify which replay_state to use
2907 * Currently the support is only for 0 or 1
2908 */
2909 uint8_t panel_inst;
2910 /**
2911 * Phy state to enter.
2912 * Values to use are defined in dmub_phy_fsm_state
2913 */
2914 uint8_t phy_fsm_state;
2915 /**
2916 * Phy rate for DP - RBR/HBR/HBR2/HBR3.
2917 * Set this using enum phy_link_rate.
2918 * This does not support HDMI/DP2 for now.
2919 */
2920 uint8_t phy_rate;
2921 };
2922
2923 /**
2924 * Definition of a DMUB_CMD__REPLAY_ENABLE command.
2925 * Replay enable/disable is controlled using action in data.
2926 */
2927 struct dmub_rb_cmd_replay_enable {
2928 /**
2929 * Command header.
2930 */
2931 struct dmub_cmd_header header;
2932
2933 struct dmub_rb_cmd_replay_enable_data data;
2934 };
2935
2936 /**
2937 * Data passed from driver to FW in a DMUB_CMD__SET_REPLAY_POWER_OPT command.
2938 */
2939 struct dmub_cmd_replay_set_power_opt_data {
2940 /**
2941 * Panel Instance.
2942 * Panel isntance to identify which replay_state to use
2943 * Currently the support is only for 0 or 1
2944 */
2945 uint8_t panel_inst;
2946 /**
2947 * Explicit padding to 4 byte boundary.
2948 */
2949 uint8_t pad[3];
2950 /**
2951 * REPLAY power option
2952 */
2953 uint32_t power_opt;
2954 };
2955
2956 /**
2957 * Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command.
2958 */
2959 struct dmub_rb_cmd_replay_set_power_opt {
2960 /**
2961 * Command header.
2962 */
2963 struct dmub_cmd_header header;
2964 /**
2965 * Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command.
2966 */
2967 struct dmub_cmd_replay_set_power_opt_data replay_set_power_opt_data;
2968 };
2969
2970 /**
2971 * Data passed from driver to FW in a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command.
2972 */
2973 struct dmub_cmd_replay_set_coasting_vtotal_data {
2974 /**
2975 * 16-bit value dicated by driver that indicates the coasting vtotal.
2976 */
2977 uint16_t coasting_vtotal;
2978 /**
2979 * REPLAY control version.
2980 */
2981 uint8_t cmd_version;
2982 /**
2983 * Panel Instance.
2984 * Panel isntance to identify which replay_state to use
2985 * Currently the support is only for 0 or 1
2986 */
2987 uint8_t panel_inst;
2988 };
2989
2990 /**
2991 * Definition of a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command.
2992 */
2993 struct dmub_rb_cmd_replay_set_coasting_vtotal {
2994 /**
2995 * Command header.
2996 */
2997 struct dmub_cmd_header header;
2998 /**
2999 * Definition of a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command.
3000 */
3001 struct dmub_cmd_replay_set_coasting_vtotal_data replay_set_coasting_vtotal_data;
3002 };
3003
3004 /**
3005 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command.
3006 */
3007 struct dmub_rb_cmd_psr_set_power_opt {
3008 /**
3009 * Command header.
3010 */
3011 struct dmub_cmd_header header;
3012 /**
3013 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command.
3014 */
3015 struct dmub_cmd_psr_set_power_opt_data psr_set_power_opt_data;
3016 };
3017
3018 /**
3019 * Set of HW components that can be locked.
3020 *
3021 * Note: If updating with more HW components, fields
3022 * in dmub_inbox0_cmd_lock_hw must be updated to match.
3023 */
3024 union dmub_hw_lock_flags {
3025 /**
3026 * Set of HW components that can be locked.
3027 */
3028 struct {
3029 /**
3030 * Lock/unlock OTG master update lock.
3031 */
3032 uint8_t lock_pipe : 1;
3033 /**
3034 * Lock/unlock cursor.
3035 */
3036 uint8_t lock_cursor : 1;
3037 /**
3038 * Lock/unlock global update lock.
3039 */
3040 uint8_t lock_dig : 1;
3041 /**
3042 * Triple buffer lock requires additional hw programming to usual OTG master lock.
3043 */
3044 uint8_t triple_buffer_lock : 1;
3045 } bits;
3046
3047 /**
3048 * Union for HW Lock flags.
3049 */
3050 uint8_t u8All;
3051 };
3052
3053 /**
3054 * Instances of HW to be locked.
3055 *
3056 * Note: If updating with more HW components, fields
3057 * in dmub_inbox0_cmd_lock_hw must be updated to match.
3058 */
3059 struct dmub_hw_lock_inst_flags {
3060 /**
3061 * OTG HW instance for OTG master update lock.
3062 */
3063 uint8_t otg_inst;
3064 /**
3065 * OPP instance for cursor lock.
3066 */
3067 uint8_t opp_inst;
3068 /**
3069 * OTG HW instance for global update lock.
3070 * TODO: Remove, and re-use otg_inst.
3071 */
3072 uint8_t dig_inst;
3073 /**
3074 * Explicit pad to 4 byte boundary.
3075 */
3076 uint8_t pad;
3077 };
3078
3079 /**
3080 * Clients that can acquire the HW Lock Manager.
3081 *
3082 * Note: If updating with more clients, fields in
3083 * dmub_inbox0_cmd_lock_hw must be updated to match.
3084 */
3085 enum hw_lock_client {
3086 /**
3087 * Driver is the client of HW Lock Manager.
3088 */
3089 HW_LOCK_CLIENT_DRIVER = 0,
3090 /**
3091 * PSR SU is the client of HW Lock Manager.
3092 */
3093 HW_LOCK_CLIENT_PSR_SU = 1,
3094 /**
3095 * Replay is the client of HW Lock Manager.
3096 */
3097 HW_LOCK_CLIENT_REPLAY = 4,
3098 /**
3099 * Invalid client.
3100 */
3101 HW_LOCK_CLIENT_INVALID = 0xFFFFFFFF,
3102 };
3103
3104 /**
3105 * Data passed to HW Lock Mgr in a DMUB_CMD__HW_LOCK command.
3106 */
3107 struct dmub_cmd_lock_hw_data {
3108 /**
3109 * Specifies the client accessing HW Lock Manager.
3110 */
3111 enum hw_lock_client client;
3112 /**
3113 * HW instances to be locked.
3114 */
3115 struct dmub_hw_lock_inst_flags inst_flags;
3116 /**
3117 * Which components to be locked.
3118 */
3119 union dmub_hw_lock_flags hw_locks;
3120 /**
3121 * Specifies lock/unlock.
3122 */
3123 uint8_t lock;
3124 /**
3125 * HW can be unlocked separately from releasing the HW Lock Mgr.
3126 * This flag is set if the client wishes to release the object.
3127 */
3128 uint8_t should_release;
3129 /**
3130 * Explicit padding to 4 byte boundary.
3131 */
3132 uint8_t pad;
3133 };
3134
3135 /**
3136 * Definition of a DMUB_CMD__HW_LOCK command.
3137 * Command is used by driver and FW.
3138 */
3139 struct dmub_rb_cmd_lock_hw {
3140 /**
3141 * Command header.
3142 */
3143 struct dmub_cmd_header header;
3144 /**
3145 * Data passed to HW Lock Mgr in a DMUB_CMD__HW_LOCK command.
3146 */
3147 struct dmub_cmd_lock_hw_data lock_hw_data;
3148 };
3149
3150 /**
3151 * ABM command sub-types.
3152 */
3153 enum dmub_cmd_abm_type {
3154 /**
3155 * Initialize parameters for ABM algorithm.
3156 * Data is passed through an indirect buffer.
3157 */
3158 DMUB_CMD__ABM_INIT_CONFIG = 0,
3159 /**
3160 * Set OTG and panel HW instance.
3161 */
3162 DMUB_CMD__ABM_SET_PIPE = 1,
3163 /**
3164 * Set user requested backklight level.
3165 */
3166 DMUB_CMD__ABM_SET_BACKLIGHT = 2,
3167 /**
3168 * Set ABM operating/aggression level.
3169 */
3170 DMUB_CMD__ABM_SET_LEVEL = 3,
3171 /**
3172 * Set ambient light level.
3173 */
3174 DMUB_CMD__ABM_SET_AMBIENT_LEVEL = 4,
3175 /**
3176 * Enable/disable fractional duty cycle for backlight PWM.
3177 */
3178 DMUB_CMD__ABM_SET_PWM_FRAC = 5,
3179
3180 /**
3181 * unregister vertical interrupt after steady state is reached
3182 */
3183 DMUB_CMD__ABM_PAUSE = 6,
3184
3185 /**
3186 * Save and Restore ABM state. On save we save parameters, and
3187 * on restore we update state with passed in data.
3188 */
3189 DMUB_CMD__ABM_SAVE_RESTORE = 7,
3190 };
3191
3192 /**
3193 * Parameters for ABM2.4 algorithm. Passed from driver to FW via an indirect buffer.
3194 * Requirements:
3195 * - Padded explicitly to 32-bit boundary.
3196 * - Must ensure this structure matches the one on driver-side,
3197 * otherwise it won't be aligned.
3198 */
3199 struct abm_config_table {
3200 /**
3201 * Gamma curve thresholds, used for crgb conversion.
3202 */
3203 uint16_t crgb_thresh[NUM_POWER_FN_SEGS]; // 0B
3204 /**
3205 * Gamma curve offsets, used for crgb conversion.
3206 */
3207 uint16_t crgb_offset[NUM_POWER_FN_SEGS]; // 16B
3208 /**
3209 * Gamma curve slopes, used for crgb conversion.
3210 */
3211 uint16_t crgb_slope[NUM_POWER_FN_SEGS]; // 32B
3212 /**
3213 * Custom backlight curve thresholds.
3214 */
3215 uint16_t backlight_thresholds[NUM_BL_CURVE_SEGS]; // 48B
3216 /**
3217 * Custom backlight curve offsets.
3218 */
3219 uint16_t backlight_offsets[NUM_BL_CURVE_SEGS]; // 78B
3220 /**
3221 * Ambient light thresholds.
3222 */
3223 uint16_t ambient_thresholds_lux[NUM_AMBI_LEVEL]; // 112B
3224 /**
3225 * Minimum programmable backlight.
3226 */
3227 uint16_t min_abm_backlight; // 122B
3228 /**
3229 * Minimum reduction values.
3230 */
3231 uint8_t min_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 124B
3232 /**
3233 * Maximum reduction values.
3234 */
3235 uint8_t max_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 144B
3236 /**
3237 * Bright positive gain.
3238 */
3239 uint8_t bright_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 164B
3240 /**
3241 * Dark negative gain.
3242 */
3243 uint8_t dark_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 184B
3244 /**
3245 * Hybrid factor.
3246 */
3247 uint8_t hybrid_factor[NUM_AGGR_LEVEL]; // 204B
3248 /**
3249 * Contrast factor.
3250 */
3251 uint8_t contrast_factor[NUM_AGGR_LEVEL]; // 208B
3252 /**
3253 * Deviation gain.
3254 */
3255 uint8_t deviation_gain[NUM_AGGR_LEVEL]; // 212B
3256 /**
3257 * Minimum knee.
3258 */
3259 uint8_t min_knee[NUM_AGGR_LEVEL]; // 216B
3260 /**
3261 * Maximum knee.
3262 */
3263 uint8_t max_knee[NUM_AGGR_LEVEL]; // 220B
3264 /**
3265 * Unused.
3266 */
3267 uint8_t iir_curve[NUM_AMBI_LEVEL]; // 224B
3268 /**
3269 * Explicit padding to 4 byte boundary.
3270 */
3271 uint8_t pad3[3]; // 229B
3272 /**
3273 * Backlight ramp reduction.
3274 */
3275 uint16_t blRampReduction[NUM_AGGR_LEVEL]; // 232B
3276 /**
3277 * Backlight ramp start.
3278 */
3279 uint16_t blRampStart[NUM_AGGR_LEVEL]; // 240B
3280 };
3281
3282 /**
3283 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PIPE command.
3284 */
3285 struct dmub_cmd_abm_set_pipe_data {
3286 /**
3287 * OTG HW instance.
3288 */
3289 uint8_t otg_inst;
3290
3291 /**
3292 * Panel Control HW instance.
3293 */
3294 uint8_t panel_inst;
3295
3296 /**
3297 * Controls how ABM will interpret a set pipe or set level command.
3298 */
3299 uint8_t set_pipe_option;
3300
3301 /**
3302 * Unused.
3303 * TODO: Remove.
3304 */
3305 uint8_t ramping_boundary;
3306
3307 /**
3308 * PwrSeq HW Instance.
3309 */
3310 uint8_t pwrseq_inst;
3311
3312 /**
3313 * Explicit padding to 4 byte boundary.
3314 */
3315 uint8_t pad[3];
3316 };
3317
3318 /**
3319 * Definition of a DMUB_CMD__ABM_SET_PIPE command.
3320 */
3321 struct dmub_rb_cmd_abm_set_pipe {
3322 /**
3323 * Command header.
3324 */
3325 struct dmub_cmd_header header;
3326
3327 /**
3328 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PIPE command.
3329 */
3330 struct dmub_cmd_abm_set_pipe_data abm_set_pipe_data;
3331 };
3332
3333 /**
3334 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_BACKLIGHT command.
3335 */
3336 struct dmub_cmd_abm_set_backlight_data {
3337 /**
3338 * Number of frames to ramp to backlight user level.
3339 */
3340 uint32_t frame_ramp;
3341
3342 /**
3343 * Requested backlight level from user.
3344 */
3345 uint32_t backlight_user_level;
3346
3347 /**
3348 * ABM control version.
3349 */
3350 uint8_t version;
3351
3352 /**
3353 * Panel Control HW instance mask.
3354 * Bit 0 is Panel Control HW instance 0.
3355 * Bit 1 is Panel Control HW instance 1.
3356 */
3357 uint8_t panel_mask;
3358
3359 /**
3360 * Explicit padding to 4 byte boundary.
3361 */
3362 uint8_t pad[2];
3363 };
3364
3365 /**
3366 * Definition of a DMUB_CMD__ABM_SET_BACKLIGHT command.
3367 */
3368 struct dmub_rb_cmd_abm_set_backlight {
3369 /**
3370 * Command header.
3371 */
3372 struct dmub_cmd_header header;
3373
3374 /**
3375 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_BACKLIGHT command.
3376 */
3377 struct dmub_cmd_abm_set_backlight_data abm_set_backlight_data;
3378 };
3379
3380 /**
3381 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_LEVEL command.
3382 */
3383 struct dmub_cmd_abm_set_level_data {
3384 /**
3385 * Set current ABM operating/aggression level.
3386 */
3387 uint32_t level;
3388
3389 /**
3390 * ABM control version.
3391 */
3392 uint8_t version;
3393
3394 /**
3395 * Panel Control HW instance mask.
3396 * Bit 0 is Panel Control HW instance 0.
3397 * Bit 1 is Panel Control HW instance 1.
3398 */
3399 uint8_t panel_mask;
3400
3401 /**
3402 * Explicit padding to 4 byte boundary.
3403 */
3404 uint8_t pad[2];
3405 };
3406
3407 /**
3408 * Definition of a DMUB_CMD__ABM_SET_LEVEL command.
3409 */
3410 struct dmub_rb_cmd_abm_set_level {
3411 /**
3412 * Command header.
3413 */
3414 struct dmub_cmd_header header;
3415
3416 /**
3417 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_LEVEL command.
3418 */
3419 struct dmub_cmd_abm_set_level_data abm_set_level_data;
3420 };
3421
3422 /**
3423 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command.
3424 */
3425 struct dmub_cmd_abm_set_ambient_level_data {
3426 /**
3427 * Ambient light sensor reading from OS.
3428 */
3429 uint32_t ambient_lux;
3430
3431 /**
3432 * ABM control version.
3433 */
3434 uint8_t version;
3435
3436 /**
3437 * Panel Control HW instance mask.
3438 * Bit 0 is Panel Control HW instance 0.
3439 * Bit 1 is Panel Control HW instance 1.
3440 */
3441 uint8_t panel_mask;
3442
3443 /**
3444 * Explicit padding to 4 byte boundary.
3445 */
3446 uint8_t pad[2];
3447 };
3448
3449 /**
3450 * Definition of a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command.
3451 */
3452 struct dmub_rb_cmd_abm_set_ambient_level {
3453 /**
3454 * Command header.
3455 */
3456 struct dmub_cmd_header header;
3457
3458 /**
3459 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command.
3460 */
3461 struct dmub_cmd_abm_set_ambient_level_data abm_set_ambient_level_data;
3462 };
3463
3464 /**
3465 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PWM_FRAC command.
3466 */
3467 struct dmub_cmd_abm_set_pwm_frac_data {
3468 /**
3469 * Enable/disable fractional duty cycle for backlight PWM.
3470 * TODO: Convert to uint8_t.
3471 */
3472 uint32_t fractional_pwm;
3473
3474 /**
3475 * ABM control version.
3476 */
3477 uint8_t version;
3478
3479 /**
3480 * Panel Control HW instance mask.
3481 * Bit 0 is Panel Control HW instance 0.
3482 * Bit 1 is Panel Control HW instance 1.
3483 */
3484 uint8_t panel_mask;
3485
3486 /**
3487 * Explicit padding to 4 byte boundary.
3488 */
3489 uint8_t pad[2];
3490 };
3491
3492 /**
3493 * Definition of a DMUB_CMD__ABM_SET_PWM_FRAC command.
3494 */
3495 struct dmub_rb_cmd_abm_set_pwm_frac {
3496 /**
3497 * Command header.
3498 */
3499 struct dmub_cmd_header header;
3500
3501 /**
3502 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PWM_FRAC command.
3503 */
3504 struct dmub_cmd_abm_set_pwm_frac_data abm_set_pwm_frac_data;
3505 };
3506
3507 /**
3508 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command.
3509 */
3510 struct dmub_cmd_abm_init_config_data {
3511 /**
3512 * Location of indirect buffer used to pass init data to ABM.
3513 */
3514 union dmub_addr src;
3515
3516 /**
3517 * Indirect buffer length.
3518 */
3519 uint16_t bytes;
3520
3521
3522 /**
3523 * ABM control version.
3524 */
3525 uint8_t version;
3526
3527 /**
3528 * Panel Control HW instance mask.
3529 * Bit 0 is Panel Control HW instance 0.
3530 * Bit 1 is Panel Control HW instance 1.
3531 */
3532 uint8_t panel_mask;
3533
3534 /**
3535 * Explicit padding to 4 byte boundary.
3536 */
3537 uint8_t pad[2];
3538 };
3539
3540 /**
3541 * Definition of a DMUB_CMD__ABM_INIT_CONFIG command.
3542 */
3543 struct dmub_rb_cmd_abm_init_config {
3544 /**
3545 * Command header.
3546 */
3547 struct dmub_cmd_header header;
3548
3549 /**
3550 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command.
3551 */
3552 struct dmub_cmd_abm_init_config_data abm_init_config_data;
3553 };
3554
3555 /**
3556 * Data passed from driver to FW in a DMUB_CMD__ABM_PAUSE command.
3557 */
3558
3559 struct dmub_cmd_abm_pause_data {
3560
3561 /**
3562 * Panel Control HW instance mask.
3563 * Bit 0 is Panel Control HW instance 0.
3564 * Bit 1 is Panel Control HW instance 1.
3565 */
3566 uint8_t panel_mask;
3567
3568 /**
3569 * OTG hw instance
3570 */
3571 uint8_t otg_inst;
3572
3573 /**
3574 * Enable or disable ABM pause
3575 */
3576 uint8_t enable;
3577
3578 /**
3579 * Explicit padding to 4 byte boundary.
3580 */
3581 uint8_t pad[1];
3582 };
3583
3584
3585 /**
3586 * Definition of a DMUB_CMD__ABM_PAUSE command.
3587 */
3588 struct dmub_rb_cmd_abm_pause {
3589 /**
3590 * Command header.
3591 */
3592 struct dmub_cmd_header header;
3593
3594 /**
3595 * Data passed from driver to FW in a DMUB_CMD__ABM_PAUSE command.
3596 */
3597 struct dmub_cmd_abm_pause_data abm_pause_data;
3598 };
3599
3600 /**
3601 * Definition of a DMUB_CMD__ABM_SAVE_RESTORE command.
3602 */
3603 struct dmub_rb_cmd_abm_save_restore {
3604 /**
3605 * Command header.
3606 */
3607 struct dmub_cmd_header header;
3608
3609 /**
3610 * OTG hw instance
3611 */
3612 uint8_t otg_inst;
3613
3614 /**
3615 * Enable or disable ABM pause
3616 */
3617 uint8_t freeze;
3618
3619 /**
3620 * Explicit padding to 4 byte boundary.
3621 */
3622 uint8_t debug;
3623
3624 /**
3625 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command.
3626 */
3627 struct dmub_cmd_abm_init_config_data abm_init_config_data;
3628 };
3629
3630 /**
3631 * Data passed from driver to FW in a DMUB_CMD__QUERY_FEATURE_CAPS command.
3632 */
3633 struct dmub_cmd_query_feature_caps_data {
3634 /**
3635 * DMUB feature capabilities.
3636 * After DMUB init, driver will query FW capabilities prior to enabling certain features.
3637 */
3638 struct dmub_feature_caps feature_caps;
3639 };
3640
3641 /**
3642 * Definition of a DMUB_CMD__QUERY_FEATURE_CAPS command.
3643 */
3644 struct dmub_rb_cmd_query_feature_caps {
3645 /**
3646 * Command header.
3647 */
3648 struct dmub_cmd_header header;
3649 /**
3650 * Data passed from driver to FW in a DMUB_CMD__QUERY_FEATURE_CAPS command.
3651 */
3652 struct dmub_cmd_query_feature_caps_data query_feature_caps_data;
3653 };
3654
3655 /**
3656 * Data passed from driver to FW in a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command.
3657 */
3658 struct dmub_cmd_visual_confirm_color_data {
3659 /**
3660 * DMUB feature capabilities.
3661 * After DMUB init, driver will query FW capabilities prior to enabling certain features.
3662 */
3663 struct dmub_visual_confirm_color visual_confirm_color;
3664 };
3665
3666 /**
3667 * Definition of a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command.
3668 */
3669 struct dmub_rb_cmd_get_visual_confirm_color {
3670 /**
3671 * Command header.
3672 */
3673 struct dmub_cmd_header header;
3674 /**
3675 * Data passed from driver to FW in a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command.
3676 */
3677 struct dmub_cmd_visual_confirm_color_data visual_confirm_color_data;
3678 };
3679
3680 struct dmub_optc_state {
3681 uint32_t v_total_max;
3682 uint32_t v_total_min;
3683 uint32_t tg_inst;
3684 };
3685
3686 struct dmub_rb_cmd_drr_update {
3687 struct dmub_cmd_header header;
3688 struct dmub_optc_state dmub_optc_state_req;
3689 };
3690
3691 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data {
3692 uint32_t pix_clk_100hz;
3693 uint8_t max_ramp_step;
3694 uint8_t pipes;
3695 uint8_t min_refresh_in_hz;
3696 uint8_t pipe_count;
3697 uint8_t pipe_index[4];
3698 };
3699
3700 struct dmub_cmd_fw_assisted_mclk_switch_config {
3701 uint8_t fams_enabled;
3702 uint8_t visual_confirm_enabled;
3703 uint16_t vactive_stretch_margin_us; // Extra vblank stretch required when doing FPO + Vactive
3704 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data pipe_data[DMUB_MAX_FPO_STREAMS];
3705 };
3706
3707 struct dmub_rb_cmd_fw_assisted_mclk_switch {
3708 struct dmub_cmd_header header;
3709 struct dmub_cmd_fw_assisted_mclk_switch_config config_data;
3710 };
3711
3712 /**
3713 * enum dmub_cmd_panel_cntl_type - Panel control command.
3714 */
3715 enum dmub_cmd_panel_cntl_type {
3716 /**
3717 * Initializes embedded panel hardware blocks.
3718 */
3719 DMUB_CMD__PANEL_CNTL_HW_INIT = 0,
3720 /**
3721 * Queries backlight info for the embedded panel.
3722 */
3723 DMUB_CMD__PANEL_CNTL_QUERY_BACKLIGHT_INFO = 1,
3724 };
3725
3726 /**
3727 * struct dmub_cmd_panel_cntl_data - Panel control data.
3728 */
3729 struct dmub_cmd_panel_cntl_data {
3730 uint32_t pwrseq_inst; /**< pwrseq instance */
3731 uint32_t current_backlight; /* in/out */
3732 uint32_t bl_pwm_cntl; /* in/out */
3733 uint32_t bl_pwm_period_cntl; /* in/out */
3734 uint32_t bl_pwm_ref_div1; /* in/out */
3735 uint8_t is_backlight_on : 1; /* in/out */
3736 uint8_t is_powered_on : 1; /* in/out */
3737 uint8_t padding[3];
3738 uint32_t bl_pwm_ref_div2; /* in/out */
3739 uint8_t reserved[4];
3740 };
3741
3742 /**
3743 * struct dmub_rb_cmd_panel_cntl - Panel control command.
3744 */
3745 struct dmub_rb_cmd_panel_cntl {
3746 struct dmub_cmd_header header; /**< header */
3747 struct dmub_cmd_panel_cntl_data data; /**< payload */
3748 };
3749
3750 /**
3751 * Data passed from driver to FW in a DMUB_CMD__VBIOS_LVTMA_CONTROL command.
3752 */
3753 struct dmub_cmd_lvtma_control_data {
3754 uint8_t uc_pwr_action; /**< LVTMA_ACTION */
3755 uint8_t bypass_panel_control_wait;
3756 uint8_t reserved_0[2]; /**< For future use */
3757 uint8_t pwrseq_inst; /**< LVTMA control instance */
3758 uint8_t reserved_1[3]; /**< For future use */
3759 };
3760
3761 /**
3762 * Definition of a DMUB_CMD__VBIOS_LVTMA_CONTROL command.
3763 */
3764 struct dmub_rb_cmd_lvtma_control {
3765 /**
3766 * Command header.
3767 */
3768 struct dmub_cmd_header header;
3769 /**
3770 * Data passed from driver to FW in a DMUB_CMD__VBIOS_LVTMA_CONTROL command.
3771 */
3772 struct dmub_cmd_lvtma_control_data data;
3773 };
3774
3775 /**
3776 * Data passed in/out in a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command.
3777 */
3778 struct dmub_rb_cmd_transmitter_query_dp_alt_data {
3779 uint8_t phy_id; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */
3780 uint8_t is_usb; /**< is phy is usb */
3781 uint8_t is_dp_alt_disable; /**< is dp alt disable */
3782 uint8_t is_dp4; /**< is dp in 4 lane */
3783 };
3784
3785 /**
3786 * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command.
3787 */
3788 struct dmub_rb_cmd_transmitter_query_dp_alt {
3789 struct dmub_cmd_header header; /**< header */
3790 struct dmub_rb_cmd_transmitter_query_dp_alt_data data; /**< payload */
3791 };
3792
3793 /**
3794 * Maximum number of bytes a chunk sent to DMUB for parsing
3795 */
3796 #define DMUB_EDID_CEA_DATA_CHUNK_BYTES 8
3797
3798 /**
3799 * Represent a chunk of CEA blocks sent to DMUB for parsing
3800 */
3801 struct dmub_cmd_send_edid_cea {
3802 uint16_t offset; /**< offset into the CEA block */
3803 uint8_t length; /**< number of bytes in payload to copy as part of CEA block */
3804 uint16_t cea_total_length; /**< total length of the CEA block */
3805 uint8_t payload[DMUB_EDID_CEA_DATA_CHUNK_BYTES]; /**< data chunk of the CEA block */
3806 uint8_t pad[3]; /**< padding and for future expansion */
3807 };
3808
3809 /**
3810 * Result of VSDB parsing from CEA block
3811 */
3812 struct dmub_cmd_edid_cea_amd_vsdb {
3813 uint8_t vsdb_found; /**< 1 if parsing has found valid AMD VSDB */
3814 uint8_t freesync_supported; /**< 1 if Freesync is supported */
3815 uint16_t amd_vsdb_version; /**< AMD VSDB version */
3816 uint16_t min_frame_rate; /**< Maximum frame rate */
3817 uint16_t max_frame_rate; /**< Minimum frame rate */
3818 };
3819
3820 /**
3821 * Result of sending a CEA chunk
3822 */
3823 struct dmub_cmd_edid_cea_ack {
3824 uint16_t offset; /**< offset of the chunk into the CEA block */
3825 uint8_t success; /**< 1 if this sending of chunk succeeded */
3826 uint8_t pad; /**< padding and for future expansion */
3827 };
3828
3829 /**
3830 * Specify whether the result is an ACK/NACK or the parsing has finished
3831 */
3832 enum dmub_cmd_edid_cea_reply_type {
3833 DMUB_CMD__EDID_CEA_AMD_VSDB = 1, /**< VSDB parsing has finished */
3834 DMUB_CMD__EDID_CEA_ACK = 2, /**< acknowledges the CEA sending is OK or failing */
3835 };
3836
3837 /**
3838 * Definition of a DMUB_CMD__EDID_CEA command.
3839 */
3840 struct dmub_rb_cmd_edid_cea {
3841 struct dmub_cmd_header header; /**< Command header */
3842 union dmub_cmd_edid_cea_data {
3843 struct dmub_cmd_send_edid_cea input; /**< input to send CEA chunks */
3844 struct dmub_cmd_edid_cea_output { /**< output with results */
3845 uint8_t type; /**< dmub_cmd_edid_cea_reply_type */
3846 union {
3847 struct dmub_cmd_edid_cea_amd_vsdb amd_vsdb;
3848 struct dmub_cmd_edid_cea_ack ack;
3849 };
3850 } output; /**< output to retrieve ACK/NACK or VSDB parsing results */
3851 } data; /**< Command data */
3852
3853 };
3854
3855 /**
3856 * struct dmub_cmd_cable_id_input - Defines the input of DMUB_CMD_GET_USBC_CABLE_ID command.
3857 */
3858 struct dmub_cmd_cable_id_input {
3859 uint8_t phy_inst; /**< phy inst for cable id data */
3860 };
3861
3862 /**
3863 * struct dmub_cmd_cable_id_input - Defines the output of DMUB_CMD_GET_USBC_CABLE_ID command.
3864 */
3865 struct dmub_cmd_cable_id_output {
3866 uint8_t UHBR10_20_CAPABILITY :2; /**< b'01 for UHBR10 support, b'10 for both UHBR10 and UHBR20 support */
3867 uint8_t UHBR13_5_CAPABILITY :1; /**< b'1 for UHBR13.5 support */
3868 uint8_t CABLE_TYPE :3; /**< b'01 for passive cable, b'10 for active LRD cable, b'11 for active retimer cable */
3869 uint8_t RESERVED :2; /**< reserved means not defined */
3870 };
3871
3872 /**
3873 * Definition of a DMUB_CMD_GET_USBC_CABLE_ID command
3874 */
3875 struct dmub_rb_cmd_get_usbc_cable_id {
3876 struct dmub_cmd_header header; /**< Command header */
3877 /**
3878 * Data passed from driver to FW in a DMUB_CMD_GET_USBC_CABLE_ID command.
3879 */
3880 union dmub_cmd_cable_id_data {
3881 struct dmub_cmd_cable_id_input input; /**< Input */
3882 struct dmub_cmd_cable_id_output output; /**< Output */
3883 uint8_t output_raw; /**< Raw data output */
3884 } data;
3885 };
3886
3887 /**
3888 * Command type of a DMUB_CMD__SECURE_DISPLAY command
3889 */
3890 enum dmub_cmd_secure_display_type {
3891 DMUB_CMD__SECURE_DISPLAY_TEST_CMD = 0, /* test command to only check if inbox message works */
3892 DMUB_CMD__SECURE_DISPLAY_CRC_STOP_UPDATE,
3893 DMUB_CMD__SECURE_DISPLAY_CRC_WIN_NOTIFY
3894 };
3895
3896 /**
3897 * Definition of a DMUB_CMD__SECURE_DISPLAY command
3898 */
3899 struct dmub_rb_cmd_secure_display {
3900 struct dmub_cmd_header header;
3901 /**
3902 * Data passed from driver to dmub firmware.
3903 */
3904 struct dmub_cmd_roi_info {
3905 uint16_t x_start;
3906 uint16_t x_end;
3907 uint16_t y_start;
3908 uint16_t y_end;
3909 uint8_t otg_id;
3910 uint8_t phy_id;
3911 } roi_info;
3912 };
3913
3914 /**
3915 * union dmub_rb_cmd - DMUB inbox command.
3916 */
3917 union dmub_rb_cmd {
3918 /**
3919 * Elements shared with all commands.
3920 */
3921 struct dmub_rb_cmd_common cmd_common;
3922 /**
3923 * Definition of a DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE command.
3924 */
3925 struct dmub_rb_cmd_read_modify_write read_modify_write;
3926 /**
3927 * Definition of a DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ command.
3928 */
3929 struct dmub_rb_cmd_reg_field_update_sequence reg_field_update_seq;
3930 /**
3931 * Definition of a DMUB_CMD__REG_SEQ_BURST_WRITE command.
3932 */
3933 struct dmub_rb_cmd_burst_write burst_write;
3934 /**
3935 * Definition of a DMUB_CMD__REG_REG_WAIT command.
3936 */
3937 struct dmub_rb_cmd_reg_wait reg_wait;
3938 /**
3939 * Definition of a DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL command.
3940 */
3941 struct dmub_rb_cmd_digx_encoder_control digx_encoder_control;
3942 /**
3943 * Definition of a DMUB_CMD__VBIOS_SET_PIXEL_CLOCK command.
3944 */
3945 struct dmub_rb_cmd_set_pixel_clock set_pixel_clock;
3946 /**
3947 * Definition of a DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING command.
3948 */
3949 struct dmub_rb_cmd_enable_disp_power_gating enable_disp_power_gating;
3950 /**
3951 * Definition of a DMUB_CMD__VBIOS_DPPHY_INIT command.
3952 */
3953 struct dmub_rb_cmd_dpphy_init dpphy_init;
3954 /**
3955 * Definition of a DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL command.
3956 */
3957 struct dmub_rb_cmd_dig1_transmitter_control dig1_transmitter_control;
3958 /**
3959 * Definition of a DMUB_CMD__VBIOS_DOMAIN_CONTROL command.
3960 */
3961 struct dmub_rb_cmd_domain_control domain_control;
3962 /**
3963 * Definition of a DMUB_CMD__PSR_SET_VERSION command.
3964 */
3965 struct dmub_rb_cmd_psr_set_version psr_set_version;
3966 /**
3967 * Definition of a DMUB_CMD__PSR_COPY_SETTINGS command.
3968 */
3969 struct dmub_rb_cmd_psr_copy_settings psr_copy_settings;
3970 /**
3971 * Definition of a DMUB_CMD__PSR_ENABLE command.
3972 */
3973 struct dmub_rb_cmd_psr_enable psr_enable;
3974 /**
3975 * Definition of a DMUB_CMD__PSR_SET_LEVEL command.
3976 */
3977 struct dmub_rb_cmd_psr_set_level psr_set_level;
3978 /**
3979 * Definition of a DMUB_CMD__PSR_FORCE_STATIC command.
3980 */
3981 struct dmub_rb_cmd_psr_force_static psr_force_static;
3982 /**
3983 * Definition of a DMUB_CMD__UPDATE_DIRTY_RECT command.
3984 */
3985 struct dmub_rb_cmd_update_dirty_rect update_dirty_rect;
3986 /**
3987 * Definition of a DMUB_CMD__UPDATE_CURSOR_INFO command.
3988 */
3989 struct dmub_rb_cmd_update_cursor_info update_cursor_info;
3990 /**
3991 * Definition of a DMUB_CMD__HW_LOCK command.
3992 * Command is used by driver and FW.
3993 */
3994 struct dmub_rb_cmd_lock_hw lock_hw;
3995 /**
3996 * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command.
3997 */
3998 struct dmub_rb_cmd_psr_set_vtotal psr_set_vtotal;
3999 /**
4000 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command.
4001 */
4002 struct dmub_rb_cmd_psr_set_power_opt psr_set_power_opt;
4003 /**
4004 * Definition of a DMUB_CMD__PLAT_54186_WA command.
4005 */
4006 struct dmub_rb_cmd_PLAT_54186_wa PLAT_54186_wa;
4007 /**
4008 * Definition of a DMUB_CMD__MALL command.
4009 */
4010 struct dmub_rb_cmd_mall mall;
4011 /**
4012 * Definition of a DMUB_CMD__CAB command.
4013 */
4014 struct dmub_rb_cmd_cab_for_ss cab;
4015
4016 struct dmub_rb_cmd_fw_assisted_mclk_switch_v2 fw_assisted_mclk_switch_v2;
4017
4018 /**
4019 * Definition of a DMUB_CMD__IDLE_OPT_DCN_RESTORE command.
4020 */
4021 struct dmub_rb_cmd_idle_opt_dcn_restore dcn_restore;
4022
4023 /**
4024 * Definition of a DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS command.
4025 */
4026 struct dmub_rb_cmd_clk_mgr_notify_clocks notify_clocks;
4027
4028 /**
4029 * Definition of DMUB_CMD__PANEL_CNTL commands.
4030 */
4031 struct dmub_rb_cmd_panel_cntl panel_cntl;
4032 /**
4033 * Definition of a DMUB_CMD__ABM_SET_PIPE command.
4034 */
4035 struct dmub_rb_cmd_abm_set_pipe abm_set_pipe;
4036
4037 /**
4038 * Definition of a DMUB_CMD__ABM_SET_BACKLIGHT command.
4039 */
4040 struct dmub_rb_cmd_abm_set_backlight abm_set_backlight;
4041
4042 /**
4043 * Definition of a DMUB_CMD__ABM_SET_LEVEL command.
4044 */
4045 struct dmub_rb_cmd_abm_set_level abm_set_level;
4046
4047 /**
4048 * Definition of a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command.
4049 */
4050 struct dmub_rb_cmd_abm_set_ambient_level abm_set_ambient_level;
4051
4052 /**
4053 * Definition of a DMUB_CMD__ABM_SET_PWM_FRAC command.
4054 */
4055 struct dmub_rb_cmd_abm_set_pwm_frac abm_set_pwm_frac;
4056
4057 /**
4058 * Definition of a DMUB_CMD__ABM_INIT_CONFIG command.
4059 */
4060 struct dmub_rb_cmd_abm_init_config abm_init_config;
4061
4062 /**
4063 * Definition of a DMUB_CMD__ABM_PAUSE command.
4064 */
4065 struct dmub_rb_cmd_abm_pause abm_pause;
4066
4067 /**
4068 * Definition of a DMUB_CMD__ABM_SAVE_RESTORE command.
4069 */
4070 struct dmub_rb_cmd_abm_save_restore abm_save_restore;
4071
4072 /**
4073 * Definition of a DMUB_CMD__DP_AUX_ACCESS command.
4074 */
4075 struct dmub_rb_cmd_dp_aux_access dp_aux_access;
4076
4077 /**
4078 * Definition of a DMUB_CMD__OUTBOX1_ENABLE command.
4079 */
4080 struct dmub_rb_cmd_outbox1_enable outbox1_enable;
4081
4082 /**
4083 * Definition of a DMUB_CMD__QUERY_FEATURE_CAPS command.
4084 */
4085 struct dmub_rb_cmd_query_feature_caps query_feature_caps;
4086
4087 /**
4088 * Definition of a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command.
4089 */
4090 struct dmub_rb_cmd_get_visual_confirm_color visual_confirm_color;
4091 struct dmub_rb_cmd_drr_update drr_update;
4092 struct dmub_rb_cmd_fw_assisted_mclk_switch fw_assisted_mclk_switch;
4093
4094 /**
4095 * Definition of a DMUB_CMD__VBIOS_LVTMA_CONTROL command.
4096 */
4097 struct dmub_rb_cmd_lvtma_control lvtma_control;
4098 /**
4099 * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command.
4100 */
4101 struct dmub_rb_cmd_transmitter_query_dp_alt query_dp_alt;
4102 /**
4103 * Definition of a DMUB_CMD__DPIA_DIG1_CONTROL command.
4104 */
4105 struct dmub_rb_cmd_dig1_dpia_control dig1_dpia_control;
4106 /**
4107 * Definition of a DMUB_CMD__DPIA_SET_CONFIG_ACCESS command.
4108 */
4109 struct dmub_rb_cmd_set_config_access set_config_access;
4110 /**
4111 * Definition of a DMUB_CMD__DPIA_MST_ALLOC_SLOTS command.
4112 */
4113 struct dmub_rb_cmd_set_mst_alloc_slots set_mst_alloc_slots;
4114 /**
4115 * Definition of a DMUB_CMD__EDID_CEA command.
4116 */
4117 struct dmub_rb_cmd_edid_cea edid_cea;
4118 /**
4119 * Definition of a DMUB_CMD_GET_USBC_CABLE_ID command.
4120 */
4121 struct dmub_rb_cmd_get_usbc_cable_id cable_id;
4122
4123 /**
4124 * Definition of a DMUB_CMD__QUERY_HPD_STATE command.
4125 */
4126 struct dmub_rb_cmd_query_hpd_state query_hpd;
4127 /**
4128 * Definition of a DMUB_CMD__SECURE_DISPLAY command.
4129 */
4130 struct dmub_rb_cmd_secure_display secure_display;
4131
4132 /**
4133 * Definition of a DMUB_CMD__DPIA_HPD_INT_ENABLE command.
4134 */
4135 struct dmub_rb_cmd_dpia_hpd_int_enable dpia_hpd_int_enable;
4136 /**
4137 * Definition of a DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE command.
4138 */
4139 struct dmub_rb_cmd_idle_opt_dcn_notify_idle idle_opt_notify_idle;
4140 /*
4141 * Definition of a DMUB_CMD__REPLAY_COPY_SETTINGS command.
4142 */
4143 struct dmub_rb_cmd_replay_copy_settings replay_copy_settings;
4144 /**
4145 * Definition of a DMUB_CMD__REPLAY_ENABLE command.
4146 */
4147 struct dmub_rb_cmd_replay_enable replay_enable;
4148 /**
4149 * Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command.
4150 */
4151 struct dmub_rb_cmd_replay_set_power_opt replay_set_power_opt;
4152 /**
4153 * Definition of a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command.
4154 */
4155 struct dmub_rb_cmd_replay_set_coasting_vtotal replay_set_coasting_vtotal;
4156 };
4157
4158 /**
4159 * union dmub_rb_out_cmd - Outbox command
4160 */
4161 union dmub_rb_out_cmd {
4162 /**
4163 * Parameters common to every command.
4164 */
4165 struct dmub_rb_cmd_common cmd_common;
4166 /**
4167 * AUX reply command.
4168 */
4169 struct dmub_rb_cmd_dp_aux_reply dp_aux_reply;
4170 /**
4171 * HPD notify command.
4172 */
4173 struct dmub_rb_cmd_dp_hpd_notify dp_hpd_notify;
4174 /**
4175 * SET_CONFIG reply command.
4176 */
4177 struct dmub_rb_cmd_dp_set_config_reply set_config_reply;
4178 /**
4179 * DPIA notification command.
4180 */
4181 struct dmub_rb_cmd_dpia_notification dpia_notification;
4182 };
4183 #pragma pack(pop)
4184
4185
4186 //==============================================================================
4187 //</DMUB_CMD>===================================================================
4188 //==============================================================================
4189 //< DMUB_RB>====================================================================
4190 //==============================================================================
4191
4192 #if defined(__cplusplus)
4193 extern "C" {
4194 #endif
4195
4196 /**
4197 * struct dmub_rb_init_params - Initialization params for DMUB ringbuffer
4198 */
4199 struct dmub_rb_init_params {
4200 void *ctx; /**< Caller provided context pointer */
4201 void *base_address; /**< CPU base address for ring's data */
4202 uint32_t capacity; /**< Ringbuffer capacity in bytes */
4203 uint32_t read_ptr; /**< Initial read pointer for consumer in bytes */
4204 uint32_t write_ptr; /**< Initial write pointer for producer in bytes */
4205 };
4206
4207 /**
4208 * struct dmub_rb - Inbox or outbox DMUB ringbuffer
4209 */
4210 struct dmub_rb {
4211 void *base_address; /**< CPU address for the ring's data */
4212 uint32_t rptr; /**< Read pointer for consumer in bytes */
4213 uint32_t wrpt; /**< Write pointer for producer in bytes */
4214 uint32_t capacity; /**< Ringbuffer capacity in bytes */
4215
4216 void *ctx; /**< Caller provided context pointer */
4217 void *dmub; /**< Pointer to the DMUB interface */
4218 };
4219
4220 /**
4221 * @brief Checks if the ringbuffer is empty.
4222 *
4223 * @param rb DMUB Ringbuffer
4224 * @return true if empty
4225 * @return false otherwise
4226 */
dmub_rb_empty(struct dmub_rb * rb)4227 static inline bool dmub_rb_empty(struct dmub_rb *rb)
4228 {
4229 return (rb->wrpt == rb->rptr);
4230 }
4231
4232 /**
4233 * @brief Checks if the ringbuffer is full
4234 *
4235 * @param rb DMUB Ringbuffer
4236 * @return true if full
4237 * @return false otherwise
4238 */
dmub_rb_full(struct dmub_rb * rb)4239 static inline bool dmub_rb_full(struct dmub_rb *rb)
4240 {
4241 uint32_t data_count;
4242
4243 if (rb->wrpt >= rb->rptr)
4244 data_count = rb->wrpt - rb->rptr;
4245 else
4246 data_count = rb->capacity - (rb->rptr - rb->wrpt);
4247
4248 return (data_count == (rb->capacity - DMUB_RB_CMD_SIZE));
4249 }
4250
4251 /**
4252 * @brief Pushes a command into the ringbuffer
4253 *
4254 * @param rb DMUB ringbuffer
4255 * @param cmd The command to push
4256 * @return true if the ringbuffer was not full
4257 * @return false otherwise
4258 */
dmub_rb_push_front(struct dmub_rb * rb,const union dmub_rb_cmd * cmd)4259 static inline bool dmub_rb_push_front(struct dmub_rb *rb,
4260 const union dmub_rb_cmd *cmd)
4261 {
4262 uint64_t volatile *dst = (uint64_t volatile *)((uint8_t *)(rb->base_address) + rb->wrpt);
4263 const uint64_t *src = (const uint64_t *)cmd;
4264 uint8_t i;
4265
4266 if (dmub_rb_full(rb))
4267 return false;
4268
4269 // copying data
4270 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++)
4271 *dst++ = *src++;
4272
4273 rb->wrpt += DMUB_RB_CMD_SIZE;
4274
4275 if (rb->wrpt >= rb->capacity)
4276 rb->wrpt %= rb->capacity;
4277
4278 return true;
4279 }
4280
4281 /**
4282 * @brief Pushes a command into the DMUB outbox ringbuffer
4283 *
4284 * @param rb DMUB outbox ringbuffer
4285 * @param cmd Outbox command
4286 * @return true if not full
4287 * @return false otherwise
4288 */
dmub_rb_out_push_front(struct dmub_rb * rb,const union dmub_rb_out_cmd * cmd)4289 static inline bool dmub_rb_out_push_front(struct dmub_rb *rb,
4290 const union dmub_rb_out_cmd *cmd)
4291 {
4292 uint8_t *dst = (uint8_t *)(rb->base_address) + rb->wrpt;
4293 const uint8_t *src = (const uint8_t *)cmd;
4294
4295 if (dmub_rb_full(rb))
4296 return false;
4297
4298 dmub_memcpy(dst, src, DMUB_RB_CMD_SIZE);
4299
4300 rb->wrpt += DMUB_RB_CMD_SIZE;
4301
4302 if (rb->wrpt >= rb->capacity)
4303 rb->wrpt %= rb->capacity;
4304
4305 return true;
4306 }
4307
4308 /**
4309 * @brief Returns the next unprocessed command in the ringbuffer.
4310 *
4311 * @param rb DMUB ringbuffer
4312 * @param cmd The command to return
4313 * @return true if not empty
4314 * @return false otherwise
4315 */
dmub_rb_front(struct dmub_rb * rb,union dmub_rb_cmd ** cmd)4316 static inline bool dmub_rb_front(struct dmub_rb *rb,
4317 union dmub_rb_cmd **cmd)
4318 {
4319 uint8_t *rb_cmd = (uint8_t *)(rb->base_address) + rb->rptr;
4320
4321 if (dmub_rb_empty(rb))
4322 return false;
4323
4324 *cmd = (union dmub_rb_cmd *)rb_cmd;
4325
4326 return true;
4327 }
4328
4329 /**
4330 * @brief Determines the next ringbuffer offset.
4331 *
4332 * @param rb DMUB inbox ringbuffer
4333 * @param num_cmds Number of commands
4334 * @param next_rptr The next offset in the ringbuffer
4335 */
dmub_rb_get_rptr_with_offset(struct dmub_rb * rb,uint32_t num_cmds,uint32_t * next_rptr)4336 static inline void dmub_rb_get_rptr_with_offset(struct dmub_rb *rb,
4337 uint32_t num_cmds,
4338 uint32_t *next_rptr)
4339 {
4340 *next_rptr = rb->rptr + DMUB_RB_CMD_SIZE * num_cmds;
4341
4342 if (*next_rptr >= rb->capacity)
4343 *next_rptr %= rb->capacity;
4344 }
4345
4346 /**
4347 * @brief Returns a pointer to a command in the inbox.
4348 *
4349 * @param rb DMUB inbox ringbuffer
4350 * @param cmd The inbox command to return
4351 * @param rptr The ringbuffer offset
4352 * @return true if not empty
4353 * @return false otherwise
4354 */
dmub_rb_peek_offset(struct dmub_rb * rb,union dmub_rb_cmd ** cmd,uint32_t rptr)4355 static inline bool dmub_rb_peek_offset(struct dmub_rb *rb,
4356 union dmub_rb_cmd **cmd,
4357 uint32_t rptr)
4358 {
4359 uint8_t *rb_cmd = (uint8_t *)(rb->base_address) + rptr;
4360
4361 if (dmub_rb_empty(rb))
4362 return false;
4363
4364 *cmd = (union dmub_rb_cmd *)rb_cmd;
4365
4366 return true;
4367 }
4368
4369 /**
4370 * @brief Returns the next unprocessed command in the outbox.
4371 *
4372 * @param rb DMUB outbox ringbuffer
4373 * @param cmd The outbox command to return
4374 * @return true if not empty
4375 * @return false otherwise
4376 */
dmub_rb_out_front(struct dmub_rb * rb,union dmub_rb_out_cmd * cmd)4377 static inline bool dmub_rb_out_front(struct dmub_rb *rb,
4378 union dmub_rb_out_cmd *cmd)
4379 {
4380 const uint64_t volatile *src = (const uint64_t volatile *)((uint8_t *)(rb->base_address) + rb->rptr);
4381 uint64_t *dst = (uint64_t *)cmd;
4382 uint8_t i;
4383
4384 if (dmub_rb_empty(rb))
4385 return false;
4386
4387 // copying data
4388 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++)
4389 *dst++ = *src++;
4390
4391 return true;
4392 }
4393
4394 /**
4395 * @brief Removes the front entry in the ringbuffer.
4396 *
4397 * @param rb DMUB ringbuffer
4398 * @return true if the command was removed
4399 * @return false if there were no commands
4400 */
dmub_rb_pop_front(struct dmub_rb * rb)4401 static inline bool dmub_rb_pop_front(struct dmub_rb *rb)
4402 {
4403 if (dmub_rb_empty(rb))
4404 return false;
4405
4406 rb->rptr += DMUB_RB_CMD_SIZE;
4407
4408 if (rb->rptr >= rb->capacity)
4409 rb->rptr %= rb->capacity;
4410
4411 return true;
4412 }
4413
4414 /**
4415 * @brief Flushes commands in the ringbuffer to framebuffer memory.
4416 *
4417 * Avoids a race condition where DMCUB accesses memory while
4418 * there are still writes in flight to framebuffer.
4419 *
4420 * @param rb DMUB ringbuffer
4421 */
dmub_rb_flush_pending(const struct dmub_rb * rb)4422 static inline void dmub_rb_flush_pending(const struct dmub_rb *rb)
4423 {
4424 uint32_t rptr = rb->rptr;
4425 uint32_t wptr = rb->wrpt;
4426
4427 while (rptr != wptr) {
4428 uint64_t *data = (uint64_t *)((uint8_t *)(rb->base_address) + rptr);
4429 uint8_t i;
4430
4431 /* Don't remove this.
4432 * The contents need to actually be read from the ring buffer
4433 * for this function to be effective.
4434 */
4435 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++)
4436 (void)READ_ONCE(*data++);
4437
4438 rptr += DMUB_RB_CMD_SIZE;
4439 if (rptr >= rb->capacity)
4440 rptr %= rb->capacity;
4441 }
4442 }
4443
4444 /**
4445 * @brief Initializes a DMCUB ringbuffer
4446 *
4447 * @param rb DMUB ringbuffer
4448 * @param init_params initial configuration for the ringbuffer
4449 */
dmub_rb_init(struct dmub_rb * rb,struct dmub_rb_init_params * init_params)4450 static inline void dmub_rb_init(struct dmub_rb *rb,
4451 struct dmub_rb_init_params *init_params)
4452 {
4453 rb->base_address = init_params->base_address;
4454 rb->capacity = init_params->capacity;
4455 rb->rptr = init_params->read_ptr;
4456 rb->wrpt = init_params->write_ptr;
4457 }
4458
4459 /**
4460 * @brief Copies output data from in/out commands into the given command.
4461 *
4462 * @param rb DMUB ringbuffer
4463 * @param cmd Command to copy data into
4464 */
dmub_rb_get_return_data(struct dmub_rb * rb,union dmub_rb_cmd * cmd)4465 static inline void dmub_rb_get_return_data(struct dmub_rb *rb,
4466 union dmub_rb_cmd *cmd)
4467 {
4468 // Copy rb entry back into command
4469 uint8_t *rd_ptr = (rb->rptr == 0) ?
4470 (uint8_t *)rb->base_address + rb->capacity - DMUB_RB_CMD_SIZE :
4471 (uint8_t *)rb->base_address + rb->rptr - DMUB_RB_CMD_SIZE;
4472
4473 dmub_memcpy(cmd, rd_ptr, DMUB_RB_CMD_SIZE);
4474 }
4475
4476 #if defined(__cplusplus)
4477 }
4478 #endif
4479
4480 //==============================================================================
4481 //</DMUB_RB>====================================================================
4482 //==============================================================================
4483
4484 #endif /* _DMUB_CMD_H_ */
4485