1// specify test for fd clear/set flip flop
2module test;
3 wire t_q;
4 reg t_clk, t_clk0, t_clk1, t_clk2, t_d, t_clr, t_set;
5
6 fd3noqn i1(t_q0, t_clk2, t_clk2, t_d0, t_clr0, t_set0);
7 fd3noqn i2(t_q1, t_clk2, t_clk2, t_d1, t_clr1, t_set1);
8 fd3noqn i3(t_q, t_clk, t_clk1, t_d, t_clr, t_set);
9
10 initial
11  begin
12   $monitor($stime,, "q=%b, clk=%b, data=%b, clr=%b, set=%b",
13    t_q, t_clk, t_d, t_clr, t_set);
14   // test set/clear logic and delays - set overrides - low assertion
15   #1000 $display("testing set/clear logic"); t_set = 1'bx;
16   #1000 t_set = 0;
17   #1000 t_clr = 0;
18   #1000 t_set = 1;
19   #1000 t_set = 0;
20   #1000 t_set = 1;
21   #1000 t_clr = 1'bx;
22   // test normal logic (set clear must be high)
23   #1000 $display("testing normal logic"); t_clr = 1; t_set = 1; t_d = 0;
24   #1000 t_clk = 1;
25   #1000 t_clk = 0;
26   #1000 t_clk = 1;
27   #1000 t_clk = 0;
28   #1000 t_clk = 1;
29   #1000 t_clk = 0;
30   #1000 t_clk = 1'bx;
31   #1000 t_clk = 0;
32   #1000 t_clk = 1'bz;
33   #1000 t_clk = 0;
34   #1000 t_clk = 1'bx;
35   #1000 t_clk = 1;
36   #1000 t_d = 1; t_clk = 1;
37   #1000 t_clk = 0;
38   #1000 t_clk = 1;
39   #1000 t_clk = 0;
40   #1000 t_clk = 1;
41   #1000 t_clk = 0;
42   #100 t_clk = 1'bx;
43   #1000 t_clk = 0;
44   #1000 t_clk = 1'bz;
45   #1000 t_clk = 0;
46   #1000 t_clk = 1'bx;
47   #1000 t_clk = 1;
48   // test setup
49   #30 t_clk = 0;
50   #30 t_d = 1;
51   #30 t_clk = 1;
52   #30 t_d = 0;
53   #30 t_clk = 0;
54   #30 t_d = 1;
55   #30 t_clk = 1; t_d = 0; t_clk = 0; t_d = 1; t_clk = 1;
56   #100 t_clk = 0; t_clk1 = 0;
57   #100 t_clk1 = 1;
58   #2000 t_clk = 1;
59
60   /* ---
61   #100 t_d = 1; t_clk = 1;
62   #100 t_d = 1;
63   #450 t_clk = 1;
64   #550 t_clk = 0;
65   #200 t_d = 0;
66
67   #350 t_clk = 1;
68   #550 t_clk = 0;
69
70   #550 t_clk = 1;
71   #550 t_clk = 0;
72  --- */
73  end
74endmodule
75
76module fd3noqn(q, clk, clk1, d, clr, set);
77 output q;
78 input clk, clk1, d, clr, set;
79 // wire xxx;
80
81 specify
82  specparam tRise_clk_q = 140, tFall_clk_q = 250;
83  specparam tRise_control = 40, tFall_control= 50;
84  specparam tSetup=70, tHold=50;
85  specparam tWpos=600, tWneg=500;
86
87  // paths
88  (clk => q) = (tRise_clk_q, tFall_clk_q);
89  (clr,set *> q) = (tRise_control, tFall_control);
90
91  // timing checks
92  // setup time: d is reference, clk is data - setup > posedge clk - last data
93  // data must be stable > setup when clock triggers (pos. edge)
94  // setup(ref, data, >setup);
95  // $setup(d, posedge clk, tSetup);
96
97  // hold time:  clk is reference, d is data - hold > d change after last clk
98  // hold(ref, data, >hold);
99  // $hold(posedge clk, d, tHold);
100
101  $setuphold(posedge clk, d, tSetup, tHold);
102
103  $width(posedge clk, tWpos);
104  $width(negedge clk, tWneg);
105  $period(posedge clk, 1000:1200:1400);
106  $skew(posedge clk1, posedge clk, 50);
107  $recovery(posedge d, clk, 200);
108 endspecify
109
110 xl_fd3 /* #10 */ i0(q, d, clk, clr, set);
111 // buf i1(q, xxx);
112 // not i2(qn, xxx);
113endmodule
114
115primitive xl_fd3(q, d, clk, clr, set);
116 output q; reg q;
117 input d, clk, clr, set;
118
119 table
120  // d  clk  clr  set  :  q  :  q
121  // -  ---  ---  ---  -  -  -  -
122  // set/clear low assertion
123     ?   ?    ?    0   :  ?  :  1 ;
124     ?   ?    ?    x   :  ?  :  x ;
125     ?   ?    0    1   :  ?  :  0 ;
126     ?   ?    x    1   :  ?  :  x ;
127
128     0   r    1    1   :  ?  :  0 ;
129     1   r    1    1   :  ?  :  1 ;
130     x   r    1    1   :  ?  :  x ;
131
132     ?   f    1    1   :  ?  :  - ;
133     ?  (x?)  1    1   :  ?  :  - ;
134     ?  (?x)  1    1   :  ?  :  - ;
135     *   ?    1    1   :  ?  :  - ;
136     ?   ?    r    1   :  ?  :  - ;
137     ?   ?    1    r   :  ?  :  - ;
138 endtable
139endprimitive
140