1 /* 2 * Copyright © 2010 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the 6 * "Software"), to deal in the Software without restriction, including 7 * without limitation the rights to use, copy, modify, merge, publish, 8 * distribute, sub license, and/or sell copies of the Software, and to 9 * permit persons to whom the Software is furnished to do so, subject to 10 * the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the 13 * next paragraph) shall be included in all copies or substantial portions 14 * of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 19 * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR 20 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 21 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 22 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: 25 * Zhou chang <chang.zhou@intel.com> 26 * 27 */ 28 29 #ifndef _I965_ENCODER_H_ 30 #define _I965_ENCODER_H_ 31 32 #include <drm.h> 33 #include <i915_drm.h> 34 #include <intel_bufmgr.h> 35 36 #include "i965_structs.h" 37 #include "i965_drv_video.h" 38 39 #define I965_BRC_NONE 0 40 #define I965_BRC_CBR 1 41 #define I965_BRC_VBR 2 42 #define I965_BRC_CQP 3 43 44 #define WIDTH_IN_MACROBLOCKS(width) (ALIGN(width, 16) >> 4) 45 #define HEIGHT_IN_MACROBLOCKS(height) (ALIGN(height, 16) >> 4) 46 #define MAX_TEMPORAL_LAYERS 4 47 48 struct intel_roi { 49 short left; 50 short right; 51 short top; 52 short bottom; 53 54 char value; 55 }; 56 57 struct intel_fraction { 58 unsigned int num; 59 unsigned int den; 60 }; 61 62 struct intel_encoder_context { 63 struct hw_context base; 64 VADriverContextP ctx; 65 int codec; 66 VASurfaceID input_yuv_surface; 67 unsigned int rate_control_mode; 68 unsigned int quality_level; 69 unsigned int quality_range; 70 unsigned int num_frames_in_sequence; 71 unsigned int frame_width_in_pixel; 72 unsigned int frame_height_in_pixel; 73 unsigned int max_slice_or_seg_num; 74 unsigned int codec_level; 75 76 struct { 77 unsigned int num_layers; 78 unsigned int size_frame_layer_ids; 79 unsigned int frame_layer_ids[32]; 80 unsigned int curr_frame_layer_id; 81 } layer; 82 83 struct { 84 unsigned short gop_size; 85 unsigned short num_iframes_in_gop; 86 unsigned short num_pframes_in_gop; 87 unsigned short num_bframes_in_gop; 88 unsigned int bits_per_second[MAX_TEMPORAL_LAYERS]; 89 struct intel_fraction framerate[MAX_TEMPORAL_LAYERS]; 90 unsigned int mb_rate_control[MAX_TEMPORAL_LAYERS]; 91 unsigned int target_percentage[MAX_TEMPORAL_LAYERS]; 92 unsigned int hrd_buffer_size; 93 unsigned int hrd_initial_buffer_fullness; 94 unsigned int window_size; 95 unsigned int initial_qp; 96 unsigned int min_qp; 97 unsigned int need_reset; 98 99 unsigned int num_roi; 100 unsigned int roi_max_delta_qp; 101 unsigned int roi_min_delta_qp; 102 unsigned int roi_value_is_qp_delta; 103 struct intel_roi roi[I965_MAX_NUM_ROI_REGIONS]; 104 } brc; 105 106 void *vme_context; 107 void *mfc_context; 108 void *enc_priv_state; 109 110 unsigned int is_tmp_id: 1; 111 unsigned int low_power_mode: 1; 112 unsigned int soft_batch_force: 1; 113 unsigned int context_roi: 1; 114 unsigned int is_new_sequence: 1; /* Currently only valid for H.264, TODO for other codecs */ 115 116 unsigned int fei_enabled: 1; 117 unsigned int fei_function_mode; /* configured VA_FEI_FUNCTION_XXX */ 118 119 unsigned int preenc_enabled: 1; 120 121 void (*vme_context_destroy)(void *vme_context); 122 VAStatus(*vme_pipeline)(VADriverContextP ctx, 123 VAProfile profile, 124 struct encode_state *encode_state, 125 struct intel_encoder_context *encoder_context); 126 void (*mfc_context_destroy)(void *mfc_context); 127 VAStatus(*mfc_pipeline)(VADriverContextP ctx, 128 VAProfile profile, 129 struct encode_state *encode_state, 130 struct intel_encoder_context *encoder_context); 131 void (*mfc_brc_prepare)(struct encode_state *encode_state, 132 struct intel_encoder_context *encoder_context); 133 134 VAStatus(*get_status)(VADriverContextP ctx, 135 struct intel_encoder_context *encoder_context, 136 struct i965_coded_buffer_segment *coded_buffer_segment); 137 }; 138 139 extern struct hw_context * 140 gen75_enc_hw_context_init(VADriverContextP ctx, struct object_config *obj_config); 141 142 extern struct hw_context * 143 gen8_enc_hw_context_init(VADriverContextP ctx, struct object_config *obj_config); 144 145 extern struct hw_context * 146 gen9_enc_hw_context_init(VADriverContextP ctx, struct object_config *obj_config); 147 #endif /* _I965_ENCODER_H_ */ 148 149 150