1 /******************************************************************************** 2 ** Copyright (c) 1998-2000 Microsoft Corporation. All Rights Reserved. 3 ** 4 ** Portions Copyright (c) 1998-1999 Intel Corporation 5 ** 6 ********************************************************************************/ 7 8 /* The file ichreg.h was reviewed by LCA in June 2011 and is acceptable for use by Microsoft. */ 9 10 #ifndef _ICHREG_H_ 11 #define _ICHREG_H_ 12 13 // We define the offsets like PI_BDBAR as ULONG (instead of UCHAR) for run 14 // time efficiency. 15 16 // CoDec AC97 register space offsets 17 const ULONG PRIMARY_CODEC = 0x00; 18 const ULONG SECONDARY_CODEC = 0x80; 19 20 // Native audio bus master control registers (offsets) 21 const ULONG PI_BDBAR = 0x00; // PCM In Buffer Descriptor Base Address Register 22 const ULONG PI_CIV = 0x04; // PCM In Current Index Value 23 const ULONG PI_LVI = 0x05; // PCM In Last Valid Index 24 const ULONG PI_SR = 0x06; // PCM In Status Register 25 const ULONG PI_PICB = 0x08; // PCM In Position In Current Buffer 26 const ULONG PI_PIV = 0x0A; // PCM In Prefetch Index Value 27 const ULONG PI_CR = 0x0B; // PCM In Control Register 28 const ULONG PO_BDBAR = 0x10; // PCM Out Buffer Descriptor Base Address Register 29 const ULONG PO_CIV = 0x14; // PCM Out Current Index Value 30 const ULONG PO_LVI = 0x15; // PCM Out Last Valid Index 31 const ULONG PO_SR = 0x16; // PCM Out Status Register 32 const ULONG PO_PICB = 0x18; // PCM Out Position In Current Buffer 33 const ULONG PO_PIV = 0x1A; // PCM Out Prefetch Index Value 34 const ULONG PO_CR = 0x1B; // PCM Out Control Register 35 const ULONG MC_BDBAR = 0x20; // Mic In Buffer Descriptor Base Address Register 36 const ULONG MC_CIV = 0x24; // Mic In Current Index Value 37 const ULONG MC_LVI = 0x25; // Mic In Last Valid Index 38 const ULONG MC_SR = 0x26; // Mic In Status Register 39 const ULONG MC_PICB = 0x28; // Mic In Position In Current Buffer 40 const ULONG MC_PIV = 0x2A; // Mic In Prefetch Index Value 41 const ULONG MC_CR = 0x2B; // Mic In Control Register 42 const ULONG GLOB_CNT = 0x2C; // Global Control 43 const ULONG GLOB_STA = 0x30; // Global Status 44 const ULONG CAS = 0x34; // Codec Access Semiphore 45 46 // Defines for relative accesses (offsets) 47 const ULONG X_PI_BASE = 0x00; // PCM In Base 48 const ULONG X_PO_BASE = 0x10; // PCM Out Base 49 const ULONG X_MC_BASE = 0x20; // Mic In Base 50 const ULONG X_BDBAR = 0x00; // Buffer Descriptor Base Address Register 51 const ULONG X_CIV = 0x04; // Current Index Value 52 const ULONG X_LVI = 0x05; // Last Valid Index 53 const ULONG X_SR = 0x06; // Status Register 54 const ULONG X_PICB = 0x08; // Position In Current Buffer 55 const ULONG X_PIV = 0x0A; // Prefetch Index Value 56 const ULONG X_CR = 0x0B; // Control Register 57 58 // Bits defined in satatus register (*_SR) 59 const USHORT SR_FIFOE = 0x0010; // FIFO error 60 const USHORT SR_BCIS = 0x0008; // Buffer Completeion Interrupt Status 61 const USHORT SR_LVBCI = 0x0004; // Last Valid Buffer Completion Interrupt 62 const USHORT SR_CELV = 0x0002; // Last Valid Buffer Completion Interrupt 63 64 // Global Control bit defines (GLOB_CNT) 65 const ULONG GLOB_CNT_PCM6 = 0x00200000; // 6 Channel Mode bit 66 const ULONG GLOB_CNT_PCM4 = 0x00100000; // 4 Channel Mode bit 67 const ULONG GLOB_CNT_SRIE = 0x00000020; // Secondary Resume Interrupt Enable 68 const ULONG GLOB_CNT_PRIE = 0x00000010; // Primary Resume Interrupt Enable 69 const ULONG GLOB_CNT_ACLOFF = 0x00000008; // ACLINK Off 70 const ULONG GLOB_CNT_WARM = 0x00000004; // AC97 Warm Reset 71 const ULONG GLOB_CNT_COLD = 0x00000002; // AC97 Cold Reset 72 const ULONG GLOB_CNT_GIE = 0x00000001; // GPI Interrupt Enable 73 74 // Global Status bit defines (GLOB_STA) 75 const ULONG GLOB_STA_MC6 = 0x00200000; // Multichannel Capability 6 channel 76 const ULONG GLOB_STA_MC4 = 0x00100000; // Multichannel Capability 4 channel 77 const ULONG GLOB_STA_MD3 = 0x00020000; // Modem Power Down Semiphore 78 const ULONG GLOB_STA_AD3 = 0x00010000; // Audio Power Down Semiphore 79 const ULONG GLOB_STA_RCS = 0x00008000; // Read Completion Status 80 const ULONG GLOB_STA_B3S12 = 0x00004000; // Bit 3 Slot 12 81 const ULONG GLOB_STA_B2S12 = 0x00002000; // Bit 2 Slot 12 82 const ULONG GLOB_STA_B1S12 = 0x00001000; // Bit 1 Slot 12 83 const ULONG GLOB_STA_SRI = 0x00000800; // Secondary Resume Interrupt 84 const ULONG GLOB_STA_PRI = 0x00000400; // Primary Resume Interrupt 85 const ULONG GLOB_STA_SCR = 0x00000200; // Secondary Codec Ready 86 const ULONG GLOB_STA_PCR = 0x00000100; // Primary Codec Ready 87 const ULONG GLOB_STA_MINT = 0x00000080; // Mic In Interrupt 88 const ULONG GLOB_STA_POINT = 0x00000040; // PCM Out Interrupt 89 const ULONG GLOB_STA_PIINT = 0x00000020; // PCM In Interrupt 90 const ULONG GLOB_STA_MOINT = 0x00000004; // Modem Out Interrupt 91 92 // CoDec Access Semiphore bit defines (CAS) 93 const UCHAR CAS_CAS = 0x01; // Codec Access Semiphore Bit 94 95 // DMA Engine Control Register (*_CR) bit defines 96 const UCHAR CR_IOCE = 0x10; // Interrupt On Completion Enable 97 const UCHAR CR_FEIE = 0x08; // FIFO Error Interrupt Enable 98 const UCHAR CR_LVBIE = 0x04; // Last Valid Buffer Interrupt Enable 99 const UCHAR CR_RPBM = 0x01; // Run/Pause Bus Master 100 const UCHAR CR_RR = 0x02; // Reset Registers (RR) 101 102 // BDL policy bits 103 const USHORT IOC_ENABLE = 0x8000; 104 const USHORT BUP_SET = 0x4000; 105 106 #endif //_ICHREG_H_ 107 108