1 /* $OpenBSD: if_epic_pci.c,v 1.18 2024/05/24 06:02:53 jsg Exp $ */
2 /* $NetBSD: if_epic_pci.c,v 1.28 2005/02/27 00:27:32 perry Exp $ */
3
4 /*-
5 * Copyright (c) 1998, 1999 The NetBSD Foundation, Inc.
6 * All rights reserved.
7 *
8 * This code is derived from software contributed to The NetBSD Foundation
9 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
10 * NASA Ames Research Center.
11 *
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions
14 * are met:
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in the
19 * documentation and/or other materials provided with the distribution.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
32 */
33
34 /*
35 * PCI bus front-end for the Standard Microsystems Corp. 83C170
36 * Ethernet PCI Integrated Controller (EPIC/100) driver.
37 */
38
39 #include <sys/param.h>
40 #include <sys/systm.h>
41 #include <sys/device.h>
42
43 #include <net/if.h>
44 #include <net/if_media.h>
45
46 #include <netinet/in.h>
47 #include <netinet/if_ether.h>
48
49 #include <machine/bus.h>
50 #include <machine/intr.h>
51
52 #include <dev/mii/miivar.h>
53
54 #include <dev/ic/smc83c170reg.h>
55 #include <dev/ic/smc83c170var.h>
56
57 #include <dev/pci/pcivar.h>
58 #include <dev/pci/pcireg.h>
59 #include <dev/pci/pcidevs.h>
60
61 /*
62 * PCI configuration space registers used by the EPIC.
63 */
64 #define EPIC_PCI_IOBA 0x10 /* i/o mapped base */
65 #define EPIC_PCI_MMBA 0x14 /* memory mapped base */
66
67 struct epic_pci_softc {
68 struct epic_softc sc_epic; /* real EPIC softc */
69
70 /* PCI-specific goo. */
71 void *sc_ih; /* interrupt handle */
72 };
73
74 int epic_pci_match(struct device *, void *, void *);
75 void epic_pci_attach(struct device *, struct device *, void *);
76
77 const struct cfattach epic_pci_ca = {
78 sizeof(struct epic_pci_softc), epic_pci_match, epic_pci_attach
79 };
80
81 const struct pci_matchid epic_pci_devices[] = {
82 { PCI_VENDOR_SMC, PCI_PRODUCT_SMC_83C170 },
83 { PCI_VENDOR_SMC, PCI_PRODUCT_SMC_83C175 },
84 };
85
86 static const struct epic_pci_subsys_info {
87 pcireg_t subsysid;
88 int flags;
89 } epic_pci_subsys_info[] = {
90 { PCI_ID_CODE(PCI_VENDOR_SMC, 0xa015), /* SMC9432BTX */
91 EPIC_HAS_BNC },
92 { PCI_ID_CODE(PCI_VENDOR_SMC, 0xa024), /* SMC9432BTX1 */
93 EPIC_HAS_BNC },
94 { PCI_ID_CODE(PCI_VENDOR_SMC, 0xa016), /* SMC9432FTX */
95 EPIC_HAS_MII_FIBER | EPIC_DUPLEXLED_ON_694 },
96 { 0xffffffff,
97 0 }
98 };
99
100 static const struct epic_pci_subsys_info *
epic_pci_subsys_lookup(const struct pci_attach_args * pa)101 epic_pci_subsys_lookup(const struct pci_attach_args *pa)
102 {
103 pci_chipset_tag_t pc = pa->pa_pc;
104 pcireg_t reg;
105 const struct epic_pci_subsys_info *esp;
106
107 reg = pci_conf_read(pc, pa->pa_tag, PCI_SUBSYS_ID_REG);
108
109 for (esp = epic_pci_subsys_info; esp->subsysid != 0xffffffff; esp++)
110 if (esp->subsysid == reg)
111 return (esp);
112
113 return (NULL);
114 }
115
116 int
epic_pci_match(struct device * parent,void * match,void * aux)117 epic_pci_match(struct device *parent, void *match, void *aux)
118 {
119 return (pci_matchbyid((struct pci_attach_args *)aux, epic_pci_devices,
120 nitems(epic_pci_devices)));
121 }
122
123 void
epic_pci_attach(struct device * parent,struct device * self,void * aux)124 epic_pci_attach(struct device *parent, struct device *self, void *aux)
125 {
126 struct epic_pci_softc *psc = (struct epic_pci_softc *)self;
127 struct epic_softc *sc = &psc->sc_epic;
128 struct pci_attach_args *pa = aux;
129 pci_chipset_tag_t pc = pa->pa_pc;
130 pci_intr_handle_t ih;
131 const char *intrstr = NULL;
132 const struct epic_pci_subsys_info *esp;
133 bus_space_tag_t iot, memt;
134 bus_space_handle_t ioh, memh;
135 int ioh_valid, memh_valid;
136
137 pci_set_powerstate(pc, pa->pa_tag, PCI_PMCSR_STATE_D0);
138
139 /*
140 * Map the device.
141 */
142 ioh_valid = (pci_mapreg_map(pa, EPIC_PCI_IOBA,
143 PCI_MAPREG_TYPE_IO, 0,
144 &iot, &ioh, NULL, NULL, 0) == 0);
145 memh_valid = (pci_mapreg_map(pa, EPIC_PCI_MMBA,
146 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0,
147 &memt, &memh, NULL, NULL, 0) == 0);
148
149 if (memh_valid) {
150 sc->sc_st = memt;
151 sc->sc_sh = memh;
152 } else if (ioh_valid) {
153 sc->sc_st = iot;
154 sc->sc_sh = ioh;
155 } else {
156 printf(": unable to map device registers\n");
157 return;
158 }
159
160 sc->sc_dmat = pa->pa_dmat;
161
162 /*
163 * Map and establish our interrupt.
164 */
165 if (pci_intr_map(pa, &ih)) {
166 printf(": unable to map interrupt\n");
167 return;
168 }
169 intrstr = pci_intr_string(pc, ih);
170 psc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, epic_intr, sc,
171 self->dv_xname);
172 if (psc->sc_ih == NULL) {
173 printf(": unable to establish interrupt");
174 if (intrstr != NULL)
175 printf(" at %s", intrstr);
176 printf("\n");
177 return;
178 }
179
180 esp = epic_pci_subsys_lookup(pa);
181 if (esp)
182 sc->sc_hwflags = esp->flags;
183
184 /*
185 * Finish off the attach.
186 */
187 epic_attach(sc, intrstr);
188 }
189