1 /* $NetBSD: mcp23xxxgpio_spi.c,v 1.4 2022/01/19 05:21:44 thorpej Exp $ */
2
3 /*-
4 * Copyright (c) 2014, 2022 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Frank Kardel, and by Jason R. Thorpe.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 */
31
32 #include <sys/cdefs.h>
33 __KERNEL_RCSID(0, "$NetBSD: mcp23xxxgpio_spi.c,v 1.4 2022/01/19 05:21:44 thorpej Exp $");
34
35 /*
36 * Driver for Microchip serial I/O expanders:
37 *
38 * MCP23S08 8-bit, SPI interface
39 * MCP23S17 16-bit, SPI interface
40 * MCP23S18 16-bit (open-drain outputs), SPI interface
41 *
42 * Data sheet:
43 *
44 * https://ww1.microchip.com/downloads/en/DeviceDoc/20001952C.pdf
45 */
46
47 #include <sys/types.h>
48 #include <sys/bitops.h>
49 #include <sys/device.h>
50 #include <sys/kernel.h>
51 #include <sys/mutex.h>
52
53 #include <dev/ic/mcp23xxxgpioreg.h>
54 #include <dev/ic/mcp23xxxgpiovar.h>
55
56 #include <dev/spi/spivar.h>
57
58 /*
59 * Multi-chip-on-select configurations appear to the upper layers like
60 * additional GPIO banks; mixing different chip types on the same chip
61 * select is not allowed.
62 *
63 * Some chips have 2 banks per chip, and we have up to 8 chips per chip
64 * select, it's a total of 16 banks per chip select / driver instance.
65 */
66 #define MCPGPIO_SPI_MAXBANKS 16
67
68 struct mcpgpio_spi_softc {
69 struct mcpgpio_softc sc_mcpgpio;
70
71 kmutex_t sc_mutex;
72 struct spi_handle *sc_sh;
73 uint8_t sc_ha[MCPGPIO_SPI_MAXBANKS];
74 };
75
76 /*
77 * SPI-specific commands (the serial interface on the I2C flavor of
78 * the chip uses the I2C protocol to infer this information). Careful
79 * readers will note that this ends up being exactly the same bits
80 * on the serial interface that the I2C flavor of the chip uses.
81 *
82 * The SPI version can have up to 4 (or 8) chips per chip-select, demuxed
83 * using the hardware address (selected by tying the 2 or 3 HA pins high/low
84 * as desired).
85 */
86 #define OP_READ(ha) (0x41 | ((ha) << 1))
87 #define OP_WRITE(ha) (0x40 | ((ha) << 1))
88
89 #define MCPGPIO_TO_SPI(sc) \
90 container_of((sc), struct mcpgpio_spi_softc, sc_mcpgpio)
91
92 #if 0
93 static const struct mcpgpio_variant mcp23s08 = {
94 .name = "MCP23S08",
95 .type = MCPGPIO_TYPE_23x08,
96 };
97 #endif
98
99 static const struct mcpgpio_variant mcp23s17 = {
100 .name = "MCP23S17",
101 .type = MCPGPIO_TYPE_23x17,
102 };
103
104 #if 0
105 static const struct mcpgpio_variant mcp23s18 = {
106 .name = "MCP23S18",
107 .type = MCPGPIO_TYPE_23x18,
108 };
109 #endif
110
111 #if 0
112 static const struct device_compatible_entry compat_data[] = {
113 { .compat = "microchip,mcp23s08", .data = &mcp23s08 },
114 { .compat = "microchip,mcp23s17", .data = &mcp23s17 },
115 { .compat = "microchip,mcp23s18", .data = &mcp23s18 },
116 DEVICE_COMPAT_EOL
117 };
118 #endif
119
120 static int
mcpgpio_spi_lock(struct mcpgpio_softc * sc)121 mcpgpio_spi_lock(struct mcpgpio_softc *sc)
122 {
123 struct mcpgpio_spi_softc *ssc = MCPGPIO_TO_SPI(sc);
124
125 mutex_enter(&ssc->sc_mutex);
126 return 0;
127 }
128
129 static void
mcpgpio_spi_unlock(struct mcpgpio_softc * sc)130 mcpgpio_spi_unlock(struct mcpgpio_softc *sc)
131 {
132 struct mcpgpio_spi_softc *ssc = MCPGPIO_TO_SPI(sc);
133
134 mutex_exit(&ssc->sc_mutex);
135 }
136
137 static int
mcpgpio_spi_read(struct mcpgpio_softc * sc,unsigned int bank,uint8_t reg,uint8_t * valp)138 mcpgpio_spi_read(struct mcpgpio_softc *sc, unsigned int bank,
139 uint8_t reg, uint8_t *valp)
140 {
141 struct mcpgpio_spi_softc *ssc = MCPGPIO_TO_SPI(sc);
142 uint8_t buf[2];
143
144 KASSERT(bank < (sc->sc_npins >> 3));
145
146 buf[0] = OP_READ(ssc->sc_ha[bank]);
147 buf[1] = reg;
148
149 return spi_send_recv(ssc->sc_sh, 2, buf, 1, valp);
150 }
151
152 static int
mcpgpio_spi_write(struct mcpgpio_softc * sc,unsigned int bank,uint8_t reg,uint8_t val)153 mcpgpio_spi_write(struct mcpgpio_softc *sc, unsigned int bank,
154 uint8_t reg, uint8_t val)
155 {
156 struct mcpgpio_spi_softc *ssc = MCPGPIO_TO_SPI(sc);
157 uint8_t buf[3];
158
159 KASSERT(bank < (sc->sc_npins >> 3));
160
161 buf[0] = OP_WRITE(ssc->sc_ha[bank]);
162 buf[1] = reg;
163 buf[2] = val;
164
165 return spi_send(ssc->sc_sh, 3, buf);
166 }
167
168 static const struct mcpgpio_accessops mcpgpio_spi_accessops = {
169 .lock = mcpgpio_spi_lock,
170 .unlock = mcpgpio_spi_unlock,
171 .read = mcpgpio_spi_read,
172 .write = mcpgpio_spi_write,
173 };
174
175 static int
mcpgpio_spi_match(device_t parent,cfdata_t cf,void * aux)176 mcpgpio_spi_match(device_t parent, cfdata_t cf, void *aux)
177 {
178
179 /* MCP23S17 has no way to detect it! */
180
181 return 1;
182 }
183
184 static void
mcpgpio_spi_attach(device_t parent,device_t self,void * aux)185 mcpgpio_spi_attach(device_t parent, device_t self, void *aux)
186 {
187 struct mcpgpio_spi_softc *ssc = device_private(self);
188 struct mcpgpio_softc *sc = &ssc->sc_mcpgpio;
189 struct spi_attach_args *sa = aux;
190 uint32_t spi_present_mask;
191 int bank, nchips, error, ha;
192
193 mutex_init(&ssc->sc_mutex, MUTEX_DEFAULT, IPL_NONE);
194 ssc->sc_sh = sa->sa_handle;
195
196 sc->sc_dev = self;
197 sc->sc_variant = &mcp23s17; /* XXX */
198 sc->sc_iocon = IOCON_HAEN | IOCON_SEQOP;
199 sc->sc_npins = MCP23x17_GPIO_NPINS;
200 sc->sc_accessops = &mcpgpio_spi_accessops;
201
202 aprint_naive("\n");
203 aprint_normal(": %s I/O Expander\n", sc->sc_variant->name);
204
205 /* run at 10MHz */
206 error = spi_configure(self, sa->sa_handle, SPI_MODE_0, 10000000);
207 if (error) {
208 return;
209 }
210
211 /*
212 * Before we decode the topology information, ensure each
213 * chip has IOCON.HAEN set so that it will actually decode
214 * the address bits.
215 *
216 * XXX Going on blind faith that IOCON.BANK is already 0.
217 */
218 if (sc->sc_variant->type == MCPGPIO_TYPE_23x08) {
219 error = mcpgpio_spi_write(sc, 0, REG_IOCON, sc->sc_iocon);
220 } else {
221 error = mcpgpio_spi_write(sc, 0, REGADDR_BANK0(0, REG_IOCON),
222 sc->sc_iocon);
223 if (error == 0) {
224 error = mcpgpio_spi_write(sc, 1,
225 REGADDR_BANK0(1, REG_IOCON), sc->sc_iocon);
226 }
227 }
228 if (error) {
229 aprint_error_dev(self,
230 "unable to initialize IOCON, error=%d\n", error);
231 return;
232 }
233
234 #if 0
235 /*
236 * The number of devices sharing this chip select, along
237 * with their assigned addresses, is encoded in the
238 * "microchip,spi-present-mask" property. Note that this
239 * device tree binding means that we will just have a
240 * single driver instance for however many chips are on
241 * this chip select. We treat them logically as banks.
242 */
243 if (of_getprop_uint32(phandle, "microchip,spi-present-mask",
244 &spi_present_mask) != 0 ||
245 of_getprop_uint32(phandle, "mcp,spi-present-mask",
246 &spi_present_mask) != 0) {
247 aprint_error_dev(self,
248 "missing \"microchip,spi-present-mask\" property\n");
249 return false;
250 }
251 #else
252 /*
253 * XXX Until we support decoding the DT properties that
254 * XXX give us the topology information.
255 */
256 spi_present_mask = __BIT(device_cfdata(self)->cf_flags & 0x7);
257 #endif
258
259 /*
260 * The 23S08 has 2 address pins (4 devices per chip select),
261 * and the others have 3 (8 devices per chip select).
262 */
263 if (spi_present_mask == 0 ||
264 (sc->sc_variant->type == MCPGPIO_TYPE_23x08 &&
265 spi_present_mask >= __BIT(4)) ||
266 (sc->sc_variant->type != MCPGPIO_TYPE_23x08 &&
267 spi_present_mask >= __BIT(8))) {
268 aprint_error_dev(self,
269 "invalid \"microchip,spi-present-mask\" value: 0x%08x\n",
270 spi_present_mask);
271 return;
272 }
273 nchips = popcount32(spi_present_mask);
274 sc->sc_npins = nchips *
275 (sc->sc_variant->type == MCPGPIO_TYPE_23x08 ? MCP23x08_GPIO_NPINS
276 : MCP23x17_GPIO_NPINS);
277
278 /* Record the hardware addresses for each logical bank of 8 pins. */
279 for (bank = 0; spi_present_mask != 0; spi_present_mask &= ~__BIT(ha)) {
280 int ha_first, ha_last;
281
282 ha = ffs32(spi_present_mask) - 1;
283 ha_first = bank * MCPGPIO_PINS_PER_BANK;
284 ssc->sc_ha[bank++] = ha;
285 if (sc->sc_variant->type != MCPGPIO_TYPE_23x08) {
286 ssc->sc_ha[bank++] = ha;
287 }
288 ha_last = (bank * MCPGPIO_PINS_PER_BANK) - 1;
289 aprint_verbose_dev(self, "pins %d..%d at HA %d\n",
290 ha_first, ha_last, ha);
291 }
292 KASSERT((bank * MCPGPIO_PINS_PER_BANK) == sc->sc_npins);
293
294 mcpgpio_attach(sc);
295 }
296
297 CFATTACH_DECL_NEW(mcpgpio_spi, sizeof(struct mcpgpio_spi_softc),
298 mcpgpio_spi_match, mcpgpio_spi_attach, NULL, NULL);
299