1 /* Copyright (C) 2009-2021 Free Software Foundation, Inc. 2 3 This file is part of GDB. 4 5 This program is free software; you can redistribute it and/or modify 6 it under the terms of the GNU General Public License as published by 7 the Free Software Foundation; either version 3 of the License, or 8 (at your option) any later version. 9 10 This program is distributed in the hope that it will be useful, 11 but WITHOUT ANY WARRANTY; without even the implied warranty of 12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 GNU General Public License for more details. 14 15 You should have received a copy of the GNU General Public License 16 along with this program. If not, see <http://www.gnu.org/licenses/>. */ 17 18 #ifndef NAT_MIPS_LINUX_WATCH_H 19 #define NAT_MIPS_LINUX_WATCH_H 20 21 #include <asm/ptrace.h> 22 #include "gdbsupport/break-common.h" 23 24 #define MAX_DEBUG_REGISTER 8 25 26 /* If macro PTRACE_GET_WATCH_REGS is not defined, kernel header doesn't 27 have hardware watchpoint-related structures. Define them below. */ 28 29 #ifndef PTRACE_GET_WATCH_REGS 30 # define PTRACE_GET_WATCH_REGS 0xd0 31 # define PTRACE_SET_WATCH_REGS 0xd1 32 33 enum pt_watch_style { 34 pt_watch_style_mips32, 35 pt_watch_style_mips64 36 }; 37 38 /* A value of zero in a watchlo indicates that it is available. */ 39 40 struct mips32_watch_regs 41 { 42 uint32_t watchlo[MAX_DEBUG_REGISTER]; 43 /* Lower 16 bits of watchhi. */ 44 uint16_t watchhi[MAX_DEBUG_REGISTER]; 45 /* Valid mask and I R W bits. 46 * bit 0 -- 1 if W bit is usable. 47 * bit 1 -- 1 if R bit is usable. 48 * bit 2 -- 1 if I bit is usable. 49 * bits 3 - 11 -- Valid watchhi mask bits. 50 */ 51 uint16_t watch_masks[MAX_DEBUG_REGISTER]; 52 /* The number of valid watch register pairs. */ 53 uint32_t num_valid; 54 /* There is confusion across gcc versions about structure alignment, 55 so we force 8 byte alignment for these structures so they match 56 the kernel even if it was build with a different gcc version. */ 57 } __attribute__ ((aligned (8))); 58 59 struct mips64_watch_regs 60 { 61 uint64_t watchlo[MAX_DEBUG_REGISTER]; 62 uint16_t watchhi[MAX_DEBUG_REGISTER]; 63 uint16_t watch_masks[MAX_DEBUG_REGISTER]; 64 uint32_t num_valid; 65 } __attribute__ ((aligned (8))); 66 67 struct pt_watch_regs 68 { 69 enum pt_watch_style style; 70 union 71 { 72 struct mips32_watch_regs mips32; 73 struct mips64_watch_regs mips64; 74 }; 75 }; 76 77 #endif /* !PTRACE_GET_WATCH_REGS */ 78 79 #define W_BIT 0 80 #define R_BIT 1 81 #define I_BIT 2 82 83 #define W_MASK (1 << W_BIT) 84 #define R_MASK (1 << R_BIT) 85 #define I_MASK (1 << I_BIT) 86 87 #define IRW_MASK (I_MASK | R_MASK | W_MASK) 88 89 /* We keep list of all watchpoints we should install and calculate the 90 watch register values each time the list changes. This allows for 91 easy sharing of watch registers for more than one watchpoint. */ 92 93 struct mips_watchpoint 94 { 95 CORE_ADDR addr; 96 int len; 97 enum target_hw_bp_type type; 98 struct mips_watchpoint *next; 99 }; 100 101 uint32_t mips_linux_watch_get_num_valid (struct pt_watch_regs *regs); 102 uint32_t mips_linux_watch_get_irw_mask (struct pt_watch_regs *regs, int n); 103 CORE_ADDR mips_linux_watch_get_watchlo (struct pt_watch_regs *regs, int n); 104 void mips_linux_watch_set_watchlo (struct pt_watch_regs *regs, int n, 105 CORE_ADDR value); 106 uint32_t mips_linux_watch_get_watchhi (struct pt_watch_regs *regs, int n); 107 void mips_linux_watch_set_watchhi (struct pt_watch_regs *regs, int n, 108 uint16_t value); 109 int mips_linux_watch_try_one_watch (struct pt_watch_regs *regs, 110 CORE_ADDR addr, int len, uint32_t irw); 111 void mips_linux_watch_populate_regs (struct mips_watchpoint *current_watches, 112 struct pt_watch_regs *regs); 113 uint32_t mips_linux_watch_type_to_irw (enum target_hw_bp_type type); 114 115 int mips_linux_read_watch_registers (long lwpid, 116 struct pt_watch_regs *watch_readback, 117 int *watch_readback_valid, int force); 118 119 #endif /* NAT_MIPS_LINUX_WATCH_H */ 120