1 return strdup ( 2 "=PC pc\n" 3 "=SP sp\n" 4 "=BP fp\n" 5 "=A0 r0\n" 6 "=A1 r1\n" 7 "=A2 r2\n" 8 "=A3 r3\n" 9 "=ZF zf\n" 10 "=SF nf\n" 11 "=OF vf\n" 12 "=CF cf\n" 13 "gpr r0 .32 4 0\n" 14 "gpr r1 .32 8 0\n" 15 "gpr r2 .32 12 0\n" 16 "gpr r3 .32 16 0\n" 17 "gpr r4 .32 20 0\n" 18 "gpr r5 .32 24 0\n" 19 "gpr r6 .32 28 0\n" 20 "gpr r7 .32 32 0\n" 21 "gpr r8 .32 36 0\n" 22 "gpr r9 .32 40 0\n" 23 "gpr r10 .32 44 0\n" 24 "gpr r11 .32 48 0\n" 25 "gpr r12 .32 52 0\n" 26 "gpr sp .32 56 0\n" 27 "gpr lr .32 60 0\n" 28 "gpr pc .32 64 0\n" 29 "flg cpsr .32 68 0 _____tfiae_____________j__qvczn\n" 30 "flg vf .1 68.28 0 overflow\n" 31 "flg cf .1 68.29 0 carry\n" 32 "flg zf .1 68.30 0 zero\n" 33 "flg nf .1 68.31 0 sign\n" 34 "gpr fpsr .32 72 0\n" 35 "fpu q0 .128 76 0\n" 36 "fpu q1 .128 92 0\n" 37 "fpu q2 .128 108 0\n" 38 "fpu q3 .128 124 0\n" 39 "fpu q4 .128 140 0\n" 40 "fpu q5 .128 156 0\n" 41 "fpu q6 .128 172 0\n" 42 "fpu q7 .128 188 0\n" 43 "fpu q8 .128 204 0\n" 44 "fpu q9 .128 220 0\n" 45 "fpu q10 .128 236 0\n" 46 "fpu q11 .128 252 0\n" 47 "fpu q12 .128 268 0\n" 48 "fpu q13 .128 284 0\n" 49 "fpu q14 .128 300 0\n" 50 "fpu q15 .128 316 0\n" 51 "drx bcr0 .32 332 0\n" 52 "drx bcr1 .32 336 0\n" 53 "drx bcr2 .32 340 0\n" 54 "drx bcr3 .32 344 0\n" 55 "drx bcr4 .32 348 0\n" 56 "drx bcr5 .32 352 0\n" 57 "drx bcr6 .32 356 0\n" 58 "drx bcr7 .32 360 0\n" 59 "drx bvr0 .32 364 0\n" 60 "drx bvr1 .32 368 0\n" 61 "drx bvr2 .32 372 0\n" 62 "drx bvr3 .32 376 0\n" 63 "drx bvr4 .32 380 0\n" 64 "drx bvr5 .32 384 0\n" 65 "drx bvr6 .32 388 0\n" 66 "drx bvr7 .32 392 0\n" 67 "drx wcr0 .32 396 0\n" 68 "drx wcr1 .32 400 0\n" 69 "drx wvr0 .32 404 0\n" 70 "drx wvr1 .32 408 0\n" 71 ); 72