1 /* 2 Copyright (c) 2005-2021 Intel Corporation 3 4 Licensed under the Apache License, Version 2.0 (the "License"); 5 you may not use this file except in compliance with the License. 6 You may obtain a copy of the License at 7 8 http://www.apache.org/licenses/LICENSE-2.0 9 10 Unless required by applicable law or agreed to in writing, software 11 distributed under the License is distributed on an "AS IS" BASIS, 12 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 See the License for the specific language governing permissions and 14 limitations under the License. 15 */ 16 17 #ifndef TBB_examples_logic_sim_oba_H 18 #define TBB_examples_logic_sim_oba_H 19 20 namespace P { 21 //input ports 22 const int CI = 0; 23 const int A0 = 1; 24 const int B0 = 2; 25 const int A1 = 3; 26 const int B1 = 4; 27 const int A2 = 5; 28 const int B2 = 6; 29 const int A3 = 7; 30 const int B3 = 8; 31 32 //output_ports 33 const int S0 = 0; 34 const int S1 = 1; 35 const int S2 = 2; 36 const int S3 = 3; 37 38 #if USE_TWO_BIT_FULL_ADDER 39 const int CO = 2; 40 #else 41 const int CO = 4; 42 #endif 43 } // namespace P 44 45 #include "basics.hpp" 46 47 class one_bit_adder 48 : public oneapi::tbb::flow::composite_node<std::tuple<signal_t, signal_t, signal_t>, 49 std::tuple<signal_t, signal_t>> { 50 oneapi::tbb::flow::broadcast_node<signal_t> A_port; 51 oneapi::tbb::flow::broadcast_node<signal_t> B_port; 52 oneapi::tbb::flow::broadcast_node<signal_t> CI_port; 53 xor_gate<2> FirstXOR; 54 xor_gate<2> SecondXOR; 55 and_gate<2> FirstAND; 56 and_gate<2> SecondAND; 57 or_gate<2> FirstOR; 58 oneapi::tbb::flow::graph& my_graph; 59 typedef oneapi::tbb::flow::composite_node<std::tuple<signal_t, signal_t, signal_t>, 60 std::tuple<signal_t, signal_t>> 61 base_type; 62 63 public: one_bit_adder(oneapi::tbb::flow::graph & g)64 one_bit_adder(oneapi::tbb::flow::graph& g) 65 : base_type(g), 66 my_graph(g), 67 A_port(g), 68 B_port(g), 69 CI_port(g), 70 FirstXOR(g), 71 SecondXOR(g), 72 FirstAND(g), 73 SecondAND(g), 74 FirstOR(g) { 75 make_connections(); 76 set_up_composite(); 77 } one_bit_adder(const one_bit_adder & src)78 one_bit_adder(const one_bit_adder& src) 79 : base_type(src.my_graph), 80 my_graph(src.my_graph), 81 A_port(src.my_graph), 82 B_port(src.my_graph), 83 CI_port(src.my_graph), 84 FirstXOR(src.my_graph), 85 SecondXOR(src.my_graph), 86 FirstAND(src.my_graph), 87 SecondAND(src.my_graph), 88 FirstOR(src.my_graph) { 89 make_connections(); 90 set_up_composite(); 91 } 92 ~one_bit_adder()93 ~one_bit_adder() {} 94 95 private: make_connections()96 void make_connections() { 97 make_edge(A_port, input_port<0>(FirstXOR)); 98 make_edge(A_port, input_port<0>(FirstAND)); 99 make_edge(B_port, input_port<1>(FirstXOR)); 100 make_edge(B_port, input_port<1>(FirstAND)); 101 make_edge(CI_port, input_port<1>(SecondXOR)); 102 make_edge(CI_port, input_port<1>(SecondAND)); 103 make_edge(FirstXOR, input_port<0>(SecondXOR)); 104 make_edge(FirstXOR, input_port<0>(SecondAND)); 105 make_edge(SecondAND, input_port<0>(FirstOR)); 106 make_edge(FirstAND, input_port<1>(FirstOR)); 107 } 108 set_up_composite()109 void set_up_composite() { 110 base_type::input_ports_type input_tuple(CI_port, A_port, B_port); 111 base_type::output_ports_type output_tuple(output_port<0>(SecondXOR), 112 output_port<0>(FirstOR)); 113 base_type::set_external_ports(input_tuple, output_tuple); 114 base_type::add_visible_nodes( 115 A_port, B_port, CI_port, FirstXOR, SecondXOR, FirstAND, SecondAND, FirstOR); 116 } 117 }; 118 119 #endif /* TBB_examples_logic_sim_oba_H */ 120