1/* $NetBSD: fpu_subr.S,v 1.2 2011/01/18 01:02:55 matt Exp $ */ 2/*- 3 * Copyright (c) 2011 The NetBSD Foundation, Inc. 4 * All rights reserved. 5 * 6 * This code is derived from software contributed to The NetBSD Foundation 7 * by Matt Thomas of 3am Software Foundry. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 19 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 20 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 21 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 22 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31/* 32 * LINTSTUB: void fpu_load_from_fpreg(const struct fpreg *); 33 */ 34ENTRY(fpu_load_from_fpreg) 35 lfd %f0,FPREG_FPSCR(%r3) 36 mtfsf 0xff,%f0 37 38 lfd %f0,FPREG_F0(%r3) 39 lfd %f1,FPREG_F1(%r3) 40 lfd %f2,FPREG_F2(%r3) 41 lfd %f3,FPREG_F3(%r3) 42 lfd %f4,FPREG_F4(%r3) 43 lfd %f5,FPREG_F5(%r3) 44 lfd %f6,FPREG_F6(%r3) 45 lfd %f7,FPREG_F7(%r3) 46 lfd %f8,FPREG_F8(%r3) 47 lfd %f9,FPREG_F9(%r3) 48 lfd %f10,FPREG_F10(%r3) 49 lfd %f11,FPREG_F11(%r3) 50 lfd %f12,FPREG_F12(%r3) 51 lfd %f13,FPREG_F13(%r3) 52 lfd %f14,FPREG_F14(%r3) 53 lfd %f15,FPREG_F15(%r3) 54 lfd %f16,FPREG_F16(%r3) 55 lfd %f17,FPREG_F17(%r3) 56 lfd %f18,FPREG_F18(%r3) 57 lfd %f19,FPREG_F19(%r3) 58 lfd %f20,FPREG_F20(%r3) 59 lfd %f21,FPREG_F21(%r3) 60 lfd %f22,FPREG_F22(%r3) 61 lfd %f23,FPREG_F23(%r3) 62 lfd %f24,FPREG_F24(%r3) 63 lfd %f25,FPREG_F25(%r3) 64 lfd %f26,FPREG_F26(%r3) 65 lfd %f27,FPREG_F27(%r3) 66 lfd %f28,FPREG_F28(%r3) 67 lfd %f29,FPREG_F29(%r3) 68 lfd %f30,FPREG_F30(%r3) 69 lfd %f31,FPREG_F31(%r3) 70 71 isync 72 blr 73END(fpu_load_from_fpreg) 74 75/* 76 * LINTSTUB: void fpu_unload_to_fpreg(struct fpreg *); 77 */ 78ENTRY(fpu_unload_to_fpreg) 79 stfd %f0,FPREG_F0(%r3) 80 stfd %f1,FPREG_F1(%r3) 81 stfd %f2,FPREG_F2(%r3) 82 stfd %f3,FPREG_F3(%r3) 83 stfd %f4,FPREG_F4(%r3) 84 stfd %f5,FPREG_F5(%r3) 85 stfd %f6,FPREG_F6(%r3) 86 stfd %f7,FPREG_F7(%r3) 87 stfd %f8,FPREG_F8(%r3) 88 stfd %f9,FPREG_F9(%r3) 89 stfd %f10,FPREG_F10(%r3) 90 stfd %f11,FPREG_F11(%r3) 91 stfd %f12,FPREG_F12(%r3) 92 stfd %f13,FPREG_F13(%r3) 93 stfd %f14,FPREG_F14(%r3) 94 stfd %f15,FPREG_F15(%r3) 95 stfd %f16,FPREG_F16(%r3) 96 stfd %f17,FPREG_F17(%r3) 97 stfd %f18,FPREG_F18(%r3) 98 stfd %f19,FPREG_F19(%r3) 99 stfd %f20,FPREG_F20(%r3) 100 stfd %f21,FPREG_F21(%r3) 101 stfd %f22,FPREG_F22(%r3) 102 stfd %f23,FPREG_F23(%r3) 103 stfd %f24,FPREG_F24(%r3) 104 stfd %f25,FPREG_F25(%r3) 105 stfd %f26,FPREG_F26(%r3) 106 stfd %f27,FPREG_F27(%r3) 107 stfd %f28,FPREG_F28(%r3) 108 stfd %f29,FPREG_F29(%r3) 109 stfd %f30,FPREG_F30(%r3) 110 stfd %f31,FPREG_F31(%r3) 111 112 mffs %f0 113 stfd %f0,FPREG_FPSCR(%r3) 114 115 sync 116 blr 117END(fpu_unload_to_fpreg) 118