1 /*
2 * QEMU SiI3112A PCI to Serial ATA Controller Emulation
3 *
4 * Copyright (C) 2017 BALATON Zoltan <balaton@eik.bme.hu>
5 *
6 * This work is licensed under the terms of the GNU GPL, version 2 or later.
7 * See the COPYING file in the top-level directory.
8 *
9 */
10
11 /* For documentation on this and similar cards see:
12 * http://wiki.osdev.org/User:Quok/Silicon_Image_Datasheets
13 */
14
15 #include "qemu/osdep.h"
16 #include "hw/ide/pci.h"
17 #include "qemu/module.h"
18 #include "trace.h"
19 #include "qom/object.h"
20 #include "ide-internal.h"
21
22 #define TYPE_SII3112_PCI "sii3112"
23 OBJECT_DECLARE_SIMPLE_TYPE(SiI3112PCIState, SII3112_PCI)
24
25 typedef struct SiI3112Regs {
26 uint32_t confstat;
27 uint32_t scontrol;
28 uint16_t sien;
29 uint8_t swdata;
30 } SiI3112Regs;
31
32 struct SiI3112PCIState {
33 PCIIDEState i;
34 MemoryRegion mmio;
35 SiI3112Regs regs[2];
36 };
37
38 /* The sii3112_reg_read and sii3112_reg_write functions implement the
39 * Internal Register Space - BAR5 (section 6.7 of the data sheet).
40 */
41
sii3112_reg_read(void * opaque,hwaddr addr,unsigned int size)42 static uint64_t sii3112_reg_read(void *opaque, hwaddr addr,
43 unsigned int size)
44 {
45 SiI3112PCIState *d = opaque;
46 uint64_t val;
47
48 switch (addr) {
49 case 0x00:
50 val = d->i.bmdma[0].cmd;
51 break;
52 case 0x01:
53 val = d->regs[0].swdata;
54 break;
55 case 0x02:
56 val = d->i.bmdma[0].status;
57 break;
58 case 0x03:
59 val = 0;
60 break;
61 case 0x04 ... 0x07:
62 val = bmdma_addr_ioport_ops.read(&d->i.bmdma[0], addr - 4, size);
63 break;
64 case 0x08:
65 val = d->i.bmdma[1].cmd;
66 break;
67 case 0x09:
68 val = d->regs[1].swdata;
69 break;
70 case 0x0a:
71 val = d->i.bmdma[1].status;
72 break;
73 case 0x0b:
74 val = 0;
75 break;
76 case 0x0c ... 0x0f:
77 val = bmdma_addr_ioport_ops.read(&d->i.bmdma[1], addr - 12, size);
78 break;
79 case 0x10:
80 val = d->i.bmdma[0].cmd;
81 val |= (d->regs[0].confstat & (1UL << 11) ? (1 << 4) : 0); /*SATAINT0*/
82 val |= (d->regs[1].confstat & (1UL << 11) ? (1 << 6) : 0); /*SATAINT1*/
83 val |= (d->i.bmdma[1].status & BM_STATUS_INT ? (1 << 14) : 0);
84 val |= (uint32_t)d->i.bmdma[0].status << 16;
85 val |= (uint32_t)d->i.bmdma[1].status << 24;
86 break;
87 case 0x18:
88 val = d->i.bmdma[1].cmd;
89 val |= (d->regs[1].confstat & (1UL << 11) ? (1 << 4) : 0);
90 val |= (uint32_t)d->i.bmdma[1].status << 16;
91 break;
92 case 0x80 ... 0x87:
93 val = pci_ide_data_le_ops.read(&d->i.bus[0], addr - 0x80, size);
94 break;
95 case 0x8a:
96 val = pci_ide_cmd_le_ops.read(&d->i.bus[0], 2, size);
97 break;
98 case 0xa0:
99 val = d->regs[0].confstat;
100 break;
101 case 0xc0 ... 0xc7:
102 val = pci_ide_data_le_ops.read(&d->i.bus[1], addr - 0xc0, size);
103 break;
104 case 0xca:
105 val = pci_ide_cmd_le_ops.read(&d->i.bus[1], 2, size);
106 break;
107 case 0xe0:
108 val = d->regs[1].confstat;
109 break;
110 case 0x100:
111 val = d->regs[0].scontrol;
112 break;
113 case 0x104:
114 val = (d->i.bus[0].ifs[0].blk) ? 0x113 : 0;
115 break;
116 case 0x148:
117 val = (uint32_t)d->regs[0].sien << 16;
118 break;
119 case 0x180:
120 val = d->regs[1].scontrol;
121 break;
122 case 0x184:
123 val = (d->i.bus[1].ifs[0].blk) ? 0x113 : 0;
124 break;
125 case 0x1c8:
126 val = (uint32_t)d->regs[1].sien << 16;
127 break;
128 default:
129 val = 0;
130 break;
131 }
132 trace_sii3112_read(size, addr, val);
133 return val;
134 }
135
sii3112_reg_write(void * opaque,hwaddr addr,uint64_t val,unsigned int size)136 static void sii3112_reg_write(void *opaque, hwaddr addr,
137 uint64_t val, unsigned int size)
138 {
139 SiI3112PCIState *d = opaque;
140
141 trace_sii3112_write(size, addr, val);
142 switch (addr) {
143 case 0x00:
144 case 0x10:
145 bmdma_cmd_writeb(&d->i.bmdma[0], val);
146 break;
147 case 0x01:
148 case 0x11:
149 d->regs[0].swdata = val & 0x3f;
150 break;
151 case 0x02:
152 case 0x12:
153 bmdma_status_writeb(&d->i.bmdma[0], val);
154 break;
155 case 0x04 ... 0x07:
156 bmdma_addr_ioport_ops.write(&d->i.bmdma[0], addr - 4, val, size);
157 break;
158 case 0x08:
159 case 0x18:
160 bmdma_cmd_writeb(&d->i.bmdma[1], val);
161 break;
162 case 0x09:
163 case 0x19:
164 d->regs[1].swdata = val & 0x3f;
165 break;
166 case 0x0a:
167 case 0x1a:
168 bmdma_status_writeb(&d->i.bmdma[1], val);
169 break;
170 case 0x0c ... 0x0f:
171 bmdma_addr_ioport_ops.write(&d->i.bmdma[1], addr - 12, val, size);
172 break;
173 case 0x80 ... 0x87:
174 pci_ide_data_le_ops.write(&d->i.bus[0], addr - 0x80, val, size);
175 break;
176 case 0x8a:
177 pci_ide_cmd_le_ops.write(&d->i.bus[0], 2, val, size);
178 break;
179 case 0xc0 ... 0xc7:
180 pci_ide_data_le_ops.write(&d->i.bus[1], addr - 0xc0, val, size);
181 break;
182 case 0xca:
183 pci_ide_cmd_le_ops.write(&d->i.bus[1], 2, val, size);
184 break;
185 case 0x100:
186 d->regs[0].scontrol = val & 0xfff;
187 if (val & 1) {
188 ide_bus_reset(&d->i.bus[0]);
189 }
190 break;
191 case 0x148:
192 d->regs[0].sien = (val >> 16) & 0x3eed;
193 break;
194 case 0x180:
195 d->regs[1].scontrol = val & 0xfff;
196 if (val & 1) {
197 ide_bus_reset(&d->i.bus[1]);
198 }
199 break;
200 case 0x1c8:
201 d->regs[1].sien = (val >> 16) & 0x3eed;
202 break;
203 default:
204 break;
205 }
206 }
207
208 static const MemoryRegionOps sii3112_reg_ops = {
209 .read = sii3112_reg_read,
210 .write = sii3112_reg_write,
211 .endianness = DEVICE_LITTLE_ENDIAN,
212 };
213
214 /* the PCI irq level is the logical OR of the two channels */
sii3112_update_irq(SiI3112PCIState * s)215 static void sii3112_update_irq(SiI3112PCIState *s)
216 {
217 int i, set = 0;
218
219 for (i = 0; i < 2; i++) {
220 set |= s->regs[i].confstat & (1UL << 11);
221 }
222 pci_set_irq(PCI_DEVICE(s), (set ? 1 : 0));
223 }
224
sii3112_set_irq(void * opaque,int channel,int level)225 static void sii3112_set_irq(void *opaque, int channel, int level)
226 {
227 SiI3112PCIState *s = opaque;
228
229 trace_sii3112_set_irq(channel, level);
230 if (level) {
231 s->regs[channel].confstat |= (1UL << 11);
232 } else {
233 s->regs[channel].confstat &= ~(1UL << 11);
234 }
235
236 sii3112_update_irq(s);
237 }
238
sii3112_reset(DeviceState * dev)239 static void sii3112_reset(DeviceState *dev)
240 {
241 SiI3112PCIState *s = SII3112_PCI(dev);
242 int i;
243
244 for (i = 0; i < 2; i++) {
245 s->regs[i].confstat = 0x6515 << 16;
246 ide_bus_reset(&s->i.bus[i]);
247 }
248 }
249
sii3112_pci_realize(PCIDevice * dev,Error ** errp)250 static void sii3112_pci_realize(PCIDevice *dev, Error **errp)
251 {
252 SiI3112PCIState *d = SII3112_PCI(dev);
253 PCIIDEState *s = PCI_IDE(dev);
254 DeviceState *ds = DEVICE(dev);
255 MemoryRegion *mr;
256 int i;
257
258 pci_config_set_interrupt_pin(dev->config, 1);
259 pci_set_byte(dev->config + PCI_CACHE_LINE_SIZE, 8);
260
261 /* BAR5 is in PCI memory space */
262 memory_region_init_io(&d->mmio, OBJECT(d), &sii3112_reg_ops, d,
263 "sii3112.bar5", 0x200);
264 pci_register_bar(dev, 5, PCI_BASE_ADDRESS_SPACE_MEMORY, &d->mmio);
265
266 /* BAR0-BAR4 are PCI I/O space aliases into BAR5 */
267 mr = g_new(MemoryRegion, 1);
268 memory_region_init_alias(mr, OBJECT(d), "sii3112.bar0", &d->mmio, 0x80, 8);
269 pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_IO, mr);
270 mr = g_new(MemoryRegion, 1);
271 memory_region_init_alias(mr, OBJECT(d), "sii3112.bar1", &d->mmio, 0x88, 4);
272 pci_register_bar(dev, 1, PCI_BASE_ADDRESS_SPACE_IO, mr);
273 mr = g_new(MemoryRegion, 1);
274 memory_region_init_alias(mr, OBJECT(d), "sii3112.bar2", &d->mmio, 0xc0, 8);
275 pci_register_bar(dev, 2, PCI_BASE_ADDRESS_SPACE_IO, mr);
276 mr = g_new(MemoryRegion, 1);
277 memory_region_init_alias(mr, OBJECT(d), "sii3112.bar3", &d->mmio, 0xc8, 4);
278 pci_register_bar(dev, 3, PCI_BASE_ADDRESS_SPACE_IO, mr);
279 mr = g_new(MemoryRegion, 1);
280 memory_region_init_alias(mr, OBJECT(d), "sii3112.bar4", &d->mmio, 0, 16);
281 pci_register_bar(dev, 4, PCI_BASE_ADDRESS_SPACE_IO, mr);
282
283 qdev_init_gpio_in(ds, sii3112_set_irq, 2);
284 for (i = 0; i < 2; i++) {
285 ide_bus_init(&s->bus[i], sizeof(s->bus[i]), ds, i, 1);
286 ide_bus_init_output_irq(&s->bus[i], qdev_get_gpio_in(ds, i));
287
288 bmdma_init(&s->bus[i], &s->bmdma[i], s);
289 ide_bus_register_restart_cb(&s->bus[i]);
290 }
291 }
292
sii3112_pci_class_init(ObjectClass * klass,void * data)293 static void sii3112_pci_class_init(ObjectClass *klass, void *data)
294 {
295 DeviceClass *dc = DEVICE_CLASS(klass);
296 PCIDeviceClass *pd = PCI_DEVICE_CLASS(klass);
297
298 pd->vendor_id = 0x1095;
299 pd->device_id = 0x3112;
300 pd->class_id = PCI_CLASS_STORAGE_RAID;
301 pd->revision = 1;
302 pd->realize = sii3112_pci_realize;
303 device_class_set_legacy_reset(dc, sii3112_reset);
304 dc->desc = "SiI3112A SATA controller";
305 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
306 }
307
308 static const TypeInfo sii3112_pci_info = {
309 .name = TYPE_SII3112_PCI,
310 .parent = TYPE_PCI_IDE,
311 .instance_size = sizeof(SiI3112PCIState),
312 .class_init = sii3112_pci_class_init,
313 };
314
sii3112_register_types(void)315 static void sii3112_register_types(void)
316 {
317 type_register_static(&sii3112_pci_info);
318 }
319
320 type_init(sii3112_register_types)
321