1 /*
2 * Simulator for the LR35902 used in the gb console.
3 * The processor is closely related to the Z-80, so the C++
4 * emulator object inherits from it.
5 *
6 */
7
8 /* This file is part of microcontroller simulator: ucsim.
9
10 UCSIM is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2 of the License, or
13 (at your option) any later version.
14
15 UCSIM is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
19
20 You should have received a copy of the GNU General Public License
21 along with UCSIM; see the file COPYING. If not, write to the Free
22 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
23 02111-1307, USA. */
24 /*@1@*/
25
26 #include "ddconfig.h"
27
28 #include <stdarg.h> /* for va_list */
29 #include <stdio.h>
30 #include <stdlib.h>
31 #include <ctype.h>
32 #include "i_string.h"
33
34 // prj
35 #include "pobjcl.h"
36
37 // sim
38 #include "simcl.h"
39
40 // local
41 #include "z80cl.h"
42 #include "lr35902cl.h"
43 #include "glob.h"
44
45 #define uint32 t_addr
46 #define uint8 unsigned char
47
48 /*******************************************************************/
49
lr35902_memory(cl_uc & uc_parent_ref)50 lr35902_memory::lr35902_memory( cl_uc &uc_parent_ref ):uc_r(uc_parent_ref) { }
51
cl_lr35902(struct cpu_entry * Itype,class cl_sim * asim)52 cl_lr35902::cl_lr35902(struct cpu_entry *Itype, class cl_sim *asim):
53 cl_z80(Itype, asim), mem(*this)
54 {
55 type= Itype;
56 }
57
58 int
init(void)59 cl_lr35902::init(void)
60 {
61 cl_uc::init(); /* Memories now exist */
62
63 //rom= address_space(MEM_ROM_ID); // code goes here...
64
65 // ram= mem(MEM_XRAM);
66 //ram= address_space(MEM_XRAM_ID); // data goes here...
67
68
69 // zero out ram(this is assumed in regression tests)
70 for (int i=0xA000; i<0xFF80; i++) {
71 ram->set((t_addr) i, 0);
72 }
73
74 return(0);
75 }
76
77 char *
id_string(void)78 cl_lr35902::id_string(void)
79 {
80 return((char*)"LR35902");
81 }
82
83
84 void
mk_hw_elements(void)85 cl_lr35902::mk_hw_elements(void)
86 {
87 //class cl_base *o;
88 cl_uc::mk_hw_elements();
89 }
90
init(void)91 void lr35902_memory::init(void) {
92 cl_address_space *as_rom;
93 cl_address_space *as_ram;
94
95 as_rom = new cl_address_space("rom"/*MEM_ROM_ID*/,
96 lr35902_rom_start, lr35902_rom_size, 8);
97 as_rom->init();
98 uc_r.address_spaces->add(as_rom);
99 rom = as_rom;
100
101 as_ram = new cl_address_space(MEM_XRAM_ID,
102 lr35902_ram_start, lr35902_ram_size, 8);
103 as_ram->init();
104 uc_r.address_spaces->add(as_ram);
105 ram = as_ram;
106 }
107
108 void
make_memories(void)109 cl_lr35902::make_memories(void)
110 {
111 mem.init( );
112 rom= mem.rom;
113 ram= mem.ram;
114
115 regs8= new cl_address_space("regs8", 0, 16, 8);
116 regs8->init();
117 regs8->get_cell(0)->decode((t_mem*)®s.raf.A);
118 regs8->get_cell(1)->decode((t_mem*)®s.raf.F);
119 regs8->get_cell(2)->decode((t_mem*)®s.bc.h);
120 regs8->get_cell(3)->decode((t_mem*)®s.bc.l);
121 regs8->get_cell(4)->decode((t_mem*)®s.de.h);
122 regs8->get_cell(5)->decode((t_mem*)®s.de.l);
123 regs8->get_cell(6)->decode((t_mem*)®s.hl.h);
124 regs8->get_cell(7)->decode((t_mem*)®s.hl.l);
125
126 regs8->get_cell(8)->decode((t_mem*)®s.ralt_af.aA);
127 regs8->get_cell(9)->decode((t_mem*)®s.ralt_af.aF);
128 regs8->get_cell(10)->decode((t_mem*)®s.a_bc.h);
129 regs8->get_cell(11)->decode((t_mem*)®s.a_bc.l);
130 regs8->get_cell(12)->decode((t_mem*)®s.a_de.h);
131 regs8->get_cell(13)->decode((t_mem*)®s.a_de.l);
132 regs8->get_cell(14)->decode((t_mem*)®s.a_hl.h);
133 regs8->get_cell(15)->decode((t_mem*)®s.a_hl.l);
134
135 regs16= new cl_address_space("regs16", 0, 11, 16);
136 regs16->init();
137
138 regs16->get_cell(0)->decode((t_mem*)®s.AF);
139 regs16->get_cell(1)->decode((t_mem*)®s.BC);
140 regs16->get_cell(2)->decode((t_mem*)®s.DE);
141 regs16->get_cell(3)->decode((t_mem*)®s.HL);
142 regs16->get_cell(4)->decode((t_mem*)®s.IX);
143 regs16->get_cell(5)->decode((t_mem*)®s.IY);
144 regs16->get_cell(6)->decode((t_mem*)®s.SP);
145 regs16->get_cell(7)->decode((t_mem*)®s.aAF);
146 regs16->get_cell(8)->decode((t_mem*)®s.aBC);
147 regs16->get_cell(9)->decode((t_mem*)®s.aDE);
148 regs16->get_cell(10)->decode((t_mem*)®s.aHL);
149
150 address_spaces->add(regs8);
151 address_spaces->add(regs16);
152
153 class cl_var *v;
154 vars->add(v= new cl_var(cchars("A"), regs8, 0, ""));
155 v->init();
156 vars->add(v= new cl_var(cchars("F"), regs8, 1, ""));
157 v->init();
158 vars->add(v= new cl_var(cchars("B"), regs8, 2, ""));
159 v->init();
160 vars->add(v= new cl_var(cchars("C"), regs8, 3, ""));
161 v->init();
162 vars->add(v= new cl_var(cchars("D"), regs8, 4, ""));
163 v->init();
164 vars->add(v= new cl_var(cchars("E"), regs8, 5, ""));
165 v->init();
166 vars->add(v= new cl_var(cchars("H"), regs8, 6, ""));
167 v->init();
168 vars->add(v= new cl_var(cchars("L"), regs8, 7, ""));
169 v->init();
170
171 vars->add(v= new cl_var(cchars("ALT_A"), regs8, 8, ""));
172 v->init();
173 vars->add(v= new cl_var(cchars("ALT_F"), regs8, 9, ""));
174 v->init();
175 vars->add(v= new cl_var(cchars("ALT_B"), regs8, 10, ""));
176 v->init();
177 vars->add(v= new cl_var(cchars("ALT_C"), regs8, 11, ""));
178 v->init();
179 vars->add(v= new cl_var(cchars("ALT_D"), regs8, 12, ""));
180 v->init();
181 vars->add(v= new cl_var(cchars("ALT_E"), regs8, 13, ""));
182 v->init();
183 vars->add(v= new cl_var(cchars("ALT_H"), regs8, 14, ""));
184 v->init();
185 vars->add(v= new cl_var(cchars("ALT_L"), regs8, 15, ""));
186 v->init();
187
188 vars->add(v= new cl_var(cchars("AF"), regs16, 0, ""));
189 v->init();
190 vars->add(v= new cl_var(cchars("BC"), regs16, 1, ""));
191 v->init();
192 vars->add(v= new cl_var(cchars("DE"), regs16, 2, ""));
193 v->init();
194 vars->add(v= new cl_var(cchars("HL"), regs16, 3, ""));
195 v->init();
196 vars->add(v= new cl_var(cchars("IX"), regs16, 4, ""));
197 v->init();
198 vars->add(v= new cl_var(cchars("IY"), regs16, 5, ""));
199 v->init();
200 vars->add(v= new cl_var(cchars("SP"), regs16, 6, ""));
201 v->init();
202 vars->add(v= new cl_var(cchars("ALT_AF"), regs16, 7, ""));
203 v->init();
204 vars->add(v= new cl_var(cchars("ALT_BC"), regs16, 8, ""));
205 v->init();
206 vars->add(v= new cl_var(cchars("ALT_DE"), regs16, 9, ""));
207 v->init();
208 vars->add(v= new cl_var(cchars("ALT_HL"), regs16, 10, ""));
209 v->init();
210 }
211
212
store1(u16_t addr,t_mem val)213 void cl_lr35902::store1( u16_t addr, t_mem val ) {
214 mem.store1( addr, val );
215 }
216
store2(u16_t addr,u16_t val)217 void cl_lr35902::store2( u16_t addr, u16_t val ) {
218 mem.store2( addr, val );
219 }
220
get1(u16_t addr)221 u8_t cl_lr35902::get1( u16_t addr ) {
222 return mem.get1( addr );
223 }
224
get2(u16_t addr)225 u16_t cl_lr35902::get2( u16_t addr ) {
226 return mem.get2( addr );
227 }
228
store1(u16_t addr,t_mem val)229 void lr35902_memory::store1( u16_t addr, t_mem val ) {
230 if (addr < lr35902_ram_start) {
231 /* flag illegal operation ? */
232 return;
233 }
234
235 if ((addr- lr35902_ram_start) < lr35902_ram_size) {
236 ram->write(addr, val);
237 }
238 }
239
store2(u16_t addr,u16_t val)240 void lr35902_memory::store2( u16_t addr, u16_t val ) {
241 store1(addr, val & 0xff);
242 store1(addr+1, (val >> 8) & 0xff);
243 }
244
get1(u16_t addr)245 u8_t lr35902_memory::get1( u16_t addr ) {
246 if (addr < lr35902_rom_size) {
247 return rom->read(addr);
248 }
249
250 if (addr < lr35902_ram_start) {
251 /* flag illegal operation ? */
252 return (addr & 0xff);
253 }
254
255 if ((addr-lr35902_ram_start) < lr35902_ram_size) {
256 return ram->read(addr);
257 }
258
259 return (addr & 0xff);
260 }
261
get2(u16_t addr)262 u16_t lr35902_memory::get2( u16_t addr ) {
263 u16_t l, h;
264
265 l = get1(addr );
266 h = get1(addr+1);
267
268 return (h << 8) | l;
269 }
270
271 /*
272 * Help command interpreter
273 */
274
275 struct dis_entry *
dis_tbl(void)276 cl_lr35902::dis_tbl(void)
277 {
278 return(disass_lr35902);
279 }
280
281
282 int
inst_length(t_addr addr)283 cl_lr35902::inst_length(t_addr addr)
284 {
285 int len = 0;
286
287 get_disasm_info(addr, &len, NULL, NULL);
288
289 return len;
290 }
291
292 int
inst_branch(t_addr addr)293 cl_lr35902::inst_branch(t_addr addr)
294 {
295 int b;
296
297 get_disasm_info(addr, NULL, &b, NULL);
298
299 return b;
300 }
301
302 int
longest_inst(void)303 cl_lr35902::longest_inst(void)
304 {
305 return 4;
306 }
307
308
309 const char *
get_disasm_info(t_addr addr,int * ret_len,int * ret_branch,int * immed_offset)310 cl_lr35902::get_disasm_info(t_addr addr,
311 int *ret_len,
312 int *ret_branch,
313 int *immed_offset)
314 {
315 const char *b = NULL;
316 uint code;
317 int len = 0;
318 int immed_n = 0;
319 int i;
320 int start_addr = addr;
321 struct dis_entry *dis_e;
322
323 code= rom->get(addr++);
324 dis_e = NULL;
325
326 switch(code) {
327 case 0xcb: /* ESC code to lots of op-codes, all 2-byte */
328 code= rom->get(addr++);
329 i= 0;
330 while ((code & disass_lr35902_cb[i].mask) != disass_lr35902_cb[i].code &&
331 disass_lr35902_cb[i].mnemonic)
332 i++;
333 dis_e = &disass_lr35902_cb[i];
334 b= disass_lr35902_cb[i].mnemonic;
335 if (b != NULL)
336 len += (disass_lr35902_cb[i].length + 1);
337 break;
338
339 default:
340 i= 0;
341 while ((code & disass_lr35902[i].mask) != disass_lr35902[i].code &&
342 disass_lr35902[i].mnemonic)
343 i++;
344 dis_e = &disass_lr35902[i];
345 b= disass_lr35902[i].mnemonic;
346 if (b != NULL)
347 len += (disass_lr35902[i].length);
348 break;
349 }
350
351
352 if (ret_branch) {
353 *ret_branch = dis_e->branch;
354 }
355
356 if (immed_offset) {
357 if (immed_n > 0)
358 *immed_offset = immed_n;
359 else *immed_offset = (addr - start_addr);
360 }
361
362 if (len == 0)
363 len = 1;
364
365 if (ret_len)
366 *ret_len = len;
367
368 return b;
369 }
370
371 char *
disass(t_addr addr,const char * sep)372 cl_lr35902::disass(t_addr addr, const char *sep)
373 {
374 char work[256], temp[20];
375 const char *b;
376 char *buf, *p, *t;
377 int len = 0;
378 int immed_offset = 0;
379
380 p= work;
381
382 b = get_disasm_info(addr, &len, NULL, &immed_offset);
383
384 if (b == NULL) {
385 buf= (char*)malloc(30);
386 strcpy(buf, "UNKNOWN/INVALID");
387 return(buf);
388 }
389
390 while (*b)
391 {
392 if (*b == '%')
393 {
394 b++;
395 switch (*(b++))
396 {
397 case 'd': // d jump relative target, signed? byte immediate operand
398 sprintf(temp, "#%d", (char)rom->get(addr+immed_offset));
399 ++immed_offset;
400 break;
401 case 'w': // w word immediate operand
402 sprintf(temp, "#0x%04x",
403 (uint)((rom->get(addr+immed_offset)) |
404 (rom->get(addr+immed_offset+1)<<8)) );
405 ++immed_offset;
406 ++immed_offset;
407 break;
408 case 'b': // b byte immediate operand
409 sprintf(temp, "#0x%02x", (uint)rom->get(addr+immed_offset));
410 ++immed_offset;
411 break;
412 default:
413 strcpy(temp, "?");
414 break;
415 }
416 t= temp;
417 while (*t)
418 *(p++)= *(t++);
419 }
420 else
421 *(p++)= *(b++);
422 }
423 *p= '\0';
424
425 p= strchr(work, ' ');
426 if (!p)
427 {
428 buf= strdup(work);
429 return(buf);
430 }
431 if (sep == NULL)
432 buf= (char *)malloc(6+strlen(p)+1);
433 else
434 buf= (char *)malloc((p-work)+strlen(sep)+strlen(p)+1);
435 for (p= work, t= buf; *p != ' '; p++, t++)
436 *t= *p;
437 p++;
438 *t= '\0';
439 if (sep == NULL)
440 {
441 while (strlen(buf) < 6)
442 strcat(buf, " ");
443 }
444 else
445 strcat(buf, sep);
446 strcat(buf, p);
447 return(buf);
448 }
449
450
451 void
print_regs(class cl_console_base * con)452 cl_lr35902::print_regs(class cl_console_base *con)
453 {
454 con->dd_printf("SZ-A-PNC Flags= 0x%02x %3d %c ",
455 regs.raf.F, regs.raf.F, isprint(regs.raf.F)?regs.raf.F:'.');
456 con->dd_printf("A= 0x%02x %3d %c\n",
457 regs.raf.A, regs.raf.A, isprint(regs.raf.A)?regs.raf.A:'.');
458 con->dd_printf("%c%c-%c-%c%c%c\n",
459 (regs.raf.F&BIT_S)?'1':'0',
460 (regs.raf.F&BIT_Z)?'1':'0',
461 (regs.raf.F&BIT_A)?'1':'0',
462 (regs.raf.F&BIT_P)?'1':'0',
463 (regs.raf.F&BIT_N)?'1':'0',
464 (regs.raf.F&BIT_C)?'1':'0');
465 con->dd_printf("BC= 0x%04x [BC]= %02x %3d %c ",
466 regs.BC, ram->get(regs.BC), ram->get(regs.BC),
467 isprint(ram->get(regs.BC))?ram->get(regs.BC):'.');
468 con->dd_printf("DE= 0x%04x [DE]= %02x %3d %c ",
469 regs.DE, ram->get(regs.DE), ram->get(regs.DE),
470 isprint(ram->get(regs.DE))?ram->get(regs.DE):'.');
471 con->dd_printf("HL= 0x%04x [HL]= %02x %3d %c\n",
472 regs.HL, ram->get(regs.HL), ram->get(regs.HL),
473 isprint(ram->get(regs.HL))?ram->get(regs.HL):'.');
474 con->dd_printf("SP= 0x%04x [SP]= %02x %3d %c\n",
475 regs.SP, ram->get(regs.SP), ram->get(regs.SP),
476 isprint(ram->get(regs.SP))?ram->get(regs.SP):'.');
477
478 print_disass(PC, con);
479 }
480
481 /*
482 * Execution
483 */
484
485 int
exec_inst(void)486 cl_lr35902::exec_inst(void)
487 {
488
489 t_mem code;
490
491
492
493 instPC= PC;
494
495
496
497 if (fetch(&code))
498
499 return(resBREAKPOINT);
500
501 tick(1);
502
503 switch (code)
504 {
505 case 0x00: return(inst_nop(code));
506 case 0x01: case 0x02: case 0x06: return(inst_ld(code));
507 case 0x03: case 0x04: return(inst_inc(code));
508 case 0x05: return(inst_dec(code));
509 case 0x07: return(inst_rlca(code));
510
511 case 0x08: return(inst_st_sp_abs(code));
512 case 0x09: return(inst_add(code));
513 case 0x0a: case 0x0e: return(inst_ld(code));
514 case 0x0b: case 0x0d: return(inst_dec(code));
515 case 0x0c: return(inst_inc(code));
516 case 0x0f: return(inst_rrca(code));
517
518
519 case 0x10: return(inst_stop0(code));
520 case 0x11: case 0x12: case 0x16: return(inst_ld(code));
521 case 0x13: case 0x14: return(inst_inc(code));
522 case 0x15: return(inst_dec(code));
523 case 0x17: return(inst_rla(code));
524
525 case 0x18: return(inst_jr(code));
526 case 0x19: return(inst_add(code));
527 case 0x1a: case 0x1e: return(inst_ld(code));
528 case 0x1b: case 0x1d: return(inst_dec(code));
529 case 0x1c: return(inst_inc(code));
530 case 0x1f: return(inst_rra(code));
531
532
533 case 0x20: return(inst_jr(code));
534 case 0x21: case 0x26: return(inst_ld(code));
535 case 0x22: return inst_ldi(code);
536 case 0x23: case 0x24: return(inst_inc(code));
537 case 0x25: return(inst_dec(code));
538 case 0x27: return(inst_daa(code));
539
540 case 0x28: return(inst_jr(code));
541 case 0x29: return(inst_add(code));
542 case 0x2a: return(inst_ldi(code));
543 case 0x2b: case 0x2d: return(inst_dec(code));
544 case 0x2c: return(inst_inc(code));
545 case 0x2e: return(inst_ld(code));
546 case 0x2f: return(inst_cpl(code));
547
548 case 0x30: return(inst_jr(code));
549 case 0x31: case 0x36: return(inst_ld(code));
550 case 0x32: return(inst_ldd(code));
551 case 0x33: case 0x34: return(inst_inc(code));
552 case 0x35: return(inst_dec(code));
553 case 0x37: return(inst_scf(code));
554
555 case 0x38: return(inst_jr(code));
556 case 0x39: return(inst_add(code));
557 case 0x3a: return inst_ldd(code);
558 case 0x3b: case 0x3d: return(inst_dec(code));
559 case 0x3c: return(inst_inc(code));
560 case 0x3e: return(inst_ld(code));
561 case 0x3f: return(inst_ccf(code));
562
563 case 0x40: case 0x41: case 0x42: case 0x43: case 0x44: case 0x45: case 0x46: case 0x47:
564 case 0x48: case 0x49: case 0x4a: case 0x4b: case 0x4c: case 0x4d: case 0x4e: case 0x4f:
565 return(inst_ld(code));
566
567 case 0x50: case 0x51: case 0x52: case 0x53: case 0x54: case 0x55: case 0x56: case 0x57:
568 case 0x58: case 0x59: case 0x5a: case 0x5b: case 0x5c: case 0x5d: case 0x5e: case 0x5f:
569 return(inst_ld(code));
570
571 case 0x60: case 0x61: case 0x62: case 0x63: case 0x64: case 0x65: case 0x66: case 0x67:
572 case 0x68: case 0x69: case 0x6a: case 0x6b: case 0x6c: case 0x6d: case 0x6e: case 0x6f:
573 return(inst_ld(code));
574
575 case 0x70: case 0x71: case 0x72: case 0x73: case 0x74: case 0x75: case 0x77:
576 case 0x78: case 0x79: case 0x7a: case 0x7b: case 0x7c: case 0x7d: case 0x7e: case 0x7f:
577 return(inst_ld(code));
578 case 0x76: return(inst_halt(code));
579
580 case 0x80: case 0x81: case 0x82: case 0x83: case 0x84: case 0x85: case 0x86: case 0x87:
581 return(inst_add(code));
582 case 0x88: case 0x89: case 0x8a: case 0x8b: case 0x8c: case 0x8d: case 0x8e: case 0x8f:
583 return(inst_adc(code));
584
585 case 0x90: case 0x91: case 0x92: case 0x93: case 0x94: case 0x95: case 0x96: case 0x97:
586 return(inst_sub(code));
587 case 0x98: case 0x99: case 0x9a: case 0x9b: case 0x9c: case 0x9d: case 0x9e: case 0x9f:
588 return(inst_sbc(code));
589
590 case 0xa0: case 0xa1: case 0xa2: case 0xa3: case 0xa4: case 0xa5: case 0xa6: case 0xa7:
591 return(inst_and(code));
592 case 0xa8: case 0xa9: case 0xaa: case 0xab: case 0xac: case 0xad: case 0xae: case 0xaf:
593 return(inst_xor(code));
594
595 case 0xb0: case 0xb1: case 0xb2: case 0xb3: case 0xb4: case 0xb5: case 0xb6: case 0xb7:
596 return(inst_or(code));
597 case 0xb8: case 0xb9: case 0xba: case 0xbb: case 0xbc: case 0xbd: case 0xbe: case 0xbf:
598 return(inst_cp(code));
599
600 case 0xc0: return(inst_ret(code));
601 case 0xc1: return(inst_pop(code));
602 case 0xc2: case 0xc3: return(inst_jp(code));
603 case 0xc4: return(inst_call(code));
604 case 0xc5: return(inst_push(code));
605 case 0xc6: return(inst_add(code));
606 case 0xc7: return(inst_rst(code));
607
608 case 0xc8: case 0xc9: return(inst_ret(code));
609 case 0xca: return(inst_jp(code));
610
611 /* CB escapes out to 2 byte opcodes(CB include), opcodes
612 to do register bit manipulations */
613 case 0xcb: return(inst_cb( ));
614 case 0xcc: case 0xcd: return(inst_call(code));
615 case 0xce: return(inst_adc(code));
616 case 0xcf: return(inst_rst(code));
617
618 case 0xd0: return(inst_ret(code));
619 case 0xd1: return(inst_pop(code));
620 case 0xd2: return(inst_jp(code));
621 case 0xd3: break;
622 case 0xd4: return(inst_call(code));
623 case 0xd5: return(inst_push(code));
624 case 0xd6: return(inst_sub(code));
625 case 0xd7: return(inst_rst(code));
626
627 case 0xd8: return(inst_ret(code));
628 case 0xd9: return(inst_reti(code));
629 case 0xda: return(inst_jp(code));
630 case 0xdb: break;
631 case 0xdc: return(inst_call(code));
632
633 case 0xdd: break; /* IX register doesn't exist on the LR35902 */
634 case 0xde: return(inst_sbc(code));
635 case 0xdf: return(inst_rst(code));
636
637
638 case 0xe0: return(inst_ldh(code));
639 case 0xe1: return(inst_pop(code));
640 case 0xe2: return(inst_ldh(code));
641 case 0xe3:
642 case 0xe4: break;
643 case 0xe5: return(inst_push(code));
644 case 0xe6: return(inst_and(code));
645 case 0xe7: return(inst_rst(code));
646
647 case 0xe8: return(inst_add_sp_d(code));
648 case 0xe9: return(inst_jp(code));
649 case 0xea: return(inst_ld16(code));
650 case 0xeb:
651 case 0xec: case 0xed: break;
652 case 0xee: return(inst_xor(code));
653 case 0xef: return(inst_rst(code));
654
655 case 0xf0: return(inst_ldh(code));
656 case 0xf1: return(inst_pop(code));
657 case 0xf2: return(inst_ldh(code));
658 case 0xf3: return(inst_di(code));
659 case 0xf4: break;
660 case 0xf5: return(inst_push(code));
661 case 0xf6: return(inst_or(code));
662 case 0xf7: return(inst_rst(code));
663
664 case 0xf8: return(inst_ldhl_sp(code));
665 case 0xf9: return(inst_ld(code));
666 case 0xfa: return(inst_ld16(code));
667 case 0xfb: return(inst_ei(code));
668 case 0xfc:
669 case 0xfd: break;
670 case 0xfe: return(inst_cp(code));
671 case 0xff: return(inst_rst(code));
672 }
673
674 PC= rom->inc_address(PC, -1);
675
676 sim->stop(resINV_INST);
677 return(resINV_INST);
678 }
679