1 /**CFile****************************************************************
2
3 FileName [simSeq.c]
4
5 SystemName [ABC: Logic synthesis and verification system.]
6
7 PackageName [Network and node package.]
8
9 Synopsis [Simulation for sequential circuits.]
10
11 Author [Alan Mishchenko]
12
13 Affiliation [UC Berkeley]
14
15 Date [Ver. 1.0. Started - June 20, 2005.]
16
17 Revision [$Id: simUtils.c,v 1.00 2005/06/20 00:00:00 alanmi Exp $]
18
19 ***********************************************************************/
20
21 #include "base/abc/abc.h"
22 #include "sim.h"
23
24 ABC_NAMESPACE_IMPL_START
25
26
27 ////////////////////////////////////////////////////////////////////////
28 /// DECLARATIONS ///
29 ////////////////////////////////////////////////////////////////////////
30
31 static void Sim_SimulateSeqFrame( Vec_Ptr_t * vInfo, Abc_Ntk_t * pNtk, int iFrames, int nWords, int fTransfer );
32
33 ////////////////////////////////////////////////////////////////////////
34 /// FUNCTION DEFINITIONS ///
35 ////////////////////////////////////////////////////////////////////////
36
37 /**Function*************************************************************
38
39 Synopsis [Simulates sequential circuit.]
40
41 Description [Takes sequential circuit (pNtk). Simulates the given number
42 (nFrames) of the circuit with the given number of machine words (nWords)
43 of random simulation data, starting from the initial state. If the initial
44 state of some latches is a don't-care, uses random input for that latch.]
45
46 SideEffects []
47
48 SeeAlso []
49
50 ***********************************************************************/
Sim_SimulateSeqRandom(Abc_Ntk_t * pNtk,int nFrames,int nWords)51 Vec_Ptr_t * Sim_SimulateSeqRandom( Abc_Ntk_t * pNtk, int nFrames, int nWords )
52 {
53 Vec_Ptr_t * vInfo;
54 Abc_Obj_t * pNode;
55 int i;
56 assert( Abc_NtkIsStrash(pNtk) );
57 vInfo = Sim_UtilInfoAlloc( Abc_NtkObjNumMax(pNtk), nWords * nFrames, 0 );
58 // set the constant data
59 pNode = Abc_AigConst1(pNtk);
60 Sim_UtilSetConst( Sim_SimInfoGet(vInfo,pNode), nWords * nFrames, 1 );
61 // set the random PI data
62 Abc_NtkForEachPi( pNtk, pNode, i )
63 Sim_UtilSetRandom( Sim_SimInfoGet(vInfo,pNode), nWords * nFrames );
64 // set the initial state data
65 Abc_NtkForEachLatch( pNtk, pNode, i )
66 if ( Abc_LatchIsInit0(pNode) )
67 Sim_UtilSetConst( Sim_SimInfoGet(vInfo,pNode), nWords, 0 );
68 else if ( Abc_LatchIsInit1(pNode) )
69 Sim_UtilSetConst( Sim_SimInfoGet(vInfo,pNode), nWords, 1 );
70 else
71 Sim_UtilSetRandom( Sim_SimInfoGet(vInfo,pNode), nWords );
72 // simulate the nodes for the given number of timeframes
73 for ( i = 0; i < nFrames; i++ )
74 Sim_SimulateSeqFrame( vInfo, pNtk, i, nWords, (int)(i < nFrames-1) );
75 return vInfo;
76 }
77
78 /**Function*************************************************************
79
80 Synopsis [Simulates sequential circuit.]
81
82 Description [Takes sequential circuit (pNtk). Simulates the given number
83 (nFrames) of the circuit with the given model. The model is assumed to
84 contain values of PIs for each frame. The latches are initialized to
85 the initial state. One word of data is simulated.]
86
87 SideEffects []
88
89 SeeAlso []
90
91 ***********************************************************************/
Sim_SimulateSeqModel(Abc_Ntk_t * pNtk,int nFrames,int * pModel)92 Vec_Ptr_t * Sim_SimulateSeqModel( Abc_Ntk_t * pNtk, int nFrames, int * pModel )
93 {
94 Vec_Ptr_t * vInfo;
95 Abc_Obj_t * pNode;
96 unsigned * pUnsigned;
97 int i, k;
98 vInfo = Sim_UtilInfoAlloc( Abc_NtkObjNumMax(pNtk), nFrames, 0 );
99 // set the constant data
100 pNode = Abc_AigConst1(pNtk);
101 Sim_UtilSetConst( Sim_SimInfoGet(vInfo,pNode), nFrames, 1 );
102 // set the random PI data
103 Abc_NtkForEachPi( pNtk, pNode, i )
104 {
105 pUnsigned = Sim_SimInfoGet(vInfo,pNode);
106 for ( k = 0; k < nFrames; k++ )
107 pUnsigned[k] = pModel[k * Abc_NtkPiNum(pNtk) + i] ? ~((unsigned)0) : 0;
108 }
109 // set the initial state data
110 Abc_NtkForEachLatch( pNtk, pNode, i )
111 {
112 pUnsigned = Sim_SimInfoGet(vInfo,pNode);
113 if ( Abc_LatchIsInit0(pNode) )
114 pUnsigned[0] = 0;
115 else if ( Abc_LatchIsInit1(pNode) )
116 pUnsigned[0] = ~((unsigned)0);
117 else
118 pUnsigned[0] = SIM_RANDOM_UNSIGNED;
119 }
120 // simulate the nodes for the given number of timeframes
121 for ( i = 0; i < nFrames; i++ )
122 Sim_SimulateSeqFrame( vInfo, pNtk, i, 1, (int)(i < nFrames-1) );
123 /*
124 // print the simulated values
125 for ( i = 0; i < nFrames; i++ )
126 {
127 printf( "Frame %d : ", i+1 );
128 Abc_NtkForEachPi( pNtk, pNode, k )
129 printf( "%d", Sim_SimInfoGet(vInfo,pNode)[i] > 0 );
130 printf( " " );
131 Abc_NtkForEachLatch( pNtk, pNode, k )
132 printf( "%d", Sim_SimInfoGet(vInfo,pNode)[i] > 0 );
133 printf( " " );
134 Abc_NtkForEachPo( pNtk, pNode, k )
135 printf( "%d", Sim_SimInfoGet(vInfo,pNode)[i] > 0 );
136 printf( "\n" );
137 }
138 printf( "\n" );
139 */
140 return vInfo;
141 }
142
143 /**Function*************************************************************
144
145 Synopsis [Simulates one frame of sequential circuit.]
146
147 Description [Assumes that the latches and POs are already initialized.
148 In the end transfers the data to the latches of the next frame.]
149
150 SideEffects []
151
152 SeeAlso []
153
154 ***********************************************************************/
Sim_SimulateSeqFrame(Vec_Ptr_t * vInfo,Abc_Ntk_t * pNtk,int iFrames,int nWords,int fTransfer)155 void Sim_SimulateSeqFrame( Vec_Ptr_t * vInfo, Abc_Ntk_t * pNtk, int iFrames, int nWords, int fTransfer )
156 {
157 Abc_Obj_t * pNode;
158 int i;
159 Abc_NtkForEachNode( pNtk, pNode, i )
160 Sim_UtilSimulateNodeOne( pNode, vInfo, nWords, iFrames * nWords );
161 Abc_NtkForEachPo( pNtk, pNode, i )
162 Sim_UtilTransferNodeOne( pNode, vInfo, nWords, iFrames * nWords, 0 );
163 if ( !fTransfer )
164 return;
165 Abc_NtkForEachLatch( pNtk, pNode, i )
166 Sim_UtilTransferNodeOne( pNode, vInfo, nWords, iFrames * nWords, 1 );
167 }
168
169
170 ////////////////////////////////////////////////////////////////////////
171 /// END OF FILE ///
172 ////////////////////////////////////////////////////////////////////////
173
174
175 ABC_NAMESPACE_IMPL_END
176
177