1 /* $NetBSD: soc15_common.h,v 1.2 2021/12/18 23:44:59 riastradh Exp $ */ 2 3 /* 4 * Copyright 2016 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 */ 25 26 #ifndef __SOC15_COMMON_H__ 27 #define __SOC15_COMMON_H__ 28 29 /* Register Access Macros */ 30 #define SOC15_REG_OFFSET(ip, inst, reg) (adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) 31 32 #define WREG32_FIELD15(ip, idx, reg, field, val) \ 33 WREG32(adev->reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg, \ 34 (RREG32(adev->reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg) \ 35 & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) 36 37 #define RREG32_SOC15(ip, inst, reg) \ 38 RREG32(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) 39 40 #define RREG32_SOC15_OFFSET(ip, inst, reg, offset) \ 41 RREG32((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) + offset) 42 43 #define WREG32_SOC15(ip, inst, reg, value) \ 44 WREG32((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg), value) 45 46 #define WREG32_SOC15_NO_KIQ(ip, inst, reg, value) \ 47 WREG32_NO_KIQ((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg), value) 48 49 #define WREG32_SOC15_OFFSET(ip, inst, reg, offset, value) \ 50 WREG32((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) + offset, value) 51 52 #define SOC15_WAIT_ON_RREG(ip, inst, reg, expected_value, mask, ret) \ 53 do { \ 54 uint32_t old_ = 0; \ 55 uint32_t tmp_ = RREG32(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg); \ 56 uint32_t loop = adev->usec_timeout; \ 57 ret = 0; \ 58 while ((tmp_ & (mask)) != (expected_value)) { \ 59 if (old_ != tmp_) { \ 60 loop = adev->usec_timeout; \ 61 old_ = tmp_; \ 62 } else \ 63 udelay(1); \ 64 tmp_ = RREG32(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg); \ 65 loop--; \ 66 if (!loop) { \ 67 DRM_WARN("Register(%d) [%s] failed to reach value 0x%08x != 0x%08x\n", \ 68 inst, #reg, (unsigned)expected_value, (unsigned)(tmp_ & (mask))); \ 69 ret = -ETIMEDOUT; \ 70 break; \ 71 } \ 72 } \ 73 } while (0) 74 75 #define AMDGPU_VIRT_SUPPORT_RLC_PRG_REG(a) (amdgpu_sriov_vf((a)) && !amdgpu_sriov_runtime((a))) 76 #define WREG32_RLC(reg, value) \ 77 do { \ 78 if (AMDGPU_VIRT_SUPPORT_RLC_PRG_REG(adev)) { \ 79 uint32_t i = 0; \ 80 uint32_t retries = 50000; \ 81 uint32_t r0 = adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG0_BASE_IDX] + mmSCRATCH_REG0; \ 82 uint32_t r1 = adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG1; \ 83 uint32_t spare_int = adev->reg_offset[GC_HWIP][0][mmRLC_SPARE_INT_BASE_IDX] + mmRLC_SPARE_INT; \ 84 WREG32(r0, value); \ 85 WREG32(r1, (reg | 0x80000000)); \ 86 WREG32(spare_int, 0x1); \ 87 for (i = 0; i < retries; i++) { \ 88 u32 tmp = RREG32(r1); \ 89 if (!(tmp & 0x80000000)) \ 90 break; \ 91 udelay(10); \ 92 } \ 93 if (i >= retries) \ 94 pr_err("timeout: rlcg program reg:0x%05x failed !\n", reg); \ 95 } else { \ 96 WREG32(reg, value); \ 97 } \ 98 } while (0) 99 100 #define WREG32_SOC15_RLC_SHADOW(ip, inst, reg, value) \ 101 do { \ 102 uint32_t target_reg = adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg;\ 103 if (AMDGPU_VIRT_SUPPORT_RLC_PRG_REG(adev)) { \ 104 uint32_t r2 = adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG2; \ 105 uint32_t r3 = adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG3; \ 106 uint32_t grbm_cntl = adev->reg_offset[GC_HWIP][0][mmGRBM_GFX_CNTL_BASE_IDX] + mmGRBM_GFX_CNTL; \ 107 uint32_t grbm_idx = adev->reg_offset[GC_HWIP][0][mmGRBM_GFX_INDEX_BASE_IDX] + mmGRBM_GFX_INDEX; \ 108 if (target_reg == grbm_cntl) \ 109 WREG32(r2, value); \ 110 else if (target_reg == grbm_idx) \ 111 WREG32(r3, value); \ 112 WREG32(target_reg, value); \ 113 } else { \ 114 WREG32(target_reg, value); \ 115 } \ 116 } while (0) 117 118 #define WREG32_SOC15_RLC(ip, inst, reg, value) \ 119 do { \ 120 uint32_t target_reg = adev->reg_offset[GC_HWIP][0][reg##_BASE_IDX] + reg;\ 121 WREG32_RLC(target_reg, value); \ 122 } while (0) 123 124 #define WREG32_FIELD15_RLC(ip, idx, reg, field, val) \ 125 WREG32_RLC((adev->reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg), \ 126 (RREG32(adev->reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg) \ 127 & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) 128 129 #define WREG32_SOC15_OFFSET_RLC(ip, inst, reg, offset, value) \ 130 WREG32_RLC(((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) + offset), value) 131 132 #endif 133