1 /** 2 ****************************************************************************** 3 * @file stm32f30x_rcc.h 4 * @author MCD Application Team 5 * @version V1.2.3 6 * @date 10-July-2015 7 * @brief This file contains all the functions prototypes for the RCC 8 * firmware library. 9 ****************************************************************************** 10 * @attention 11 * 12 * <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2> 13 * 14 * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); 15 * You may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at: 17 * 18 * http://www.st.com/software_license_agreement_liberty_v2 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 ****************************************************************************** 27 */ 28 29 /* Define to prevent recursive inclusion -------------------------------------*/ 30 #ifndef __STM32F30x_RCC_H 31 #define __STM32F30x_RCC_H 32 33 #ifdef __cplusplus 34 extern "C" { 35 #endif 36 37 /* Includes ------------------------------------------------------------------*/ 38 #include "stm32f30x.h" 39 40 /** @addtogroup STM32F30x_StdPeriph_Driver 41 * @{ 42 */ 43 44 /** @addtogroup RCC 45 * @{ 46 */ 47 48 /* Exported types ------------------------------------------------------------*/ 49 50 typedef struct 51 { 52 uint32_t SYSCLK_Frequency; 53 uint32_t HCLK_Frequency; 54 uint32_t PCLK1_Frequency; 55 uint32_t PCLK2_Frequency; 56 uint32_t ADC12CLK_Frequency; 57 uint32_t ADC34CLK_Frequency; 58 uint32_t I2C1CLK_Frequency; 59 uint32_t I2C2CLK_Frequency; 60 uint32_t I2C3CLK_Frequency; 61 uint32_t TIM1CLK_Frequency; 62 uint32_t HRTIM1CLK_Frequency; 63 uint32_t TIM8CLK_Frequency; 64 uint32_t TIM2CLK_Frequency; 65 uint32_t TIM3CLK_Frequency; 66 uint32_t USART1CLK_Frequency; 67 uint32_t USART2CLK_Frequency; 68 uint32_t USART3CLK_Frequency; 69 uint32_t UART4CLK_Frequency; 70 uint32_t UART5CLK_Frequency; 71 uint32_t TIM15CLK_Frequency; 72 uint32_t TIM16CLK_Frequency; 73 uint32_t TIM17CLK_Frequency; 74 uint32_t TIM20CLK_Frequency; 75 }RCC_ClocksTypeDef; 76 77 /* Exported constants --------------------------------------------------------*/ 78 79 /** @defgroup RCC_Exported_Constants 80 * @{ 81 */ 82 83 /** @defgroup RCC_HSE_configuration 84 * @{ 85 */ 86 87 #define RCC_HSE_OFF ((uint8_t)0x00) 88 #define RCC_HSE_ON ((uint8_t)0x01) 89 #define RCC_HSE_Bypass ((uint8_t)0x05) 90 #define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \ 91 ((HSE) == RCC_HSE_Bypass)) 92 93 /** 94 * @} 95 */ 96 97 /** @defgroup RCC_PLL_Clock_Source 98 * @{ 99 */ 100 #define RCC_PLLSource_HSI RCC_CFGR_PLLSRC_HSI_PREDIV /*!< Only applicable for STM32F303xE devices */ 101 #define RCC_PLLSource_HSI_Div2 RCC_CFGR_PLLSRC_HSI_Div2 102 #define RCC_PLLSource_PREDIV1 RCC_CFGR_PLLSRC_PREDIV1 103 104 #define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI_Div2) || \ 105 ((SOURCE) == RCC_PLLSource_PREDIV1)|| \ 106 ((SOURCE) == RCC_PLLSource_HSI)) 107 108 /** 109 * @} 110 */ 111 112 /** @defgroup RCC_PLL_Multiplication_Factor 113 * @{ 114 */ 115 116 #define RCC_PLLMul_2 RCC_CFGR_PLLMULL2 117 #define RCC_PLLMul_3 RCC_CFGR_PLLMULL3 118 #define RCC_PLLMul_4 RCC_CFGR_PLLMULL4 119 #define RCC_PLLMul_5 RCC_CFGR_PLLMULL5 120 #define RCC_PLLMul_6 RCC_CFGR_PLLMULL6 121 #define RCC_PLLMul_7 RCC_CFGR_PLLMULL7 122 #define RCC_PLLMul_8 RCC_CFGR_PLLMULL8 123 #define RCC_PLLMul_9 RCC_CFGR_PLLMULL9 124 #define RCC_PLLMul_10 RCC_CFGR_PLLMULL10 125 #define RCC_PLLMul_11 RCC_CFGR_PLLMULL11 126 #define RCC_PLLMul_12 RCC_CFGR_PLLMULL12 127 #define RCC_PLLMul_13 RCC_CFGR_PLLMULL13 128 #define RCC_PLLMul_14 RCC_CFGR_PLLMULL14 129 #define RCC_PLLMul_15 RCC_CFGR_PLLMULL15 130 #define RCC_PLLMul_16 RCC_CFGR_PLLMULL16 131 #define IS_RCC_PLL_MUL(MUL) (((MUL) == RCC_PLLMul_2) || ((MUL) == RCC_PLLMul_3) || \ 132 ((MUL) == RCC_PLLMul_4) || ((MUL) == RCC_PLLMul_5) || \ 133 ((MUL) == RCC_PLLMul_6) || ((MUL) == RCC_PLLMul_7) || \ 134 ((MUL) == RCC_PLLMul_8) || ((MUL) == RCC_PLLMul_9) || \ 135 ((MUL) == RCC_PLLMul_10) || ((MUL) == RCC_PLLMul_11) || \ 136 ((MUL) == RCC_PLLMul_12) || ((MUL) == RCC_PLLMul_13) || \ 137 ((MUL) == RCC_PLLMul_14) || ((MUL) == RCC_PLLMul_15) || \ 138 ((MUL) == RCC_PLLMul_16)) 139 /** 140 * @} 141 */ 142 143 /** @defgroup RCC_PREDIV1_division_factor 144 * @{ 145 */ 146 #define RCC_PREDIV1_Div1 RCC_CFGR2_PREDIV1_DIV1 147 #define RCC_PREDIV1_Div2 RCC_CFGR2_PREDIV1_DIV2 148 #define RCC_PREDIV1_Div3 RCC_CFGR2_PREDIV1_DIV3 149 #define RCC_PREDIV1_Div4 RCC_CFGR2_PREDIV1_DIV4 150 #define RCC_PREDIV1_Div5 RCC_CFGR2_PREDIV1_DIV5 151 #define RCC_PREDIV1_Div6 RCC_CFGR2_PREDIV1_DIV6 152 #define RCC_PREDIV1_Div7 RCC_CFGR2_PREDIV1_DIV7 153 #define RCC_PREDIV1_Div8 RCC_CFGR2_PREDIV1_DIV8 154 #define RCC_PREDIV1_Div9 RCC_CFGR2_PREDIV1_DIV9 155 #define RCC_PREDIV1_Div10 RCC_CFGR2_PREDIV1_DIV10 156 #define RCC_PREDIV1_Div11 RCC_CFGR2_PREDIV1_DIV11 157 #define RCC_PREDIV1_Div12 RCC_CFGR2_PREDIV1_DIV12 158 #define RCC_PREDIV1_Div13 RCC_CFGR2_PREDIV1_DIV13 159 #define RCC_PREDIV1_Div14 RCC_CFGR2_PREDIV1_DIV14 160 #define RCC_PREDIV1_Div15 RCC_CFGR2_PREDIV1_DIV15 161 #define RCC_PREDIV1_Div16 RCC_CFGR2_PREDIV1_DIV16 162 163 #define IS_RCC_PREDIV1(PREDIV1) (((PREDIV1) == RCC_PREDIV1_Div1) || ((PREDIV1) == RCC_PREDIV1_Div2) || \ 164 ((PREDIV1) == RCC_PREDIV1_Div3) || ((PREDIV1) == RCC_PREDIV1_Div4) || \ 165 ((PREDIV1) == RCC_PREDIV1_Div5) || ((PREDIV1) == RCC_PREDIV1_Div6) || \ 166 ((PREDIV1) == RCC_PREDIV1_Div7) || ((PREDIV1) == RCC_PREDIV1_Div8) || \ 167 ((PREDIV1) == RCC_PREDIV1_Div9) || ((PREDIV1) == RCC_PREDIV1_Div10) || \ 168 ((PREDIV1) == RCC_PREDIV1_Div11) || ((PREDIV1) == RCC_PREDIV1_Div12) || \ 169 ((PREDIV1) == RCC_PREDIV1_Div13) || ((PREDIV1) == RCC_PREDIV1_Div14) || \ 170 ((PREDIV1) == RCC_PREDIV1_Div15) || ((PREDIV1) == RCC_PREDIV1_Div16)) 171 /** 172 * @} 173 */ 174 175 /** @defgroup RCC_System_Clock_Source 176 * @{ 177 */ 178 179 #define RCC_SYSCLKSource_HSI RCC_CFGR_SW_HSI 180 #define RCC_SYSCLKSource_HSE RCC_CFGR_SW_HSE 181 #define RCC_SYSCLKSource_PLLCLK RCC_CFGR_SW_PLL 182 #define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_HSI) || \ 183 ((SOURCE) == RCC_SYSCLKSource_HSE) || \ 184 ((SOURCE) == RCC_SYSCLKSource_PLLCLK)) 185 /** 186 * @} 187 */ 188 189 /** @defgroup RCC_AHB_Clock_Source 190 * @{ 191 */ 192 193 #define RCC_SYSCLK_Div1 RCC_CFGR_HPRE_DIV1 194 #define RCC_SYSCLK_Div2 RCC_CFGR_HPRE_DIV2 195 #define RCC_SYSCLK_Div4 RCC_CFGR_HPRE_DIV4 196 #define RCC_SYSCLK_Div8 RCC_CFGR_HPRE_DIV8 197 #define RCC_SYSCLK_Div16 RCC_CFGR_HPRE_DIV16 198 #define RCC_SYSCLK_Div64 RCC_CFGR_HPRE_DIV64 199 #define RCC_SYSCLK_Div128 RCC_CFGR_HPRE_DIV128 200 #define RCC_SYSCLK_Div256 RCC_CFGR_HPRE_DIV256 201 #define RCC_SYSCLK_Div512 RCC_CFGR_HPRE_DIV512 202 #define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_Div1) || ((HCLK) == RCC_SYSCLK_Div2) || \ 203 ((HCLK) == RCC_SYSCLK_Div4) || ((HCLK) == RCC_SYSCLK_Div8) || \ 204 ((HCLK) == RCC_SYSCLK_Div16) || ((HCLK) == RCC_SYSCLK_Div64) || \ 205 ((HCLK) == RCC_SYSCLK_Div128) || ((HCLK) == RCC_SYSCLK_Div256) || \ 206 ((HCLK) == RCC_SYSCLK_Div512)) 207 /** 208 * @} 209 */ 210 211 /** @defgroup RCC_APB1_APB2_clock_source 212 * @{ 213 */ 214 215 #define RCC_HCLK_Div1 ((uint32_t)0x00000000) 216 #define RCC_HCLK_Div2 ((uint32_t)0x00000400) 217 #define RCC_HCLK_Div4 ((uint32_t)0x00000500) 218 #define RCC_HCLK_Div8 ((uint32_t)0x00000600) 219 #define RCC_HCLK_Div16 ((uint32_t)0x00000700) 220 #define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_Div1) || ((PCLK) == RCC_HCLK_Div2) || \ 221 ((PCLK) == RCC_HCLK_Div4) || ((PCLK) == RCC_HCLK_Div8) || \ 222 ((PCLK) == RCC_HCLK_Div16)) 223 /** 224 * @} 225 */ 226 227 /** @defgroup RCC_ADC_clock_source 228 * @{ 229 */ 230 231 /* ADC1 & ADC2 */ 232 #define RCC_ADC12PLLCLK_OFF ((uint32_t)0x00000000) 233 #define RCC_ADC12PLLCLK_Div1 ((uint32_t)0x00000100) 234 #define RCC_ADC12PLLCLK_Div2 ((uint32_t)0x00000110) 235 #define RCC_ADC12PLLCLK_Div4 ((uint32_t)0x00000120) 236 #define RCC_ADC12PLLCLK_Div6 ((uint32_t)0x00000130) 237 #define RCC_ADC12PLLCLK_Div8 ((uint32_t)0x00000140) 238 #define RCC_ADC12PLLCLK_Div10 ((uint32_t)0x00000150) 239 #define RCC_ADC12PLLCLK_Div12 ((uint32_t)0x00000160) 240 #define RCC_ADC12PLLCLK_Div16 ((uint32_t)0x00000170) 241 #define RCC_ADC12PLLCLK_Div32 ((uint32_t)0x00000180) 242 #define RCC_ADC12PLLCLK_Div64 ((uint32_t)0x00000190) 243 #define RCC_ADC12PLLCLK_Div128 ((uint32_t)0x000001A0) 244 #define RCC_ADC12PLLCLK_Div256 ((uint32_t)0x000001B0) 245 246 /* ADC3 & ADC4 */ 247 #define RCC_ADC34PLLCLK_OFF ((uint32_t)0x10000000) 248 #define RCC_ADC34PLLCLK_Div1 ((uint32_t)0x10002000) 249 #define RCC_ADC34PLLCLK_Div2 ((uint32_t)0x10002200) 250 #define RCC_ADC34PLLCLK_Div4 ((uint32_t)0x10002400) 251 #define RCC_ADC34PLLCLK_Div6 ((uint32_t)0x10002600) 252 #define RCC_ADC34PLLCLK_Div8 ((uint32_t)0x10002800) 253 #define RCC_ADC34PLLCLK_Div10 ((uint32_t)0x10002A00) 254 #define RCC_ADC34PLLCLK_Div12 ((uint32_t)0x10002C00) 255 #define RCC_ADC34PLLCLK_Div16 ((uint32_t)0x10002E00) 256 #define RCC_ADC34PLLCLK_Div32 ((uint32_t)0x10003000) 257 #define RCC_ADC34PLLCLK_Div64 ((uint32_t)0x10003200) 258 #define RCC_ADC34PLLCLK_Div128 ((uint32_t)0x10003400) 259 #define RCC_ADC34PLLCLK_Div256 ((uint32_t)0x10003600) 260 261 #define IS_RCC_ADCCLK(ADCCLK) (((ADCCLK) == RCC_ADC12PLLCLK_OFF) || ((ADCCLK) == RCC_ADC12PLLCLK_Div1) || \ 262 ((ADCCLK) == RCC_ADC12PLLCLK_Div2) || ((ADCCLK) == RCC_ADC12PLLCLK_Div4) || \ 263 ((ADCCLK) == RCC_ADC12PLLCLK_Div6) || ((ADCCLK) == RCC_ADC12PLLCLK_Div8) || \ 264 ((ADCCLK) == RCC_ADC12PLLCLK_Div10) || ((ADCCLK) == RCC_ADC12PLLCLK_Div12) || \ 265 ((ADCCLK) == RCC_ADC12PLLCLK_Div16) || ((ADCCLK) == RCC_ADC12PLLCLK_Div32) || \ 266 ((ADCCLK) == RCC_ADC12PLLCLK_Div64) || ((ADCCLK) == RCC_ADC12PLLCLK_Div128) || \ 267 ((ADCCLK) == RCC_ADC12PLLCLK_Div256) || ((ADCCLK) == RCC_ADC34PLLCLK_OFF) || \ 268 ((ADCCLK) == RCC_ADC34PLLCLK_Div1) || ((ADCCLK) == RCC_ADC34PLLCLK_Div2) || \ 269 ((ADCCLK) == RCC_ADC34PLLCLK_Div4) || ((ADCCLK) == RCC_ADC34PLLCLK_Div6) || \ 270 ((ADCCLK) == RCC_ADC34PLLCLK_Div8) || ((ADCCLK) == RCC_ADC34PLLCLK_Div10) || \ 271 ((ADCCLK) == RCC_ADC34PLLCLK_Div12) || ((ADCCLK) == RCC_ADC34PLLCLK_Div16) || \ 272 ((ADCCLK) == RCC_ADC34PLLCLK_Div32) || ((ADCCLK) == RCC_ADC34PLLCLK_Div64) || \ 273 ((ADCCLK) == RCC_ADC34PLLCLK_Div128) || ((ADCCLK) == RCC_ADC34PLLCLK_Div256)) 274 275 /** 276 * @} 277 */ 278 279 /** @defgroup RCC_TIM_clock_source 280 * @{ 281 */ 282 283 #define RCC_TIM1CLK_PCLK ((uint32_t)0x00000000) 284 #define RCC_TIM1CLK_PLLCLK RCC_CFGR3_TIM1SW 285 286 #define RCC_TIM8CLK_PCLK ((uint32_t)0x10000000) 287 #define RCC_TIM8CLK_PLLCLK ((uint32_t)0x10000200) 288 289 #define RCC_TIM15CLK_PCLK ((uint32_t)0x20000000) 290 #define RCC_TIM15CLK_PLLCLK ((uint32_t)0x20000400) 291 292 #define RCC_TIM16CLK_PCLK ((uint32_t)0x30000000) 293 #define RCC_TIM16CLK_PLLCLK ((uint32_t)0x30000800) 294 295 #define RCC_TIM17CLK_PCLK ((uint32_t)0x40000000) 296 #define RCC_TIM17CLK_PLLCLK ((uint32_t)0x40002000) 297 298 #define RCC_TIM20CLK_PCLK ((uint32_t)0x50000000) 299 #define RCC_TIM20CLK_PLLCLK ((uint32_t)0x50008000) 300 301 #define RCC_TIM2CLK_PCLK ((uint32_t)0x60000000) 302 #define RCC_TIM2CLK_PLLCLK ((uint32_t)0x61000000) 303 304 #define RCC_TIM3TIM4CLK_PCLK ((uint32_t)0x70000000) 305 #define RCC_TIM3TIM4CLK_PLLCLK ((uint32_t)0x72000000) 306 307 #define IS_RCC_TIMCLK(TIMCLK) (((TIMCLK) == RCC_TIM1CLK_PCLK) || ((TIMCLK) == RCC_TIM1CLK_PLLCLK) || \ 308 ((TIMCLK) == RCC_TIM8CLK_PCLK) || ((TIMCLK) == RCC_TIM8CLK_PLLCLK) || \ 309 ((TIMCLK) == RCC_TIM15CLK_PCLK) || ((TIMCLK) == RCC_TIM15CLK_PLLCLK) || \ 310 ((TIMCLK) == RCC_TIM16CLK_PCLK) || ((TIMCLK) == RCC_TIM16CLK_PLLCLK) || \ 311 ((TIMCLK) == RCC_TIM17CLK_PCLK) || ((TIMCLK) == RCC_TIM17CLK_PLLCLK)|| \ 312 ((TIMCLK) == RCC_TIM20CLK_PCLK) || ((TIMCLK) == RCC_TIM20CLK_PLLCLK)|| \ 313 ((TIMCLK) == RCC_TIM2CLK_PCLK) || ((TIMCLK) == RCC_TIM2CLK_PLLCLK)|| \ 314 ((TIMCLK) == RCC_TIM3TIM4CLK_PCLK) || ((TIMCLK) == RCC_TIM3TIM4CLK_PLLCLK)) 315 /* legacy RCC_TIM_clock_source*/ 316 #define RCC_TIM1CLK_HCLK RCC_TIM1CLK_PCLK 317 #define RCC_TIM8CLK_HCLK RCC_TIM8CLK_PCLK 318 #define RCC_TIM15CLK_HCLK RCC_TIM15CLK_PCLK 319 #define RCC_TIM16CLK_HCLK RCC_TIM16CLK_PCLK 320 #define RCC_TIM17CLK_HCLK RCC_TIM17CLK_PCLK 321 #define RCC_TIM20CLK_HCLK RCC_TIM20CLK_PCLK 322 #define RCC_TIM2CLK_HCLK RCC_TIM2CLK_PCLK 323 #define RCC_TIM3CLK_HCLK RCC_TIM3TIM4CLK_PCLK 324 #define RCC_TIM3CLK_PLLCLK RCC_TIM3TIM4CLK_PLLCLK 325 /** 326 * @} 327 */ 328 329 /** @defgroup RCC_HRTIM_clock_source 330 * @{ 331 */ 332 333 #define RCC_HRTIM1CLK_HCLK ((uint32_t)0x00000000) 334 #define RCC_HRTIM1CLK_PLLCLK RCC_CFGR3_HRTIM1SW 335 336 #define IS_RCC_HRTIMCLK(HRTIMCLK) (((HRTIMCLK) == RCC_HRTIM1CLK_HCLK) || ((HRTIMCLK) == RCC_HRTIM1CLK_PLLCLK)) 337 338 /** 339 * @} 340 */ 341 342 /** @defgroup RCC_I2C_clock_source 343 * @{ 344 */ 345 346 #define RCC_I2C1CLK_HSI ((uint32_t)0x00000000) 347 #define RCC_I2C1CLK_SYSCLK RCC_CFGR3_I2C1SW 348 349 #define RCC_I2C2CLK_HSI ((uint32_t)0x10000000) 350 #define RCC_I2C2CLK_SYSCLK ((uint32_t)0x10000020) 351 352 #define RCC_I2C3CLK_HSI ((uint32_t)0x20000000) 353 #define RCC_I2C3CLK_SYSCLK ((uint32_t)0x20000040) 354 355 #define IS_RCC_I2CCLK(I2CCLK) (((I2CCLK) == RCC_I2C1CLK_HSI) || ((I2CCLK) == RCC_I2C1CLK_SYSCLK) || \ 356 ((I2CCLK) == RCC_I2C2CLK_HSI) || ((I2CCLK) == RCC_I2C2CLK_SYSCLK) || \ 357 ((I2CCLK) == RCC_I2C3CLK_HSI) || ((I2CCLK) == RCC_I2C3CLK_SYSCLK)) 358 359 /** 360 * @} 361 */ 362 363 /** @defgroup RCC_USART_clock_source 364 * @{ 365 */ 366 367 #define RCC_USART1CLK_PCLK ((uint32_t)0x10000000) 368 #define RCC_USART1CLK_SYSCLK ((uint32_t)0x10000001) 369 #define RCC_USART1CLK_LSE ((uint32_t)0x10000002) 370 #define RCC_USART1CLK_HSI ((uint32_t)0x10000003) 371 372 #define RCC_USART2CLK_PCLK ((uint32_t)0x20000000) 373 #define RCC_USART2CLK_SYSCLK ((uint32_t)0x20010000) 374 #define RCC_USART2CLK_LSE ((uint32_t)0x20020000) 375 #define RCC_USART2CLK_HSI ((uint32_t)0x20030000) 376 377 #define RCC_USART3CLK_PCLK ((uint32_t)0x30000000) 378 #define RCC_USART3CLK_SYSCLK ((uint32_t)0x30040000) 379 #define RCC_USART3CLK_LSE ((uint32_t)0x30080000) 380 #define RCC_USART3CLK_HSI ((uint32_t)0x300C0000) 381 382 #define RCC_UART4CLK_PCLK ((uint32_t)0x40000000) 383 #define RCC_UART4CLK_SYSCLK ((uint32_t)0x40100000) 384 #define RCC_UART4CLK_LSE ((uint32_t)0x40200000) 385 #define RCC_UART4CLK_HSI ((uint32_t)0x40300000) 386 387 #define RCC_UART5CLK_PCLK ((uint32_t)0x50000000) 388 #define RCC_UART5CLK_SYSCLK ((uint32_t)0x50400000) 389 #define RCC_UART5CLK_LSE ((uint32_t)0x50800000) 390 #define RCC_UART5CLK_HSI ((uint32_t)0x50C00000) 391 392 #define IS_RCC_USARTCLK(USARTCLK) (((USARTCLK) == RCC_USART1CLK_PCLK) || ((USARTCLK) == RCC_USART1CLK_SYSCLK) || \ 393 ((USARTCLK) == RCC_USART1CLK_LSE) || ((USARTCLK) == RCC_USART1CLK_HSI) ||\ 394 ((USARTCLK) == RCC_USART2CLK_PCLK) || ((USARTCLK) == RCC_USART2CLK_SYSCLK) || \ 395 ((USARTCLK) == RCC_USART2CLK_LSE) || ((USARTCLK) == RCC_USART2CLK_HSI) || \ 396 ((USARTCLK) == RCC_USART3CLK_PCLK) || ((USARTCLK) == RCC_USART3CLK_SYSCLK) || \ 397 ((USARTCLK) == RCC_USART3CLK_LSE) || ((USARTCLK) == RCC_USART3CLK_HSI) || \ 398 ((USARTCLK) == RCC_UART4CLK_PCLK) || ((USARTCLK) == RCC_UART4CLK_SYSCLK) || \ 399 ((USARTCLK) == RCC_UART4CLK_LSE) || ((USARTCLK) == RCC_UART4CLK_HSI) || \ 400 ((USARTCLK) == RCC_UART5CLK_PCLK) || ((USARTCLK) == RCC_UART5CLK_SYSCLK) || \ 401 ((USARTCLK) == RCC_UART5CLK_LSE) || ((USARTCLK) == RCC_UART5CLK_HSI)) 402 403 /** 404 * @} 405 */ 406 407 /** @defgroup RCC_Interrupt_Source 408 * @{ 409 */ 410 411 #define RCC_IT_LSIRDY ((uint8_t)0x01) 412 #define RCC_IT_LSERDY ((uint8_t)0x02) 413 #define RCC_IT_HSIRDY ((uint8_t)0x04) 414 #define RCC_IT_HSERDY ((uint8_t)0x08) 415 #define RCC_IT_PLLRDY ((uint8_t)0x10) 416 #define RCC_IT_CSS ((uint8_t)0x80) 417 418 #define IS_RCC_IT(IT) ((((IT) & (uint8_t)0xC0) == 0x00) && ((IT) != 0x00)) 419 420 #define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \ 421 ((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \ 422 ((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_CSS)) 423 424 425 #define IS_RCC_CLEAR_IT(IT) ((((IT) & (uint8_t)0x40) == 0x00) && ((IT) != 0x00)) 426 427 /** 428 * @} 429 */ 430 431 /** @defgroup RCC_LSE_configuration 432 * @{ 433 */ 434 435 #define RCC_LSE_OFF ((uint32_t)0x00000000) 436 #define RCC_LSE_ON RCC_BDCR_LSEON 437 #define RCC_LSE_Bypass ((uint32_t)(RCC_BDCR_LSEON | RCC_BDCR_LSEBYP)) 438 #define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \ 439 ((LSE) == RCC_LSE_Bypass)) 440 /** 441 * @} 442 */ 443 444 /** @defgroup RCC_RTC_Clock_Source 445 * @{ 446 */ 447 448 #define RCC_RTCCLKSource_LSE RCC_BDCR_RTCSEL_LSE 449 #define RCC_RTCCLKSource_LSI RCC_BDCR_RTCSEL_LSI 450 #define RCC_RTCCLKSource_HSE_Div32 RCC_BDCR_RTCSEL_HSE 451 452 #define IS_RCC_RTCCLK_SOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSource_LSE) || \ 453 ((SOURCE) == RCC_RTCCLKSource_LSI) || \ 454 ((SOURCE) == RCC_RTCCLKSource_HSE_Div32)) 455 /** 456 * @} 457 */ 458 459 /** @defgroup RCC_I2S_Clock_Source 460 * @{ 461 */ 462 #define RCC_I2S2CLKSource_SYSCLK ((uint8_t)0x00) 463 #define RCC_I2S2CLKSource_Ext ((uint8_t)0x01) 464 465 #define IS_RCC_I2SCLK_SOURCE(SOURCE) (((SOURCE) == RCC_I2S2CLKSource_SYSCLK) || ((SOURCE) == RCC_I2S2CLKSource_Ext)) 466 467 /** @defgroup RCC_LSE_Drive_Configuration 468 * @{ 469 */ 470 471 #define RCC_LSEDrive_Low ((uint32_t)0x00000000) 472 #define RCC_LSEDrive_MediumLow RCC_BDCR_LSEDRV_0 473 #define RCC_LSEDrive_MediumHigh RCC_BDCR_LSEDRV_1 474 #define RCC_LSEDrive_High RCC_BDCR_LSEDRV 475 #define IS_RCC_LSE_DRIVE(DRIVE) (((DRIVE) == RCC_LSEDrive_Low) || ((DRIVE) == RCC_LSEDrive_MediumLow) || \ 476 ((DRIVE) == RCC_LSEDrive_MediumHigh) || ((DRIVE) == RCC_LSEDrive_High)) 477 /** 478 * @} 479 */ 480 481 /** @defgroup RCC_AHB_Peripherals 482 * @{ 483 */ 484 485 #define RCC_AHBPeriph_ADC34 RCC_AHBENR_ADC34EN 486 #define RCC_AHBPeriph_ADC12 RCC_AHBENR_ADC12EN 487 #define RCC_AHBPeriph_GPIOA RCC_AHBENR_GPIOAEN 488 #define RCC_AHBPeriph_GPIOB RCC_AHBENR_GPIOBEN 489 #define RCC_AHBPeriph_GPIOC RCC_AHBENR_GPIOCEN 490 #define RCC_AHBPeriph_GPIOD RCC_AHBENR_GPIODEN 491 #define RCC_AHBPeriph_GPIOE RCC_AHBENR_GPIOEEN 492 #define RCC_AHBPeriph_GPIOF RCC_AHBENR_GPIOFEN 493 #define RCC_AHBPeriph_GPIOG RCC_AHBENR_GPIOGEN 494 #define RCC_AHBPeriph_GPIOH RCC_AHBENR_GPIOHEN 495 #define RCC_AHBPeriph_TS RCC_AHBENR_TSEN 496 #define RCC_AHBPeriph_CRC RCC_AHBENR_CRCEN 497 #define RCC_AHBPeriph_FMC RCC_AHBENR_FMCEN 498 #define RCC_AHBPeriph_FLITF RCC_AHBENR_FLITFEN 499 #define RCC_AHBPeriph_SRAM RCC_AHBENR_SRAMEN 500 #define RCC_AHBPeriph_DMA2 RCC_AHBENR_DMA2EN 501 #define RCC_AHBPeriph_DMA1 RCC_AHBENR_DMA1EN 502 503 #define IS_RCC_AHB_PERIPH(PERIPH) ((((PERIPH) & 0xCE00FF88) == 0x00) && ((PERIPH) != 0x00)) 504 #define IS_RCC_AHB_RST_PERIPH(PERIPH) ((((PERIPH) & 0xCE00FFDF) == 0x00) && ((PERIPH) != 0x00)) 505 506 /** 507 * @} 508 */ 509 510 /** @defgroup RCC_APB2_Peripherals 511 * @{ 512 */ 513 514 #define RCC_APB2Periph_SYSCFG RCC_APB2ENR_SYSCFGEN 515 #define RCC_APB2Periph_TIM1 RCC_APB2ENR_TIM1EN 516 #define RCC_APB2Periph_SPI1 RCC_APB2ENR_SPI1EN 517 #define RCC_APB2Periph_TIM8 RCC_APB2ENR_TIM8EN 518 #define RCC_APB2Periph_USART1 RCC_APB2ENR_USART1EN 519 #define RCC_APB2Periph_SPI4 RCC_APB2ENR_SPI4EN 520 #define RCC_APB2Periph_TIM15 RCC_APB2ENR_TIM15EN 521 #define RCC_APB2Periph_TIM16 RCC_APB2ENR_TIM16EN 522 #define RCC_APB2Periph_TIM17 RCC_APB2ENR_TIM17EN 523 #define RCC_APB2Periph_TIM20 RCC_APB2ENR_TIM20EN 524 #define RCC_APB2Periph_HRTIM1 RCC_APB2ENR_HRTIM1 525 526 #define IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH) & 0xDFE807FE) == 0x00) && ((PERIPH) != 0x00)) 527 528 /** 529 * @} 530 */ 531 532 /** @defgroup RCC_APB1_Peripherals 533 * @{ 534 */ 535 #define RCC_APB1Periph_TIM2 RCC_APB1ENR_TIM2EN 536 #define RCC_APB1Periph_TIM3 RCC_APB1ENR_TIM3EN 537 #define RCC_APB1Periph_TIM4 RCC_APB1ENR_TIM4EN 538 #define RCC_APB1Periph_TIM6 RCC_APB1ENR_TIM6EN 539 #define RCC_APB1Periph_TIM7 RCC_APB1ENR_TIM7EN 540 #define RCC_APB1Periph_WWDG RCC_APB1ENR_WWDGEN 541 #define RCC_APB1Periph_SPI2 RCC_APB1ENR_SPI2EN 542 #define RCC_APB1Periph_SPI3 RCC_APB1ENR_SPI3EN 543 #define RCC_APB1Periph_USART2 RCC_APB1ENR_USART2EN 544 #define RCC_APB1Periph_USART3 RCC_APB1ENR_USART3EN 545 #define RCC_APB1Periph_UART4 RCC_APB1ENR_UART4EN 546 #define RCC_APB1Periph_UART5 RCC_APB1ENR_UART5EN 547 #define RCC_APB1Periph_I2C1 RCC_APB1ENR_I2C1EN 548 #define RCC_APB1Periph_I2C2 RCC_APB1ENR_I2C2EN 549 #define RCC_APB1Periph_USB RCC_APB1ENR_USBEN 550 #define RCC_APB1Periph_CAN1 RCC_APB1ENR_CAN1EN 551 #define RCC_APB1Periph_PWR RCC_APB1ENR_PWREN 552 #define RCC_APB1Periph_DAC1 RCC_APB1ENR_DAC1EN 553 #define RCC_APB1Periph_I2C3 RCC_APB1ENR_I2C3EN 554 #define RCC_APB1Periph_DAC2 RCC_APB1ENR_DAC2EN 555 #define RCC_APB1Periph_DAC RCC_APB1Periph_DAC1 556 557 558 #define IS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH) & 0x890137C8) == 0x00) && ((PERIPH) != 0x00)) 559 /** 560 * @} 561 */ 562 563 /** @defgroup RCC_MCO_Clock_Source 564 * @{ 565 */ 566 567 #define RCC_MCOSource_NoClock ((uint8_t)0x00) 568 #define RCC_MCOSource_LSI ((uint8_t)0x02) 569 #define RCC_MCOSource_LSE ((uint8_t)0x03) 570 #define RCC_MCOSource_SYSCLK ((uint8_t)0x04) 571 #define RCC_MCOSource_HSI ((uint8_t)0x05) 572 #define RCC_MCOSource_HSE ((uint8_t)0x06) 573 #define RCC_MCOSource_PLLCLK_Div2 ((uint8_t)0x07) 574 #define RCC_MCOSource_PLLCLK ((uint8_t)0x87) 575 576 #define IS_RCC_MCO_SOURCE(SOURCE) (((SOURCE) == RCC_MCOSource_NoClock) ||((SOURCE) == RCC_MCOSource_SYSCLK) ||\ 577 ((SOURCE) == RCC_MCOSource_HSI) || ((SOURCE) == RCC_MCOSource_HSE) || \ 578 ((SOURCE) == RCC_MCOSource_LSI) || ((SOURCE) == RCC_MCOSource_LSE) || \ 579 ((SOURCE) == RCC_MCOSource_PLLCLK_Div2)|| ((SOURCE) == RCC_MCOSource_PLLCLK)) 580 /** 581 * @} 582 */ 583 584 /** @defgroup RCC_MCOPrescaler 585 * @{ 586 */ 587 588 #define RCC_MCOPrescaler_1 RCC_CFGR_MCO_PRE_1 589 #define RCC_MCOPrescaler_2 RCC_CFGR_MCO_PRE_2 590 #define RCC_MCOPrescaler_4 RCC_CFGR_MCO_PRE_4 591 #define RCC_MCOPrescaler_8 RCC_CFGR_MCO_PRE_8 592 #define RCC_MCOPrescaler_16 RCC_CFGR_MCO_PRE_16 593 #define RCC_MCOPrescaler_32 RCC_CFGR_MCO_PRE_32 594 #define RCC_MCOPrescaler_64 RCC_CFGR_MCO_PRE_64 595 #define RCC_MCOPrescaler_128 RCC_CFGR_MCO_PRE_128 596 597 #define IS_RCC_MCO_PRESCALER(PRESCALER) (((PRESCALER) == RCC_MCOPrescaler_1) || \ 598 ((PRESCALER) == RCC_MCOPrescaler_2) || \ 599 ((PRESCALER) == RCC_MCOPrescaler_4) || \ 600 ((PRESCALER) == RCC_MCOPrescaler_8) || \ 601 ((PRESCALER) == RCC_MCOPrescaler_16) || \ 602 ((PRESCALER) == RCC_MCOPrescaler_32) || \ 603 ((PRESCALER) == RCC_MCOPrescaler_64) || \ 604 ((PRESCALER) == RCC_MCOPrescaler_128)) 605 /** 606 * @} 607 */ 608 609 /** @defgroup RCC_USB_Device_clock_source 610 * @{ 611 */ 612 613 #define RCC_USBCLKSource_PLLCLK_1Div5 ((uint8_t)0x00) 614 #define RCC_USBCLKSource_PLLCLK_Div1 ((uint8_t)0x01) 615 616 #define IS_RCC_USBCLK_SOURCE(SOURCE) (((SOURCE) == RCC_USBCLKSource_PLLCLK_1Div5) || \ 617 ((SOURCE) == RCC_USBCLKSource_PLLCLK_Div1)) 618 /** 619 * @} 620 */ 621 622 /** @defgroup RCC_Flag 623 * @{ 624 */ 625 #define RCC_FLAG_HSIRDY ((uint8_t)0x01) 626 #define RCC_FLAG_HSERDY ((uint8_t)0x11) 627 #define RCC_FLAG_PLLRDY ((uint8_t)0x19) 628 #define RCC_FLAG_MCOF ((uint8_t)0x9C) 629 #define RCC_FLAG_LSERDY ((uint8_t)0x21) 630 #define RCC_FLAG_LSIRDY ((uint8_t)0x41) 631 #define RCC_FLAG_OBLRST ((uint8_t)0x59) 632 #define RCC_FLAG_PINRST ((uint8_t)0x5A) 633 #define RCC_FLAG_PORRST ((uint8_t)0x5B) 634 #define RCC_FLAG_SFTRST ((uint8_t)0x5C) 635 #define RCC_FLAG_IWDGRST ((uint8_t)0x5D) 636 #define RCC_FLAG_WWDGRST ((uint8_t)0x5E) 637 #define RCC_FLAG_LPWRRST ((uint8_t)0x5F) 638 639 #define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \ 640 ((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || \ 641 ((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_OBLRST) || \ 642 ((FLAG) == RCC_FLAG_PINRST) || ((FLAG) == RCC_FLAG_PORRST) || \ 643 ((FLAG) == RCC_FLAG_SFTRST) || ((FLAG) == RCC_FLAG_IWDGRST)|| \ 644 ((FLAG) == RCC_FLAG_WWDGRST)|| ((FLAG) == RCC_FLAG_LPWRRST)|| \ 645 ((FLAG) == RCC_FLAG_MCOF)) 646 647 #define IS_RCC_HSI_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F) 648 649 /** 650 * @} 651 */ 652 653 /** 654 * @} 655 */ 656 657 /* Exported macro ------------------------------------------------------------*/ 658 /* Exported functions ------------------------------------------------------- */ 659 660 /* Function used to set the RCC clock configuration to the default reset state */ 661 void RCC_DeInit(void); 662 663 /* Internal/external clocks, PLL, CSS and MCO configuration functions *********/ 664 void RCC_HSEConfig(uint8_t RCC_HSE); 665 ErrorStatus RCC_WaitForHSEStartUp(void); 666 void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue); 667 void RCC_HSICmd(FunctionalState NewState); 668 void RCC_LSEConfig(uint32_t RCC_LSE); 669 void RCC_LSEDriveConfig(uint32_t RCC_LSEDrive); 670 void RCC_LSICmd(FunctionalState NewState); 671 void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul); 672 void RCC_PLLCmd(FunctionalState NewState); 673 void RCC_PREDIV1Config(uint32_t RCC_PREDIV1_Div); 674 void RCC_ClockSecuritySystemCmd(FunctionalState NewState); 675 #ifdef STM32F303xC 676 void RCC_MCOConfig(uint8_t RCC_MCOSource); 677 #else 678 void RCC_MCOConfig(uint8_t RCC_MCOSource,uint32_t RCC_MCOPrescaler); 679 #endif /* STM32F303xC */ 680 681 /* System, AHB and APB busses clocks configuration functions ******************/ 682 void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource); 683 uint8_t RCC_GetSYSCLKSource(void); 684 void RCC_HCLKConfig(uint32_t RCC_SYSCLK); 685 void RCC_PCLK1Config(uint32_t RCC_HCLK); 686 void RCC_PCLK2Config(uint32_t RCC_HCLK); 687 void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks); 688 689 /* Peripheral clocks configuration functions **********************************/ 690 void RCC_ADCCLKConfig(uint32_t RCC_PLLCLK); 691 void RCC_I2CCLKConfig(uint32_t RCC_I2CCLK); 692 void RCC_TIMCLKConfig(uint32_t RCC_TIMCLK); 693 void RCC_HRTIM1CLKConfig(uint32_t RCC_HRTIMCLK); 694 void RCC_I2SCLKConfig(uint32_t RCC_I2SCLKSource); 695 void RCC_USARTCLKConfig(uint32_t RCC_USARTCLK); 696 void RCC_USBCLKConfig(uint32_t RCC_USBCLKSource); 697 698 void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource); 699 void RCC_RTCCLKCmd(FunctionalState NewState); 700 void RCC_BackupResetCmd(FunctionalState NewState); 701 702 void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState); 703 void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState); 704 void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState); 705 706 void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState); 707 void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState); 708 void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState); 709 710 /* Interrupts and flags management functions **********************************/ 711 void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState); 712 FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG); 713 void RCC_ClearFlag(void); 714 ITStatus RCC_GetITStatus(uint8_t RCC_IT); 715 void RCC_ClearITPendingBit(uint8_t RCC_IT); 716 717 #ifdef __cplusplus 718 } 719 #endif 720 721 #endif /* __STM32F30x_RCC_H */ 722 723 /** 724 * @} 725 */ 726 727 /** 728 * @} 729 */ 730 731 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 732