1 /** 2 ****************************************************************************** 3 * @file stm32f30x_tim.h 4 * @author MCD Application Team 5 * @version V1.2.3 6 * @date 10-July-2015 7 * @brief This file contains all the functions prototypes for the TIM firmware 8 * library. 9 ****************************************************************************** 10 * @attention 11 * 12 * <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2> 13 * 14 * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); 15 * You may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at: 17 * 18 * http://www.st.com/software_license_agreement_liberty_v2 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 ****************************************************************************** 27 */ 28 29 /* Define to prevent recursive inclusion -------------------------------------*/ 30 #ifndef __STM32F30x_TIM_H 31 #define __STM32F30x_TIM_H 32 33 #ifdef __cplusplus 34 extern "C" { 35 #endif 36 37 /* Includes ------------------------------------------------------------------*/ 38 #include "stm32f30x.h" 39 40 /** @addtogroup stm32f30x_StdPeriph_Driver 41 * @{ 42 */ 43 44 /** @addtogroup TIM 45 * @{ 46 */ 47 48 /* Exported types ------------------------------------------------------------*/ 49 50 /** 51 * @brief TIM Time Base Init structure definition 52 * @note This structure is used with all TIMx except for TIM6 and TIM7. 53 */ 54 55 typedef struct 56 { 57 uint16_t TIM_Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock. 58 This parameter can be a number between 0x0000 and 0xFFFF */ 59 60 uint16_t TIM_CounterMode; /*!< Specifies the counter mode. 61 This parameter can be a value of @ref TIM_Counter_Mode */ 62 63 uint32_t TIM_Period; /*!< Specifies the period value to be loaded into the active 64 Auto-Reload Register at the next update event. 65 This parameter must be a number between 0x0000 and 0xFFFF. */ 66 67 uint16_t TIM_ClockDivision; /*!< Specifies the clock division. 68 This parameter can be a value of @ref TIM_Clock_Division_CKD */ 69 70 uint16_t TIM_RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter 71 reaches zero, an update event is generated and counting restarts 72 from the RCR value (N). 73 This means in PWM mode that (N+1) corresponds to: 74 - the number of PWM periods in edge-aligned mode 75 - the number of half PWM period in center-aligned mode 76 This parameter must be a number between 0x00 and 0xFF. 77 @note This parameter is valid only for TIM1 and TIM8. */ 78 } TIM_TimeBaseInitTypeDef; 79 80 /** 81 * @brief TIM Output Compare Init structure definition 82 */ 83 84 typedef struct 85 { 86 uint32_t TIM_OCMode; /*!< Specifies the TIM mode. 87 This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ 88 89 uint16_t TIM_OutputState; /*!< Specifies the TIM Output Compare state. 90 This parameter can be a value of @ref TIM_Output_Compare_State */ 91 92 uint16_t TIM_OutputNState; /*!< Specifies the TIM complementary Output Compare state. 93 This parameter can be a value of @ref TIM_Output_Compare_N_State 94 @note This parameter is valid only for TIM1 and TIM8. */ 95 96 uint32_t TIM_Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. 97 This parameter can be a number between 0x0000 and 0xFFFF */ 98 99 uint16_t TIM_OCPolarity; /*!< Specifies the output polarity. 100 This parameter can be a value of @ref TIM_Output_Compare_Polarity */ 101 102 uint16_t TIM_OCNPolarity; /*!< Specifies the complementary output polarity. 103 This parameter can be a value of @ref TIM_Output_Compare_N_Polarity 104 @note This parameter is valid only for TIM1 and TIM8. */ 105 106 uint16_t TIM_OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. 107 This parameter can be a value of @ref TIM_Output_Compare_Idle_State 108 @note This parameter is valid only for TIM1 and TIM8. */ 109 110 uint16_t TIM_OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. 111 This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State 112 @note This parameter is valid only for TIM1 and TIM8. */ 113 } TIM_OCInitTypeDef; 114 115 /** 116 * @brief TIM Input Capture Init structure definition 117 */ 118 119 typedef struct 120 { 121 122 uint16_t TIM_Channel; /*!< Specifies the TIM channel. 123 This parameter can be a value of @ref TIM_Channel */ 124 125 uint16_t TIM_ICPolarity; /*!< Specifies the active edge of the input signal. 126 This parameter can be a value of @ref TIM_Input_Capture_Polarity */ 127 128 uint16_t TIM_ICSelection; /*!< Specifies the input. 129 This parameter can be a value of @ref TIM_Input_Capture_Selection */ 130 131 uint16_t TIM_ICPrescaler; /*!< Specifies the Input Capture Prescaler. 132 This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ 133 134 uint16_t TIM_ICFilter; /*!< Specifies the input capture filter. 135 This parameter can be a number between 0x0 and 0xF */ 136 } TIM_ICInitTypeDef; 137 138 /** 139 * @brief BDTR structure definition 140 * @note This structure is used only with TIM1 and TIM8. 141 */ 142 143 typedef struct 144 { 145 146 uint16_t TIM_OSSRState; /*!< Specifies the Off-State selection used in Run mode. 147 This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */ 148 149 uint16_t TIM_OSSIState; /*!< Specifies the Off-State used in Idle state. 150 This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */ 151 152 uint16_t TIM_LOCKLevel; /*!< Specifies the LOCK level parameters. 153 This parameter can be a value of @ref TIM_Lock_level */ 154 155 uint16_t TIM_DeadTime; /*!< Specifies the delay time between the switching-off and the 156 switching-on of the outputs. 157 This parameter can be a number between 0x00 and 0xFF */ 158 159 uint16_t TIM_Break; /*!< Specifies whether the TIM Break input is enabled or not. 160 This parameter can be a value of @ref TIM_Break_Input_enable_disable */ 161 162 uint16_t TIM_BreakPolarity; /*!< Specifies the TIM Break Input pin polarity. 163 This parameter can be a value of @ref TIM_Break_Polarity */ 164 165 uint16_t TIM_AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not. 166 This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */ 167 } TIM_BDTRInitTypeDef; 168 169 /* Exported constants --------------------------------------------------------*/ 170 171 /** @defgroup TIM_Exported_constants 172 * @{ 173 */ 174 175 #define IS_TIM_ALL_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ 176 ((PERIPH) == TIM2) || \ 177 ((PERIPH) == TIM3) || \ 178 ((PERIPH) == TIM4) || \ 179 ((PERIPH) == TIM6) || \ 180 ((PERIPH) == TIM7) || \ 181 ((PERIPH) == TIM8) || \ 182 ((PERIPH) == TIM15) || \ 183 ((PERIPH) == TIM16) || \ 184 ((PERIPH) == TIM17) || \ 185 ((PERIPH) == TIM20)) 186 187 /* LIST1: TIM1, TIM2, TIM3, TIM4, TIM8, TIM15, TIM16, TIM20 and TIM17 */ 188 #define IS_TIM_LIST1_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ 189 ((PERIPH) == TIM2) || \ 190 ((PERIPH) == TIM3) || \ 191 ((PERIPH) == TIM4) || \ 192 ((PERIPH) == TIM8) || \ 193 ((PERIPH) == TIM15) || \ 194 ((PERIPH) == TIM16) || \ 195 ((PERIPH) == TIM17) || \ 196 ((PERIPH) == TIM20)) 197 198 /* LIST2: TIM1, TIM2, TIM3, TIM4, TIM8, TIM20 and TIM15 */ 199 #define IS_TIM_LIST2_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ 200 ((PERIPH) == TIM2) || \ 201 ((PERIPH) == TIM3) || \ 202 ((PERIPH) == TIM4) || \ 203 ((PERIPH) == TIM8) || \ 204 ((PERIPH) == TIM15)|| \ 205 ((PERIPH) == TIM20)) 206 207 /* LIST3: TIM1, TIM2, TIM3, TIM4, TIM20 and TIM8 */ 208 #define IS_TIM_LIST3_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ 209 ((PERIPH) == TIM2) || \ 210 ((PERIPH) == TIM3) || \ 211 ((PERIPH) == TIM4) || \ 212 ((PERIPH) == TIM8) || \ 213 ((PERIPH) == TIM20)) 214 215 /* LIST4: TIM1, TIM20 and TIM8 */ 216 #define IS_TIM_LIST4_PERIPH(PERIPH) (((PERIPH) == TIM1) ||\ 217 ((PERIPH) == TIM8) ||\ 218 ((PERIPH) == TIM20)) 219 220 /* LIST5: TIM1, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7 and TIM8 */ 221 #define IS_TIM_LIST5_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ 222 ((PERIPH) == TIM2) || \ 223 ((PERIPH) == TIM3) || \ 224 ((PERIPH) == TIM4) || \ 225 ((PERIPH) == TIM6) || \ 226 ((PERIPH) == TIM7) || \ 227 ((PERIPH) == TIM8)) 228 /* LIST6: TIM1, TIM8, TIM15, TIM16, TIM20 and TIM17 */ 229 #define IS_TIM_LIST6_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ 230 ((PERIPH) == TIM8) || \ 231 ((PERIPH) == TIM15) || \ 232 ((PERIPH) == TIM16) || \ 233 ((PERIPH) == TIM17) || \ 234 ((PERIPH) == TIM20)) 235 236 /* LIST5: TIM1, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM20 and TIM8 */ 237 #define IS_TIM_LIST7_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ 238 ((PERIPH) == TIM2) || \ 239 ((PERIPH) == TIM3) || \ 240 ((PERIPH) == TIM4) || \ 241 ((PERIPH) == TIM6) || \ 242 ((PERIPH) == TIM7) || \ 243 ((PERIPH) == TIM8) || \ 244 ((PERIPH) == TIM15)|| \ 245 ((PERIPH) == TIM20)) 246 247 /* LIST8: TIM16 (option register) */ 248 #define IS_TIM_LIST8_PERIPH(PERIPH) (((PERIPH) == TIM16)|| \ 249 ((PERIPH) == TIM1) ||\ 250 ((PERIPH) == TIM8) ||\ 251 ((PERIPH) == TIM20)) 252 253 /** @defgroup TIM_Output_Compare_and_PWM_modes 254 * @{ 255 */ 256 257 #define TIM_OCMode_Timing ((uint32_t)0x00000) 258 #define TIM_OCMode_Active ((uint32_t)0x00010) 259 #define TIM_OCMode_Inactive ((uint32_t)0x00020) 260 #define TIM_OCMode_Toggle ((uint32_t)0x00030) 261 #define TIM_OCMode_PWM1 ((uint32_t)0x00060) 262 #define TIM_OCMode_PWM2 ((uint32_t)0x00070) 263 264 #define TIM_OCMode_Retrigerrable_OPM1 ((uint32_t)0x10000) 265 #define TIM_OCMode_Retrigerrable_OPM2 ((uint32_t)0x10010) 266 #define TIM_OCMode_Combined_PWM1 ((uint32_t)0x10040) 267 #define TIM_OCMode_Combined_PWM2 ((uint32_t)0x10050) 268 #define TIM_OCMode_Asymmetric_PWM1 ((uint32_t)0x10060) 269 #define TIM_OCMode_Asymmetric_PWM2 ((uint32_t)0x10070) 270 271 #define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMode_Timing) || \ 272 ((MODE) == TIM_OCMode_Active) || \ 273 ((MODE) == TIM_OCMode_Inactive) || \ 274 ((MODE) == TIM_OCMode_Toggle)|| \ 275 ((MODE) == TIM_OCMode_PWM1) || \ 276 ((MODE) == TIM_OCMode_PWM2) || \ 277 ((MODE) == TIM_OCMode_Retrigerrable_OPM1) || \ 278 ((MODE) == TIM_OCMode_Retrigerrable_OPM2) || \ 279 ((MODE) == TIM_OCMode_Combined_PWM1) || \ 280 ((MODE) == TIM_OCMode_Combined_PWM2) || \ 281 ((MODE) == TIM_OCMode_Asymmetric_PWM1) || \ 282 ((MODE) == TIM_OCMode_Asymmetric_PWM2)) 283 284 #define IS_TIM_OCM(MODE) (((MODE) == TIM_OCMode_Timing) || \ 285 ((MODE) == TIM_OCMode_Active) || \ 286 ((MODE) == TIM_OCMode_Inactive) || \ 287 ((MODE) == TIM_OCMode_Toggle)|| \ 288 ((MODE) == TIM_OCMode_PWM1) || \ 289 ((MODE) == TIM_OCMode_PWM2) || \ 290 ((MODE) == TIM_ForcedAction_Active) || \ 291 ((MODE) == TIM_ForcedAction_InActive) || \ 292 ((MODE) == TIM_OCMode_Retrigerrable_OPM1) || \ 293 ((MODE) == TIM_OCMode_Retrigerrable_OPM2) || \ 294 ((MODE) == TIM_OCMode_Combined_PWM1) || \ 295 ((MODE) == TIM_OCMode_Combined_PWM2) || \ 296 ((MODE) == TIM_OCMode_Asymmetric_PWM1) || \ 297 ((MODE) == TIM_OCMode_Asymmetric_PWM2)) 298 /** 299 * @} 300 */ 301 302 /** @defgroup TIM_One_Pulse_Mode 303 * @{ 304 */ 305 306 #define TIM_OPMode_Single ((uint16_t)0x0008) 307 #define TIM_OPMode_Repetitive ((uint16_t)0x0000) 308 #define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMode_Single) || \ 309 ((MODE) == TIM_OPMode_Repetitive)) 310 /** 311 * @} 312 */ 313 314 /** @defgroup TIM_Channel 315 * @{ 316 */ 317 318 #define TIM_Channel_1 ((uint16_t)0x0000) 319 #define TIM_Channel_2 ((uint16_t)0x0004) 320 #define TIM_Channel_3 ((uint16_t)0x0008) 321 #define TIM_Channel_4 ((uint16_t)0x000C) 322 #define TIM_Channel_5 ((uint16_t)0x0010) 323 #define TIM_Channel_6 ((uint16_t)0x0014) 324 325 #define IS_TIM_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \ 326 ((CHANNEL) == TIM_Channel_2) || \ 327 ((CHANNEL) == TIM_Channel_3) || \ 328 ((CHANNEL) == TIM_Channel_4)) 329 330 #define IS_TIM_PWMI_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \ 331 ((CHANNEL) == TIM_Channel_2)) 332 #define IS_TIM_COMPLEMENTARY_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \ 333 ((CHANNEL) == TIM_Channel_2) || \ 334 ((CHANNEL) == TIM_Channel_3)) 335 /** 336 * @} 337 */ 338 339 /** @defgroup TIM_Clock_Division_CKD 340 * @{ 341 */ 342 343 #define TIM_CKD_DIV1 ((uint16_t)0x0000) 344 #define TIM_CKD_DIV2 ((uint16_t)0x0100) 345 #define TIM_CKD_DIV4 ((uint16_t)0x0200) 346 #define IS_TIM_CKD_DIV(DIV) (((DIV) == TIM_CKD_DIV1) || \ 347 ((DIV) == TIM_CKD_DIV2) || \ 348 ((DIV) == TIM_CKD_DIV4)) 349 /** 350 * @} 351 */ 352 353 /** @defgroup TIM_Counter_Mode 354 * @{ 355 */ 356 357 #define TIM_CounterMode_Up ((uint16_t)0x0000) 358 #define TIM_CounterMode_Down ((uint16_t)0x0010) 359 #define TIM_CounterMode_CenterAligned1 ((uint16_t)0x0020) 360 #define TIM_CounterMode_CenterAligned2 ((uint16_t)0x0040) 361 #define TIM_CounterMode_CenterAligned3 ((uint16_t)0x0060) 362 #define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_CounterMode_Up) || \ 363 ((MODE) == TIM_CounterMode_Down) || \ 364 ((MODE) == TIM_CounterMode_CenterAligned1) || \ 365 ((MODE) == TIM_CounterMode_CenterAligned2) || \ 366 ((MODE) == TIM_CounterMode_CenterAligned3)) 367 /** 368 * @} 369 */ 370 371 /** @defgroup TIM_Output_Compare_Polarity 372 * @{ 373 */ 374 375 #define TIM_OCPolarity_High ((uint16_t)0x0000) 376 #define TIM_OCPolarity_Low ((uint16_t)0x0002) 377 #define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPolarity_High) || \ 378 ((POLARITY) == TIM_OCPolarity_Low)) 379 /** 380 * @} 381 */ 382 383 /** @defgroup TIM_Output_Compare_N_Polarity 384 * @{ 385 */ 386 387 #define TIM_OCNPolarity_High ((uint16_t)0x0000) 388 #define TIM_OCNPolarity_Low ((uint16_t)0x0008) 389 #define IS_TIM_OCN_POLARITY(POLARITY) (((POLARITY) == TIM_OCNPolarity_High) || \ 390 ((POLARITY) == TIM_OCNPolarity_Low)) 391 /** 392 * @} 393 */ 394 395 /** @defgroup TIM_Output_Compare_State 396 * @{ 397 */ 398 399 #define TIM_OutputState_Disable ((uint16_t)0x0000) 400 #define TIM_OutputState_Enable ((uint16_t)0x0001) 401 #define IS_TIM_OUTPUT_STATE(STATE) (((STATE) == TIM_OutputState_Disable) || \ 402 ((STATE) == TIM_OutputState_Enable)) 403 /** 404 * @} 405 */ 406 407 /** @defgroup TIM_Output_Compare_N_State 408 * @{ 409 */ 410 411 #define TIM_OutputNState_Disable ((uint16_t)0x0000) 412 #define TIM_OutputNState_Enable ((uint16_t)0x0004) 413 #define IS_TIM_OUTPUTN_STATE(STATE) (((STATE) == TIM_OutputNState_Disable) || \ 414 ((STATE) == TIM_OutputNState_Enable)) 415 /** 416 * @} 417 */ 418 419 /** @defgroup TIM_Capture_Compare_State 420 * @{ 421 */ 422 423 #define TIM_CCx_Enable ((uint16_t)0x0001) 424 #define TIM_CCx_Disable ((uint16_t)0x0000) 425 #define IS_TIM_CCX(CCX) (((CCX) == TIM_CCx_Enable) || \ 426 ((CCX) == TIM_CCx_Disable)) 427 /** 428 * @} 429 */ 430 431 /** @defgroup TIM_Capture_Compare_N_State 432 * @{ 433 */ 434 435 #define TIM_CCxN_Enable ((uint16_t)0x0004) 436 #define TIM_CCxN_Disable ((uint16_t)0x0000) 437 #define IS_TIM_CCXN(CCXN) (((CCXN) == TIM_CCxN_Enable) || \ 438 ((CCXN) == TIM_CCxN_Disable)) 439 /** 440 * @} 441 */ 442 443 /** @defgroup TIM_Break_Input_enable_disable 444 * @{ 445 */ 446 447 #define TIM_Break_Enable ((uint16_t)0x1000) 448 #define TIM_Break_Disable ((uint16_t)0x0000) 449 #define IS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_Break_Enable) || \ 450 ((STATE) == TIM_Break_Disable)) 451 /** 452 * @} 453 */ 454 455 /** @defgroup TIM_Break1_Input_enable_disable 456 * @{ 457 */ 458 459 #define TIM_Break1_Enable ((uint32_t)0x00001000) 460 #define TIM_Break1_Disable ((uint32_t)0x00000000) 461 #define IS_TIM_BREAK1_STATE(STATE) (((STATE) == TIM_Break1_Enable) || \ 462 ((STATE) == TIM_Break1_Disable)) 463 /** 464 * @} 465 */ 466 467 /** @defgroup TIM_Break2_Input_enable_disable 468 * @{ 469 */ 470 471 #define TIM_Break2_Enable ((uint32_t)0x01000000) 472 #define TIM_Break2_Disable ((uint32_t)0x00000000) 473 #define IS_TIM_BREAK2_STATE(STATE) (((STATE) == TIM_Break2_Enable) || \ 474 ((STATE) == TIM_Break2_Disable)) 475 /** 476 * @} 477 */ 478 479 /** @defgroup TIM_Break_Polarity 480 * @{ 481 */ 482 483 #define TIM_BreakPolarity_Low ((uint16_t)0x0000) 484 #define TIM_BreakPolarity_High ((uint16_t)0x2000) 485 #define IS_TIM_BREAK_POLARITY(POLARITY) (((POLARITY) == TIM_BreakPolarity_Low) || \ 486 ((POLARITY) == TIM_BreakPolarity_High)) 487 /** 488 * @} 489 */ 490 491 /** @defgroup TIM_Break1_Polarity 492 * @{ 493 */ 494 495 #define TIM_Break1Polarity_Low ((uint32_t)0x00000000) 496 #define TIM_Break1Polarity_High ((uint32_t)0x00002000) 497 #define IS_TIM_BREAK1_POLARITY(POLARITY) (((POLARITY) == TIM_Break1Polarity_Low) || \ 498 ((POLARITY) == TIM_Break1Polarity_High)) 499 /** 500 * @} 501 */ 502 503 /** @defgroup TIM_Break2_Polarity 504 * @{ 505 */ 506 507 #define TIM_Break2Polarity_Low ((uint32_t)0x00000000) 508 #define TIM_Break2Polarity_High ((uint32_t)0x02000000) 509 #define IS_TIM_BREAK2_POLARITY(POLARITY) (((POLARITY) == TIM_Break2Polarity_Low) || \ 510 ((POLARITY) == TIM_Break2Polarity_High)) 511 /** 512 * @} 513 */ 514 515 /** @defgroup TIM_Break1_Filter 516 * @{ 517 */ 518 519 #define IS_TIM_BREAK1_FILTER(FILTER) ((FILTER) <= 0xF) 520 /** 521 * @} 522 */ 523 524 /** @defgroup TIM_Break2_Filter 525 * @{ 526 */ 527 528 #define IS_TIM_BREAK2_FILTER(FILTER) ((FILTER) <= 0xF) 529 /** 530 * @} 531 */ 532 533 /** @defgroup TIM_AOE_Bit_Set_Reset 534 * @{ 535 */ 536 537 #define TIM_AutomaticOutput_Enable ((uint16_t)0x4000) 538 #define TIM_AutomaticOutput_Disable ((uint16_t)0x0000) 539 #define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AutomaticOutput_Enable) || \ 540 ((STATE) == TIM_AutomaticOutput_Disable)) 541 /** 542 * @} 543 */ 544 545 /** @defgroup TIM_Lock_level 546 * @{ 547 */ 548 549 #define TIM_LOCKLevel_OFF ((uint16_t)0x0000) 550 #define TIM_LOCKLevel_1 ((uint16_t)0x0100) 551 #define TIM_LOCKLevel_2 ((uint16_t)0x0200) 552 #define TIM_LOCKLevel_3 ((uint16_t)0x0300) 553 #define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLevel_OFF) || \ 554 ((LEVEL) == TIM_LOCKLevel_1) || \ 555 ((LEVEL) == TIM_LOCKLevel_2) || \ 556 ((LEVEL) == TIM_LOCKLevel_3)) 557 /** 558 * @} 559 */ 560 561 /** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state 562 * @{ 563 */ 564 565 #define TIM_OSSIState_Enable ((uint16_t)0x0400) 566 #define TIM_OSSIState_Disable ((uint16_t)0x0000) 567 #define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSIState_Enable) || \ 568 ((STATE) == TIM_OSSIState_Disable)) 569 /** 570 * @} 571 */ 572 573 /** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state 574 * @{ 575 */ 576 577 #define TIM_OSSRState_Enable ((uint16_t)0x0800) 578 #define TIM_OSSRState_Disable ((uint16_t)0x0000) 579 #define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSRState_Enable) || \ 580 ((STATE) == TIM_OSSRState_Disable)) 581 /** 582 * @} 583 */ 584 585 /** @defgroup TIM_Output_Compare_Idle_State 586 * @{ 587 */ 588 589 #define TIM_OCIdleState_Set ((uint16_t)0x0100) 590 #define TIM_OCIdleState_Reset ((uint16_t)0x0000) 591 #define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIdleState_Set) || \ 592 ((STATE) == TIM_OCIdleState_Reset)) 593 /** 594 * @} 595 */ 596 597 /** @defgroup TIM_Output_Compare_N_Idle_State 598 * @{ 599 */ 600 601 #define TIM_OCNIdleState_Set ((uint16_t)0x0200) 602 #define TIM_OCNIdleState_Reset ((uint16_t)0x0000) 603 #define IS_TIM_OCNIDLE_STATE(STATE) (((STATE) == TIM_OCNIdleState_Set) || \ 604 ((STATE) == TIM_OCNIdleState_Reset)) 605 /** 606 * @} 607 */ 608 609 /** @defgroup TIM_Input_Capture_Polarity 610 * @{ 611 */ 612 613 #define TIM_ICPolarity_Rising ((uint16_t)0x0000) 614 #define TIM_ICPolarity_Falling ((uint16_t)0x0002) 615 #define TIM_ICPolarity_BothEdge ((uint16_t)0x000A) 616 #define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPolarity_Rising) || \ 617 ((POLARITY) == TIM_ICPolarity_Falling)|| \ 618 ((POLARITY) == TIM_ICPolarity_BothEdge)) 619 /** 620 * @} 621 */ 622 623 /** @defgroup TIM_Input_Capture_Selection 624 * @{ 625 */ 626 627 #define TIM_ICSelection_DirectTI ((uint16_t)0x0001) /*!< TIM Input 1, 2, 3 or 4 is selected to be 628 connected to IC1, IC2, IC3 or IC4, respectively */ 629 #define TIM_ICSelection_IndirectTI ((uint16_t)0x0002) /*!< TIM Input 1, 2, 3 or 4 is selected to be 630 connected to IC2, IC1, IC4 or IC3, respectively. */ 631 #define TIM_ICSelection_TRC ((uint16_t)0x0003) /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC. */ 632 #define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSelection_DirectTI) || \ 633 ((SELECTION) == TIM_ICSelection_IndirectTI) || \ 634 ((SELECTION) == TIM_ICSelection_TRC)) 635 /** 636 * @} 637 */ 638 639 /** @defgroup TIM_Input_Capture_Prescaler 640 * @{ 641 */ 642 643 #define TIM_ICPSC_DIV1 ((uint16_t)0x0000) /*!< Capture performed each time an edge is detected on the capture input. */ 644 #define TIM_ICPSC_DIV2 ((uint16_t)0x0004) /*!< Capture performed once every 2 events. */ 645 #define TIM_ICPSC_DIV4 ((uint16_t)0x0008) /*!< Capture performed once every 4 events. */ 646 #define TIM_ICPSC_DIV8 ((uint16_t)0x000C) /*!< Capture performed once every 8 events. */ 647 #define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) || \ 648 ((PRESCALER) == TIM_ICPSC_DIV2) || \ 649 ((PRESCALER) == TIM_ICPSC_DIV4) || \ 650 ((PRESCALER) == TIM_ICPSC_DIV8)) 651 /** 652 * @} 653 */ 654 655 /** @defgroup TIM_interrupt_sources 656 * @{ 657 */ 658 659 #define TIM_IT_Update ((uint16_t)0x0001) 660 #define TIM_IT_CC1 ((uint16_t)0x0002) 661 #define TIM_IT_CC2 ((uint16_t)0x0004) 662 #define TIM_IT_CC3 ((uint16_t)0x0008) 663 #define TIM_IT_CC4 ((uint16_t)0x0010) 664 #define TIM_IT_COM ((uint16_t)0x0020) 665 #define TIM_IT_Trigger ((uint16_t)0x0040) 666 #define TIM_IT_Break ((uint16_t)0x0080) 667 #define IS_TIM_IT(IT) ((((IT) & (uint16_t)0xFF00) == 0x0000) && ((IT) != 0x0000)) 668 669 #define IS_TIM_GET_IT(IT) (((IT) == TIM_IT_Update) || \ 670 ((IT) == TIM_IT_CC1) || \ 671 ((IT) == TIM_IT_CC2) || \ 672 ((IT) == TIM_IT_CC3) || \ 673 ((IT) == TIM_IT_CC4) || \ 674 ((IT) == TIM_IT_COM) || \ 675 ((IT) == TIM_IT_Trigger) || \ 676 ((IT) == TIM_IT_Break)) 677 /** 678 * @} 679 */ 680 681 /** @defgroup TIM_DMA_Base_address 682 * @{ 683 */ 684 685 #define TIM_DMABase_CR1 ((uint16_t)0x0000) 686 #define TIM_DMABase_CR2 ((uint16_t)0x0001) 687 #define TIM_DMABase_SMCR ((uint16_t)0x0002) 688 #define TIM_DMABase_DIER ((uint16_t)0x0003) 689 #define TIM_DMABase_SR ((uint16_t)0x0004) 690 #define TIM_DMABase_EGR ((uint16_t)0x0005) 691 #define TIM_DMABase_CCMR1 ((uint16_t)0x0006) 692 #define TIM_DMABase_CCMR2 ((uint16_t)0x0007) 693 #define TIM_DMABase_CCER ((uint16_t)0x0008) 694 #define TIM_DMABase_CNT ((uint16_t)0x0009) 695 #define TIM_DMABase_PSC ((uint16_t)0x000A) 696 #define TIM_DMABase_ARR ((uint16_t)0x000B) 697 #define TIM_DMABase_RCR ((uint16_t)0x000C) 698 #define TIM_DMABase_CCR1 ((uint16_t)0x000D) 699 #define TIM_DMABase_CCR2 ((uint16_t)0x000E) 700 #define TIM_DMABase_CCR3 ((uint16_t)0x000F) 701 #define TIM_DMABase_CCR4 ((uint16_t)0x0010) 702 #define TIM_DMABase_BDTR ((uint16_t)0x0011) 703 #define TIM_DMABase_DCR ((uint16_t)0x0012) 704 #define TIM_DMABase_OR ((uint16_t)0x0013) 705 #define TIM_DMABase_CCMR3 ((uint16_t)0x0014) 706 #define TIM_DMABase_CCR5 ((uint16_t)0x0015) 707 #define TIM_DMABase_CCR6 ((uint16_t)0x0016) 708 #define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABase_CR1) || \ 709 ((BASE) == TIM_DMABase_CR2) || \ 710 ((BASE) == TIM_DMABase_SMCR) || \ 711 ((BASE) == TIM_DMABase_DIER) || \ 712 ((BASE) == TIM_DMABase_SR) || \ 713 ((BASE) == TIM_DMABase_EGR) || \ 714 ((BASE) == TIM_DMABase_CCMR1) || \ 715 ((BASE) == TIM_DMABase_CCMR2) || \ 716 ((BASE) == TIM_DMABase_CCER) || \ 717 ((BASE) == TIM_DMABase_CNT) || \ 718 ((BASE) == TIM_DMABase_PSC) || \ 719 ((BASE) == TIM_DMABase_ARR) || \ 720 ((BASE) == TIM_DMABase_RCR) || \ 721 ((BASE) == TIM_DMABase_CCR1) || \ 722 ((BASE) == TIM_DMABase_CCR2) || \ 723 ((BASE) == TIM_DMABase_CCR3) || \ 724 ((BASE) == TIM_DMABase_CCR4) || \ 725 ((BASE) == TIM_DMABase_BDTR) || \ 726 ((BASE) == TIM_DMABase_DCR) || \ 727 ((BASE) == TIM_DMABase_OR) || \ 728 ((BASE) == TIM_DMABase_CCMR3) || \ 729 ((BASE) == TIM_DMABase_CCR5) || \ 730 ((BASE) == TIM_DMABase_CCR6)) 731 /** 732 * @} 733 */ 734 735 /** @defgroup TIM_DMA_Burst_Length 736 * @{ 737 */ 738 739 #define TIM_DMABurstLength_1Transfer ((uint16_t)0x0000) 740 #define TIM_DMABurstLength_2Transfers ((uint16_t)0x0100) 741 #define TIM_DMABurstLength_3Transfers ((uint16_t)0x0200) 742 #define TIM_DMABurstLength_4Transfers ((uint16_t)0x0300) 743 #define TIM_DMABurstLength_5Transfers ((uint16_t)0x0400) 744 #define TIM_DMABurstLength_6Transfers ((uint16_t)0x0500) 745 #define TIM_DMABurstLength_7Transfers ((uint16_t)0x0600) 746 #define TIM_DMABurstLength_8Transfers ((uint16_t)0x0700) 747 #define TIM_DMABurstLength_9Transfers ((uint16_t)0x0800) 748 #define TIM_DMABurstLength_10Transfers ((uint16_t)0x0900) 749 #define TIM_DMABurstLength_11Transfers ((uint16_t)0x0A00) 750 #define TIM_DMABurstLength_12Transfers ((uint16_t)0x0B00) 751 #define TIM_DMABurstLength_13Transfers ((uint16_t)0x0C00) 752 #define TIM_DMABurstLength_14Transfers ((uint16_t)0x0D00) 753 #define TIM_DMABurstLength_15Transfers ((uint16_t)0x0E00) 754 #define TIM_DMABurstLength_16Transfers ((uint16_t)0x0F00) 755 #define TIM_DMABurstLength_17Transfers ((uint16_t)0x1000) 756 #define TIM_DMABurstLength_18Transfers ((uint16_t)0x1100) 757 #define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABurstLength_1Transfer) || \ 758 ((LENGTH) == TIM_DMABurstLength_2Transfers) || \ 759 ((LENGTH) == TIM_DMABurstLength_3Transfers) || \ 760 ((LENGTH) == TIM_DMABurstLength_4Transfers) || \ 761 ((LENGTH) == TIM_DMABurstLength_5Transfers) || \ 762 ((LENGTH) == TIM_DMABurstLength_6Transfers) || \ 763 ((LENGTH) == TIM_DMABurstLength_7Transfers) || \ 764 ((LENGTH) == TIM_DMABurstLength_8Transfers) || \ 765 ((LENGTH) == TIM_DMABurstLength_9Transfers) || \ 766 ((LENGTH) == TIM_DMABurstLength_10Transfers) || \ 767 ((LENGTH) == TIM_DMABurstLength_11Transfers) || \ 768 ((LENGTH) == TIM_DMABurstLength_12Transfers) || \ 769 ((LENGTH) == TIM_DMABurstLength_13Transfers) || \ 770 ((LENGTH) == TIM_DMABurstLength_14Transfers) || \ 771 ((LENGTH) == TIM_DMABurstLength_15Transfers) || \ 772 ((LENGTH) == TIM_DMABurstLength_16Transfers) || \ 773 ((LENGTH) == TIM_DMABurstLength_17Transfers) || \ 774 ((LENGTH) == TIM_DMABurstLength_18Transfers)) 775 /** 776 * @} 777 */ 778 779 /** @defgroup TIM_DMA_sources 780 * @{ 781 */ 782 783 #define TIM_DMA_Update ((uint16_t)0x0100) 784 #define TIM_DMA_CC1 ((uint16_t)0x0200) 785 #define TIM_DMA_CC2 ((uint16_t)0x0400) 786 #define TIM_DMA_CC3 ((uint16_t)0x0800) 787 #define TIM_DMA_CC4 ((uint16_t)0x1000) 788 #define TIM_DMA_COM ((uint16_t)0x2000) 789 #define TIM_DMA_Trigger ((uint16_t)0x4000) 790 #define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0x80FF) == 0x0000) && ((SOURCE) != 0x0000)) 791 792 /** 793 * @} 794 */ 795 796 /** @defgroup TIM_External_Trigger_Prescaler 797 * @{ 798 */ 799 800 #define TIM_ExtTRGPSC_OFF ((uint16_t)0x0000) 801 #define TIM_ExtTRGPSC_DIV2 ((uint16_t)0x1000) 802 #define TIM_ExtTRGPSC_DIV4 ((uint16_t)0x2000) 803 #define TIM_ExtTRGPSC_DIV8 ((uint16_t)0x3000) 804 #define IS_TIM_EXT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ExtTRGPSC_OFF) || \ 805 ((PRESCALER) == TIM_ExtTRGPSC_DIV2) || \ 806 ((PRESCALER) == TIM_ExtTRGPSC_DIV4) || \ 807 ((PRESCALER) == TIM_ExtTRGPSC_DIV8)) 808 /** 809 * @} 810 */ 811 812 /** @defgroup TIM_Internal_Trigger_Selection 813 * @{ 814 */ 815 816 #define TIM_TS_ITR0 ((uint16_t)0x0000) 817 #define TIM_TS_ITR1 ((uint16_t)0x0010) 818 #define TIM_TS_ITR2 ((uint16_t)0x0020) 819 #define TIM_TS_ITR3 ((uint16_t)0x0030) 820 #define TIM_TS_TI1F_ED ((uint16_t)0x0040) 821 #define TIM_TS_TI1FP1 ((uint16_t)0x0050) 822 #define TIM_TS_TI2FP2 ((uint16_t)0x0060) 823 #define TIM_TS_ETRF ((uint16_t)0x0070) 824 #define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \ 825 ((SELECTION) == TIM_TS_ITR1) || \ 826 ((SELECTION) == TIM_TS_ITR2) || \ 827 ((SELECTION) == TIM_TS_ITR3) || \ 828 ((SELECTION) == TIM_TS_TI1F_ED) || \ 829 ((SELECTION) == TIM_TS_TI1FP1) || \ 830 ((SELECTION) == TIM_TS_TI2FP2) || \ 831 ((SELECTION) == TIM_TS_ETRF)) 832 #define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \ 833 ((SELECTION) == TIM_TS_ITR1) || \ 834 ((SELECTION) == TIM_TS_ITR2) || \ 835 ((SELECTION) == TIM_TS_ITR3)) 836 /** 837 * @} 838 */ 839 840 /** @defgroup TIM_TIx_External_Clock_Source 841 * @{ 842 */ 843 844 #define TIM_TIxExternalCLK1Source_TI1 ((uint16_t)0x0050) 845 #define TIM_TIxExternalCLK1Source_TI2 ((uint16_t)0x0060) 846 #define TIM_TIxExternalCLK1Source_TI1ED ((uint16_t)0x0040) 847 848 /** 849 * @} 850 */ 851 852 /** @defgroup TIM_External_Trigger_Polarity 853 * @{ 854 */ 855 #define TIM_ExtTRGPolarity_Inverted ((uint16_t)0x8000) 856 #define TIM_ExtTRGPolarity_NonInverted ((uint16_t)0x0000) 857 #define IS_TIM_EXT_POLARITY(POLARITY) (((POLARITY) == TIM_ExtTRGPolarity_Inverted) || \ 858 ((POLARITY) == TIM_ExtTRGPolarity_NonInverted)) 859 /** 860 * @} 861 */ 862 863 /** @defgroup TIM_Prescaler_Reload_Mode 864 * @{ 865 */ 866 867 #define TIM_PSCReloadMode_Update ((uint16_t)0x0000) 868 #define TIM_PSCReloadMode_Immediate ((uint16_t)0x0001) 869 #define IS_TIM_PRESCALER_RELOAD(RELOAD) (((RELOAD) == TIM_PSCReloadMode_Update) || \ 870 ((RELOAD) == TIM_PSCReloadMode_Immediate)) 871 /** 872 * @} 873 */ 874 875 /** @defgroup TIM_Forced_Action 876 * @{ 877 */ 878 879 #define TIM_ForcedAction_Active ((uint16_t)0x0050) 880 #define TIM_ForcedAction_InActive ((uint16_t)0x0040) 881 #define IS_TIM_FORCED_ACTION(ACTION) (((ACTION) == TIM_ForcedAction_Active) || \ 882 ((ACTION) == TIM_ForcedAction_InActive)) 883 /** 884 * @} 885 */ 886 887 /** @defgroup TIM_Encoder_Mode 888 * @{ 889 */ 890 891 #define TIM_EncoderMode_TI1 ((uint16_t)0x0001) 892 #define TIM_EncoderMode_TI2 ((uint16_t)0x0002) 893 #define TIM_EncoderMode_TI12 ((uint16_t)0x0003) 894 #define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_EncoderMode_TI1) || \ 895 ((MODE) == TIM_EncoderMode_TI2) || \ 896 ((MODE) == TIM_EncoderMode_TI12)) 897 /** 898 * @} 899 */ 900 901 902 /** @defgroup TIM_Event_Source 903 * @{ 904 */ 905 906 #define TIM_EventSource_Update ((uint16_t)0x0001) 907 #define TIM_EventSource_CC1 ((uint16_t)0x0002) 908 #define TIM_EventSource_CC2 ((uint16_t)0x0004) 909 #define TIM_EventSource_CC3 ((uint16_t)0x0008) 910 #define TIM_EventSource_CC4 ((uint16_t)0x0010) 911 #define TIM_EventSource_COM ((uint16_t)0x0020) 912 #define TIM_EventSource_Trigger ((uint16_t)0x0040) 913 #define TIM_EventSource_Break ((uint16_t)0x0080) 914 #define TIM_EventSource_Break2 ((uint16_t)0x0100) 915 #define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0xFE00) == 0x0000) && ((SOURCE) != 0x0000)) 916 917 /** 918 * @} 919 */ 920 921 /** @defgroup TIM_Update_Source 922 * @{ 923 */ 924 925 #define TIM_UpdateSource_Global ((uint16_t)0x0000) /*!< Source of update is the counter overflow/underflow 926 or the setting of UG bit, or an update generation 927 through the slave mode controller. */ 928 #define TIM_UpdateSource_Regular ((uint16_t)0x0001) /*!< Source of update is counter overflow/underflow. */ 929 #define IS_TIM_UPDATE_SOURCE(SOURCE) (((SOURCE) == TIM_UpdateSource_Global) || \ 930 ((SOURCE) == TIM_UpdateSource_Regular)) 931 /** 932 * @} 933 */ 934 935 /** @defgroup TIM_Output_Compare_Preload_State 936 * @{ 937 */ 938 939 #define TIM_OCPreload_Enable ((uint16_t)0x0008) 940 #define TIM_OCPreload_Disable ((uint16_t)0x0000) 941 #define IS_TIM_OCPRELOAD_STATE(STATE) (((STATE) == TIM_OCPreload_Enable) || \ 942 ((STATE) == TIM_OCPreload_Disable)) 943 /** 944 * @} 945 */ 946 947 /** @defgroup TIM_Output_Compare_Fast_State 948 * @{ 949 */ 950 951 #define TIM_OCFast_Enable ((uint16_t)0x0004) 952 #define TIM_OCFast_Disable ((uint16_t)0x0000) 953 #define IS_TIM_OCFAST_STATE(STATE) (((STATE) == TIM_OCFast_Enable) || \ 954 ((STATE) == TIM_OCFast_Disable)) 955 956 /** 957 * @} 958 */ 959 960 /** @defgroup TIM_Output_Compare_Clear_State 961 * @{ 962 */ 963 964 #define TIM_OCClear_Enable ((uint16_t)0x0080) 965 #define TIM_OCClear_Disable ((uint16_t)0x0000) 966 #define IS_TIM_OCCLEAR_STATE(STATE) (((STATE) == TIM_OCClear_Enable) || \ 967 ((STATE) == TIM_OCClear_Disable)) 968 /** 969 * @} 970 */ 971 972 /** @defgroup TIM_Trigger_Output_Source 973 * @{ 974 */ 975 976 #define TIM_TRGOSource_Reset ((uint16_t)0x0000) 977 #define TIM_TRGOSource_Enable ((uint16_t)0x0010) 978 #define TIM_TRGOSource_Update ((uint16_t)0x0020) 979 #define TIM_TRGOSource_OC1 ((uint16_t)0x0030) 980 #define TIM_TRGOSource_OC1Ref ((uint16_t)0x0040) 981 #define TIM_TRGOSource_OC2Ref ((uint16_t)0x0050) 982 #define TIM_TRGOSource_OC3Ref ((uint16_t)0x0060) 983 #define TIM_TRGOSource_OC4Ref ((uint16_t)0x0070) 984 #define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGOSource_Reset) || \ 985 ((SOURCE) == TIM_TRGOSource_Enable) || \ 986 ((SOURCE) == TIM_TRGOSource_Update) || \ 987 ((SOURCE) == TIM_TRGOSource_OC1) || \ 988 ((SOURCE) == TIM_TRGOSource_OC1Ref) || \ 989 ((SOURCE) == TIM_TRGOSource_OC2Ref) || \ 990 ((SOURCE) == TIM_TRGOSource_OC3Ref) || \ 991 ((SOURCE) == TIM_TRGOSource_OC4Ref)) 992 993 994 #define TIM_TRGO2Source_Reset ((uint32_t)0x00000000) 995 #define TIM_TRGO2Source_Enable ((uint32_t)0x00100000) 996 #define TIM_TRGO2Source_Update ((uint32_t)0x00200000) 997 #define TIM_TRGO2Source_OC1 ((uint32_t)0x00300000) 998 #define TIM_TRGO2Source_OC1Ref ((uint32_t)0x00400000) 999 #define TIM_TRGO2Source_OC2Ref ((uint32_t)0x00500000) 1000 #define TIM_TRGO2Source_OC3Ref ((uint32_t)0x00600000) 1001 #define TIM_TRGO2Source_OC4Ref ((uint32_t)0x00700000) 1002 #define TIM_TRGO2Source_OC5Ref ((uint32_t)0x00800000) 1003 #define TIM_TRGO2Source_OC6Ref ((uint32_t)0x00900000) 1004 #define TIM_TRGO2Source_OC4Ref_RisingFalling ((uint32_t)0x00A00000) 1005 #define TIM_TRGO2Source_OC6Ref_RisingFalling ((uint32_t)0x00B00000) 1006 #define TIM_TRGO2Source_OC4RefRising_OC6RefRising ((uint32_t)0x00C00000) 1007 #define TIM_TRGO2Source_OC4RefRising_OC6RefFalling ((uint32_t)0x00D00000) 1008 #define TIM_TRGO2Source_OC5RefRising_OC6RefRising ((uint32_t)0x00E00000) 1009 #define TIM_TRGO2Source_OC5RefRising_OC6RefFalling ((uint32_t)0x00F00000) 1010 #define IS_TIM_TRGO2_SOURCE(SOURCE) (((SOURCE) == TIM_TRGO2Source_Reset) || \ 1011 ((SOURCE) == TIM_TRGO2Source_Enable) || \ 1012 ((SOURCE) == TIM_TRGO2Source_Update) || \ 1013 ((SOURCE) == TIM_TRGO2Source_OC1) || \ 1014 ((SOURCE) == TIM_TRGO2Source_OC1Ref) || \ 1015 ((SOURCE) == TIM_TRGO2Source_OC2Ref) || \ 1016 ((SOURCE) == TIM_TRGO2Source_OC3Ref) || \ 1017 ((SOURCE) == TIM_TRGO2Source_OC4Ref) || \ 1018 ((SOURCE) == TIM_TRGO2Source_OC5Ref) || \ 1019 ((SOURCE) == TIM_TRGO2Source_OC6Ref) || \ 1020 ((SOURCE) == TIM_TRGO2Source_OC4Ref_RisingFalling) || \ 1021 ((SOURCE) == TIM_TRGO2Source_OC6Ref_RisingFalling) || \ 1022 ((SOURCE) == TIM_TRGO2Source_OC4RefRising_OC6RefRising) || \ 1023 ((SOURCE) == TIM_TRGO2Source_OC4RefRising_OC6RefFalling) || \ 1024 ((SOURCE) == TIM_TRGO2Source_OC5RefRising_OC6RefRising) || \ 1025 ((SOURCE) == TIM_TRGO2Source_OC5RefRising_OC6RefFalling)) 1026 /** 1027 * @} 1028 */ 1029 1030 /** @defgroup TIM_Slave_Mode 1031 * @{ 1032 */ 1033 1034 #define TIM_SlaveMode_Reset ((uint32_t)0x00004) 1035 #define TIM_SlaveMode_Gated ((uint32_t)0x00005) 1036 #define TIM_SlaveMode_Trigger ((uint32_t)0x00006) 1037 #define TIM_SlaveMode_External1 ((uint32_t)0x00007) 1038 #define TIM_SlaveMode_Combined_ResetTrigger ((uint32_t)0x10000) 1039 #define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SlaveMode_Reset) || \ 1040 ((MODE) == TIM_SlaveMode_Gated) || \ 1041 ((MODE) == TIM_SlaveMode_Trigger) || \ 1042 ((MODE) == TIM_SlaveMode_External1) || \ 1043 ((MODE) == TIM_SlaveMode_Combined_ResetTrigger)) 1044 /** 1045 * @} 1046 */ 1047 1048 /** @defgroup TIM_Master_Slave_Mode 1049 * @{ 1050 */ 1051 1052 #define TIM_MasterSlaveMode_Enable ((uint16_t)0x0080) 1053 #define TIM_MasterSlaveMode_Disable ((uint16_t)0x0000) 1054 #define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MasterSlaveMode_Enable) || \ 1055 ((STATE) == TIM_MasterSlaveMode_Disable)) 1056 /** 1057 * @} 1058 */ 1059 /** @defgroup TIM_Remap 1060 * @{ 1061 */ 1062 #define TIM16_GPIO ((uint16_t)0x0000) 1063 #define TIM16_RTC_CLK ((uint16_t)0x0001) 1064 #define TIM16_HSEDiv32 ((uint16_t)0x0002) 1065 #define TIM16_MCO ((uint16_t)0x0003) 1066 1067 #define TIM1_ADC1_AWDG1 ((uint16_t)0x0001) 1068 #define TIM1_ADC1_AWDG2 ((uint16_t)0x0002) 1069 #define TIM1_ADC1_AWDG3 ((uint16_t)0x0003) 1070 #define TIM1_ADC4_AWDG1 ((uint16_t)0x0004) 1071 #define TIM1_ADC4_AWDG2 ((uint16_t)0x0008) 1072 #define TIM1_ADC4_AWDG3 ((uint16_t)0x000C) 1073 1074 #define TIM8_ADC2_AWDG1 ((uint16_t)0x0001) 1075 #define TIM8_ADC2_AWDG2 ((uint16_t)0x0002) 1076 #define TIM8_ADC2_AWDG3 ((uint16_t)0x0003) 1077 #define TIM8_ADC3_AWDG1 ((uint16_t)0x0004) 1078 #define TIM8_ADC3_AWDG2 ((uint16_t)0x0008) 1079 #define TIM8_ADC3_AWDG3 ((uint16_t)0x000C) 1080 1081 #define TIM20_ADC3_AWDG1 ((uint16_t)0x0001) 1082 #define TIM20_ADC3_AWDG2 ((uint16_t)0x0002) 1083 #define TIM20_ADC3_AWDG3 ((uint16_t)0x0003) 1084 #define TIM20_ADC4_AWDG1 ((uint16_t)0x0004) 1085 #define TIM20_ADC4_AWDG2 ((uint16_t)0x0008) 1086 #define TIM20_ADC4_AWDG3 ((uint16_t)0x000C) 1087 1088 #define IS_TIM_REMAP(TIM_REMAP) (((TIM_REMAP) == TIM16_GPIO)|| \ 1089 ((TIM_REMAP) == TIM16_RTC_CLK) || \ 1090 ((TIM_REMAP) == TIM16_HSEDiv32) || \ 1091 ((TIM_REMAP) == TIM16_MCO) ||\ 1092 ((TIM_REMAP) == TIM1_ADC1_AWDG1) ||\ 1093 ((TIM_REMAP) == TIM1_ADC1_AWDG2) ||\ 1094 ((TIM_REMAP) == TIM1_ADC1_AWDG3) ||\ 1095 ((TIM_REMAP) == TIM1_ADC4_AWDG1) ||\ 1096 ((TIM_REMAP) == TIM1_ADC4_AWDG2) ||\ 1097 ((TIM_REMAP) == TIM1_ADC4_AWDG3) ||\ 1098 ((TIM_REMAP) == TIM8_ADC2_AWDG1) ||\ 1099 ((TIM_REMAP) == TIM8_ADC2_AWDG2) ||\ 1100 ((TIM_REMAP) == TIM8_ADC2_AWDG3) ||\ 1101 ((TIM_REMAP) == TIM8_ADC3_AWDG1) ||\ 1102 ((TIM_REMAP) == TIM8_ADC3_AWDG2) ||\ 1103 ((TIM_REMAP) == TIM8_ADC3_AWDG3) ||\ 1104 ((TIM_REMAP) == TIM20_ADC3_AWDG1)||\ 1105 ((TIM_REMAP) == TIM20_ADC3_AWDG2)||\ 1106 ((TIM_REMAP) == TIM20_ADC3_AWDG3)||\ 1107 ((TIM_REMAP) == TIM20_ADC4_AWDG1)||\ 1108 ((TIM_REMAP) == TIM20_ADC4_AWDG2)||\ 1109 ((TIM_REMAP) == TIM20_ADC4_AWDG3)) 1110 1111 /** 1112 * @} 1113 */ 1114 /** @defgroup TIM_Flags 1115 * @{ 1116 */ 1117 1118 #define TIM_FLAG_Update ((uint32_t)0x00001) 1119 #define TIM_FLAG_CC1 ((uint32_t)0x00002) 1120 #define TIM_FLAG_CC2 ((uint32_t)0x00004) 1121 #define TIM_FLAG_CC3 ((uint32_t)0x00008) 1122 #define TIM_FLAG_CC4 ((uint32_t)0x00010) 1123 #define TIM_FLAG_COM ((uint32_t)0x00020) 1124 #define TIM_FLAG_Trigger ((uint32_t)0x00040) 1125 #define TIM_FLAG_Break ((uint32_t)0x00080) 1126 #define TIM_FLAG_Break2 ((uint32_t)0x00100) 1127 #define TIM_FLAG_CC1OF ((uint32_t)0x00200) 1128 #define TIM_FLAG_CC2OF ((uint32_t)0x00400) 1129 #define TIM_FLAG_CC3OF ((uint32_t)0x00800) 1130 #define TIM_FLAG_CC4OF ((uint32_t)0x01000) 1131 #define TIM_FLAG_CC5 ((uint32_t)0x10000) 1132 #define TIM_FLAG_CC6 ((uint32_t)0x20000) 1133 #define IS_TIM_GET_FLAG(FLAG) (((FLAG) == TIM_FLAG_Update) || \ 1134 ((FLAG) == TIM_FLAG_CC1) || \ 1135 ((FLAG) == TIM_FLAG_CC2) || \ 1136 ((FLAG) == TIM_FLAG_CC3) || \ 1137 ((FLAG) == TIM_FLAG_CC4) || \ 1138 ((FLAG) == TIM_FLAG_COM) || \ 1139 ((FLAG) == TIM_FLAG_Trigger) || \ 1140 ((FLAG) == TIM_FLAG_Break) || \ 1141 ((FLAG) == TIM_FLAG_Break2) || \ 1142 ((FLAG) == TIM_FLAG_CC1OF) || \ 1143 ((FLAG) == TIM_FLAG_CC2OF) || \ 1144 ((FLAG) == TIM_FLAG_CC3OF) || \ 1145 ((FLAG) == TIM_FLAG_CC4OF) ||\ 1146 ((FLAG) == TIM_FLAG_CC5) ||\ 1147 ((FLAG) == TIM_FLAG_CC6)) 1148 1149 #define IS_TIM_CLEAR_FLAG(TIM_FLAG) ((((TIM_FLAG) & (uint32_t)0xE000) == 0x0000) && ((TIM_FLAG) != 0x0000)) 1150 /** 1151 * @} 1152 */ 1153 1154 /** @defgroup TIM_OCReferenceClear 1155 * @{ 1156 */ 1157 #define TIM_OCReferenceClear_ETRF ((uint16_t)0x0008) 1158 #define TIM_OCReferenceClear_OCREFCLR ((uint16_t)0x0000) 1159 #define TIM_OCREFERENCECECLEAR_SOURCE(SOURCE) (((SOURCE) == TIM_OCReferenceClear_ETRF) || \ 1160 ((SOURCE) == TIM_OCReferenceClear_OCREFCLR)) 1161 1162 /** @defgroup TIM_Input_Capture_Filer_Value 1163 * @{ 1164 */ 1165 1166 #define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF) 1167 /** 1168 * @} 1169 */ 1170 1171 /** @defgroup TIM_External_Trigger_Filter 1172 * @{ 1173 */ 1174 1175 #define IS_TIM_EXT_FILTER(EXTFILTER) ((EXTFILTER) <= 0xF) 1176 /** 1177 * @} 1178 */ 1179 1180 /** @defgroup TIM_Legacy 1181 * @{ 1182 */ 1183 1184 #define TIM_DMABurstLength_1Byte TIM_DMABurstLength_1Transfer 1185 #define TIM_DMABurstLength_2Bytes TIM_DMABurstLength_2Transfers 1186 #define TIM_DMABurstLength_3Bytes TIM_DMABurstLength_3Transfers 1187 #define TIM_DMABurstLength_4Bytes TIM_DMABurstLength_4Transfers 1188 #define TIM_DMABurstLength_5Bytes TIM_DMABurstLength_5Transfers 1189 #define TIM_DMABurstLength_6Bytes TIM_DMABurstLength_6Transfers 1190 #define TIM_DMABurstLength_7Bytes TIM_DMABurstLength_7Transfers 1191 #define TIM_DMABurstLength_8Bytes TIM_DMABurstLength_8Transfers 1192 #define TIM_DMABurstLength_9Bytes TIM_DMABurstLength_9Transfers 1193 #define TIM_DMABurstLength_10Bytes TIM_DMABurstLength_10Transfers 1194 #define TIM_DMABurstLength_11Bytes TIM_DMABurstLength_11Transfers 1195 #define TIM_DMABurstLength_12Bytes TIM_DMABurstLength_12Transfers 1196 #define TIM_DMABurstLength_13Bytes TIM_DMABurstLength_13Transfers 1197 #define TIM_DMABurstLength_14Bytes TIM_DMABurstLength_14Transfers 1198 #define TIM_DMABurstLength_15Bytes TIM_DMABurstLength_15Transfers 1199 #define TIM_DMABurstLength_16Bytes TIM_DMABurstLength_16Transfers 1200 #define TIM_DMABurstLength_17Bytes TIM_DMABurstLength_17Transfers 1201 #define TIM_DMABurstLength_18Bytes TIM_DMABurstLength_18Transfers 1202 /** 1203 * @} 1204 */ 1205 1206 /** 1207 * @} 1208 */ 1209 1210 /* Exported macro ------------------------------------------------------------*/ 1211 /* Exported functions --------------------------------------------------------*/ 1212 1213 /* TimeBase management ********************************************************/ 1214 void TIM_DeInit(TIM_TypeDef* TIMx); 1215 void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct); 1216 void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct); 1217 void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode); 1218 void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode); 1219 void TIM_SetCounter(TIM_TypeDef* TIMx, uint32_t Counter); 1220 void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint32_t Autoreload); 1221 uint32_t TIM_GetCounter(TIM_TypeDef* TIMx); 1222 uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx); 1223 void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState); 1224 void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource); 1225 void TIM_UIFRemap(TIM_TypeDef* TIMx, FunctionalState NewState); 1226 void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState); 1227 void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode); 1228 void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD); 1229 void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState); 1230 1231 /* Output Compare management **************************************************/ 1232 void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); 1233 void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); 1234 void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); 1235 void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); 1236 void TIM_OC5Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); 1237 void TIM_OC6Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); 1238 void TIM_SelectGC5C1(TIM_TypeDef* TIMx, FunctionalState NewState); 1239 void TIM_SelectGC5C2(TIM_TypeDef* TIMx, FunctionalState NewState); 1240 void TIM_SelectGC5C3(TIM_TypeDef* TIMx, FunctionalState NewState); 1241 void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct); 1242 void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint32_t TIM_OCMode); 1243 void TIM_SetCompare1(TIM_TypeDef* TIMx, uint32_t Compare1); 1244 void TIM_SetCompare2(TIM_TypeDef* TIMx, uint32_t Compare2); 1245 void TIM_SetCompare3(TIM_TypeDef* TIMx, uint32_t Compare3); 1246 void TIM_SetCompare4(TIM_TypeDef* TIMx, uint32_t Compare4); 1247 void TIM_SetCompare5(TIM_TypeDef* TIMx, uint32_t Compare5); 1248 void TIM_SetCompare6(TIM_TypeDef* TIMx, uint32_t Compare6); 1249 void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction); 1250 void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction); 1251 void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction); 1252 void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction); 1253 void TIM_ForcedOC5Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction); 1254 void TIM_ForcedOC6Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction); 1255 void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload); 1256 void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload); 1257 void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload); 1258 void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload); 1259 void TIM_OC5PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload); 1260 void TIM_OC6PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload); 1261 void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast); 1262 void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast); 1263 void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast); 1264 void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast); 1265 void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear); 1266 void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear); 1267 void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear); 1268 void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear); 1269 void TIM_ClearOC5Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear); 1270 void TIM_ClearOC6Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear); 1271 void TIM_SelectOCREFClear(TIM_TypeDef* TIMx, uint16_t TIM_OCReferenceClear); 1272 void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity); 1273 void TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity); 1274 void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity); 1275 void TIM_OC2NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity); 1276 void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity); 1277 void TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity); 1278 void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity); 1279 void TIM_OC5PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity); 1280 void TIM_OC6PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity); 1281 void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx); 1282 void TIM_CCxNCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN); 1283 1284 /* Input Capture management ***************************************************/ 1285 void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct); 1286 void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct); 1287 void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct); 1288 uint32_t TIM_GetCapture1(TIM_TypeDef* TIMx); 1289 uint32_t TIM_GetCapture2(TIM_TypeDef* TIMx); 1290 uint32_t TIM_GetCapture3(TIM_TypeDef* TIMx); 1291 uint32_t TIM_GetCapture4(TIM_TypeDef* TIMx); 1292 void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC); 1293 void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC); 1294 void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC); 1295 void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC); 1296 1297 /* Advanced-control timers (TIM1 and TIM8) specific features ******************/ 1298 void TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct); 1299 void TIM_Break1Config(TIM_TypeDef* TIMx, uint32_t TIM_Break1Polarity, uint8_t TIM_Break1Filter); 1300 void TIM_Break2Config(TIM_TypeDef* TIMx, uint32_t TIM_Break2Polarity, uint8_t TIM_Break2Filter); 1301 void TIM_Break1Cmd(TIM_TypeDef* TIMx, FunctionalState NewState); 1302 void TIM_Break2Cmd(TIM_TypeDef* TIMx, FunctionalState NewState); 1303 void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* TIM_BDTRInitStruct); 1304 void TIM_CtrlPWMOutputs(TIM_TypeDef* TIMx, FunctionalState NewState); 1305 void TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState); 1306 void TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState); 1307 1308 /* Interrupts, DMA and flags management ***************************************/ 1309 void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState); 1310 void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource); 1311 FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint32_t TIM_FLAG); 1312 void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG); 1313 ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT); 1314 void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT); 1315 void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength); 1316 void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState); 1317 void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState); 1318 1319 /* Clocks management **********************************************************/ 1320 void TIM_InternalClockConfig(TIM_TypeDef* TIMx); 1321 void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource); 1322 void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource, 1323 uint16_t TIM_ICPolarity, uint16_t ICFilter); 1324 void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, 1325 uint16_t ExtTRGFilter); 1326 void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, 1327 uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter); 1328 1329 /* Synchronization management *************************************************/ 1330 void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource); 1331 void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource); 1332 void TIM_SelectOutputTrigger2(TIM_TypeDef* TIMx, uint32_t TIM_TRGO2Source); 1333 void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint32_t TIM_SlaveMode); 1334 void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode); 1335 void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, 1336 uint16_t ExtTRGFilter); 1337 1338 /* Specific interface management **********************************************/ 1339 void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode, 1340 uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity); 1341 void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState); 1342 1343 /* Specific remapping management **********************************************/ 1344 void TIM_RemapConfig(TIM_TypeDef* TIMx, uint16_t TIM_Remap); 1345 1346 #ifdef __cplusplus 1347 } 1348 #endif 1349 1350 #endif /*__STM32F30x_TIM_H */ 1351 1352 /** 1353 * @} 1354 */ 1355 1356 /** 1357 * @} 1358 */ 1359 1360 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 1361