1 /* $NetBSD: ppb.c,v 1.55 2015/11/16 09:10:58 msaitoh Exp $ */
2
3 /*
4 * Copyright (c) 1996, 1998 Christopher G. Demetriou. All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. All advertising materials mentioning features or use of this software
15 * must display the following acknowledgement:
16 * This product includes software developed by Christopher G. Demetriou
17 * for the NetBSD Project.
18 * 4. The name of the author may not be used to endorse or promote products
19 * derived from this software without specific prior written permission
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 */
32
33 #include <sys/cdefs.h>
34 __KERNEL_RCSID(0, "$NetBSD: ppb.c,v 1.55 2015/11/16 09:10:58 msaitoh Exp $");
35
36 #include <sys/param.h>
37 #include <sys/systm.h>
38 #include <sys/kernel.h>
39 #include <sys/device.h>
40
41 #include <dev/pci/pcireg.h>
42 #include <dev/pci/pcivar.h>
43 #include <dev/pci/ppbreg.h>
44 #include <dev/pci/pcidevs.h>
45
46 #define PCIE_SLCSR_NOTIFY_MASK \
47 (PCIE_SLCSR_ABE | PCIE_SLCSR_PFE | PCIE_SLCSR_MSE | \
48 PCIE_SLCSR_PDE | PCIE_SLCSR_CCE | PCIE_SLCSR_HPE)
49
50 struct ppb_softc {
51 device_t sc_dev; /* generic device glue */
52 pci_chipset_tag_t sc_pc; /* our PCI chipset... */
53 pcitag_t sc_tag; /* ...and tag. */
54
55 pcireg_t sc_pciconfext[48];
56 };
57
58 static const char pcie_linkspeed_strings[4][5] = {
59 "1.25", "2.5", "5.0", "8.0",
60 };
61
62 static bool ppb_resume(device_t, const pmf_qual_t *);
63 static bool ppb_suspend(device_t, const pmf_qual_t *);
64
65 static int
ppbmatch(device_t parent,cfdata_t match,void * aux)66 ppbmatch(device_t parent, cfdata_t match, void *aux)
67 {
68 struct pci_attach_args *pa = aux;
69
70 /*
71 * Check the ID register to see that it's a PCI bridge.
72 * If it is, we assume that we can deal with it; it _should_
73 * work in a standardized way...
74 */
75 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE &&
76 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_PCI)
77 return 1;
78
79 #ifdef __powerpc__
80 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_PROCESSOR &&
81 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_PROCESSOR_POWERPC) {
82 pcireg_t bhlc = pci_conf_read(pa->pa_pc, pa->pa_tag,
83 PCI_BHLC_REG);
84 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_FREESCALE
85 && PCI_HDRTYPE(bhlc) == PCI_HDRTYPE_RC)
86 return 1;
87 }
88 #endif
89
90 #ifdef _MIPS_PADDR_T_64BIT
91 /* The LDT HB acts just like a PPB. */
92 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_SIBYTE
93 && PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_SIBYTE_BCM1250_LDTHB)
94 return 1;
95 #endif
96
97 return 0;
98 }
99
100 static void
ppb_fix_pcie(device_t self)101 ppb_fix_pcie(device_t self)
102 {
103 struct ppb_softc *sc = device_private(self);
104 pcireg_t reg;
105 int off, capversion, devtype;
106
107 if (!pci_get_capability(sc->sc_pc, sc->sc_tag, PCI_CAP_PCIEXPRESS,
108 &off, ®))
109 return; /* Not a PCIe device */
110
111 capversion = PCIE_XCAP_VER(reg);
112 devtype = PCIE_XCAP_TYPE(reg);
113 aprint_normal_dev(self, "PCI Express capability version ");
114 switch (capversion) {
115 case PCIE_XCAP_VER_1:
116 aprint_normal("1");
117 break;
118 case PCIE_XCAP_VER_2:
119 aprint_normal("2");
120 break;
121 default:
122 aprint_normal_dev(self, "unsupported (%d)\n", capversion);
123 return;
124 }
125 aprint_normal(" <");
126 switch (devtype) {
127 case PCIE_XCAP_TYPE_PCIE_DEV:
128 aprint_normal("PCI-E Endpoint device");
129 break;
130 case PCIE_XCAP_TYPE_PCI_DEV:
131 aprint_normal("Legacy PCI-E Endpoint device");
132 break;
133 case PCIE_XCAP_TYPE_ROOT:
134 aprint_normal("Root Port of PCI-E Root Complex");
135 break;
136 case PCIE_XCAP_TYPE_UP:
137 aprint_normal("Upstream Port of PCI-E Switch");
138 break;
139 case PCIE_XCAP_TYPE_DOWN:
140 aprint_normal("Downstream Port of PCI-E Switch");
141 break;
142 case PCIE_XCAP_TYPE_PCIE2PCI:
143 aprint_normal("PCI-E to PCI/PCI-X Bridge");
144 break;
145 case PCIE_XCAP_TYPE_PCI2PCIE:
146 aprint_normal("PCI/PCI-X to PCI-E Bridge");
147 break;
148 default:
149 aprint_normal("Device/Port Type %x", devtype);
150 break;
151 }
152
153 switch (devtype) {
154 case PCIE_XCAP_TYPE_ROOT:
155 case PCIE_XCAP_TYPE_DOWN:
156 case PCIE_XCAP_TYPE_PCI2PCIE:
157 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, off + PCIE_LCAP);
158 u_int mlw = __SHIFTOUT(reg, PCIE_LCAP_MAX_WIDTH);
159 u_int mls = __SHIFTOUT(reg, PCIE_LCAP_MAX_SPEED);
160
161 if (mls < __arraycount(pcie_linkspeed_strings)) {
162 aprint_normal("> x%d @ %sGT/s\n",
163 mlw, pcie_linkspeed_strings[mls]);
164 } else {
165 aprint_normal("> x%d @ %d.%dGT/s\n",
166 mlw, (mls * 25) / 10, (mls * 25) % 10);
167 }
168
169 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, off + PCIE_LCSR);
170 if (reg & PCIE_LCSR_DLACTIVE) { /* DLLA */
171 u_int lw = __SHIFTOUT(reg, PCIE_LCSR_NLW);
172 u_int ls = __SHIFTOUT(reg, PCIE_LCSR_LINKSPEED);
173
174 if (lw != mlw || ls != mls) {
175 if (ls < __arraycount(pcie_linkspeed_strings)) {
176 aprint_normal_dev(self,
177 "link is x%d @ %sGT/s\n",
178 lw, pcie_linkspeed_strings[ls]);
179 } else {
180 aprint_normal_dev(self,
181 "link is x%d @ %d.%dGT/s\n",
182 lw, (ls * 25) / 10, (ls * 25) % 10);
183 }
184 }
185 }
186 break;
187 default:
188 aprint_normal(">\n");
189 break;
190 }
191
192 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, off + PCIE_SLCSR);
193 if (reg & PCIE_SLCSR_NOTIFY_MASK) {
194 aprint_debug_dev(self, "disabling notification events\n");
195 reg &= ~PCIE_SLCSR_NOTIFY_MASK;
196 pci_conf_write(sc->sc_pc, sc->sc_tag,
197 off + PCIE_SLCSR, reg);
198 }
199 }
200
201 static void
ppbattach(device_t parent,device_t self,void * aux)202 ppbattach(device_t parent, device_t self, void *aux)
203 {
204 struct ppb_softc *sc = device_private(self);
205 struct pci_attach_args *pa = aux;
206 pci_chipset_tag_t pc = pa->pa_pc;
207 struct pcibus_attach_args pba;
208 pcireg_t busdata;
209
210 pci_aprint_devinfo(pa, NULL);
211
212 sc->sc_pc = pc;
213 sc->sc_tag = pa->pa_tag;
214 sc->sc_dev = self;
215
216 busdata = pci_conf_read(pc, pa->pa_tag, PPB_REG_BUSINFO);
217
218 if (PPB_BUSINFO_SECONDARY(busdata) == 0) {
219 aprint_normal_dev(self, "not configured by system firmware\n");
220 return;
221 }
222
223 ppb_fix_pcie(self);
224
225 #if 0
226 /*
227 * XXX can't do this, because we're not given our bus number
228 * (we shouldn't need it), and because we've no way to
229 * decompose our tag.
230 */
231 /* sanity check. */
232 if (pa->pa_bus != PPB_BUSINFO_PRIMARY(busdata))
233 panic("ppbattach: bus in tag (%d) != bus in reg (%d)",
234 pa->pa_bus, PPB_BUSINFO_PRIMARY(busdata));
235 #endif
236
237 if (!pmf_device_register(self, ppb_suspend, ppb_resume))
238 aprint_error_dev(self, "couldn't establish power handler\n");
239
240 /*
241 * Attach the PCI bus than hangs off of it.
242 *
243 * XXX Don't pass-through Memory Read Multiple. Should we?
244 * XXX Consult the spec...
245 */
246 pba.pba_iot = pa->pa_iot;
247 pba.pba_memt = pa->pa_memt;
248 pba.pba_dmat = pa->pa_dmat;
249 pba.pba_dmat64 = pa->pa_dmat64;
250 pba.pba_pc = pc;
251 pba.pba_flags = pa->pa_flags & ~PCI_FLAGS_MRM_OKAY;
252 pba.pba_bus = PPB_BUSINFO_SECONDARY(busdata);
253 pba.pba_sub = PPB_BUSINFO_SUBORDINATE(busdata);
254 pba.pba_bridgetag = &sc->sc_tag;
255 pba.pba_intrswiz = pa->pa_intrswiz;
256 pba.pba_intrtag = pa->pa_intrtag;
257
258 config_found_ia(self, "pcibus", &pba, pcibusprint);
259 }
260
261 static int
ppbdetach(device_t self,int flags)262 ppbdetach(device_t self, int flags)
263 {
264 int rc;
265
266 if ((rc = config_detach_children(self, flags)) != 0)
267 return rc;
268 pmf_device_deregister(self);
269 return 0;
270 }
271
272 static bool
ppb_resume(device_t dv,const pmf_qual_t * qual)273 ppb_resume(device_t dv, const pmf_qual_t *qual)
274 {
275 struct ppb_softc *sc = device_private(dv);
276 int off;
277 pcireg_t val;
278
279 for (off = 0x40; off <= 0xff; off += 4) {
280 val = pci_conf_read(sc->sc_pc, sc->sc_tag, off);
281 if (val != sc->sc_pciconfext[(off - 0x40) / 4])
282 pci_conf_write(sc->sc_pc, sc->sc_tag, off,
283 sc->sc_pciconfext[(off - 0x40)/4]);
284 }
285
286 ppb_fix_pcie(dv);
287
288 return true;
289 }
290
291 static bool
ppb_suspend(device_t dv,const pmf_qual_t * qual)292 ppb_suspend(device_t dv, const pmf_qual_t *qual)
293 {
294 struct ppb_softc *sc = device_private(dv);
295 int off;
296
297 for (off = 0x40; off <= 0xff; off += 4)
298 sc->sc_pciconfext[(off - 0x40) / 4] =
299 pci_conf_read(sc->sc_pc, sc->sc_tag, off);
300
301 return true;
302 }
303
304 static void
ppbchilddet(device_t self,device_t child)305 ppbchilddet(device_t self, device_t child)
306 {
307 /* we keep no references to child devices, so do nothing */
308 }
309
310 CFATTACH_DECL3_NEW(ppb, sizeof(struct ppb_softc),
311 ppbmatch, ppbattach, ppbdetach, NULL, NULL, ppbchilddet,
312 DVF_DETACH_SHUTDOWN);
313