1// DESCRIPTION: Verilator: Verilog Test module 2// 3// This file ONLY is placed under the Creative Commons Public Domain, for 4// any use, without warranty, 2007 by Wilson Snyder. 5// SPDX-License-Identifier: CC0-1.0 6 7module t (/*AUTOARG*/ 8 // Inputs 9 clk 10 ); 11 12 input clk; 13 14 always @ (posedge clk) begin 15 assert (0); 16 $finish; 17 end 18 19endmodule 20