1// DESCRIPTION: Verilator: Verilog Test module
2// This file ONLY is placed under the Creative Commons Public Domain, for
3// any use, without warranty, 2020 by Wilson Snyder.
4// SPDX-License-Identifier: CC0-1.0
5
6module t (/*AUTOARG*/
7   // Inputs
8   clk
9   );
10   input clk;
11
12   integer 	cyc = 0;
13   reg [63:0] 	crc;
14   reg [63:0] 	sum;
15
16   // Take CRC data and apply to testblock inputs
17   wire [9:0]  in = crc[9:0];
18
19   /*AUTOWIRE*/
20
21   Test test (/*AUTOINST*/
22	      // Inputs
23	      .clk			(clk),
24	      .in			(in[9:0]));
25
26   // Aggregate outputs into a single result vector
27   wire [63:0] result = {64'h0};
28
29   // Test loop
30   always @ (posedge clk) begin
31`ifdef TEST_VERBOSE
32      $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
33`endif
34      cyc <= cyc + 1;
35      crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
36      sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
37      if (cyc==0) begin
38	 // Setup
39	 crc <= 64'h5aef0c8d_d70a4497;
40      end
41      else if (cyc<10) begin
42	 sum <= 64'h0;
43      end
44      else if (cyc<90) begin
45      end
46      else if (cyc==99) begin
47	 $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
48	 if (crc !== 64'hc77bb9b3784ea091) $stop;
49	 // What checksum will we end up with (above print should match)
50`define EXPECTED_SUM 64'h0
51	 if (sum !== `EXPECTED_SUM) $stop;
52	 $write("*-* All Finished *-*\n");
53	 $finish;
54      end
55   end
56
57endmodule
58
59module Test (/*AUTOARG*/
60   // Inputs
61   clk, in
62   );
63   input clk;
64   input [9:0] in;
65
66   reg a [9:0];
67   integer ai;
68   always @* begin
69      for (ai=0;ai<10;ai=ai+1) begin
70	 a[ai]=in[ai];
71      end
72   end
73
74   reg [1:0] b [9:0];
75   integer   j;
76
77   generate
78      genvar i;
79      for (i=0; i<2; i=i+1) begin
80	 always @(posedge clk) begin
81	    for (j=0; j<10; j=j+1) begin
82	       if (a[j])
83		 b[i][j] <= 1'b0;
84	       else
85		 b[i][j] <= 1'b1;
86	    end
87	 end
88      end
89   endgenerate
90endmodule
91