1// DESCRIPTION: Verilator: Verilog Test module 2// 3// This file ONLY is placed under the Creative Commons Public Domain, for 4// any use, without warranty, 2013 by Wilson Snyder. 5// SPDX-License-Identifier: CC0-1.0 6 7// bug789 generates 8 9module t (/*AUTOARG*/ 10 // Inputs 11 clk 12 ); 13 14 input clk; 15 integer cyc=1; 16 17 ifc #(1) itopa(); 18 ifc #(2) itopb(); 19 20 sub #(1) ca (.isub(itopa), 21 .i_value(4)); 22 sub #(2) cb (.isub(itopb), 23 .i_value(5)); 24 25 always @ (posedge clk) begin 26 cyc <= cyc + 1; 27 if (cyc==1) begin 28 if (itopa.MODE != 1) $stop; 29 if (itopb.MODE != 2) $stop; 30 end 31 if (cyc==20) begin 32 if (itopa.i != 4) $stop; 33 if (itopb.i != 5) $stop; 34 $write("*-* All Finished *-*\n"); 35 $finish; 36 end 37 end 38endmodule 39 40module sub 41 #(parameter MODE = 0) 42 ( 43 ifc isub, 44 input integer i_value 45 ); 46 47 // Commercial unsupported Xmrs into scopes within interfaces 48 generate 49 always_comb isub.i = i_value; 50 endgenerate 51endmodule 52 53interface ifc; 54 parameter MODE = 0; 55 // Commercial unsupported Xmrs into scopes within interfaces 56 generate 57 integer i; 58 endgenerate 59endinterface 60