1// DESCRIPTION: Verilator: Verilog Test module
2//
3// This file ONLY is placed under the Creative Commons Public Domain, for
4// any use, without warranty, 2021 by Wilson Snyder.
5// SPDX-License-Identifier: CC0-1.0
6
7`define stop $stop
8`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d:  got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0)
9
10interface ifc
11  #(
12    parameter int unsigned WIDTH
13    ) ();
14   typedef struct {
15     logic [WIDTH-1:0] data;
16   } struct_t;
17endinterface
18
19module t (/*AUTOARG*/
20   // Inputs
21   clk
22   );
23   input clk;
24
25   ifc #(10) i_ifc10();
26   ifc #(20) i_ifc20();
27
28   sub #(10) u_sub10 (.clk, .ifc_if(i_ifc10));
29   sub #(20) u_sub20 (.clk, .ifc_if(i_ifc20));
30
31   integer cyc = 1;
32   always @ (posedge clk) begin
33      cyc <= cyc + 1;
34      if (cyc==20) begin
35         $write("*-* All Finished *-*\n");
36         $finish;
37      end
38   end
39endmodule
40
41module sub #(
42     parameter int EXP_WIDTH)
43   (
44    input logic clk,
45    ifc ifc_if);
46   typedef ifc_if.struct_t struct_t;
47
48   wire [EXP_WIDTH-1:0] expval = '1;
49
50   initial begin
51      struct_t substruct;
52      substruct.data = '1;
53      `checkh(substruct.data, expval);
54   end
55
56endmodule
57