1// DESCRIPTION: Verilator: Verilog Test module 2// 3// This file ONLY is placed under the Creative Commons Public Domain, for 4// any use, without warranty, 2021 by Wilson Snyder. 5// SPDX-License-Identifier: CC0-1.0 6 7module t (/*AUTOARG*/ 8 // Inputs 9 clk 10 ); 11 input clk; 12 13 int i; 14 15 reg [2:0] cyc; 16 17 initial cyc = 0; 18 always @(posedge clk) cyc <= cyc + 1; 19 20 /* verilator lint_off LATCH */ 21 always @* begin 22 case (cyc) 23 3'b000: i = 0; 24 3'b001: i = 1; 25 3'b010: ; // unset 26 3'b100: i = 4; 27 3'b101: i = 5; 28 default: i = 99; 29 endcase 30 end 31 /* verilator lint_on LATCH */ 32 33 always @(posedge clk) begin 34 $display("cyle %d = %d", cyc, i); 35 if (cyc == 7) begin 36 $write("*-* All Finished *-*\n"); 37 $finish; 38 end 39 end 40endmodule 41