1// DESCRIPTION: Verilator: Verilog Test module 2// 3// This file ONLY is placed under the Creative Commons Public Domain, for 4// any use, without warranty, 2012 by Wilson Snyder. 5// SPDX-License-Identifier: CC0-1.0 6 7module t (/*AUTOARG*/ 8 // Inputs 9 clk, model 10 ); 11 /*verilator no_inline_module*/ // So we'll get hiearachy we can test 12 input clk; 13 14 // Parameter so we can test for different model error 15 parameter MODEL_WIDTH = 10; 16 input [MODEL_WIDTH-1:0] model; 17 18 initial $write("Model width = %0d\n", MODEL_WIDTH); 19 20 sub sub (/*AUTOINST*/ 21 // Inputs 22 .clk (clk)); 23endmodule 24 25module sub (/*AUTOARG*/ 26 // Inputs 27 clk 28 ); 29 30 input clk; 31 /*verilator no_inline_module*/ // So we'll get hiearachy we can test 32 33 integer cyc = 0; 34 35 reg [127:0] save128; 36 reg [47:0] save48; 37 reg [1:0] save2; 38 reg [255:0] cycdone; // Make sure each cycle executes exactly once 39 reg [31:0] vec[2:1][2:1]; 40 reg [2:1][2:1][31:0] pvec; 41 real r; 42 string s,s2; 43 string sarr[2:1]; 44 string assoc[string]; 45 46 string si; 47 48 // Test loop 49 always @ (posedge clk) begin 50`ifdef TEST_VERBOSE 51 $write("[%0t] cyc==%0d\n", $time, cyc); 52`endif 53 si = "siimmed"; 54 cyc <= cyc + 1; 55 if (cycdone[cyc[7:0]]) $stop; 56 cycdone[cyc[7:0]] <= '1; 57 if (cyc==0) begin 58 // Setup 59 save128 <= 128'hc77bb9b3784ea0914afe43fb79d7b71e; 60 save48 <= 48'h4afe43fb79d7; 61 save2 <= 2'b10; 62 vec[1][1] <= 32'h0101; 63 vec[1][2] <= 32'h0102; 64 vec[2][1] <= 32'h0201; 65 vec[2][2] <= 32'h0202; 66 pvec[1][1] <= 32'h10101; 67 pvec[1][2] <= 32'h10102; 68 pvec[2][1] <= 32'h10201; 69 pvec[2][2] <= 32'h10202; 70 r <= 1.234; 71 s <= "hello"; 72 sarr[1] <= "sarr[1]"; 73 sarr[2] <= "sarr[2]"; 74 assoc["mapped"] <= "Is mapped"; 75 end 76 if (cyc==1) begin 77 if ($test$plusargs("save_restore")!=0) begin 78 // Don't allow the restored model to run from time 0, it must run from a restore 79 $write("%%Error: didn't really restore\n"); 80 $stop; 81 end 82 end 83 else if (cyc==99) begin 84 if (save128 !== 128'hc77bb9b3784ea0914afe43fb79d7b71e) $stop; 85 if (save48 !== 48'h4afe43fb79d7) $stop; 86 if (save2 !== 2'b10) $stop; 87 if (cycdone !== {{(256-99){1'b0}}, {99{1'b1}}}) $stop; 88 if (vec[1][1] !== 32'h0101) $stop; 89 if (vec[1][2] !== 32'h0102) $stop; 90 if (vec[2][1] !== 32'h0201) $stop; 91 if (vec[2][2] !== 32'h0202) $stop; 92 if (pvec[1][1] !== 32'h10101) $stop; 93 if (pvec[1][2] !== 32'h10102) $stop; 94 if (pvec[2][1] !== 32'h10201) $stop; 95 if (pvec[2][2] !== 32'h10202) $stop; 96 if (r != 1.234) $stop; 97 $display("%s",s); 98 $display("%s",sarr[1]); 99 $display("%s",sarr[2]); 100 if (assoc["mapped"] != "Is mapped") $stop; 101 $write("*-* All Finished *-*\n"); 102 $finish; 103 end 104 end 105endmodule 106