1// DESCRIPTION: Verilator: Verilog Test module
2//
3// This file ONLY is placed under the Creative Commons Public Domain, for
4// any use, without warranty, 2003 by Wilson Snyder.
5// SPDX-License-Identifier: CC0-1.0
6
7module t (clk);
8   input clk;
9
10   reg [43:0] mi;
11   reg        sel;
12   reg [3:0]  sel2;
13
14   always @ (posedge clk) begin
15      mi = 44'h123;
16      sel = mi[44];
17      sel2 = mi[44:41];
18      $write ("Bad select %x %x\n", sel, sel2);
19   end
20endmodule
21