1// DESCRIPTION: Verilator: Verilog Test module
2//
3// This file ONLY is placed under the Creative Commons Public Domain, for
4// any use, without warranty, 2020 by Wilson Snyder.
5// SPDX-License-Identifier: CC0-1.0
6
7`ifdef USE_INLINE
8 `define INLINE_MODULE /*verilator inline_module*/
9`else
10 `define INLINE_MODULE /*verilator public_module*/
11`endif
12
13module t (/*AUTOARG*/);
14
15`define DRAM1(bank) mem.mem_bank[bank].dccm.dccm_bank.ram_core
16`define DRAM2(bank) mem.mem_bank2[bank].dccm.dccm_bank.ram_core
17`define DRAM3(bank) mem.mem_bank3[bank].dccm.dccm_bank.ram_core
18`define DRAM4(bank) mem.sub4.mem_bank4[bank].dccm.dccm_bank.ram_core
19
20   initial begin
21      `DRAM1(0)[3] = 130;
22      `DRAM1(1)[3] = 131;
23      `DRAM2(0)[3] = 230;
24      `DRAM2(1)[3] = 231;
25      `DRAM3(0)[3] = 330;
26      `DRAM3(1)[3] = 331;
27      `DRAM4(0)[3] = 430;
28      `DRAM4(1)[3] = 431;
29      if (`DRAM1(0)[3] !== 130) $stop;
30      if (`DRAM1(1)[3] !== 131) $stop;
31      if (`DRAM2(0)[3] !== 230) $stop;
32      if (`DRAM2(1)[3] !== 231) $stop;
33      if (`DRAM3(0)[3] !== 330) $stop;
34      if (`DRAM3(1)[3] !== 331) $stop;
35      if (`DRAM4(0)[3] !== 430) $stop;
36      if (`DRAM4(1)[3] !== 431) $stop;
37      $write("*-* All Finished *-*\n");
38      $finish;
39   end
40
41   eh2_lsu_dccm_mem mem (/*AUTOINST*/);
42
43endmodule
44
45module eh2_lsu_dccm_mem
46#(
47  DCCM_INDEX_DEPTH = 8192,
48  DCCM_NUM_BANKS = 2
49 )(
50);
51   `INLINE_MODULE
52
53   // 8 Banks, 16KB each (2048 x 72)
54   for (genvar i=0; i<DCCM_NUM_BANKS; i++) begin: mem_bank
55      if (DCCM_INDEX_DEPTH == 16384) begin : dccm
56         eh2_ram
57           #(.depth(16384), .width(32))
58         dccm_bank (.*);
59      end
60      else if (DCCM_INDEX_DEPTH == 8192) begin : dccm
61         eh2_ram
62           #(.depth(8192), .width(32))
63         dccm_bank (.*);
64      end
65      else if (DCCM_INDEX_DEPTH == 4096) begin : dccm
66         eh2_ram
67           #(.depth(4096), .width(32))
68         dccm_bank (.*);
69      end
70   end : mem_bank
71
72   // Check that generate doesn't also add a genblk
73   generate
74      for (genvar i=0; i<DCCM_NUM_BANKS; i++) begin: mem_bank2
75         if (DCCM_INDEX_DEPTH == 8192) begin : dccm
76            eh2_ram
77              #(.depth(8192), .width(32))
78            dccm_bank (.*);
79         end
80      end
81   endgenerate
82
83   // Nor this
84   generate
85      begin
86         for (genvar i=0; i<DCCM_NUM_BANKS; i++) begin: mem_bank3
87            if (DCCM_INDEX_DEPTH == 8192) begin : dccm
88               eh2_ram
89                 #(.depth(8192), .width(32))
90               dccm_bank (.*);
91            end
92         end
93      end
94   endgenerate
95
96   // This does
97   generate
98      begin : sub4
99         for (genvar i=0; i<DCCM_NUM_BANKS; i++) begin: mem_bank4
100            if (DCCM_INDEX_DEPTH == 8192) begin : dccm
101               eh2_ram
102                 #(.depth(8192), .width(32))
103               dccm_bank (.*);
104            end
105         end
106      end
107   endgenerate
108
109   // This is an error (previously declared)
110   //generate
111   //   begin
112   //      eh2_ram
113   //      #(.depth(8192), .width(32))
114   //    dccm_bank (.*);
115   //   end
116   //   begin
117   //      eh2_ram
118   //      #(.depth(8192), .width(32))
119   //    dccm_bank (.*);
120   //   end
121   //endgenerate
122
123endmodule
124
125module eh2_ram #(depth=4096, width=39)
126   ();
127
128   `INLINE_MODULE
129
130   reg [(width-1):0] ram_core [(depth-1):0];
131
132endmodule
133