1// DESCRIPTION: Verilator: Verilog Test module
2//
3// Copyright 2010 by Wilson Snyder. This program is free software; you can
4// redistribute it and/or modify it under the terms of either the GNU
5// Lesser General Public License Version 3 or the Perl Artistic License
6// Version 2.0.
7// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
8
9`ifdef USE_VPI_NOT_DPI
10//We call it via $c so we can verify DPI isn't required - see bug572
11`else
12import "DPI-C" context function int mon_check();
13`endif
14
15import "DPI-C" function void dpi_print(input string somestring);
16
17`ifdef VERILATOR_COMMENTS
18 `define PUBLIC_FLAT_RD /*verilator public_flat_rd*/
19 `define PUBLIC_FLAT_RW /*verilator public_flat_rw @(posedge clk)*/
20`else
21 `define PUBLIC_FLAT_RD
22 `define PUBLIC_FLAT_RW
23`endif
24
25interface intf #(parameter int param `PUBLIC_FLAT_RD = 7);
26   localparam int lparam `PUBLIC_FLAT_RD = param + 1;
27   logic [7:0] bytesig `PUBLIC_FLAT_RD;
28endinterface
29
30module t (/*AUTOARG*/
31   // Inputs
32   input clk                            `PUBLIC_FLAT_RD,
33
34   // test ports
35   input  [15:0]        testin          `PUBLIC_FLAT_RD,
36   output [23:0]        testout     `PUBLIC_FLAT_RW
37
38   );
39
40`ifdef VERILATOR
41`systemc_header
42extern "C" int mon_check();
43`verilog
44`endif
45
46   reg          onebit          `PUBLIC_FLAT_RW;
47   reg [2:1]    twoone          `PUBLIC_FLAT_RW;
48   reg          onetwo [1:2]    `PUBLIC_FLAT_RW;
49   reg [2:1]    fourthreetwoone[4:3] `PUBLIC_FLAT_RW;
50   reg [1:0] [1:0] twobytwo     `PUBLIC_FLAT_RW;
51   int          theint          `PUBLIC_FLAT_RW;
52
53   integer      status;
54
55`ifdef IVERILOG
56   // stop icarus optimizing signals away
57   wire 	redundant = onebit | onetwo[1] | twoone | fourthreetwoone[3] | twobytwo;
58`endif
59
60   wire         subin  `PUBLIC_FLAT_RD;
61   wire         subout `PUBLIC_FLAT_RD;
62   sub sub(.*);
63
64   // Test loop
65   initial begin
66      dpi_print("foo");
67`ifdef VERILATOR
68      status = $c32("mon_check()");
69`endif
70`ifdef IVERILOG
71     status = $mon_check();
72`endif
73`ifndef USE_VPI_NOT_DPI
74     status = mon_check();
75`endif
76      if (status!=0) begin
77	 $write("%%Error: t_vpi_get.cpp:%0d: C Test failed\n", status);
78	 $stop;
79      end
80      $write("*-* All Finished *-*\n");
81      $finish;
82   end
83
84endmodule : t
85
86module sub #(
87   parameter int subparam `PUBLIC_FLAT_RD = 2
88) (
89   input  subin  `PUBLIC_FLAT_RD,
90   output subout `PUBLIC_FLAT_RD
91);
92   intf the_intf();
93endmodule : sub
94