1 /* $NetBSD: ta_ras_if.h,v 1.2 2021/12/18 23:44:59 riastradh Exp $ */ 2 3 /* 4 * Copyright 2019 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 */ 25 26 #ifndef _TA_RAS_IF_H 27 #define _TA_RAS_IF_H 28 29 /* Responses have bit 31 set */ 30 #define RSP_ID_MASK (1U << 31) 31 #define RSP_ID(cmdId) (((uint32_t)(cmdId)) | RSP_ID_MASK) 32 33 /* RAS related enumerations */ 34 /**********************************************************/ 35 enum ras_command { 36 TA_RAS_COMMAND__ENABLE_FEATURES = 0, 37 TA_RAS_COMMAND__DISABLE_FEATURES, 38 TA_RAS_COMMAND__TRIGGER_ERROR, 39 }; 40 41 enum ta_ras_status { 42 TA_RAS_STATUS__SUCCESS = 0x00, 43 TA_RAS_STATUS__RESET_NEEDED = 0x01, 44 TA_RAS_STATUS__ERROR_INVALID_PARAMETER = 0x02, 45 TA_RAS_STATUS__ERROR_RAS_NOT_AVAILABLE = 0x03, 46 TA_RAS_STATUS__ERROR_RAS_DUPLICATE_CMD = 0x04, 47 TA_RAS_STATUS__ERROR_INJECTION_FAILED = 0x05, 48 TA_RAS_STATUS__ERROR_ASD_READ_WRITE = 0x06, 49 TA_RAS_STATUS__ERROR_TOGGLE_DF_CSTATE = 0x07, 50 TA_RAS_STATUS__ERROR_TIMEOUT = 0x08, 51 TA_RAS_STATUS__ERROR_BLOCK_DISABLED = 0x09, 52 TA_RAS_STATUS__ERROR_GENERIC = 0x10, 53 }; 54 55 enum ta_ras_block { 56 TA_RAS_BLOCK__UMC = 0, 57 TA_RAS_BLOCK__SDMA, 58 TA_RAS_BLOCK__GFX, 59 TA_RAS_BLOCK__MMHUB, 60 TA_RAS_BLOCK__ATHUB, 61 TA_RAS_BLOCK__PCIE_BIF, 62 TA_RAS_BLOCK__HDP, 63 TA_RAS_BLOCK__XGMI_WAFL, 64 TA_RAS_BLOCK__DF, 65 TA_RAS_BLOCK__SMN, 66 TA_RAS_BLOCK__SEM, 67 TA_RAS_BLOCK__MP0, 68 TA_RAS_BLOCK__MP1, 69 TA_RAS_BLOCK__FUSE, 70 TA_NUM_BLOCK_MAX 71 }; 72 73 enum ta_ras_error_type { 74 TA_RAS_ERROR__NONE = 0, 75 TA_RAS_ERROR__PARITY = 1, 76 TA_RAS_ERROR__SINGLE_CORRECTABLE = 2, 77 TA_RAS_ERROR__MULTI_UNCORRECTABLE = 4, 78 TA_RAS_ERROR__POISON = 8, 79 }; 80 81 /* Input/output structures for RAS commands */ 82 /**********************************************************/ 83 84 struct ta_ras_enable_features_input { 85 enum ta_ras_block block_id; 86 enum ta_ras_error_type error_type; 87 }; 88 89 struct ta_ras_disable_features_input { 90 enum ta_ras_block block_id; 91 enum ta_ras_error_type error_type; 92 }; 93 94 struct ta_ras_trigger_error_input { 95 enum ta_ras_block block_id; // ras-block. i.e. umc, gfx 96 enum ta_ras_error_type inject_error_type; // type of error. i.e. single_correctable 97 uint32_t sub_block_index; // mem block. i.e. hbm, sram etc. 98 uint64_t address; // explicit address of error 99 uint64_t value; // method if error injection. i.e persistent, coherent etc. 100 }; 101 102 /* Common input structure for RAS callbacks */ 103 /**********************************************************/ 104 union ta_ras_cmd_input { 105 struct ta_ras_enable_features_input enable_features; 106 struct ta_ras_disable_features_input disable_features; 107 struct ta_ras_trigger_error_input trigger_error; 108 }; 109 110 /* Shared Memory structures */ 111 /**********************************************************/ 112 struct ta_ras_shared_memory { 113 uint32_t cmd_id; 114 uint32_t resp_id; 115 enum ta_ras_status ras_status; 116 uint32_t reserved; 117 union ta_ras_cmd_input ras_in_message; 118 }; 119 120 #endif // TL_RAS_IF_H_ 121