/dports/lang/angelscript/sdk/angelscript/projects/msvc2017/ |
H A D | angelscript.sln | 4 …11-00A0C91BC942}") = "angelscript", "angelscript.vcxproj", "{39E6AF97-6BA3-4A72-8C61-BCEBF214EBFD}" 14 {39E6AF97-6BA3-4A72-8C61-BCEBF214EBFD}.Debug|Win32.ActiveCfg = Debug|Win32 15 {39E6AF97-6BA3-4A72-8C61-BCEBF214EBFD}.Debug|Win32.Build.0 = Debug|Win32 16 {39E6AF97-6BA3-4A72-8C61-BCEBF214EBFD}.Debug|x64.ActiveCfg = Debug|x64 17 {39E6AF97-6BA3-4A72-8C61-BCEBF214EBFD}.Debug|x64.Build.0 = Debug|x64 18 {39E6AF97-6BA3-4A72-8C61-BCEBF214EBFD}.Release|Win32.ActiveCfg = Release|Win32 19 {39E6AF97-6BA3-4A72-8C61-BCEBF214EBFD}.Release|Win32.Build.0 = Release|Win32 20 {39E6AF97-6BA3-4A72-8C61-BCEBF214EBFD}.Release|x64.ActiveCfg = Release|x64 21 {39E6AF97-6BA3-4A72-8C61-BCEBF214EBFD}.Release|x64.Build.0 = Release|x64
|
/dports/lang/angelscript/sdk/angelscript/projects/msvc2015/ |
H A D | angelscript.sln | 4 …11-00A0C91BC942}") = "angelscript", "angelscript.vcxproj", "{39E6AF97-6BA3-4A72-8C61-BCEBF214EBFD}" 14 {39E6AF97-6BA3-4A72-8C61-BCEBF214EBFD}.Debug|Win32.ActiveCfg = Debug|Win32 15 {39E6AF97-6BA3-4A72-8C61-BCEBF214EBFD}.Debug|Win32.Build.0 = Debug|Win32 16 {39E6AF97-6BA3-4A72-8C61-BCEBF214EBFD}.Debug|x64.ActiveCfg = Debug|x64 17 {39E6AF97-6BA3-4A72-8C61-BCEBF214EBFD}.Debug|x64.Build.0 = Debug|x64 18 {39E6AF97-6BA3-4A72-8C61-BCEBF214EBFD}.Release|Win32.ActiveCfg = Release|Win32 19 {39E6AF97-6BA3-4A72-8C61-BCEBF214EBFD}.Release|Win32.Build.0 = Release|Win32 20 {39E6AF97-6BA3-4A72-8C61-BCEBF214EBFD}.Release|x64.ActiveCfg = Release|x64 21 {39E6AF97-6BA3-4A72-8C61-BCEBF214EBFD}.Release|x64.Build.0 = Release|x64
|
/dports/net/libexosip2/libexosip2-5.3.0/platform/vsnet/ |
H A D | eXosip.sln | 9 Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "libcares", "libcares.vcxproj", "{6BCE0E64-5A72… 43 {6BCE0E64-5A72-4243-B385-88E62C8E398A}.Debug|Win32.ActiveCfg = Debug|Win32 44 {6BCE0E64-5A72-4243-B385-88E62C8E398A}.Debug|Win32.Build.0 = Debug|Win32 45 {6BCE0E64-5A72-4243-B385-88E62C8E398A}.Debug|x64.ActiveCfg = Debug|x64 46 {6BCE0E64-5A72-4243-B385-88E62C8E398A}.Debug|x64.Build.0 = Debug|x64 47 {6BCE0E64-5A72-4243-B385-88E62C8E398A}.Release|Win32.ActiveCfg = Release|Win32 48 {6BCE0E64-5A72-4243-B385-88E62C8E398A}.Release|Win32.Build.0 = Release|Win32 49 {6BCE0E64-5A72-4243-B385-88E62C8E398A}.Release|x64.ActiveCfg = Release|x64 50 {6BCE0E64-5A72-4243-B385-88E62C8E398A}.Release|x64.Build.0 = Release|x64
|
/dports/sysutils/u-boot-olinuxino-lime/u-boot-2021.07/board/ti/j721e/ |
H A D | README | 16 - Dual core 64-bit ARM Cortex-A72 29 | DMSC | MCU R5 | A72 | MAIN R5/C66x/C7x | 74 | | |<--------|---| Start A72 | | | | 87 | | |<--------|-----------------------|---->| *A72 SPL* | | | 117 - Here DMSC acts as master and provides all the critical services. R5/A72 155 4.2. A72: 194 | | A72 ATF | | 197 | | A72 OPTEE | | 200 | | A72 SPL | |
|
/dports/sysutils/u-boot-olinuxino-lime2-emmc/u-boot-2021.07/board/ti/j721e/ |
H A D | README | 16 - Dual core 64-bit ARM Cortex-A72 29 | DMSC | MCU R5 | A72 | MAIN R5/C66x/C7x | 74 | | |<--------|---| Start A72 | | | | 87 | | |<--------|-----------------------|---->| *A72 SPL* | | | 117 - Here DMSC acts as master and provides all the critical services. R5/A72 155 4.2. A72: 194 | | A72 ATF | | 197 | | A72 OPTEE | | 200 | | A72 SPL | |
|
/dports/sysutils/u-boot-olinuxino-lime2/u-boot-2021.07/board/ti/j721e/ |
H A D | README | 16 - Dual core 64-bit ARM Cortex-A72 29 | DMSC | MCU R5 | A72 | MAIN R5/C66x/C7x | 74 | | |<--------|---| Start A72 | | | | 87 | | |<--------|-----------------------|---->| *A72 SPL* | | | 117 - Here DMSC acts as master and provides all the critical services. R5/A72 155 4.2. A72: 194 | | A72 ATF | | 197 | | A72 OPTEE | | 200 | | A72 SPL | |
|
/dports/sysutils/u-boot-wandboard/u-boot-2021.07/board/ti/j721e/ |
H A D | README | 16 - Dual core 64-bit ARM Cortex-A72 29 | DMSC | MCU R5 | A72 | MAIN R5/C66x/C7x | 74 | | |<--------|---| Start A72 | | | | 87 | | |<--------|-----------------------|---->| *A72 SPL* | | | 117 - Here DMSC acts as master and provides all the critical services. R5/A72 155 4.2. A72: 194 | | A72 ATF | | 197 | | A72 OPTEE | | 200 | | A72 SPL | |
|
/dports/sysutils/u-boot-cubox-hummingboard/u-boot-2021.07/board/ti/j721e/ |
H A D | README | 16 - Dual core 64-bit ARM Cortex-A72 29 | DMSC | MCU R5 | A72 | MAIN R5/C66x/C7x | 74 | | |<--------|---| Start A72 | | | | 87 | | |<--------|-----------------------|---->| *A72 SPL* | | | 117 - Here DMSC acts as master and provides all the critical services. R5/A72 155 4.2. A72: 194 | | A72 ATF | | 197 | | A72 OPTEE | | 200 | | A72 SPL | |
|
/dports/sysutils/u-boot-cubieboard2/u-boot-2021.07/board/ti/j721e/ |
H A D | README | 16 - Dual core 64-bit ARM Cortex-A72 29 | DMSC | MCU R5 | A72 | MAIN R5/C66x/C7x | 74 | | |<--------|---| Start A72 | | | | 87 | | |<--------|-----------------------|---->| *A72 SPL* | | | 117 - Here DMSC acts as master and provides all the critical services. R5/A72 155 4.2. A72: 194 | | A72 ATF | | 197 | | A72 OPTEE | | 200 | | A72 SPL | |
|
/dports/sysutils/u-boot-cubieboard/u-boot-2021.07/board/ti/j721e/ |
H A D | README | 16 - Dual core 64-bit ARM Cortex-A72 29 | DMSC | MCU R5 | A72 | MAIN R5/C66x/C7x | 74 | | |<--------|---| Start A72 | | | | 87 | | |<--------|-----------------------|---->| *A72 SPL* | | | 117 - Here DMSC acts as master and provides all the critical services. R5/A72 155 4.2. A72: 194 | | A72 ATF | | 197 | | A72 OPTEE | | 200 | | A72 SPL | |
|
/dports/sysutils/u-boot-firefly-rk3399/u-boot-2021.07/board/ti/j721e/ |
H A D | README | 16 - Dual core 64-bit ARM Cortex-A72 29 | DMSC | MCU R5 | A72 | MAIN R5/C66x/C7x | 74 | | |<--------|---| Start A72 | | | | 87 | | |<--------|-----------------------|---->| *A72 SPL* | | | 117 - Here DMSC acts as master and provides all the critical services. R5/A72 155 4.2. A72: 194 | | A72 ATF | | 197 | | A72 OPTEE | | 200 | | A72 SPL | |
|
/dports/sysutils/u-boot-sinovoip-bpi-m3/u-boot-2021.07/board/ti/j721e/ |
H A D | README | 16 - Dual core 64-bit ARM Cortex-A72 29 | DMSC | MCU R5 | A72 | MAIN R5/C66x/C7x | 74 | | |<--------|---| Start A72 | | | | 87 | | |<--------|-----------------------|---->| *A72 SPL* | | | 117 - Here DMSC acts as master and provides all the critical services. R5/A72 155 4.2. A72: 194 | | A72 ATF | | 197 | | A72 OPTEE | | 200 | | A72 SPL | |
|
/dports/sysutils/u-boot-a13-olinuxino/u-boot-2021.07/board/ti/j721e/ |
H A D | README | 16 - Dual core 64-bit ARM Cortex-A72 29 | DMSC | MCU R5 | A72 | MAIN R5/C66x/C7x | 74 | | |<--------|---| Start A72 | | | | 87 | | |<--------|-----------------------|---->| *A72 SPL* | | | 117 - Here DMSC acts as master and provides all the critical services. R5/A72 155 4.2. A72: 194 | | A72 ATF | | 197 | | A72 OPTEE | | 200 | | A72 SPL | |
|
/dports/sysutils/u-boot-a64-olinuxino/u-boot-2021.07/board/ti/j721e/ |
H A D | README | 16 - Dual core 64-bit ARM Cortex-A72 29 | DMSC | MCU R5 | A72 | MAIN R5/C66x/C7x | 74 | | |<--------|---| Start A72 | | | | 87 | | |<--------|-----------------------|---->| *A72 SPL* | | | 117 - Here DMSC acts as master and provides all the critical services. R5/A72 155 4.2. A72: 194 | | A72 ATF | | 197 | | A72 OPTEE | | 200 | | A72 SPL | |
|
/dports/sysutils/u-boot-sopine/u-boot-2021.07/board/ti/j721e/ |
H A D | README | 16 - Dual core 64-bit ARM Cortex-A72 29 | DMSC | MCU R5 | A72 | MAIN R5/C66x/C7x | 74 | | |<--------|---| Start A72 | | | | 87 | | |<--------|-----------------------|---->| *A72 SPL* | | | 117 - Here DMSC acts as master and provides all the critical services. R5/A72 155 4.2. A72: 194 | | A72 ATF | | 197 | | A72 OPTEE | | 200 | | A72 SPL | |
|
/dports/sysutils/u-boot-qemu-arm64/u-boot-2021.07/board/ti/j721e/ |
H A D | README | 16 - Dual core 64-bit ARM Cortex-A72 29 | DMSC | MCU R5 | A72 | MAIN R5/C66x/C7x | 74 | | |<--------|---| Start A72 | | | | 87 | | |<--------|-----------------------|---->| *A72 SPL* | | | 117 - Here DMSC acts as master and provides all the critical services. R5/A72 155 4.2. A72: 194 | | A72 ATF | | 197 | | A72 OPTEE | | 200 | | A72 SPL | |
|
/dports/sysutils/u-boot-rpi-0-w/u-boot-2021.07/board/ti/j721e/ |
H A D | README | 16 - Dual core 64-bit ARM Cortex-A72 29 | DMSC | MCU R5 | A72 | MAIN R5/C66x/C7x | 74 | | |<--------|---| Start A72 | | | | 87 | | |<--------|-----------------------|---->| *A72 SPL* | | | 117 - Here DMSC acts as master and provides all the critical services. R5/A72 155 4.2. A72: 194 | | A72 ATF | | 197 | | A72 OPTEE | | 200 | | A72 SPL | |
|
/dports/sysutils/u-boot-nanopi-r4s/u-boot-2021.07/board/ti/j721e/ |
H A D | README | 16 - Dual core 64-bit ARM Cortex-A72 29 | DMSC | MCU R5 | A72 | MAIN R5/C66x/C7x | 74 | | |<--------|---| Start A72 | | | | 87 | | |<--------|-----------------------|---->| *A72 SPL* | | | 117 - Here DMSC acts as master and provides all the critical services. R5/A72 155 4.2. A72: 194 | | A72 ATF | | 197 | | A72 OPTEE | | 200 | | A72 SPL | |
|
/dports/sysutils/u-boot-olimex-a20-som-evb/u-boot-2021.07/board/ti/j721e/ |
H A D | README | 16 - Dual core 64-bit ARM Cortex-A72 29 | DMSC | MCU R5 | A72 | MAIN R5/C66x/C7x | 74 | | |<--------|---| Start A72 | | | | 87 | | |<--------|-----------------------|---->| *A72 SPL* | | | 117 - Here DMSC acts as master and provides all the critical services. R5/A72 155 4.2. A72: 194 | | A72 ATF | | 197 | | A72 OPTEE | | 200 | | A72 SPL | |
|
/dports/sysutils/u-boot-nanopi-m1plus/u-boot-2021.07/board/ti/j721e/ |
H A D | README | 16 - Dual core 64-bit ARM Cortex-A72 29 | DMSC | MCU R5 | A72 | MAIN R5/C66x/C7x | 74 | | |<--------|---| Start A72 | | | | 87 | | |<--------|-----------------------|---->| *A72 SPL* | | | 117 - Here DMSC acts as master and provides all the critical services. R5/A72 155 4.2. A72: 194 | | A72 ATF | | 197 | | A72 OPTEE | | 200 | | A72 SPL | |
|
/dports/sysutils/u-boot-nanopi-neo/u-boot-2021.07/board/ti/j721e/ |
H A D | README | 16 - Dual core 64-bit ARM Cortex-A72 29 | DMSC | MCU R5 | A72 | MAIN R5/C66x/C7x | 74 | | |<--------|---| Start A72 | | | | 87 | | |<--------|-----------------------|---->| *A72 SPL* | | | 117 - Here DMSC acts as master and provides all the critical services. R5/A72 155 4.2. A72: 194 | | A72 ATF | | 197 | | A72 OPTEE | | 200 | | A72 SPL | |
|
/dports/sysutils/u-boot-nanopi-neo-air/u-boot-2021.07/board/ti/j721e/ |
H A D | README | 16 - Dual core 64-bit ARM Cortex-A72 29 | DMSC | MCU R5 | A72 | MAIN R5/C66x/C7x | 74 | | |<--------|---| Start A72 | | | | 87 | | |<--------|-----------------------|---->| *A72 SPL* | | | 117 - Here DMSC acts as master and provides all the critical services. R5/A72 155 4.2. A72: 194 | | A72 ATF | | 197 | | A72 OPTEE | | 200 | | A72 SPL | |
|
/dports/sysutils/u-boot-chip/u-boot-2021.07/board/ti/j721e/ |
H A D | README | 16 - Dual core 64-bit ARM Cortex-A72 29 | DMSC | MCU R5 | A72 | MAIN R5/C66x/C7x | 74 | | |<--------|---| Start A72 | | | | 87 | | |<--------|-----------------------|---->| *A72 SPL* | | | 117 - Here DMSC acts as master and provides all the critical services. R5/A72 155 4.2. A72: 194 | | A72 ATF | | 197 | | A72 OPTEE | | 200 | | A72 SPL | |
|
/dports/sysutils/u-boot-clearfog/u-boot-2021.07/board/ti/j721e/ |
H A D | README | 16 - Dual core 64-bit ARM Cortex-A72 29 | DMSC | MCU R5 | A72 | MAIN R5/C66x/C7x | 74 | | |<--------|---| Start A72 | | | | 87 | | |<--------|-----------------------|---->| *A72 SPL* | | | 117 - Here DMSC acts as master and provides all the critical services. R5/A72 155 4.2. A72: 194 | | A72 ATF | | 197 | | A72 OPTEE | | 200 | | A72 SPL | |
|
/dports/sysutils/u-boot-orangepi-zero/u-boot-2021.07/board/ti/j721e/ |
H A D | README | 16 - Dual core 64-bit ARM Cortex-A72 29 | DMSC | MCU R5 | A72 | MAIN R5/C66x/C7x | 74 | | |<--------|---| Start A72 | | | | 87 | | |<--------|-----------------------|---->| *A72 SPL* | | | 117 - Here DMSC acts as master and provides all the critical services. R5/A72 155 4.2. A72: 194 | | A72 ATF | | 197 | | A72 OPTEE | | 200 | | A72 SPL | |
|