1 /* 2 * The authors hereby grant permission to use, copy, modify, distribute, 3 * and license this software and its documentation for any purpose, provided 4 * that existing copyright notices are retained in all copies and that this 5 * notice is included verbatim in any distributions. No written agreement, 6 * license, or royalty fee is required for any of the authorized uses. 7 * Modifications to this software may be copyrighted by their authors 8 * and need not follow the licensing terms described here, provided that 9 * the new terms are clearly indicated on the first page of each file where 10 * they apply. 11 */ 12 13 /* 14 ** defBF50x_base.h 15 ** 16 ** This include file contains a list of macro "defines" to enable the programmer 17 ** to use symbolic names for the system MMRs common to the ADSP-BF50x parts 18 ** peripherals. 19 ** 20 ** Copyright (C) 2009 Analog Devices Inc., All Rights Reserved. 21 */ 22 23 #ifndef _DEF_BF50X_H 24 #define _DEF_BF50X_H 25 26 #ifdef _MISRA_RULES 27 #pragma diag(push) 28 #pragma diag(suppress:misra_rule_19_7:"ADI header allows function macros.") 29 #endif /* _MISRA_RULES */ 30 31 32 /* ************************************************************************************************************** */ 33 /* SYSTEM & MMR ADDRESS DEFINITIONS COMMON TO ALL ADSP-BF50x */ 34 /* ************************************************************************************************************** */ 35 36 /* Clock and System Control (0xFFC00000 - 0xFFC000FF) */ 37 #define PLL_CTL 0xFFC00000 /* PLL Control Register */ 38 #define PLL_DIV 0xFFC00004 /* PLL Divide Register */ 39 #define VR_CTL 0xFFC00008 /* Voltage Regulator Control Register */ 40 #define PLL_STAT 0xFFC0000C /* PLL Status Register */ 41 #define PLL_LOCKCNT 0xFFC00010 /* PLL Lock Count Register */ 42 #define CHIPID 0xFFC00014 /* Device ID Register */ 43 44 45 /* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */ 46 #define SWRST 0xFFC00100 /* Software Reset Register */ 47 #define SYSCR 0xFFC00104 /* System Configuration Register */ 48 49 #define SIC_IMASK0 0xFFC0010C /* Interrupt Mask Register */ 50 /* legacy register name (below) provided for backwards code compatibility */ 51 #define SIC_IMASK (SIC_IMASK0) 52 #define SIC_IAR0 0xFFC00110 /* Interrupt Assignment Register 0 */ 53 #define SIC_IAR1 0xFFC00114 /* Interrupt Assignment Register 1 */ 54 #define SIC_IAR2 0xFFC00118 /* Interrupt Assignment Register 2 */ 55 #define SIC_IAR3 0xFFC0011C /* Interrupt Assignment Register 3 */ 56 #define SIC_ISR0 0xFFC00120 /* Interrupt Status Register */ 57 /* legacy register name (below) provided for backwards code compatibility */ 58 #define SIC_ISR (SIC_ISR0) 59 #define SIC_IWR0 0xFFC00124 /* Interrupt Wakeup Register */ 60 /* legacy register name (below) provided for backwards code compatibility */ 61 #define SIC_IWR (SIC_IWR0) 62 63 /* SIC Additions to ADSP-BF50x (0xFFC0014C - 0xFFC00162) */ 64 #define SIC_IMASK1 0xFFC0014C /* Interrupt Mask register of SIC2 */ 65 #define SIC_IAR4 0xFFC00150 /* Interrupt Assignment register4 */ 66 #define SIC_IAR5 0xFFC00154 /* Interrupt Assignment register5 */ 67 #define SIC_IAR6 0xFFC00158 /* Interrupt Assignment register6 */ 68 #define SIC_ISR1 0xFFC00160 /* Interrupt Statur register */ 69 #define SIC_IWR1 0xFFC00164 /* Interrupt Wakeup register */ 70 71 72 /* Watchdog Timer (0xFFC00200 - 0xFFC002FF) */ 73 #define WDOG_CTL 0xFFC00200 /* Watchdog Control Register */ 74 #define WDOG_CNT 0xFFC00204 /* Watchdog Count Register */ 75 #define WDOG_STAT 0xFFC00208 /* Watchdog Status Register */ 76 77 78 /* UART0 Controller (0xFFC00400 - 0xFFC004FF) */ 79 #define UART0_DLL 0xffc00400 /* Divisor Latch Low Byte */ 80 #define UART0_DLH 0xffc00404 /* Divisor Latch High Byte */ 81 #define UART0_GCTL 0xffc00408 /* Global Control Register */ 82 #define UART0_LCR 0xffc0040c /* Line Control Register */ 83 #define UART0_MCR 0xffc00410 /* Modem Control Register */ 84 #define UART0_LSR 0xffc00414 /* Line Status Register */ 85 #define UART0_MSR 0xffc00418 /* Modem Status Register */ 86 #define UART0_SCR 0xffc0041c /* Scratch Register */ 87 #define UART0_IER_SET 0xffc00420 /* Interrupt Enable Register Set */ 88 #define UART0_IER_CLEAR 0xffc00424 /* Interrupt Enable Register Clear */ 89 #define UART0_THR 0xffc00428 /* Transmit Hold Register */ 90 #define UART0_RBR 0xffc0042c /* Receive Buffer Register */ 91 92 /* SPI0 Controller (0xFFC00500 - 0xFFC005FF) */ 93 #define SPI0_CTL 0xFFC00500 /* SPI Control Register */ 94 /* legacy register name (below) provided for backwards code compatibility */ 95 #define SPI_CTL (SPI0_CTL) 96 #define SPI0_FLG 0xFFC00504 /* SPI Flag register */ 97 /* legacy register name (below) provided for backwards code compatibility */ 98 #define SPI_FLG (SPI0_FLG) 99 #define SPI0_STAT 0xFFC00508 /* SPI Status register */ 100 /* legacy register name (below) provided for backwards code compatibility */ 101 #define SPI_STAT (SPI0_STAT) 102 #define SPI0_TDBR 0xFFC0050C /* SPI Transmit Data Buffer Register */ 103 /* legacy register name (below) provided for backwards code compatibility */ 104 #define SPI_TDBR (SPI0_TDBR) 105 #define SPI0_RDBR 0xFFC00510 /* SPI Receive Data Buffer Register */ 106 /* legacy register name (below) provided for backwards code compatibility */ 107 #define SPI_RDBR (SPI0_RDBR) 108 #define SPI0_BAUD 0xFFC00514 /* SPI Baud rate Register */ 109 /* legacy register name (below) provided for backwards code compatibility */ 110 #define SPI_BAUD (SPI0_BAUD) 111 #define SPI0_SHADOW 0xFFC00518 /* SPI_RDBR Shadow Register */ 112 /* legacy register name (below) provided for backwards code compatibility */ 113 #define SPI_SHADOW (SPI0_SHADOW) 114 115 116 /* TIMER0-7 Registers (0xFFC00600 - 0xFFC006FF) */ 117 #define TIMER0_CONFIG 0xFFC00600 /* Timer 0 Configuration Register */ 118 #define TIMER0_COUNTER 0xFFC00604 /* Timer 0 Counter Register */ 119 #define TIMER0_PERIOD 0xFFC00608 /* Timer 0 Period Register */ 120 #define TIMER0_WIDTH 0xFFC0060C /* Timer 0 Width Register */ 121 122 #define TIMER1_CONFIG 0xFFC00610 /* Timer 1 Configuration Register */ 123 #define TIMER1_COUNTER 0xFFC00614 /* Timer 1 Counter Register */ 124 #define TIMER1_PERIOD 0xFFC00618 /* Timer 1 Period Register */ 125 #define TIMER1_WIDTH 0xFFC0061C /* Timer 1 Width Register */ 126 127 #define TIMER2_CONFIG 0xFFC00620 /* Timer 2 Configuration Register */ 128 #define TIMER2_COUNTER 0xFFC00624 /* Timer 2 Counter Register */ 129 #define TIMER2_PERIOD 0xFFC00628 /* Timer 2 Period Register */ 130 #define TIMER2_WIDTH 0xFFC0062C /* Timer 2 Width Register */ 131 132 #define TIMER3_CONFIG 0xFFC00630 /* Timer 3 Configuration Register */ 133 #define TIMER3_COUNTER 0xFFC00634 /* Timer 3 Counter Register */ 134 #define TIMER3_PERIOD 0xFFC00638 /* Timer 3 Period Register */ 135 #define TIMER3_WIDTH 0xFFC0063C /* Timer 3 Width Register */ 136 137 #define TIMER4_CONFIG 0xFFC00640 /* Timer 4 Configuration Register */ 138 #define TIMER4_COUNTER 0xFFC00644 /* Timer 4 Counter Register */ 139 #define TIMER4_PERIOD 0xFFC00648 /* Timer 4 Period Register */ 140 #define TIMER4_WIDTH 0xFFC0064C /* Timer 4 Width Register */ 141 142 #define TIMER5_CONFIG 0xFFC00650 /* Timer 5 Configuration Register */ 143 #define TIMER5_COUNTER 0xFFC00654 /* Timer 5 Counter Register */ 144 #define TIMER5_PERIOD 0xFFC00658 /* Timer 5 Period Register */ 145 #define TIMER5_WIDTH 0xFFC0065C /* Timer 5 Width Register */ 146 147 #define TIMER6_CONFIG 0xFFC00660 /* Timer 6 Configuration Register */ 148 #define TIMER6_COUNTER 0xFFC00664 /* Timer 6 Counter Register */ 149 #define TIMER6_PERIOD 0xFFC00668 /* Timer 6 Period Register */ 150 #define TIMER6_WIDTH 0xFFC0066C /* Timer 6 Width Register */ 151 152 #define TIMER7_CONFIG 0xFFC00670 /* Timer 7 Configuration Register */ 153 #define TIMER7_COUNTER 0xFFC00674 /* Timer 7 Counter Register */ 154 #define TIMER7_PERIOD 0xFFC00678 /* Timer 7 Period Register */ 155 #define TIMER7_WIDTH 0xFFC0067C /* Timer 7 Width Register */ 156 157 #define TIMER_ENABLE 0xFFC00680 /* Timer Enable Register */ 158 #define TIMER_DISABLE 0xFFC00684 /* Timer Disable Register */ 159 #define TIMER_STATUS 0xFFC00688 /* Timer Status Register */ 160 161 162 /* General Purpose I/O Port F (0xFFC00700 - 0xFFC007FF) */ 163 #define PORTFIO 0xFFC00700 /* Port F I/O Pin State Specify Register */ 164 #define PORTFIO_CLEAR 0xFFC00704 /* Port F I/O Peripheral Interrupt Clear Register */ 165 #define PORTFIO_SET 0xFFC00708 /* Port F I/O Peripheral Interrupt Set Register */ 166 #define PORTFIO_TOGGLE 0xFFC0070C /* Port F I/O Pin State Toggle Register */ 167 #define PORTFIO_MASKA 0xFFC00710 /* Port F I/O Mask State Specify Interrupt A Register */ 168 #define PORTFIO_MASKA_CLEAR 0xFFC00714 /* Port F I/O Mask Disable Interrupt A Register */ 169 #define PORTFIO_MASKA_SET 0xFFC00718 /* Port F I/O Mask Enable Interrupt A Register */ 170 #define PORTFIO_MASKA_TOGGLE 0xFFC0071C /* Port F I/O Mask Toggle Enable Interrupt A Register */ 171 #define PORTFIO_MASKB 0xFFC00720 /* Port F I/O Mask State Specify Interrupt B Register */ 172 #define PORTFIO_MASKB_CLEAR 0xFFC00724 /* Port F I/O Mask Disable Interrupt B Register */ 173 #define PORTFIO_MASKB_SET 0xFFC00728 /* Port F I/O Mask Enable Interrupt B Register */ 174 #define PORTFIO_MASKB_TOGGLE 0xFFC0072C /* Port F I/O Mask Toggle Enable Interrupt B Register */ 175 #define PORTFIO_DIR 0xFFC00730 /* Port F I/O Direction Register */ 176 #define PORTFIO_POLAR 0xFFC00734 /* Port F I/O Source Polarity Register */ 177 #define PORTFIO_EDGE 0xFFC00738 /* Port F I/O Source Sensitivity Register */ 178 #define PORTFIO_BOTH 0xFFC0073C /* Port F I/O Set on BOTH Edges Register */ 179 #define PORTFIO_INEN 0xFFC00740 /* Port F I/O Input Enable Register */ 180 181 182 /* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */ 183 #define SPORT0_TCR1 0xFFC00800 /* SPORT0 Transmit Configuration 1 Register */ 184 #define SPORT0_TCR2 0xFFC00804 /* SPORT0 Transmit Configuration 2 Register */ 185 #define SPORT0_TCLKDIV 0xFFC00808 /* SPORT0 Transmit Clock Divider */ 186 #define SPORT0_TFSDIV 0xFFC0080C /* SPORT0 Transmit Frame Sync Divider */ 187 #define SPORT0_TX 0xFFC00810 /* SPORT0 TX Data Register */ 188 #define SPORT0_RX 0xFFC00818 /* SPORT0 RX Data Register */ 189 #define SPORT0_RCR1 0xFFC00820 /* SPORT0 Transmit Configuration 1 Register */ 190 #define SPORT0_RCR2 0xFFC00824 /* SPORT0 Transmit Configuration 2 Register */ 191 #define SPORT0_RCLKDIV 0xFFC00828 /* SPORT0 Receive Clock Divider */ 192 #define SPORT0_RFSDIV 0xFFC0082C /* SPORT0 Receive Frame Sync Divider */ 193 #define SPORT0_STAT 0xFFC00830 /* SPORT0 Status Register */ 194 #define SPORT0_CHNL 0xFFC00834 /* SPORT0 Current Channel Register */ 195 #define SPORT0_MCMC1 0xFFC00838 /* SPORT0 Multi-Channel Configuration Register 1 */ 196 #define SPORT0_MCMC2 0xFFC0083C /* SPORT0 Multi-Channel Configuration Register 2 */ 197 #define SPORT0_MTCS0 0xFFC00840 /* SPORT0 Multi-Channel Transmit Select Register 0 */ 198 #define SPORT0_MTCS1 0xFFC00844 /* SPORT0 Multi-Channel Transmit Select Register 1 */ 199 #define SPORT0_MTCS2 0xFFC00848 /* SPORT0 Multi-Channel Transmit Select Register 2 */ 200 #define SPORT0_MTCS3 0xFFC0084C /* SPORT0 Multi-Channel Transmit Select Register 3 */ 201 #define SPORT0_MRCS0 0xFFC00850 /* SPORT0 Multi-Channel Receive Select Register 0 */ 202 #define SPORT0_MRCS1 0xFFC00854 /* SPORT0 Multi-Channel Receive Select Register 1 */ 203 #define SPORT0_MRCS2 0xFFC00858 /* SPORT0 Multi-Channel Receive Select Register 2 */ 204 #define SPORT0_MRCS3 0xFFC0085C /* SPORT0 Multi-Channel Receive Select Register 3 */ 205 206 207 /* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */ 208 #define SPORT1_TCR1 0xFFC00900 /* SPORT1 Transmit Configuration 1 Register */ 209 #define SPORT1_TCR2 0xFFC00904 /* SPORT1 Transmit Configuration 2 Register */ 210 #define SPORT1_TCLKDIV 0xFFC00908 /* SPORT1 Transmit Clock Divider */ 211 #define SPORT1_TFSDIV 0xFFC0090C /* SPORT1 Transmit Frame Sync Divider */ 212 #define SPORT1_TX 0xFFC00910 /* SPORT1 TX Data Register */ 213 #define SPORT1_RX 0xFFC00918 /* SPORT1 RX Data Register */ 214 #define SPORT1_RCR1 0xFFC00920 /* SPORT1 Transmit Configuration 1 Register */ 215 #define SPORT1_RCR2 0xFFC00924 /* SPORT1 Transmit Configuration 2 Register */ 216 #define SPORT1_RCLKDIV 0xFFC00928 /* SPORT1 Receive Clock Divider */ 217 #define SPORT1_RFSDIV 0xFFC0092C /* SPORT1 Receive Frame Sync Divider */ 218 #define SPORT1_STAT 0xFFC00930 /* SPORT1 Status Register */ 219 #define SPORT1_CHNL 0xFFC00934 /* SPORT1 Current Channel Register */ 220 #define SPORT1_MCMC1 0xFFC00938 /* SPORT1 Multi-Channel Configuration Register 1 */ 221 #define SPORT1_MCMC2 0xFFC0093C /* SPORT1 Multi-Channel Configuration Register 2 */ 222 #define SPORT1_MTCS0 0xFFC00940 /* SPORT1 Multi-Channel Transmit Select Register 0 */ 223 #define SPORT1_MTCS1 0xFFC00944 /* SPORT1 Multi-Channel Transmit Select Register 1 */ 224 #define SPORT1_MTCS2 0xFFC00948 /* SPORT1 Multi-Channel Transmit Select Register 2 */ 225 #define SPORT1_MTCS3 0xFFC0094C /* SPORT1 Multi-Channel Transmit Select Register 3 */ 226 #define SPORT1_MRCS0 0xFFC00950 /* SPORT1 Multi-Channel Receive Select Register 0 */ 227 #define SPORT1_MRCS1 0xFFC00954 /* SPORT1 Multi-Channel Receive Select Register 1 */ 228 #define SPORT1_MRCS2 0xFFC00958 /* SPORT1 Multi-Channel Receive Select Register 2 */ 229 #define SPORT1_MRCS3 0xFFC0095C /* SPORT1 Multi-Channel Receive Select Register 3 */ 230 231 232 /* External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */ 233 #define EBIU_AMGCTL 0xFFC00A00 /* Asynchronous Memory Global Control Register */ 234 #define EBIU_AMBCTL 0xFFC00A04 /* Asynchronous Memory Bank Control Register */ 235 #define EBIU_MODE 0xFFC00A20 /* Asynchronous Memory Mode Control Register */ 236 #define EBIU_FCTL 0xFFC00A24 /* Asynchronous Memory Parameter Control Register */ 237 238 #define EBIU_AMBCTL0 (EBIU_AMBCTL)/* Asynchronous Memory Bank Control Register */ 239 240 /* DMA Traffic Control Registers (0xFFC00B00 - 0xFFC00BFF) */ 241 #define DMA_TC_PER 0xFFC00B0C /* Traffic Control Periods Register */ 242 #define DMA_TC_CNT 0xFFC00B10 /* Traffic Control Current Counts Register */ 243 244 /* Alternate deprecated register names (below) provided for backwards code compatibility */ 245 #define DMA_TCPER 0xFFC00B0C /* Traffic Control Periods Register */ 246 #define DMA_TCCNT 0xFFC00B10 /* Traffic Control Current Counts Register */ 247 248 /* DMA Controller (0xFFC00C00 - 0xFFC00FFF) */ 249 #define DMA0_NEXT_DESC_PTR 0xFFC00C00 /* DMA Channel 0 Next Descriptor Pointer Register */ 250 #define DMA0_START_ADDR 0xFFC00C04 /* DMA Channel 0 Start Address Register */ 251 #define DMA0_CONFIG 0xFFC00C08 /* DMA Channel 0 Configuration Register */ 252 #define DMA0_X_COUNT 0xFFC00C10 /* DMA Channel 0 X Count Register */ 253 #define DMA0_X_MODIFY 0xFFC00C14 /* DMA Channel 0 X Modify Register */ 254 #define DMA0_Y_COUNT 0xFFC00C18 /* DMA Channel 0 Y Count Register */ 255 #define DMA0_Y_MODIFY 0xFFC00C1C /* DMA Channel 0 Y Modify Register */ 256 #define DMA0_CURR_DESC_PTR 0xFFC00C20 /* DMA Channel 0 Current Descriptor Pointer Register */ 257 #define DMA0_CURR_ADDR 0xFFC00C24 /* DMA Channel 0 Current Address Register */ 258 #define DMA0_IRQ_STATUS 0xFFC00C28 /* DMA Channel 0 Interrupt/Status Register */ 259 #define DMA0_PERIPHERAL_MAP 0xFFC00C2C /* DMA Channel 0 Peripheral Map Register */ 260 #define DMA0_CURR_X_COUNT 0xFFC00C30 /* DMA Channel 0 Current X Count Register */ 261 #define DMA0_CURR_Y_COUNT 0xFFC00C38 /* DMA Channel 0 Current Y Count Register */ 262 263 #define DMA1_NEXT_DESC_PTR 0xFFC00C40 /* DMA Channel 1 Next Descriptor Pointer Register */ 264 #define DMA1_START_ADDR 0xFFC00C44 /* DMA Channel 1 Start Address Register */ 265 #define DMA1_CONFIG 0xFFC00C48 /* DMA Channel 1 Configuration Register */ 266 #define DMA1_X_COUNT 0xFFC00C50 /* DMA Channel 1 X Count Register */ 267 #define DMA1_X_MODIFY 0xFFC00C54 /* DMA Channel 1 X Modify Register */ 268 #define DMA1_Y_COUNT 0xFFC00C58 /* DMA Channel 1 Y Count Register */ 269 #define DMA1_Y_MODIFY 0xFFC00C5C /* DMA Channel 1 Y Modify Register */ 270 #define DMA1_CURR_DESC_PTR 0xFFC00C60 /* DMA Channel 1 Current Descriptor Pointer Register */ 271 #define DMA1_CURR_ADDR 0xFFC00C64 /* DMA Channel 1 Current Address Register */ 272 #define DMA1_IRQ_STATUS 0xFFC00C68 /* DMA Channel 1 Interrupt/Status Register */ 273 #define DMA1_PERIPHERAL_MAP 0xFFC00C6C /* DMA Channel 1 Peripheral Map Register */ 274 #define DMA1_CURR_X_COUNT 0xFFC00C70 /* DMA Channel 1 Current X Count Register */ 275 #define DMA1_CURR_Y_COUNT 0xFFC00C78 /* DMA Channel 1 Current Y Count Register */ 276 277 #define DMA2_NEXT_DESC_PTR 0xFFC00C80 /* DMA Channel 2 Next Descriptor Pointer Register */ 278 #define DMA2_START_ADDR 0xFFC00C84 /* DMA Channel 2 Start Address Register */ 279 #define DMA2_CONFIG 0xFFC00C88 /* DMA Channel 2 Configuration Register */ 280 #define DMA2_X_COUNT 0xFFC00C90 /* DMA Channel 2 X Count Register */ 281 #define DMA2_X_MODIFY 0xFFC00C94 /* DMA Channel 2 X Modify Register */ 282 #define DMA2_Y_COUNT 0xFFC00C98 /* DMA Channel 2 Y Count Register */ 283 #define DMA2_Y_MODIFY 0xFFC00C9C /* DMA Channel 2 Y Modify Register */ 284 #define DMA2_CURR_DESC_PTR 0xFFC00CA0 /* DMA Channel 2 Current Descriptor Pointer Register */ 285 #define DMA2_CURR_ADDR 0xFFC00CA4 /* DMA Channel 2 Current Address Register */ 286 #define DMA2_IRQ_STATUS 0xFFC00CA8 /* DMA Channel 2 Interrupt/Status Register */ 287 #define DMA2_PERIPHERAL_MAP 0xFFC00CAC /* DMA Channel 2 Peripheral Map Register */ 288 #define DMA2_CURR_X_COUNT 0xFFC00CB0 /* DMA Channel 2 Current X Count Register */ 289 #define DMA2_CURR_Y_COUNT 0xFFC00CB8 /* DMA Channel 2 Current Y Count Register */ 290 291 #define DMA3_NEXT_DESC_PTR 0xFFC00CC0 /* DMA Channel 3 Next Descriptor Pointer Register */ 292 #define DMA3_START_ADDR 0xFFC00CC4 /* DMA Channel 3 Start Address Register */ 293 #define DMA3_CONFIG 0xFFC00CC8 /* DMA Channel 3 Configuration Register */ 294 #define DMA3_X_COUNT 0xFFC00CD0 /* DMA Channel 3 X Count Register */ 295 #define DMA3_X_MODIFY 0xFFC00CD4 /* DMA Channel 3 X Modify Register */ 296 #define DMA3_Y_COUNT 0xFFC00CD8 /* DMA Channel 3 Y Count Register */ 297 #define DMA3_Y_MODIFY 0xFFC00CDC /* DMA Channel 3 Y Modify Register */ 298 #define DMA3_CURR_DESC_PTR 0xFFC00CE0 /* DMA Channel 3 Current Descriptor Pointer Register */ 299 #define DMA3_CURR_ADDR 0xFFC00CE4 /* DMA Channel 3 Current Address Register */ 300 #define DMA3_IRQ_STATUS 0xFFC00CE8 /* DMA Channel 3 Interrupt/Status Register */ 301 #define DMA3_PERIPHERAL_MAP 0xFFC00CEC /* DMA Channel 3 Peripheral Map Register */ 302 #define DMA3_CURR_X_COUNT 0xFFC00CF0 /* DMA Channel 3 Current X Count Register */ 303 #define DMA3_CURR_Y_COUNT 0xFFC00CF8 /* DMA Channel 3 Current Y Count Register */ 304 305 #define DMA4_NEXT_DESC_PTR 0xFFC00D00 /* DMA Channel 4 Next Descriptor Pointer Register */ 306 #define DMA4_START_ADDR 0xFFC00D04 /* DMA Channel 4 Start Address Register */ 307 #define DMA4_CONFIG 0xFFC00D08 /* DMA Channel 4 Configuration Register */ 308 #define DMA4_X_COUNT 0xFFC00D10 /* DMA Channel 4 X Count Register */ 309 #define DMA4_X_MODIFY 0xFFC00D14 /* DMA Channel 4 X Modify Register */ 310 #define DMA4_Y_COUNT 0xFFC00D18 /* DMA Channel 4 Y Count Register */ 311 #define DMA4_Y_MODIFY 0xFFC00D1C /* DMA Channel 4 Y Modify Register */ 312 #define DMA4_CURR_DESC_PTR 0xFFC00D20 /* DMA Channel 4 Current Descriptor Pointer Register */ 313 #define DMA4_CURR_ADDR 0xFFC00D24 /* DMA Channel 4 Current Address Register */ 314 #define DMA4_IRQ_STATUS 0xFFC00D28 /* DMA Channel 4 Interrupt/Status Register */ 315 #define DMA4_PERIPHERAL_MAP 0xFFC00D2C /* DMA Channel 4 Peripheral Map Register */ 316 #define DMA4_CURR_X_COUNT 0xFFC00D30 /* DMA Channel 4 Current X Count Register */ 317 #define DMA4_CURR_Y_COUNT 0xFFC00D38 /* DMA Channel 4 Current Y Count Register */ 318 319 #define DMA5_NEXT_DESC_PTR 0xFFC00D40 /* DMA Channel 5 Next Descriptor Pointer Register */ 320 #define DMA5_START_ADDR 0xFFC00D44 /* DMA Channel 5 Start Address Register */ 321 #define DMA5_CONFIG 0xFFC00D48 /* DMA Channel 5 Configuration Register */ 322 #define DMA5_X_COUNT 0xFFC00D50 /* DMA Channel 5 X Count Register */ 323 #define DMA5_X_MODIFY 0xFFC00D54 /* DMA Channel 5 X Modify Register */ 324 #define DMA5_Y_COUNT 0xFFC00D58 /* DMA Channel 5 Y Count Register */ 325 #define DMA5_Y_MODIFY 0xFFC00D5C /* DMA Channel 5 Y Modify Register */ 326 #define DMA5_CURR_DESC_PTR 0xFFC00D60 /* DMA Channel 5 Current Descriptor Pointer Register */ 327 #define DMA5_CURR_ADDR 0xFFC00D64 /* DMA Channel 5 Current Address Register */ 328 #define DMA5_IRQ_STATUS 0xFFC00D68 /* DMA Channel 5 Interrupt/Status Register */ 329 #define DMA5_PERIPHERAL_MAP 0xFFC00D6C /* DMA Channel 5 Peripheral Map Register */ 330 #define DMA5_CURR_X_COUNT 0xFFC00D70 /* DMA Channel 5 Current X Count Register */ 331 #define DMA5_CURR_Y_COUNT 0xFFC00D78 /* DMA Channel 5 Current Y Count Register */ 332 333 #define DMA6_NEXT_DESC_PTR 0xFFC00D80 /* DMA Channel 6 Next Descriptor Pointer Register */ 334 #define DMA6_START_ADDR 0xFFC00D84 /* DMA Channel 6 Start Address Register */ 335 #define DMA6_CONFIG 0xFFC00D88 /* DMA Channel 6 Configuration Register */ 336 #define DMA6_X_COUNT 0xFFC00D90 /* DMA Channel 6 X Count Register */ 337 #define DMA6_X_MODIFY 0xFFC00D94 /* DMA Channel 6 X Modify Register */ 338 #define DMA6_Y_COUNT 0xFFC00D98 /* DMA Channel 6 Y Count Register */ 339 #define DMA6_Y_MODIFY 0xFFC00D9C /* DMA Channel 6 Y Modify Register */ 340 #define DMA6_CURR_DESC_PTR 0xFFC00DA0 /* DMA Channel 6 Current Descriptor Pointer Register */ 341 #define DMA6_CURR_ADDR 0xFFC00DA4 /* DMA Channel 6 Current Address Register */ 342 #define DMA6_IRQ_STATUS 0xFFC00DA8 /* DMA Channel 6 Interrupt/Status Register */ 343 #define DMA6_PERIPHERAL_MAP 0xFFC00DAC /* DMA Channel 6 Peripheral Map Register */ 344 #define DMA6_CURR_X_COUNT 0xFFC00DB0 /* DMA Channel 6 Current X Count Register */ 345 #define DMA6_CURR_Y_COUNT 0xFFC00DB8 /* DMA Channel 6 Current Y Count Register */ 346 347 #define DMA7_NEXT_DESC_PTR 0xFFC00DC0 /* DMA Channel 7 Next Descriptor Pointer Register */ 348 #define DMA7_START_ADDR 0xFFC00DC4 /* DMA Channel 7 Start Address Register */ 349 #define DMA7_CONFIG 0xFFC00DC8 /* DMA Channel 7 Configuration Register */ 350 #define DMA7_X_COUNT 0xFFC00DD0 /* DMA Channel 7 X Count Register */ 351 #define DMA7_X_MODIFY 0xFFC00DD4 /* DMA Channel 7 X Modify Register */ 352 #define DMA7_Y_COUNT 0xFFC00DD8 /* DMA Channel 7 Y Count Register */ 353 #define DMA7_Y_MODIFY 0xFFC00DDC /* DMA Channel 7 Y Modify Register */ 354 #define DMA7_CURR_DESC_PTR 0xFFC00DE0 /* DMA Channel 7 Current Descriptor Pointer Register */ 355 #define DMA7_CURR_ADDR 0xFFC00DE4 /* DMA Channel 7 Current Address Register */ 356 #define DMA7_IRQ_STATUS 0xFFC00DE8 /* DMA Channel 7 Interrupt/Status Register */ 357 #define DMA7_PERIPHERAL_MAP 0xFFC00DEC /* DMA Channel 7 Peripheral Map Register */ 358 #define DMA7_CURR_X_COUNT 0xFFC00DF0 /* DMA Channel 7 Current X Count Register */ 359 #define DMA7_CURR_Y_COUNT 0xFFC00DF8 /* DMA Channel 7 Current Y Count Register */ 360 361 #define DMA8_NEXT_DESC_PTR 0xFFC00E00 /* DMA Channel 8 Next Descriptor Pointer Register */ 362 #define DMA8_START_ADDR 0xFFC00E04 /* DMA Channel 8 Start Address Register */ 363 #define DMA8_CONFIG 0xFFC00E08 /* DMA Channel 8 Configuration Register */ 364 #define DMA8_X_COUNT 0xFFC00E10 /* DMA Channel 8 X Count Register */ 365 #define DMA8_X_MODIFY 0xFFC00E14 /* DMA Channel 8 X Modify Register */ 366 #define DMA8_Y_COUNT 0xFFC00E18 /* DMA Channel 8 Y Count Register */ 367 #define DMA8_Y_MODIFY 0xFFC00E1C /* DMA Channel 8 Y Modify Register */ 368 #define DMA8_CURR_DESC_PTR 0xFFC00E20 /* DMA Channel 8 Current Descriptor Pointer Register */ 369 #define DMA8_CURR_ADDR 0xFFC00E24 /* DMA Channel 8 Current Address Register */ 370 #define DMA8_IRQ_STATUS 0xFFC00E28 /* DMA Channel 8 Interrupt/Status Register */ 371 #define DMA8_PERIPHERAL_MAP 0xFFC00E2C /* DMA Channel 8 Peripheral Map Register */ 372 #define DMA8_CURR_X_COUNT 0xFFC00E30 /* DMA Channel 8 Current X Count Register */ 373 #define DMA8_CURR_Y_COUNT 0xFFC00E38 /* DMA Channel 8 Current Y Count Register */ 374 375 #define DMA9_NEXT_DESC_PTR 0xFFC00E40 /* DMA Channel 9 Next Descriptor Pointer Register */ 376 #define DMA9_START_ADDR 0xFFC00E44 /* DMA Channel 9 Start Address Register */ 377 #define DMA9_CONFIG 0xFFC00E48 /* DMA Channel 9 Configuration Register */ 378 #define DMA9_X_COUNT 0xFFC00E50 /* DMA Channel 9 X Count Register */ 379 #define DMA9_X_MODIFY 0xFFC00E54 /* DMA Channel 9 X Modify Register */ 380 #define DMA9_Y_COUNT 0xFFC00E58 /* DMA Channel 9 Y Count Register */ 381 #define DMA9_Y_MODIFY 0xFFC00E5C /* DMA Channel 9 Y Modify Register */ 382 #define DMA9_CURR_DESC_PTR 0xFFC00E60 /* DMA Channel 9 Current Descriptor Pointer Register */ 383 #define DMA9_CURR_ADDR 0xFFC00E64 /* DMA Channel 9 Current Address Register */ 384 #define DMA9_IRQ_STATUS 0xFFC00E68 /* DMA Channel 9 Interrupt/Status Register */ 385 #define DMA9_PERIPHERAL_MAP 0xFFC00E6C /* DMA Channel 9 Peripheral Map Register */ 386 #define DMA9_CURR_X_COUNT 0xFFC00E70 /* DMA Channel 9 Current X Count Register */ 387 #define DMA9_CURR_Y_COUNT 0xFFC00E78 /* DMA Channel 9 Current Y Count Register */ 388 389 #define DMA10_NEXT_DESC_PTR 0xFFC00E80 /* DMA Channel 10 Next Descriptor Pointer Register */ 390 #define DMA10_START_ADDR 0xFFC00E84 /* DMA Channel 10 Start Address Register */ 391 #define DMA10_CONFIG 0xFFC00E88 /* DMA Channel 10 Configuration Register */ 392 #define DMA10_X_COUNT 0xFFC00E90 /* DMA Channel 10 X Count Register */ 393 #define DMA10_X_MODIFY 0xFFC00E94 /* DMA Channel 10 X Modify Register */ 394 #define DMA10_Y_COUNT 0xFFC00E98 /* DMA Channel 10 Y Count Register */ 395 #define DMA10_Y_MODIFY 0xFFC00E9C /* DMA Channel 10 Y Modify Register */ 396 #define DMA10_CURR_DESC_PTR 0xFFC00EA0 /* DMA Channel 10 Current Descriptor Pointer Register */ 397 #define DMA10_CURR_ADDR 0xFFC00EA4 /* DMA Channel 10 Current Address Register */ 398 #define DMA10_IRQ_STATUS 0xFFC00EA8 /* DMA Channel 10 Interrupt/Status Register */ 399 #define DMA10_PERIPHERAL_MAP 0xFFC00EAC /* DMA Channel 10 Peripheral Map Register */ 400 #define DMA10_CURR_X_COUNT 0xFFC00EB0 /* DMA Channel 10 Current X Count Register */ 401 #define DMA10_CURR_Y_COUNT 0xFFC00EB8 /* DMA Channel 10 Current Y Count Register */ 402 403 #define DMA11_NEXT_DESC_PTR 0xFFC00EC0 /* DMA Channel 11 Next Descriptor Pointer Register */ 404 #define DMA11_START_ADDR 0xFFC00EC4 /* DMA Channel 11 Start Address Register */ 405 #define DMA11_CONFIG 0xFFC00EC8 /* DMA Channel 11 Configuration Register */ 406 #define DMA11_X_COUNT 0xFFC00ED0 /* DMA Channel 11 X Count Register */ 407 #define DMA11_X_MODIFY 0xFFC00ED4 /* DMA Channel 11 X Modify Register */ 408 #define DMA11_Y_COUNT 0xFFC00ED8 /* DMA Channel 11 Y Count Register */ 409 #define DMA11_Y_MODIFY 0xFFC00EDC /* DMA Channel 11 Y Modify Register */ 410 #define DMA11_CURR_DESC_PTR 0xFFC00EE0 /* DMA Channel 11 Current Descriptor Pointer Register */ 411 #define DMA11_CURR_ADDR 0xFFC00EE4 /* DMA Channel 11 Current Address Register */ 412 #define DMA11_IRQ_STATUS 0xFFC00EE8 /* DMA Channel 11 Interrupt/Status Register */ 413 #define DMA11_PERIPHERAL_MAP 0xFFC00EEC /* DMA Channel 11 Peripheral Map Register */ 414 #define DMA11_CURR_X_COUNT 0xFFC00EF0 /* DMA Channel 11 Current X Count Register */ 415 #define DMA11_CURR_Y_COUNT 0xFFC00EF8 /* DMA Channel 11 Current Y Count Register */ 416 417 #define MDMA_D0_NEXT_DESC_PTR 0xFFC00F00 /* MemDMA Stream 0 Destination Next Descriptor Pointer Register */ 418 #define MDMA_D0_START_ADDR 0xFFC00F04 /* MemDMA Stream 0 Destination Start Address Register */ 419 #define MDMA_D0_CONFIG 0xFFC00F08 /* MemDMA Stream 0 Destination Configuration Register */ 420 #define MDMA_D0_X_COUNT 0xFFC00F10 /* MemDMA Stream 0 Destination X Count Register */ 421 #define MDMA_D0_X_MODIFY 0xFFC00F14 /* MemDMA Stream 0 Destination X Modify Register */ 422 #define MDMA_D0_Y_COUNT 0xFFC00F18 /* MemDMA Stream 0 Destination Y Count Register */ 423 #define MDMA_D0_Y_MODIFY 0xFFC00F1C /* MemDMA Stream 0 Destination Y Modify Register */ 424 #define MDMA_D0_CURR_DESC_PTR 0xFFC00F20 /* MemDMA Stream 0 Destination Current Descriptor Pointer Register */ 425 #define MDMA_D0_CURR_ADDR 0xFFC00F24 /* MemDMA Stream 0 Destination Current Address Register */ 426 #define MDMA_D0_IRQ_STATUS 0xFFC00F28 /* MemDMA Stream 0 Destination Interrupt/Status Register */ 427 #define MDMA_D0_PERIPHERAL_MAP 0xFFC00F2C /* MemDMA Stream 0 Destination Peripheral Map Register */ 428 #define MDMA_D0_CURR_X_COUNT 0xFFC00F30 /* MemDMA Stream 0 Destination Current X Count Register */ 429 #define MDMA_D0_CURR_Y_COUNT 0xFFC00F38 /* MemDMA Stream 0 Destination Current Y Count Register */ 430 431 #define MDMA_S0_NEXT_DESC_PTR 0xFFC00F40 /* MemDMA Stream 0 Source Next Descriptor Pointer Register */ 432 #define MDMA_S0_START_ADDR 0xFFC00F44 /* MemDMA Stream 0 Source Start Address Register */ 433 #define MDMA_S0_CONFIG 0xFFC00F48 /* MemDMA Stream 0 Source Configuration Register */ 434 #define MDMA_S0_X_COUNT 0xFFC00F50 /* MemDMA Stream 0 Source X Count Register */ 435 #define MDMA_S0_X_MODIFY 0xFFC00F54 /* MemDMA Stream 0 Source X Modify Register */ 436 #define MDMA_S0_Y_COUNT 0xFFC00F58 /* MemDMA Stream 0 Source Y Count Register */ 437 #define MDMA_S0_Y_MODIFY 0xFFC00F5C /* MemDMA Stream 0 Source Y Modify Register */ 438 #define MDMA_S0_CURR_DESC_PTR 0xFFC00F60 /* MemDMA Stream 0 Source Current Descriptor Pointer Register */ 439 #define MDMA_S0_CURR_ADDR 0xFFC00F64 /* MemDMA Stream 0 Source Current Address Register */ 440 #define MDMA_S0_IRQ_STATUS 0xFFC00F68 /* MemDMA Stream 0 Source Interrupt/Status Register */ 441 #define MDMA_S0_PERIPHERAL_MAP 0xFFC00F6C /* MemDMA Stream 0 Source Peripheral Map Register */ 442 #define MDMA_S0_CURR_X_COUNT 0xFFC00F70 /* MemDMA Stream 0 Source Current X Count Register */ 443 #define MDMA_S0_CURR_Y_COUNT 0xFFC00F78 /* MemDMA Stream 0 Source Current Y Count Register */ 444 445 #define MDMA_D1_NEXT_DESC_PTR 0xFFC00F80 /* MemDMA Stream 1 Destination Next Descriptor Pointer Register */ 446 #define MDMA_D1_START_ADDR 0xFFC00F84 /* MemDMA Stream 1 Destination Start Address Register */ 447 #define MDMA_D1_CONFIG 0xFFC00F88 /* MemDMA Stream 1 Destination Configuration Register */ 448 #define MDMA_D1_X_COUNT 0xFFC00F90 /* MemDMA Stream 1 Destination X Count Register */ 449 #define MDMA_D1_X_MODIFY 0xFFC00F94 /* MemDMA Stream 1 Destination X Modify Register */ 450 #define MDMA_D1_Y_COUNT 0xFFC00F98 /* MemDMA Stream 1 Destination Y Count Register */ 451 #define MDMA_D1_Y_MODIFY 0xFFC00F9C /* MemDMA Stream 1 Destination Y Modify Register */ 452 #define MDMA_D1_CURR_DESC_PTR 0xFFC00FA0 /* MemDMA Stream 1 Destination Current Descriptor Pointer Register */ 453 #define MDMA_D1_CURR_ADDR 0xFFC00FA4 /* MemDMA Stream 1 Destination Current Address Register */ 454 #define MDMA_D1_IRQ_STATUS 0xFFC00FA8 /* MemDMA Stream 1 Destination Interrupt/Status Register */ 455 #define MDMA_D1_PERIPHERAL_MAP 0xFFC00FAC /* MemDMA Stream 1 Destination Peripheral Map Register */ 456 #define MDMA_D1_CURR_X_COUNT 0xFFC00FB0 /* MemDMA Stream 1 Destination Current X Count Register */ 457 #define MDMA_D1_CURR_Y_COUNT 0xFFC00FB8 /* MemDMA Stream 1 Destination Current Y Count Register */ 458 459 #define MDMA_S1_NEXT_DESC_PTR 0xFFC00FC0 /* MemDMA Stream 1 Source Next Descriptor Pointer Register */ 460 #define MDMA_S1_START_ADDR 0xFFC00FC4 /* MemDMA Stream 1 Source Start Address Register */ 461 #define MDMA_S1_CONFIG 0xFFC00FC8 /* MemDMA Stream 1 Source Configuration Register */ 462 #define MDMA_S1_X_COUNT 0xFFC00FD0 /* MemDMA Stream 1 Source X Count Register */ 463 #define MDMA_S1_X_MODIFY 0xFFC00FD4 /* MemDMA Stream 1 Source X Modify Register */ 464 #define MDMA_S1_Y_COUNT 0xFFC00FD8 /* MemDMA Stream 1 Source Y Count Register */ 465 #define MDMA_S1_Y_MODIFY 0xFFC00FDC /* MemDMA Stream 1 Source Y Modify Register */ 466 #define MDMA_S1_CURR_DESC_PTR 0xFFC00FE0 /* MemDMA Stream 1 Source Current Descriptor Pointer Register */ 467 #define MDMA_S1_CURR_ADDR 0xFFC00FE4 /* MemDMA Stream 1 Source Current Address Register */ 468 #define MDMA_S1_IRQ_STATUS 0xFFC00FE8 /* MemDMA Stream 1 Source Interrupt/Status Register */ 469 #define MDMA_S1_PERIPHERAL_MAP 0xFFC00FEC /* MemDMA Stream 1 Source Peripheral Map Register */ 470 #define MDMA_S1_CURR_X_COUNT 0xFFC00FF0 /* MemDMA Stream 1 Source Current X Count Register */ 471 #define MDMA_S1_CURR_Y_COUNT 0xFFC00FF8 /* MemDMA Stream 1 Source Current Y Count Register */ 472 473 474 /* Parallel Peripheral Interface (0xFFC01000 - 0xFFC010FF) */ 475 #define PPI_CONTROL 0xFFC01000 /* PPI Control Register */ 476 #define PPI_STATUS 0xFFC01004 /* PPI Status Register */ 477 #define PPI_COUNT 0xFFC01008 /* PPI Transfer Count Register */ 478 #define PPI_DELAY 0xFFC0100C /* PPI Delay Count Register */ 479 #define PPI_FRAME 0xFFC01010 /* PPI Frame Length Register */ 480 481 482 /* Two-Wire Interface (0xFFC01400 - 0xFFC014FF) */ 483 #define TWI_CLKDIV 0xFFC01400 /* Serial Clock Divider Register */ 484 #define TWI_CONTROL 0xFFC01404 /* TWI Control Register */ 485 #define TWI_SLAVE_CTL 0xFFC01408 /* Slave Mode Control Register */ 486 #define TWI_SLAVE_STAT 0xFFC0140C /* Slave Mode Status Register */ 487 #define TWI_SLAVE_ADDR 0xFFC01410 /* Slave Mode Address Register */ 488 #define TWI_MASTER_CTL 0xFFC01414 /* Master Mode Control Register */ 489 #define TWI_MASTER_STAT 0xFFC01418 /* Master Mode Status Register */ 490 #define TWI_MASTER_ADDR 0xFFC0141C /* Master Mode Address Register */ 491 #define TWI_INT_STAT 0xFFC01420 /* TWI Interrupt Status Register */ 492 #define TWI_INT_MASK 0xFFC01424 /* TWI Master Interrupt Mask Register */ 493 #define TWI_FIFO_CTL 0xFFC01428 /* FIFO Control Register */ 494 #define TWI_FIFO_STAT 0xFFC0142C /* FIFO Status Register */ 495 #define TWI_XMT_DATA8 0xFFC01480 /* FIFO Transmit Data Single Byte Register */ 496 #define TWI_XMT_DATA16 0xFFC01484 /* FIFO Transmit Data Double Byte Register */ 497 #define TWI_RCV_DATA8 0xFFC01488 /* FIFO Receive Data Single Byte Register */ 498 #define TWI_RCV_DATA16 0xFFC0148C /* FIFO Receive Data Double Byte Register */ 499 500 501 /* General Purpose I/O Port G (0xFFC01500 - 0xFFC015FF) */ 502 #define PORTGIO 0xFFC01500 /* Port G I/O Pin State Specify Register */ 503 #define PORTGIO_CLEAR 0xFFC01504 /* Port G I/O Peripheral Interrupt Clear Register */ 504 #define PORTGIO_SET 0xFFC01508 /* Port G I/O Peripheral Interrupt Set Register */ 505 #define PORTGIO_TOGGLE 0xFFC0150C /* Port G I/O Pin State Toggle Register */ 506 #define PORTGIO_MASKA 0xFFC01510 /* Port G I/O Mask State Specify Interrupt A Register */ 507 #define PORTGIO_MASKA_CLEAR 0xFFC01514 /* Port G I/O Mask Disable Interrupt A Register */ 508 #define PORTGIO_MASKA_SET 0xFFC01518 /* Port G I/O Mask Enable Interrupt A Register */ 509 #define PORTGIO_MASKA_TOGGLE 0xFFC0151C /* Port G I/O Mask Toggle Enable Interrupt A Register */ 510 #define PORTGIO_MASKB 0xFFC01520 /* Port G I/O Mask State Specify Interrupt B Register */ 511 #define PORTGIO_MASKB_CLEAR 0xFFC01524 /* Port G I/O Mask Disable Interrupt B Register */ 512 #define PORTGIO_MASKB_SET 0xFFC01528 /* Port G I/O Mask Enable Interrupt B Register */ 513 #define PORTGIO_MASKB_TOGGLE 0xFFC0152C /* Port G I/O Mask Toggle Enable Interrupt B Register */ 514 #define PORTGIO_DIR 0xFFC01530 /* Port G I/O Direction Register */ 515 #define PORTGIO_POLAR 0xFFC01534 /* Port G I/O Source Polarity Register */ 516 #define PORTGIO_EDGE 0xFFC01538 /* Port G I/O Source Sensitivity Register */ 517 #define PORTGIO_BOTH 0xFFC0153C /* Port G I/O Set on BOTH Edges Register */ 518 #define PORTGIO_INEN 0xFFC01540 /* Port G I/O Input Enable Register */ 519 520 521 /* General Purpose I/O Port H (0xFFC01700 - 0xFFC017FF) */ 522 #define PORTHIO 0xFFC01700 /* Port H I/O Pin State Specify Register */ 523 #define PORTHIO_CLEAR 0xFFC01704 /* Port H I/O Peripheral Interrupt Clear Register */ 524 #define PORTHIO_SET 0xFFC01708 /* Port H I/O Peripheral Interrupt Set Register */ 525 #define PORTHIO_TOGGLE 0xFFC0170C /* Port H I/O Pin State Toggle Register */ 526 #define PORTHIO_MASKA 0xFFC01710 /* Port H I/O Mask State Specify Interrupt A Register */ 527 #define PORTHIO_MASKA_CLEAR 0xFFC01714 /* Port H I/O Mask Disable Interrupt A Register */ 528 #define PORTHIO_MASKA_SET 0xFFC01718 /* Port H I/O Mask Enable Interrupt A Register */ 529 #define PORTHIO_MASKA_TOGGLE 0xFFC0171C /* Port H I/O Mask Toggle Enable Interrupt A Register */ 530 #define PORTHIO_MASKB 0xFFC01720 /* Port H I/O Mask State Specify Interrupt B Register */ 531 #define PORTHIO_MASKB_CLEAR 0xFFC01724 /* Port H I/O Mask Disable Interrupt B Register */ 532 #define PORTHIO_MASKB_SET 0xFFC01728 /* Port H I/O Mask Enable Interrupt B Register */ 533 #define PORTHIO_MASKB_TOGGLE 0xFFC0172C /* Port H I/O Mask Toggle Enable Interrupt B Register */ 534 #define PORTHIO_DIR 0xFFC01730 /* Port H I/O Direction Register */ 535 #define PORTHIO_POLAR 0xFFC01734 /* Port H I/O Source Polarity Register */ 536 #define PORTHIO_EDGE 0xFFC01738 /* Port H I/O Source Sensitivity Register */ 537 #define PORTHIO_BOTH 0xFFC0173C /* Port H I/O Set on BOTH Edges Register */ 538 #define PORTHIO_INEN 0xFFC01740 /* Port H I/O Input Enable Register */ 539 540 541 /* UART1 Controller (0xFFC02000 - 0xFFC020FF) */ 542 #define UART1_DLL 0xffc02000 /* Divisor Latch Low Byte */ 543 #define UART1_DLH 0xffc02004 /* Divisor Latch High Byte */ 544 #define UART1_GCTL 0xffc02008 /* Global Control Register */ 545 #define UART1_LCR 0xffc0200c /* Line Control Register */ 546 #define UART1_MCR 0xffc02010 /* Modem Control Register */ 547 #define UART1_LSR 0xffc02014 /* Line Status Register */ 548 #define UART1_MSR 0xffc02018 /* Modem Status Register */ 549 #define UART1_SCR 0xffc0201c /* Scratch Register */ 550 #define UART1_IER_SET 0xffc02020 /* Interrupt Enable Register Set */ 551 #define UART1_IER_CLEAR 0xffc02024 /* Interrupt Enable Register Clear */ 552 #define UART1_THR 0xffc02028 /* Transmit Hold Register */ 553 #define UART1_RBR 0xffc0202c /* Receive Buffer Register */ 554 555 556 /* CAN Controller (0xFFC02A00 - 0xFFC02FFF) */ 557 /* For Mailboxes 0-15 */ 558 #define CAN_MC1 0xFFC02A00 /* Mailbox config reg 1 */ 559 #define CAN_MD1 0xFFC02A04 /* Mailbox direction reg 1 */ 560 #define CAN_TRS1 0xFFC02A08 /* Transmit Request Set reg 1 */ 561 #define CAN_TRR1 0xFFC02A0C /* Transmit Request Reset reg 1 */ 562 #define CAN_TA1 0xFFC02A10 /* Transmit Acknowledge reg 1 */ 563 #define CAN_AA1 0xFFC02A14 /* Transmit Abort Acknowledge reg 1 */ 564 #define CAN_RMP1 0xFFC02A18 /* Receive Message Pending reg 1 */ 565 #define CAN_RML1 0xFFC02A1C /* Receive Message Lost reg 1 */ 566 #define CAN_MBTIF1 0xFFC02A20 /* Mailbox Transmit Interrupt Flag reg 1 */ 567 #define CAN_MBRIF1 0xFFC02A24 /* Mailbox Receive Interrupt Flag reg 1 */ 568 #define CAN_MBIM1 0xFFC02A28 /* Mailbox Interrupt Mask reg 1 */ 569 #define CAN_RFH1 0xFFC02A2C /* Remote Frame Handling reg 1 */ 570 #define CAN_OPSS1 0xFFC02A30 /* Overwrite Protection Single Shot Xmission reg 1 */ 571 572 /* For Mailboxes 16-31 */ 573 #define CAN_MC2 0xFFC02A40 /* Mailbox config reg 2 */ 574 #define CAN_MD2 0xFFC02A44 /* Mailbox direction reg 2 */ 575 #define CAN_TRS2 0xFFC02A48 /* Transmit Request Set reg 2 */ 576 #define CAN_TRR2 0xFFC02A4C /* Transmit Request Reset reg 2 */ 577 #define CAN_TA2 0xFFC02A50 /* Transmit Acknowledge reg 2 */ 578 #define CAN_AA2 0xFFC02A54 /* Transmit Abort Acknowledge reg 2 */ 579 #define CAN_RMP2 0xFFC02A58 /* Receive Message Pending reg 2 */ 580 #define CAN_RML2 0xFFC02A5C /* Receive Message Lost reg 2 */ 581 #define CAN_MBTIF2 0xFFC02A60 /* Mailbox Transmit Interrupt Flag reg 2 */ 582 #define CAN_MBRIF2 0xFFC02A64 /* Mailbox Receive Interrupt Flag reg 2 */ 583 #define CAN_MBIM2 0xFFC02A68 /* Mailbox Interrupt Mask reg 2 */ 584 #define CAN_RFH2 0xFFC02A6C /* Remote Frame Handling reg 2 */ 585 #define CAN_OPSS2 0xFFC02A70 /* Overwrite Protection Single Shot Xmission reg 2 */ 586 587 #define CAN_CLOCK 0xFFC02A80 /* Bit Timing Configuration register 0 */ 588 #define CAN_TIMING 0xFFC02A84 /* Bit Timing Configuration register 1 */ 589 590 #define CAN_DEBUG 0xFFC02A88 /* Debug Register */ 591 /* the following is for backwards compatibility */ 592 #define CAN_CNF (CAN_DEBUG ) 593 594 #define CAN_STATUS 0xFFC02A8C /* Global Status Register */ 595 #define CAN_CEC 0xFFC02A90 /* Error Counter Register */ 596 #define CAN_GIS 0xFFC02A94 /* Global Interrupt Status Register */ 597 #define CAN_GIM 0xFFC02A98 /* Global Interrupt Mask Register */ 598 #define CAN_GIF 0xFFC02A9C /* Global Interrupt Flag Register */ 599 #define CAN_CONTROL 0xFFC02AA0 /* Master Control Register */ 600 #define CAN_INTR 0xFFC02AA4 /* Interrupt Pending Register */ 601 #define CAN_MBTD 0xFFC02AAC /* Mailbox Temporary Disable Feature */ 602 #define CAN_EWR 0xFFC02AB0 /* Programmable Warning Level */ 603 #define CAN_ESR 0xFFC02AB4 /* Error Status Register */ 604 #define CAN_UCCNT 0xFFC02AC4 /* Universal Counter */ 605 #define CAN_UCRC 0xFFC02AC8 /* Universal Counter Reload/Capture Register */ 606 #define CAN_UCCNF 0xFFC02ACC /* Universal Counter Configuration Register */ 607 608 /* Mailbox Acceptance Masks */ 609 #define CAN_AM00L 0xFFC02B00 /* Mailbox 0 Low Acceptance Mask */ 610 #define CAN_AM00H 0xFFC02B04 /* Mailbox 0 High Acceptance Mask */ 611 #define CAN_AM01L 0xFFC02B08 /* Mailbox 1 Low Acceptance Mask */ 612 #define CAN_AM01H 0xFFC02B0C /* Mailbox 1 High Acceptance Mask */ 613 #define CAN_AM02L 0xFFC02B10 /* Mailbox 2 Low Acceptance Mask */ 614 #define CAN_AM02H 0xFFC02B14 /* Mailbox 2 High Acceptance Mask */ 615 #define CAN_AM03L 0xFFC02B18 /* Mailbox 3 Low Acceptance Mask */ 616 #define CAN_AM03H 0xFFC02B1C /* Mailbox 3 High Acceptance Mask */ 617 #define CAN_AM04L 0xFFC02B20 /* Mailbox 4 Low Acceptance Mask */ 618 #define CAN_AM04H 0xFFC02B24 /* Mailbox 4 High Acceptance Mask */ 619 #define CAN_AM05L 0xFFC02B28 /* Mailbox 5 Low Acceptance Mask */ 620 #define CAN_AM05H 0xFFC02B2C /* Mailbox 5 High Acceptance Mask */ 621 #define CAN_AM06L 0xFFC02B30 /* Mailbox 6 Low Acceptance Mask */ 622 #define CAN_AM06H 0xFFC02B34 /* Mailbox 6 High Acceptance Mask */ 623 #define CAN_AM07L 0xFFC02B38 /* Mailbox 7 Low Acceptance Mask */ 624 #define CAN_AM07H 0xFFC02B3C /* Mailbox 7 High Acceptance Mask */ 625 #define CAN_AM08L 0xFFC02B40 /* Mailbox 8 Low Acceptance Mask */ 626 #define CAN_AM08H 0xFFC02B44 /* Mailbox 8 High Acceptance Mask */ 627 #define CAN_AM09L 0xFFC02B48 /* Mailbox 9 Low Acceptance Mask */ 628 #define CAN_AM09H 0xFFC02B4C /* Mailbox 9 High Acceptance Mask */ 629 #define CAN_AM10L 0xFFC02B50 /* Mailbox 10 Low Acceptance Mask */ 630 #define CAN_AM10H 0xFFC02B54 /* Mailbox 10 High Acceptance Mask */ 631 #define CAN_AM11L 0xFFC02B58 /* Mailbox 11 Low Acceptance Mask */ 632 #define CAN_AM11H 0xFFC02B5C /* Mailbox 11 High Acceptance Mask */ 633 #define CAN_AM12L 0xFFC02B60 /* Mailbox 12 Low Acceptance Mask */ 634 #define CAN_AM12H 0xFFC02B64 /* Mailbox 12 High Acceptance Mask */ 635 #define CAN_AM13L 0xFFC02B68 /* Mailbox 13 Low Acceptance Mask */ 636 #define CAN_AM13H 0xFFC02B6C /* Mailbox 13 High Acceptance Mask */ 637 #define CAN_AM14L 0xFFC02B70 /* Mailbox 14 Low Acceptance Mask */ 638 #define CAN_AM14H 0xFFC02B74 /* Mailbox 14 High Acceptance Mask */ 639 #define CAN_AM15L 0xFFC02B78 /* Mailbox 15 Low Acceptance Mask */ 640 #define CAN_AM15H 0xFFC02B7C /* Mailbox 15 High Acceptance Mask */ 641 642 #define CAN_AM16L 0xFFC02B80 /* Mailbox 16 Low Acceptance Mask */ 643 #define CAN_AM16H 0xFFC02B84 /* Mailbox 16 High Acceptance Mask */ 644 #define CAN_AM17L 0xFFC02B88 /* Mailbox 17 Low Acceptance Mask */ 645 #define CAN_AM17H 0xFFC02B8C /* Mailbox 17 High Acceptance Mask */ 646 #define CAN_AM18L 0xFFC02B90 /* Mailbox 18 Low Acceptance Mask */ 647 #define CAN_AM18H 0xFFC02B94 /* Mailbox 18 High Acceptance Mask */ 648 #define CAN_AM19L 0xFFC02B98 /* Mailbox 19 Low Acceptance Mask */ 649 #define CAN_AM19H 0xFFC02B9C /* Mailbox 19 High Acceptance Mask */ 650 #define CAN_AM20L 0xFFC02BA0 /* Mailbox 20 Low Acceptance Mask */ 651 #define CAN_AM20H 0xFFC02BA4 /* Mailbox 20 High Acceptance Mask */ 652 #define CAN_AM21L 0xFFC02BA8 /* Mailbox 21 Low Acceptance Mask */ 653 #define CAN_AM21H 0xFFC02BAC /* Mailbox 21 High Acceptance Mask */ 654 #define CAN_AM22L 0xFFC02BB0 /* Mailbox 22 Low Acceptance Mask */ 655 #define CAN_AM22H 0xFFC02BB4 /* Mailbox 22 High Acceptance Mask */ 656 #define CAN_AM23L 0xFFC02BB8 /* Mailbox 23 Low Acceptance Mask */ 657 #define CAN_AM23H 0xFFC02BBC /* Mailbox 23 High Acceptance Mask */ 658 #define CAN_AM24L 0xFFC02BC0 /* Mailbox 24 Low Acceptance Mask */ 659 #define CAN_AM24H 0xFFC02BC4 /* Mailbox 24 High Acceptance Mask */ 660 #define CAN_AM25L 0xFFC02BC8 /* Mailbox 25 Low Acceptance Mask */ 661 #define CAN_AM25H 0xFFC02BCC /* Mailbox 25 High Acceptance Mask */ 662 #define CAN_AM26L 0xFFC02BD0 /* Mailbox 26 Low Acceptance Mask */ 663 #define CAN_AM26H 0xFFC02BD4 /* Mailbox 26 High Acceptance Mask */ 664 #define CAN_AM27L 0xFFC02BD8 /* Mailbox 27 Low Acceptance Mask */ 665 #define CAN_AM27H 0xFFC02BDC /* Mailbox 27 High Acceptance Mask */ 666 #define CAN_AM28L 0xFFC02BE0 /* Mailbox 28 Low Acceptance Mask */ 667 #define CAN_AM28H 0xFFC02BE4 /* Mailbox 28 High Acceptance Mask */ 668 #define CAN_AM29L 0xFFC02BE8 /* Mailbox 29 Low Acceptance Mask */ 669 #define CAN_AM29H 0xFFC02BEC /* Mailbox 29 High Acceptance Mask */ 670 #define CAN_AM30L 0xFFC02BF0 /* Mailbox 30 Low Acceptance Mask */ 671 #define CAN_AM30H 0xFFC02BF4 /* Mailbox 30 High Acceptance Mask */ 672 #define CAN_AM31L 0xFFC02BF8 /* Mailbox 31 Low Acceptance Mask */ 673 #define CAN_AM31H 0xFFC02BFC /* Mailbox 31 High Acceptance Mask */ 674 675 /* CAN Acceptance Mask Macros */ 676 #define CAN_AM_L(x) (CAN_AM00L+((x)*0x8)) 677 #define CAN_AM_H(x) (CAN_AM00H+((x)*0x8)) 678 679 /* Mailbox Registers */ 680 #define CAN_MB00_DATA0 0xFFC02C00 /* Mailbox 0 Data Word 0 [15:0] Register */ 681 #define CAN_MB00_DATA1 0xFFC02C04 /* Mailbox 0 Data Word 1 [31:16] Register */ 682 #define CAN_MB00_DATA2 0xFFC02C08 /* Mailbox 0 Data Word 2 [47:32] Register */ 683 #define CAN_MB00_DATA3 0xFFC02C0C /* Mailbox 0 Data Word 3 [63:48] Register */ 684 #define CAN_MB00_LENGTH 0xFFC02C10 /* Mailbox 0 Data Length Code Register */ 685 #define CAN_MB00_TIMESTAMP 0xFFC02C14 /* Mailbox 0 Time Stamp Value Register */ 686 #define CAN_MB00_ID0 0xFFC02C18 /* Mailbox 0 Identifier Low Register */ 687 #define CAN_MB00_ID1 0xFFC02C1C /* Mailbox 0 Identifier High Register */ 688 689 #define CAN_MB01_DATA0 0xFFC02C20 /* Mailbox 1 Data Word 0 [15:0] Register */ 690 #define CAN_MB01_DATA1 0xFFC02C24 /* Mailbox 1 Data Word 1 [31:16] Register */ 691 #define CAN_MB01_DATA2 0xFFC02C28 /* Mailbox 1 Data Word 2 [47:32] Register */ 692 #define CAN_MB01_DATA3 0xFFC02C2C /* Mailbox 1 Data Word 3 [63:48] Register */ 693 #define CAN_MB01_LENGTH 0xFFC02C30 /* Mailbox 1 Data Length Code Register */ 694 #define CAN_MB01_TIMESTAMP 0xFFC02C34 /* Mailbox 1 Time Stamp Value Register */ 695 #define CAN_MB01_ID0 0xFFC02C38 /* Mailbox 1 Identifier Low Register */ 696 #define CAN_MB01_ID1 0xFFC02C3C /* Mailbox 1 Identifier High Register */ 697 698 #define CAN_MB02_DATA0 0xFFC02C40 /* Mailbox 2 Data Word 0 [15:0] Register */ 699 #define CAN_MB02_DATA1 0xFFC02C44 /* Mailbox 2 Data Word 1 [31:16] Register */ 700 #define CAN_MB02_DATA2 0xFFC02C48 /* Mailbox 2 Data Word 2 [47:32] Register */ 701 #define CAN_MB02_DATA3 0xFFC02C4C /* Mailbox 2 Data Word 3 [63:48] Register */ 702 #define CAN_MB02_LENGTH 0xFFC02C50 /* Mailbox 2 Data Length Code Register */ 703 #define CAN_MB02_TIMESTAMP 0xFFC02C54 /* Mailbox 2 Time Stamp Value Register */ 704 #define CAN_MB02_ID0 0xFFC02C58 /* Mailbox 2 Identifier Low Register */ 705 #define CAN_MB02_ID1 0xFFC02C5C /* Mailbox 2 Identifier High Register */ 706 707 #define CAN_MB03_DATA0 0xFFC02C60 /* Mailbox 3 Data Word 0 [15:0] Register */ 708 #define CAN_MB03_DATA1 0xFFC02C64 /* Mailbox 3 Data Word 1 [31:16] Register */ 709 #define CAN_MB03_DATA2 0xFFC02C68 /* Mailbox 3 Data Word 2 [47:32] Register */ 710 #define CAN_MB03_DATA3 0xFFC02C6C /* Mailbox 3 Data Word 3 [63:48] Register */ 711 #define CAN_MB03_LENGTH 0xFFC02C70 /* Mailbox 3 Data Length Code Register */ 712 #define CAN_MB03_TIMESTAMP 0xFFC02C74 /* Mailbox 3 Time Stamp Value Register */ 713 #define CAN_MB03_ID0 0xFFC02C78 /* Mailbox 3 Identifier Low Register */ 714 #define CAN_MB03_ID1 0xFFC02C7C /* Mailbox 3 Identifier High Register */ 715 716 #define CAN_MB04_DATA0 0xFFC02C80 /* Mailbox 4 Data Word 0 [15:0] Register */ 717 #define CAN_MB04_DATA1 0xFFC02C84 /* Mailbox 4 Data Word 1 [31:16] Register */ 718 #define CAN_MB04_DATA2 0xFFC02C88 /* Mailbox 4 Data Word 2 [47:32] Register */ 719 #define CAN_MB04_DATA3 0xFFC02C8C /* Mailbox 4 Data Word 3 [63:48] Register */ 720 #define CAN_MB04_LENGTH 0xFFC02C90 /* Mailbox 4 Data Length Code Register */ 721 #define CAN_MB04_TIMESTAMP 0xFFC02C94 /* Mailbox 4 Time Stamp Value Register */ 722 #define CAN_MB04_ID0 0xFFC02C98 /* Mailbox 4 Identifier Low Register */ 723 #define CAN_MB04_ID1 0xFFC02C9C /* Mailbox 4 Identifier High Register */ 724 725 #define CAN_MB05_DATA0 0xFFC02CA0 /* Mailbox 5 Data Word 0 [15:0] Register */ 726 #define CAN_MB05_DATA1 0xFFC02CA4 /* Mailbox 5 Data Word 1 [31:16] Register */ 727 #define CAN_MB05_DATA2 0xFFC02CA8 /* Mailbox 5 Data Word 2 [47:32] Register */ 728 #define CAN_MB05_DATA3 0xFFC02CAC /* Mailbox 5 Data Word 3 [63:48] Register */ 729 #define CAN_MB05_LENGTH 0xFFC02CB0 /* Mailbox 5 Data Length Code Register */ 730 #define CAN_MB05_TIMESTAMP 0xFFC02CB4 /* Mailbox 5 Time Stamp Value Register */ 731 #define CAN_MB05_ID0 0xFFC02CB8 /* Mailbox 5 Identifier Low Register */ 732 #define CAN_MB05_ID1 0xFFC02CBC /* Mailbox 5 Identifier High Register */ 733 734 #define CAN_MB06_DATA0 0xFFC02CC0 /* Mailbox 6 Data Word 0 [15:0] Register */ 735 #define CAN_MB06_DATA1 0xFFC02CC4 /* Mailbox 6 Data Word 1 [31:16] Register */ 736 #define CAN_MB06_DATA2 0xFFC02CC8 /* Mailbox 6 Data Word 2 [47:32] Register */ 737 #define CAN_MB06_DATA3 0xFFC02CCC /* Mailbox 6 Data Word 3 [63:48] Register */ 738 #define CAN_MB06_LENGTH 0xFFC02CD0 /* Mailbox 6 Data Length Code Register */ 739 #define CAN_MB06_TIMESTAMP 0xFFC02CD4 /* Mailbox 6 Time Stamp Value Register */ 740 #define CAN_MB06_ID0 0xFFC02CD8 /* Mailbox 6 Identifier Low Register */ 741 #define CAN_MB06_ID1 0xFFC02CDC /* Mailbox 6 Identifier High Register */ 742 743 #define CAN_MB07_DATA0 0xFFC02CE0 /* Mailbox 7 Data Word 0 [15:0] Register */ 744 #define CAN_MB07_DATA1 0xFFC02CE4 /* Mailbox 7 Data Word 1 [31:16] Register */ 745 #define CAN_MB07_DATA2 0xFFC02CE8 /* Mailbox 7 Data Word 2 [47:32] Register */ 746 #define CAN_MB07_DATA3 0xFFC02CEC /* Mailbox 7 Data Word 3 [63:48] Register */ 747 #define CAN_MB07_LENGTH 0xFFC02CF0 /* Mailbox 7 Data Length Code Register */ 748 #define CAN_MB07_TIMESTAMP 0xFFC02CF4 /* Mailbox 7 Time Stamp Value Register */ 749 #define CAN_MB07_ID0 0xFFC02CF8 /* Mailbox 7 Identifier Low Register */ 750 #define CAN_MB07_ID1 0xFFC02CFC /* Mailbox 7 Identifier High Register */ 751 752 #define CAN_MB08_DATA0 0xFFC02D00 /* Mailbox 8 Data Word 0 [15:0] Register */ 753 #define CAN_MB08_DATA1 0xFFC02D04 /* Mailbox 8 Data Word 1 [31:16] Register */ 754 #define CAN_MB08_DATA2 0xFFC02D08 /* Mailbox 8 Data Word 2 [47:32] Register */ 755 #define CAN_MB08_DATA3 0xFFC02D0C /* Mailbox 8 Data Word 3 [63:48] Register */ 756 #define CAN_MB08_LENGTH 0xFFC02D10 /* Mailbox 8 Data Length Code Register */ 757 #define CAN_MB08_TIMESTAMP 0xFFC02D14 /* Mailbox 8 Time Stamp Value Register */ 758 #define CAN_MB08_ID0 0xFFC02D18 /* Mailbox 8 Identifier Low Register */ 759 #define CAN_MB08_ID1 0xFFC02D1C /* Mailbox 8 Identifier High Register */ 760 761 #define CAN_MB09_DATA0 0xFFC02D20 /* Mailbox 9 Data Word 0 [15:0] Register */ 762 #define CAN_MB09_DATA1 0xFFC02D24 /* Mailbox 9 Data Word 1 [31:16] Register */ 763 #define CAN_MB09_DATA2 0xFFC02D28 /* Mailbox 9 Data Word 2 [47:32] Register */ 764 #define CAN_MB09_DATA3 0xFFC02D2C /* Mailbox 9 Data Word 3 [63:48] Register */ 765 #define CAN_MB09_LENGTH 0xFFC02D30 /* Mailbox 9 Data Length Code Register */ 766 #define CAN_MB09_TIMESTAMP 0xFFC02D34 /* Mailbox 9 Time Stamp Value Register */ 767 #define CAN_MB09_ID0 0xFFC02D38 /* Mailbox 9 Identifier Low Register */ 768 #define CAN_MB09_ID1 0xFFC02D3C /* Mailbox 9 Identifier High Register */ 769 770 #define CAN_MB10_DATA0 0xFFC02D40 /* Mailbox 10 Data Word 0 [15:0] Register */ 771 #define CAN_MB10_DATA1 0xFFC02D44 /* Mailbox 10 Data Word 1 [31:16] Register */ 772 #define CAN_MB10_DATA2 0xFFC02D48 /* Mailbox 10 Data Word 2 [47:32] Register */ 773 #define CAN_MB10_DATA3 0xFFC02D4C /* Mailbox 10 Data Word 3 [63:48] Register */ 774 #define CAN_MB10_LENGTH 0xFFC02D50 /* Mailbox 10 Data Length Code Register */ 775 #define CAN_MB10_TIMESTAMP 0xFFC02D54 /* Mailbox 10 Time Stamp Value Register */ 776 #define CAN_MB10_ID0 0xFFC02D58 /* Mailbox 10 Identifier Low Register */ 777 #define CAN_MB10_ID1 0xFFC02D5C /* Mailbox 10 Identifier High Register */ 778 779 #define CAN_MB11_DATA0 0xFFC02D60 /* Mailbox 11 Data Word 0 [15:0] Register */ 780 #define CAN_MB11_DATA1 0xFFC02D64 /* Mailbox 11 Data Word 1 [31:16] Register */ 781 #define CAN_MB11_DATA2 0xFFC02D68 /* Mailbox 11 Data Word 2 [47:32] Register */ 782 #define CAN_MB11_DATA3 0xFFC02D6C /* Mailbox 11 Data Word 3 [63:48] Register */ 783 #define CAN_MB11_LENGTH 0xFFC02D70 /* Mailbox 11 Data Length Code Register */ 784 #define CAN_MB11_TIMESTAMP 0xFFC02D74 /* Mailbox 11 Time Stamp Value Register */ 785 #define CAN_MB11_ID0 0xFFC02D78 /* Mailbox 11 Identifier Low Register */ 786 #define CAN_MB11_ID1 0xFFC02D7C /* Mailbox 11 Identifier High Register */ 787 788 #define CAN_MB12_DATA0 0xFFC02D80 /* Mailbox 12 Data Word 0 [15:0] Register */ 789 #define CAN_MB12_DATA1 0xFFC02D84 /* Mailbox 12 Data Word 1 [31:16] Register */ 790 #define CAN_MB12_DATA2 0xFFC02D88 /* Mailbox 12 Data Word 2 [47:32] Register */ 791 #define CAN_MB12_DATA3 0xFFC02D8C /* Mailbox 12 Data Word 3 [63:48] Register */ 792 #define CAN_MB12_LENGTH 0xFFC02D90 /* Mailbox 12 Data Length Code Register */ 793 #define CAN_MB12_TIMESTAMP 0xFFC02D94 /* Mailbox 12 Time Stamp Value Register */ 794 #define CAN_MB12_ID0 0xFFC02D98 /* Mailbox 12 Identifier Low Register */ 795 #define CAN_MB12_ID1 0xFFC02D9C /* Mailbox 12 Identifier High Register */ 796 797 #define CAN_MB13_DATA0 0xFFC02DA0 /* Mailbox 13 Data Word 0 [15:0] Register */ 798 #define CAN_MB13_DATA1 0xFFC02DA4 /* Mailbox 13 Data Word 1 [31:16] Register */ 799 #define CAN_MB13_DATA2 0xFFC02DA8 /* Mailbox 13 Data Word 2 [47:32] Register */ 800 #define CAN_MB13_DATA3 0xFFC02DAC /* Mailbox 13 Data Word 3 [63:48] Register */ 801 #define CAN_MB13_LENGTH 0xFFC02DB0 /* Mailbox 13 Data Length Code Register */ 802 #define CAN_MB13_TIMESTAMP 0xFFC02DB4 /* Mailbox 13 Time Stamp Value Register */ 803 #define CAN_MB13_ID0 0xFFC02DB8 /* Mailbox 13 Identifier Low Register */ 804 #define CAN_MB13_ID1 0xFFC02DBC /* Mailbox 13 Identifier High Register */ 805 806 #define CAN_MB14_DATA0 0xFFC02DC0 /* Mailbox 14 Data Word 0 [15:0] Register */ 807 #define CAN_MB14_DATA1 0xFFC02DC4 /* Mailbox 14 Data Word 1 [31:16] Register */ 808 #define CAN_MB14_DATA2 0xFFC02DC8 /* Mailbox 14 Data Word 2 [47:32] Register */ 809 #define CAN_MB14_DATA3 0xFFC02DCC /* Mailbox 14 Data Word 3 [63:48] Register */ 810 #define CAN_MB14_LENGTH 0xFFC02DD0 /* Mailbox 14 Data Length Code Register */ 811 #define CAN_MB14_TIMESTAMP 0xFFC02DD4 /* Mailbox 14 Time Stamp Value Register */ 812 #define CAN_MB14_ID0 0xFFC02DD8 /* Mailbox 14 Identifier Low Register */ 813 #define CAN_MB14_ID1 0xFFC02DDC /* Mailbox 14 Identifier High Register */ 814 815 #define CAN_MB15_DATA0 0xFFC02DE0 /* Mailbox 15 Data Word 0 [15:0] Register */ 816 #define CAN_MB15_DATA1 0xFFC02DE4 /* Mailbox 15 Data Word 1 [31:16] Register */ 817 #define CAN_MB15_DATA2 0xFFC02DE8 /* Mailbox 15 Data Word 2 [47:32] Register */ 818 #define CAN_MB15_DATA3 0xFFC02DEC /* Mailbox 15 Data Word 3 [63:48] Register */ 819 #define CAN_MB15_LENGTH 0xFFC02DF0 /* Mailbox 15 Data Length Code Register */ 820 #define CAN_MB15_TIMESTAMP 0xFFC02DF4 /* Mailbox 15 Time Stamp Value Register */ 821 #define CAN_MB15_ID0 0xFFC02DF8 /* Mailbox 15 Identifier Low Register */ 822 #define CAN_MB15_ID1 0xFFC02DFC /* Mailbox 15 Identifier High Register */ 823 824 #define CAN_MB16_DATA0 0xFFC02E00 /* Mailbox 16 Data Word 0 [15:0] Register */ 825 #define CAN_MB16_DATA1 0xFFC02E04 /* Mailbox 16 Data Word 1 [31:16] Register */ 826 #define CAN_MB16_DATA2 0xFFC02E08 /* Mailbox 16 Data Word 2 [47:32] Register */ 827 #define CAN_MB16_DATA3 0xFFC02E0C /* Mailbox 16 Data Word 3 [63:48] Register */ 828 #define CAN_MB16_LENGTH 0xFFC02E10 /* Mailbox 16 Data Length Code Register */ 829 #define CAN_MB16_TIMESTAMP 0xFFC02E14 /* Mailbox 16 Time Stamp Value Register */ 830 #define CAN_MB16_ID0 0xFFC02E18 /* Mailbox 16 Identifier Low Register */ 831 #define CAN_MB16_ID1 0xFFC02E1C /* Mailbox 16 Identifier High Register */ 832 833 #define CAN_MB17_DATA0 0xFFC02E20 /* Mailbox 17 Data Word 0 [15:0] Register */ 834 #define CAN_MB17_DATA1 0xFFC02E24 /* Mailbox 17 Data Word 1 [31:16] Register */ 835 #define CAN_MB17_DATA2 0xFFC02E28 /* Mailbox 17 Data Word 2 [47:32] Register */ 836 #define CAN_MB17_DATA3 0xFFC02E2C /* Mailbox 17 Data Word 3 [63:48] Register */ 837 #define CAN_MB17_LENGTH 0xFFC02E30 /* Mailbox 17 Data Length Code Register */ 838 #define CAN_MB17_TIMESTAMP 0xFFC02E34 /* Mailbox 17 Time Stamp Value Register */ 839 #define CAN_MB17_ID0 0xFFC02E38 /* Mailbox 17 Identifier Low Register */ 840 #define CAN_MB17_ID1 0xFFC02E3C /* Mailbox 17 Identifier High Register */ 841 842 #define CAN_MB18_DATA0 0xFFC02E40 /* Mailbox 18 Data Word 0 [15:0] Register */ 843 #define CAN_MB18_DATA1 0xFFC02E44 /* Mailbox 18 Data Word 1 [31:16] Register */ 844 #define CAN_MB18_DATA2 0xFFC02E48 /* Mailbox 18 Data Word 2 [47:32] Register */ 845 #define CAN_MB18_DATA3 0xFFC02E4C /* Mailbox 18 Data Word 3 [63:48] Register */ 846 #define CAN_MB18_LENGTH 0xFFC02E50 /* Mailbox 18 Data Length Code Register */ 847 #define CAN_MB18_TIMESTAMP 0xFFC02E54 /* Mailbox 18 Time Stamp Value Register */ 848 #define CAN_MB18_ID0 0xFFC02E58 /* Mailbox 18 Identifier Low Register */ 849 #define CAN_MB18_ID1 0xFFC02E5C /* Mailbox 18 Identifier High Register */ 850 851 #define CAN_MB19_DATA0 0xFFC02E60 /* Mailbox 19 Data Word 0 [15:0] Register */ 852 #define CAN_MB19_DATA1 0xFFC02E64 /* Mailbox 19 Data Word 1 [31:16] Register */ 853 #define CAN_MB19_DATA2 0xFFC02E68 /* Mailbox 19 Data Word 2 [47:32] Register */ 854 #define CAN_MB19_DATA3 0xFFC02E6C /* Mailbox 19 Data Word 3 [63:48] Register */ 855 #define CAN_MB19_LENGTH 0xFFC02E70 /* Mailbox 19 Data Length Code Register */ 856 #define CAN_MB19_TIMESTAMP 0xFFC02E74 /* Mailbox 19 Time Stamp Value Register */ 857 #define CAN_MB19_ID0 0xFFC02E78 /* Mailbox 19 Identifier Low Register */ 858 #define CAN_MB19_ID1 0xFFC02E7C /* Mailbox 19 Identifier High Register */ 859 860 #define CAN_MB20_DATA0 0xFFC02E80 /* Mailbox 20 Data Word 0 [15:0] Register */ 861 #define CAN_MB20_DATA1 0xFFC02E84 /* Mailbox 20 Data Word 1 [31:16] Register */ 862 #define CAN_MB20_DATA2 0xFFC02E88 /* Mailbox 20 Data Word 2 [47:32] Register */ 863 #define CAN_MB20_DATA3 0xFFC02E8C /* Mailbox 20 Data Word 3 [63:48] Register */ 864 #define CAN_MB20_LENGTH 0xFFC02E90 /* Mailbox 20 Data Length Code Register */ 865 #define CAN_MB20_TIMESTAMP 0xFFC02E94 /* Mailbox 20 Time Stamp Value Register */ 866 #define CAN_MB20_ID0 0xFFC02E98 /* Mailbox 20 Identifier Low Register */ 867 #define CAN_MB20_ID1 0xFFC02E9C /* Mailbox 20 Identifier High Register */ 868 869 #define CAN_MB21_DATA0 0xFFC02EA0 /* Mailbox 21 Data Word 0 [15:0] Register */ 870 #define CAN_MB21_DATA1 0xFFC02EA4 /* Mailbox 21 Data Word 1 [31:16] Register */ 871 #define CAN_MB21_DATA2 0xFFC02EA8 /* Mailbox 21 Data Word 2 [47:32] Register */ 872 #define CAN_MB21_DATA3 0xFFC02EAC /* Mailbox 21 Data Word 3 [63:48] Register */ 873 #define CAN_MB21_LENGTH 0xFFC02EB0 /* Mailbox 21 Data Length Code Register */ 874 #define CAN_MB21_TIMESTAMP 0xFFC02EB4 /* Mailbox 21 Time Stamp Value Register */ 875 #define CAN_MB21_ID0 0xFFC02EB8 /* Mailbox 21 Identifier Low Register */ 876 #define CAN_MB21_ID1 0xFFC02EBC /* Mailbox 21 Identifier High Register */ 877 878 #define CAN_MB22_DATA0 0xFFC02EC0 /* Mailbox 22 Data Word 0 [15:0] Register */ 879 #define CAN_MB22_DATA1 0xFFC02EC4 /* Mailbox 22 Data Word 1 [31:16] Register */ 880 #define CAN_MB22_DATA2 0xFFC02EC8 /* Mailbox 22 Data Word 2 [47:32] Register */ 881 #define CAN_MB22_DATA3 0xFFC02ECC /* Mailbox 22 Data Word 3 [63:48] Register */ 882 #define CAN_MB22_LENGTH 0xFFC02ED0 /* Mailbox 22 Data Length Code Register */ 883 #define CAN_MB22_TIMESTAMP 0xFFC02ED4 /* Mailbox 22 Time Stamp Value Register */ 884 #define CAN_MB22_ID0 0xFFC02ED8 /* Mailbox 22 Identifier Low Register */ 885 #define CAN_MB22_ID1 0xFFC02EDC /* Mailbox 22 Identifier High Register */ 886 887 #define CAN_MB23_DATA0 0xFFC02EE0 /* Mailbox 23 Data Word 0 [15:0] Register */ 888 #define CAN_MB23_DATA1 0xFFC02EE4 /* Mailbox 23 Data Word 1 [31:16] Register */ 889 #define CAN_MB23_DATA2 0xFFC02EE8 /* Mailbox 23 Data Word 2 [47:32] Register */ 890 #define CAN_MB23_DATA3 0xFFC02EEC /* Mailbox 23 Data Word 3 [63:48] Register */ 891 #define CAN_MB23_LENGTH 0xFFC02EF0 /* Mailbox 23 Data Length Code Register */ 892 #define CAN_MB23_TIMESTAMP 0xFFC02EF4 /* Mailbox 23 Time Stamp Value Register */ 893 #define CAN_MB23_ID0 0xFFC02EF8 /* Mailbox 23 Identifier Low Register */ 894 #define CAN_MB23_ID1 0xFFC02EFC /* Mailbox 23 Identifier High Register */ 895 896 #define CAN_MB24_DATA0 0xFFC02F00 /* Mailbox 24 Data Word 0 [15:0] Register */ 897 #define CAN_MB24_DATA1 0xFFC02F04 /* Mailbox 24 Data Word 1 [31:16] Register */ 898 #define CAN_MB24_DATA2 0xFFC02F08 /* Mailbox 24 Data Word 2 [47:32] Register */ 899 #define CAN_MB24_DATA3 0xFFC02F0C /* Mailbox 24 Data Word 3 [63:48] Register */ 900 #define CAN_MB24_LENGTH 0xFFC02F10 /* Mailbox 24 Data Length Code Register */ 901 #define CAN_MB24_TIMESTAMP 0xFFC02F14 /* Mailbox 24 Time Stamp Value Register */ 902 #define CAN_MB24_ID0 0xFFC02F18 /* Mailbox 24 Identifier Low Register */ 903 #define CAN_MB24_ID1 0xFFC02F1C /* Mailbox 24 Identifier High Register */ 904 905 #define CAN_MB25_DATA0 0xFFC02F20 /* Mailbox 25 Data Word 0 [15:0] Register */ 906 #define CAN_MB25_DATA1 0xFFC02F24 /* Mailbox 25 Data Word 1 [31:16] Register */ 907 #define CAN_MB25_DATA2 0xFFC02F28 /* Mailbox 25 Data Word 2 [47:32] Register */ 908 #define CAN_MB25_DATA3 0xFFC02F2C /* Mailbox 25 Data Word 3 [63:48] Register */ 909 #define CAN_MB25_LENGTH 0xFFC02F30 /* Mailbox 25 Data Length Code Register */ 910 #define CAN_MB25_TIMESTAMP 0xFFC02F34 /* Mailbox 25 Time Stamp Value Register */ 911 #define CAN_MB25_ID0 0xFFC02F38 /* Mailbox 25 Identifier Low Register */ 912 #define CAN_MB25_ID1 0xFFC02F3C /* Mailbox 25 Identifier High Register */ 913 914 #define CAN_MB26_DATA0 0xFFC02F40 /* Mailbox 26 Data Word 0 [15:0] Register */ 915 #define CAN_MB26_DATA1 0xFFC02F44 /* Mailbox 26 Data Word 1 [31:16] Register */ 916 #define CAN_MB26_DATA2 0xFFC02F48 /* Mailbox 26 Data Word 2 [47:32] Register */ 917 #define CAN_MB26_DATA3 0xFFC02F4C /* Mailbox 26 Data Word 3 [63:48] Register */ 918 #define CAN_MB26_LENGTH 0xFFC02F50 /* Mailbox 26 Data Length Code Register */ 919 #define CAN_MB26_TIMESTAMP 0xFFC02F54 /* Mailbox 26 Time Stamp Value Register */ 920 #define CAN_MB26_ID0 0xFFC02F58 /* Mailbox 26 Identifier Low Register */ 921 #define CAN_MB26_ID1 0xFFC02F5C /* Mailbox 26 Identifier High Register */ 922 923 #define CAN_MB27_DATA0 0xFFC02F60 /* Mailbox 27 Data Word 0 [15:0] Register */ 924 #define CAN_MB27_DATA1 0xFFC02F64 /* Mailbox 27 Data Word 1 [31:16] Register */ 925 #define CAN_MB27_DATA2 0xFFC02F68 /* Mailbox 27 Data Word 2 [47:32] Register */ 926 #define CAN_MB27_DATA3 0xFFC02F6C /* Mailbox 27 Data Word 3 [63:48] Register */ 927 #define CAN_MB27_LENGTH 0xFFC02F70 /* Mailbox 27 Data Length Code Register */ 928 #define CAN_MB27_TIMESTAMP 0xFFC02F74 /* Mailbox 27 Time Stamp Value Register */ 929 #define CAN_MB27_ID0 0xFFC02F78 /* Mailbox 27 Identifier Low Register */ 930 #define CAN_MB27_ID1 0xFFC02F7C /* Mailbox 27 Identifier High Register */ 931 932 #define CAN_MB28_DATA0 0xFFC02F80 /* Mailbox 28 Data Word 0 [15:0] Register */ 933 #define CAN_MB28_DATA1 0xFFC02F84 /* Mailbox 28 Data Word 1 [31:16] Register */ 934 #define CAN_MB28_DATA2 0xFFC02F88 /* Mailbox 28 Data Word 2 [47:32] Register */ 935 #define CAN_MB28_DATA3 0xFFC02F8C /* Mailbox 28 Data Word 3 [63:48] Register */ 936 #define CAN_MB28_LENGTH 0xFFC02F90 /* Mailbox 28 Data Length Code Register */ 937 #define CAN_MB28_TIMESTAMP 0xFFC02F94 /* Mailbox 28 Time Stamp Value Register */ 938 #define CAN_MB28_ID0 0xFFC02F98 /* Mailbox 28 Identifier Low Register */ 939 #define CAN_MB28_ID1 0xFFC02F9C /* Mailbox 28 Identifier High Register */ 940 941 #define CAN_MB29_DATA0 0xFFC02FA0 /* Mailbox 29 Data Word 0 [15:0] Register */ 942 #define CAN_MB29_DATA1 0xFFC02FA4 /* Mailbox 29 Data Word 1 [31:16] Register */ 943 #define CAN_MB29_DATA2 0xFFC02FA8 /* Mailbox 29 Data Word 2 [47:32] Register */ 944 #define CAN_MB29_DATA3 0xFFC02FAC /* Mailbox 29 Data Word 3 [63:48] Register */ 945 #define CAN_MB29_LENGTH 0xFFC02FB0 /* Mailbox 29 Data Length Code Register */ 946 #define CAN_MB29_TIMESTAMP 0xFFC02FB4 /* Mailbox 29 Time Stamp Value Register */ 947 #define CAN_MB29_ID0 0xFFC02FB8 /* Mailbox 29 Identifier Low Register */ 948 #define CAN_MB29_ID1 0xFFC02FBC /* Mailbox 29 Identifier High Register */ 949 950 #define CAN_MB30_DATA0 0xFFC02FC0 /* Mailbox 30 Data Word 0 [15:0] Register */ 951 #define CAN_MB30_DATA1 0xFFC02FC4 /* Mailbox 30 Data Word 1 [31:16] Register */ 952 #define CAN_MB30_DATA2 0xFFC02FC8 /* Mailbox 30 Data Word 2 [47:32] Register */ 953 #define CAN_MB30_DATA3 0xFFC02FCC /* Mailbox 30 Data Word 3 [63:48] Register */ 954 #define CAN_MB30_LENGTH 0xFFC02FD0 /* Mailbox 30 Data Length Code Register */ 955 #define CAN_MB30_TIMESTAMP 0xFFC02FD4 /* Mailbox 30 Time Stamp Value Register */ 956 #define CAN_MB30_ID0 0xFFC02FD8 /* Mailbox 30 Identifier Low Register */ 957 #define CAN_MB30_ID1 0xFFC02FDC /* Mailbox 30 Identifier High Register */ 958 959 #define CAN_MB31_DATA0 0xFFC02FE0 /* Mailbox 31 Data Word 0 [15:0] Register */ 960 #define CAN_MB31_DATA1 0xFFC02FE4 /* Mailbox 31 Data Word 1 [31:16] Register */ 961 #define CAN_MB31_DATA2 0xFFC02FE8 /* Mailbox 31 Data Word 2 [47:32] Register */ 962 #define CAN_MB31_DATA3 0xFFC02FEC /* Mailbox 31 Data Word 3 [63:48] Register */ 963 #define CAN_MB31_LENGTH 0xFFC02FF0 /* Mailbox 31 Data Length Code Register */ 964 #define CAN_MB31_TIMESTAMP 0xFFC02FF4 /* Mailbox 31 Time Stamp Value Register */ 965 #define CAN_MB31_ID0 0xFFC02FF8 /* Mailbox 31 Identifier Low Register */ 966 #define CAN_MB31_ID1 0xFFC02FFC /* Mailbox 31 Identifier High Register */ 967 968 /* CAN Mailbox Area Macros */ 969 #define CAN_MB_ID1(x) (CAN_MB00_ID1+((x)*0x20)) 970 #define CAN_MB_ID0(x) (CAN_MB00_ID0+((x)*0x20)) 971 #define CAN_MB_TIMESTAMP(x) (CAN_MB00_TIMESTAMP+((x)*0x20)) 972 #define CAN_MB_LENGTH(x) (CAN_MB00_LENGTH+((x)*0x20)) 973 #define CAN_MB_DATA3(x) (CAN_MB00_DATA3+((x)*0x20)) 974 #define CAN_MB_DATA2(x) (CAN_MB00_DATA2+((x)*0x20)) 975 #define CAN_MB_DATA1(x) (CAN_MB00_DATA1+((x)*0x20)) 976 #define CAN_MB_DATA0(x) (CAN_MB00_DATA0+((x)*0x20)) 977 978 979 980 /* Motor Control PWM1 Registers (0xFFC03000 - 0xFFC030FF) */ 981 #define PWM1_CTRL 0xFFC03000 /* PWM1 Control Register */ 982 #define PWM1_STAT 0xFFC03004 /* PWM1 Status Register */ 983 #define PWM1_TM 0xFFC03008 /* PWM1 Period Register */ 984 #define PWM1_DT 0xFFC0300C /* PWM1 Dead Time Register */ 985 #define PWM1_GATE 0xFFC03010 /* PWM1 Chopping Control */ 986 #define PWM1_CHA 0xFFC03014 /* PWM1 Channel A Duty Control */ 987 #define PWM1_CHB 0xFFC03018 /* PWM1 Channel B Duty Control */ 988 #define PWM1_CHC 0xFFC0301C /* PWM1 Channel C Duty Control */ 989 #define PWM1_SEG 0xFFC03020 /* PWM1 Crossover and Output Enable */ 990 #define PWM1_SYNCWT 0xFFC03024 /* PWM1 Sync pulse width control */ 991 #define PWM1_CHAL 0xFFC03028 /* PWM1 Channel AL Duty Control (SR mode only) */ 992 #define PWM1_CHBL 0xFFC0302C /* PWM1 Channel BL Duty Control (SR mode only) */ 993 #define PWM1_CHCL 0xFFC03030 /* PWM1 Channel CL Duty Control (SR mode only) */ 994 #define PWM1_LSI 0xFFC03034 /* Low Side Invert (SR mode only) */ 995 #define PWM1_STAT2 0xFFC03038 /* PWM1 Status Register */ 996 997 998 /* ADC Controller Module Registers (0xFFC03100 - 0xFFC031FF) */ 999 #define ACM_CTL 0xFFC03100 /* ACM Control Register */ 1000 #define ACM_TC0 0xFFC03104 /* ACM Timing Configuration 0 Register */ 1001 #define ACM_TC1 0xFFC03108 /* ACM Timing Configuration 1 Register */ 1002 #define ACM_STAT 0xFFC0310C /* ACM Status Register */ 1003 #define ACM_ES 0xFFC03110 /* ACM Event Status Register */ 1004 #define ACM_IMSK 0xFFC03114 /* ACM Interrupt Mask Register */ 1005 #define ACM_MS 0xFFC03118 /* ACM Missed Event Status Register */ 1006 #define ACM_EMSK 0xFFC0311C /* ACM Missed Event Interrupt Mask Register */ 1007 1008 #define ACM_ER0 0xFFC03120 /* ACM Event 0 Control Register */ 1009 #define ACM_ER1 0xFFC03124 /* ACM Event 1 Control Register */ 1010 #define ACM_ER2 0xFFC03128 /* ACM Event 2 Control Register */ 1011 #define ACM_ER3 0xFFC0312C /* ACM Event 3 Control Register */ 1012 #define ACM_ER4 0xFFC03130 /* ACM Event 4 Control Register */ 1013 #define ACM_ER5 0xFFC03134 /* ACM Event 5 Control Register */ 1014 #define ACM_ER6 0xFFC03138 /* ACM Event 6 Control Register */ 1015 #define ACM_ER7 0xFFC0313C /* ACM Event 7 Control Register */ 1016 #define ACM_ER8 0xFFC03140 /* ACM Event 8 Control Register */ 1017 #define ACM_ER9 0xFFC03144 /* ACM Event 9 Control Register */ 1018 #define ACM_ER10 0xFFC03148 /* ACM Event 10 Control Register */ 1019 #define ACM_ER11 0xFFC0314C /* ACM Event 11 Control Register */ 1020 #define ACM_ER12 0xFFC03150 /* ACM Event 12 Control Register */ 1021 #define ACM_ER13 0xFFC03154 /* ACM Event 13 Control Register */ 1022 #define ACM_ER14 0xFFC03158 /* ACM Event 14 Control Register */ 1023 #define ACM_ER15 0xFFC0315C /* ACM Event 15 Control Register */ 1024 1025 #define ACM_ET0 0xFFC03180 /* ACM Event 0 Time Register */ 1026 #define ACM_ET1 0xFFC03184 /* ACM Event 1 Time Register */ 1027 #define ACM_ET2 0xFFC03188 /* ACM Event 2 Time Register */ 1028 #define ACM_ET3 0xFFC0318C /* ACM Event 3 Time Register */ 1029 #define ACM_ET4 0xFFC03190 /* ACM Event 4 Time Register */ 1030 #define ACM_ET5 0xFFC03194 /* ACM Event 5 Time Register */ 1031 #define ACM_ET6 0xFFC03198 /* ACM Event 6 Time Register */ 1032 #define ACM_ET7 0xFFC0319C /* ACM Event 7 Time Register */ 1033 #define ACM_ET8 0xFFC031A0 /* ACM Event 8 Time Register */ 1034 #define ACM_ET9 0xFFC031A4 /* ACM Event 9 Time Register */ 1035 #define ACM_ET10 0xFFC031A8 /* ACM Event 10 Time Register */ 1036 #define ACM_ET11 0xFFC031AC /* ACM Event 11 Time Register */ 1037 #define ACM_ET12 0xFFC031B0 /* ACM Event 12 Time Register */ 1038 #define ACM_ET13 0xFFC031B4 /* ACM Event 13 Time Register */ 1039 #define ACM_ET14 0xFFC031B8 /* ACM Event 14 Time Register */ 1040 #define ACM_ET15 0xFFC031BC /* ACM Event 15 Time Register */ 1041 1042 #define ACM_TMR0 0xFFC031C0 /* ACM Timer 0 Registers */ 1043 #define ACM_TMR1 0xFFC031C4 /* ACM Timer 1 Registers */ 1044 1045 1046 /* Pin Control Registers (0xFFC03200 - 0xFFC032FF) */ 1047 #define PORTF_FER 0xFFC03200 /* Port F Function Enable Register (Alternate/Flag*) */ 1048 #define PORTG_FER 0xFFC03204 /* Port G Function Enable Register (Alternate/Flag*) */ 1049 #define PORTH_FER 0xFFC03208 /* Port H Function Enable Register (Alternate/Flag*) */ 1050 1051 1052 /* GPIO PIN mux (0xFFC03210 - OxFFC03288) */ 1053 #define PORTF_MUX 0xFFC03210 /* Port F mux control */ 1054 #define PORTG_MUX 0xFFC03214 /* Port G mux control */ 1055 #define PORTH_MUX 0xFFC03218 /* Port H mux control */ 1056 #define PORTF_HYSTERESIS 0xFFC03240 /* Port F Schmitt trigger control */ 1057 #define PORTG_HYSTERESIS 0xFFC03244 /* Port G Schmitt trigger control */ 1058 #define PORTH_HYSTERESIS 0xFFC03248 /* Port H Schmitt trigger control */ 1059 1060 #define NONGPIO_DRIVE 0xFFC03280 /* Misc Port drive strength control */ 1061 #define NONGPIO_HYSTERESIS 0xFFC03288 /* Misc Port Schmitt Trigger control */ 1062 1063 #define FLASH_CONTROL 0xFFC0328C /* Stacked flash control register */ 1064 #define FLASH_CONTROL_SET 0xFFC03290 /* Stacked flash control set register */ 1065 #define FLASH_CONTROL_CLEAR 0xFFC03294 /* Stacked flash control clear register */ 1066 1067 1068 /* Counter 1 Registers (0xFFC03300 - 0xFFC033FF) */ 1069 #define CNT1_CONFIG 0xFFC03300 /* Counter 1 Configuration Register */ 1070 #define CNT1_IMASK 0xFFC03304 /* Counter 1 Interrupt Mask Register */ 1071 #define CNT1_STATUS 0xFFC03308 /* Counter 1 Status Register */ 1072 #define CNT1_COMMAND 0xFFC0330C /* Counter 1 Command Register */ 1073 #define CNT1_DEBOUNCE 0xFFC03310 /* Counter 1 Debounce Register */ 1074 #define CNT1_COUNTER 0xFFC03314 /* Counter 1 Counter Register */ 1075 #define CNT1_MAX 0xFFC03318 /* Counter 1 Boundry Value Register - max count */ 1076 #define CNT1_MIN 0xFFC0331C /* Counter 1 Boundry Value Register - min count */ 1077 1078 1079 /* SPI1 Controller (0xFFC03400 - 0xFFC034FF) */ 1080 #define SPI1_CTL 0xFFC03400 /* SPI1 Control Register */ 1081 #define SPI1_FLG 0xFFC03404 /* SPI1 Flag register */ 1082 #define SPI1_STAT 0xFFC03408 /* SPI1 Status register */ 1083 #define SPI1_TDBR 0xFFC0340C /* SPI1 Transmit Data Buffer Register */ 1084 #define SPI1_RDBR 0xFFC03410 /* SPI1 Receive Data Buffer Register */ 1085 #define SPI1_BAUD 0xFFC03414 /* SPI1 Baud rate Register */ 1086 #define SPI1_SHADOW 0xFFC03418 /* SPI1_RDBR Shadow Register */ 1087 1088 1089 /* Counter 0 Registers (0xFFC03500 - 0xFFC035FF) */ 1090 #define CNT0_CONFIG 0xFFC03500 /* Counter 0 Configuration Register */ 1091 #define CNT0_IMASK 0xFFC03504 /* Counter 0 Interrupt Mask Register */ 1092 #define CNT0_STATUS 0xFFC03508 /* Counter 0 Status Register */ 1093 #define CNT0_COMMAND 0xFFC0350C /* Counter 0 Command Register */ 1094 #define CNT0_DEBOUNCE 0xFFC03510 /* Counter 0 Debounce Register */ 1095 #define CNT0_COUNTER 0xFFC03514 /* Counter 0 Counter Register */ 1096 #define CNT0_MAX 0xFFC03518 /* Counter 0 Boundry Value Register - max count */ 1097 #define CNT0_MIN 0xFFC0351C /* Counter 0 Boundry Value Register - min count */ 1098 1099 1100 /* Motor Control PWM0 Registers (0xFFC03700 - 0xFFC037FF) */ 1101 #define PWM0_CTRL 0xFFC03700 /* PWM0 Control Register */ 1102 #define PWM0_STAT 0xFFC03704 /* PWM0 Status Register */ 1103 #define PWM0_TM 0xFFC03708 /* PWM0 Period Register */ 1104 #define PWM0_DT 0xFFC0370C /* PWM0 Dead Time Register */ 1105 #define PWM0_GATE 0xFFC03710 /* PWM0 Chopping Control */ 1106 #define PWM0_CHA 0xFFC03714 /* PWM0 Channel A Duty Control */ 1107 #define PWM0_CHB 0xFFC03718 /* PWM0 Channel B Duty Control */ 1108 #define PWM0_CHC 0xFFC0371C /* PWM0 Channel C Duty Control */ 1109 #define PWM0_SEG 0xFFC03720 /* PWM0 Crossover and Output Enable */ 1110 #define PWM0_SYNCWT 0xFFC03724 /* PWM0 Sync pulse width control */ 1111 #define PWM0_CHAL 0xFFC03728 /* PWM0 Channel AL Duty Control (SR mode only) */ 1112 #define PWM0_CHBL 0xFFC0372C /* PWM0 Channel BL Duty Control (SR mode only) */ 1113 #define PWM0_CHCL 0xFFC03730 /* PWM0 Channel CL Duty Control (SR mode only) */ 1114 #define PWM0_LSI 0xFFC03734 /* Low Side Invert (SR mode only) */ 1115 #define PWM0_STAT2 0xFFC03738 /* PWM0 Status Register */ 1116 1117 1118 /* RSI Registers (0xFFC03800 - 0xFFC03CFF) */ 1119 #define RSI_PWR_CONTROL 0xFFC03800 /* RSI Power Control Register */ 1120 /* legacy register name (below) provided for backwards code compatibility */ 1121 #define SDH_PWR_CTL (RSI_PWR_CONTROL)/* SDH Power Control */ 1122 #define RSI_CLK_CONTROL 0xFFC03804 /* RSI Clock Control Register */ 1123 /* legacy register name (below) provided for backwards code compatibility */ 1124 #define SDH_CLK_CTL (RSI_CLK_CONTROL)/* SDH Clock Control */ 1125 #define RSI_ARGUMENT 0xFFC03808 /* RSI Argument Register */ 1126 /* legacy register name (below) provided for backwards code compatibility */ 1127 #define SDH_ARGUMENT (RSI_ARGUMENT) /* SDH Argument */ 1128 #define RSI_COMMAND 0xFFC0380C /* RSI Command Register */ 1129 /* legacy register name (below) provided for backwards code compatibility */ 1130 #define SDH_COMMAND (RSI_COMMAND) /* SDH Command */ 1131 #define RSI_RESP_CMD 0xFFC03810 /* RSI Response Command Register */ 1132 /* legacy register name (below) provided for backwards code compatibility */ 1133 #define SDH_RESP_CMD (RSI_RESP_CMD) /* SDH Response Command */ 1134 #define RSI_RESPONSE0 0xFFC03814 /* RSI Response Register */ 1135 /* legacy register name (below) provided for backwards code compatibility */ 1136 #define SDH_RESPONSE0 (RSI_RESPONSE0) /* SDH Response0 */ 1137 #define RSI_RESPONSE1 0xFFC03818 /* RSI Response Register */ 1138 /* legacy register name (below) provided for backwards code compatibility */ 1139 #define SDH_RESPONSE1 (RSI_RESPONSE1) /* SDH Response1 */ 1140 #define RSI_RESPONSE2 0xFFC0381C /* RSI Response Register */ 1141 /* legacy register name (below) provided for backwards code compatibility */ 1142 #define SDH_RESPONSE2 (RSI_RESPONSE2) /* SDH Response2 */ 1143 #define RSI_RESPONSE3 0xFFC03820 /* RSI Response Register */ 1144 /* legacy register name (below) provided for backwards code compatibility */ 1145 #define SDH_RESPONSE3 (RSI_RESPONSE3) /* SDH Response3 */ 1146 #define RSI_DATA_TIMER 0xFFC03824 /* RSI Data Timer Register */ 1147 /* legacy register name (below) provided for backwards code compatibility */ 1148 #define SDH_DATA_TIMER (RSI_DATA_TIMER) /* SDH Data Timer */ 1149 #define RSI_DATA_LGTH 0xFFC03828 /* RSI Data Length Register */ 1150 /* legacy register name (below) provided for backwards code compatibility */ 1151 #define SDH_DATA_LGTH (RSI_DATA_LGTH) /* SDH Data Length */ 1152 #define RSI_DATA_CONTROL 0xFFC0382C /* RSI Data Control Register */ 1153 /* legacy register name (below) provided for backwards code compatibility */ 1154 #define SDH_DATA_CTL (RSI_DATA_CONTROL) /* SDH Data Control */ 1155 #define RSI_DATA_CNT 0xFFC03830 /* RSI Data Counter Register */ 1156 /* legacy register name (below) provided for backwards code compatibility */ 1157 #define SDH_DATA_CNT (RSI_DATA_CNT) /* SDH Data Counter */ 1158 #define RSI_STATUS 0xFFC03834 /* RSI Status Register */ 1159 /* legacy register name (below) provided for backwards code compatibility */ 1160 #define SDH_STATUS (RSI_STATUS) /* SDH Status */ 1161 #define RSI_STATUSCL 0xFFC03838 /* RSI Status Clear Register */ 1162 /* legacy register name (below) provided for backwards code compatibility */ 1163 #define SDH_STATUS_CLR (RSI_STATUSCL) /* SDH Status Clear */ 1164 #define RSI_MASK0 0xFFC0383C /* RSI Interrupt 0 Mask Register */ 1165 /* legacy register name (below) provided for backwards code compatibility */ 1166 #define SDH_MASK0 (RSI_MASK0) /* SDH Interrupt0 Mask */ 1167 #define RSI_MASK1 0xFFC03840 /* RSI Interrupt 1 Mask Register */ 1168 /* legacy register name (below) provided for backwards code compatibility */ 1169 #define SDH_MASK1 (RSI_MASK1) /* SDH Interrupt1 Mask */ 1170 #define RSI_FIFO_CNT 0xFFC03848 /* RSI FIFO Counter Register */ 1171 /* legacy register name (below) provided for backwards code compatibility */ 1172 #define SDH_FIFO_CNT (RSI_FIFO_CNT) /* SDH FIFO Counter */ 1173 #define RSI_CEATA_CONTROL 0xFFC0384C /* RSI CEATA Register */ 1174 #define RSI_FIFO 0xFFC03880 /* RSI Data FIFO Register */ 1175 /* legacy register name (below) provided for backwards code compatibility */ 1176 #define SDH_FIFO (RSI_FIFO) /* SDH Data FIFO */ 1177 #define RSI_ESTAT 0xFFC038C0 /* RSI Exception Status Register */ 1178 /* legacy register name (below) provided for backwards code compatibility */ 1179 #define SDH_E_STATUS (RSI_ESTAT) /* SDH Exception Status */ 1180 #define RSI_EMASK 0xFFC038C4 /* RSI Exception Mask Register */ 1181 /* legacy register name (below) provided for backwards code compatibility */ 1182 #define SDH_E_MASK (RSI_EMASK) /* SDH Exception Mask */ 1183 #define RSI_CONFIG 0xFFC038C8 /* RSI Configuration Register */ 1184 /* legacy register name (below) provided for backwards code compatibility */ 1185 #define SDH_CFG (RSI_CONFIG) /* SDH Configuration */ 1186 #define RSI_RD_WAIT_EN 0xFFC038CC /* RSI Read Wait Enable Register */ 1187 /* legacy register name (below) provided for backwards code compatibility */ 1188 #define SDH_RD_WAIT_EN (RSI_RD_WAIT_EN) /* SDH Read Wait Enable */ 1189 #define RSI_PID0 0xFFC038D0 /* RSI Peripheral ID Register 0 */ 1190 /* legacy register name (below) provided for backwards code compatibility */ 1191 #define SDH_PID0 (RSI_PID0) /* SDH Peripheral Identification0 */ 1192 #define RSI_PID1 0xFFC038D4 /* RSI Peripheral ID Register 1 */ 1193 /* legacy register name (below) provided for backwards code compatibility */ 1194 #define SDH_PID1 (RSI_PID1) /* SDH Peripheral Identification1 */ 1195 #define RSI_PID2 0xFFC038D8 /* RSI Peripheral ID Register 2 */ 1196 /* legacy register name (below) provided for backwards code compatibility */ 1197 #define SDH_PID2 (RSI_PID2) /* SDH Peripheral Identification2 */ 1198 #define RSI_PID3 0xFFC038DC /* RSI Peripheral ID Register 3 */ 1199 /* legacy register name (below) provided for backwards code compatibility */ 1200 #define SDH_PID3 (RSI_PID3) /* SDH Peripheral Identification3 */ 1201 1202 1203 /****************************************************************************************************************** 1204 ** System MMR Register Bits And Macros 1205 ** 1206 ** Disclaimer: All macros are intended to make C and Assembly code more readable. 1207 ** Use these macros carefully, as any that do left shifts for field 1208 ** depositing will result in the lower order bits being destroyed. Any 1209 ** macro that shifts left to properly position the bit-field should be 1210 ** used as part of an OR to initialize a register and NOT as a dynamic 1211 ** modifier UNLESS the lower order bits are saved and ORed back in when 1212 ** the macro is used. 1213 *******************************************************************************************************************/ 1214 1215 /************************************** PLL AND RESET MASKS *******************************************************/ 1216 1217 /* PLL_CTL Masks */ 1218 #define DF 0x0001 /* 0: PLL = CLKIN, 1: PLL = CLKIN/2 */ 1219 #define PLL_OFF 0x0002 /* PLL Not Powered */ 1220 #define STOPCK 0x0008 /* Core Clock Off */ 1221 #define PDWN 0x0020 /* Enter Deep Sleep Mode */ 1222 #define IN_DELAY 0x0040 /* Add 200ps Delay To EBIU Input Latches */ 1223 #define OUT_DELAY 0x0080 /* Add 200ps Delay To EBIU Output Signals */ 1224 #define BYPASS 0x0100 /* Bypass the PLL */ 1225 #define MSEL 0x7E00 /* Multiplier Select For CCLK/VCO Factors */ 1226 1227 /* PLL_CTL Macros (Only Use With Logic OR While Setting Lower Order Bits) */ 1228 #ifdef _MISRA_RULES 1229 #define SET_MSEL(x) (((x)&0x3Fu) << 0x9) /* Set MSEL = 0-63 --> VCO = CLKIN*MSEL */ 1230 #else 1231 #define SET_MSEL(x) (((x)&0x3F) << 0x9) /* Set MSEL = 0-63 --> VCO = CLKIN*MSEL */ 1232 #endif /* _MISRA_RULES */ 1233 1234 /* PLL_DIV Masks */ 1235 #define SSEL 0x000F /* System Select */ 1236 #define CSEL 0x0030 /* Core Select */ 1237 #define CSEL_DIV1 0x0000 /* CCLK = VCO / 1 */ 1238 #define CSEL_DIV2 0x0010 /* CCLK = VCO / 2 */ 1239 #define CSEL_DIV4 0x0020 /* CCLK = VCO / 4 */ 1240 #define CSEL_DIV8 0x0030 /* CCLK = VCO / 8 */ 1241 1242 /* PLL_DIV Macros */ 1243 #ifdef _MISRA_RULES 1244 #define SET_SSEL(x) ((x)&0xFu) /* Set SSEL = 0-15 --> SCLK = VCO/SSEL */ 1245 #else 1246 #define SET_SSEL(x) ((x)&0xF) /* Set SSEL = 0-15 --> SCLK = VCO/SSEL */ 1247 #endif /* _MISRA_RULES */ 1248 1249 /* VR_CTL Masks */ 1250 #define WAKE_POLARITY 0x8000 /* GPIO wakeup active level */ 1251 #define EXTCLK_OE 0x4000 /* Enable/disable EXTCLK */ 1252 #define EXTCLK_SEL 0x2000 /* EXTCLK Select */ 1253 #define HIBERNATEB 0x1000 /* Bit mask for HIBERNATEB */ 1254 #define HIBERNATE 0x0000 /* Enter Hibernate - this bit is active LOW */ 1255 #define WAKE_EN0 0x0100 /* Enable Wakeup From Hibernate/Deep Sleep on the WAKEN0 signal */ 1256 #define WAKE_EN1 0x0200 /* Enable Wakeup From Hibernate/Deep Sleep on the WAKEN1 signal */ 1257 #define CANWE 0x0400 /* CAN Rx Wakeup Enable */ 1258 #define WAKE_EN2 0x0800 /* Enable Wakeup From Hibernate/Deep Sleep on the WAKEN3 signal */ 1259 1260 /* PLL_STAT Masks */ 1261 #define ACTIVE_PLLENABLED 0x0001 /* Processor In Active Mode With PLL Enabled */ 1262 #define FULL_ON 0x0002 /* Processor In Full On Mode */ 1263 #define ACTIVE_PLLDISABLED 0x0004 /* Processor In Active Mode With PLL Disabled */ 1264 #define PLL_LOCKED 0x0020 /* PLL_LOCKCNT Has Been Reached */ 1265 1266 /* SWRST Masks */ 1267 #define SYSTEM_RESET 0x0007 /* Initiates A System Software Reset */ 1268 #define DOUBLE_FAULT 0x0008 /* Core Double Fault Causes Reset */ 1269 #define RESET_DOUBLE 0x2000 /* SW Reset Generated By Core Double-Fault */ 1270 #define RESET_WDOG 0x4000 /* SW Reset Generated By Watchdog Timer */ 1271 #define RESET_SOFTWARE 0x8000 /* SW Reset Occurred Since Last Read Of SWRST */ 1272 1273 /* SYSCR Masks */ 1274 #define BMODE_BYPASS 0x0000 /* Bypass boot ROM, execute from 16-bit external memory */ 1275 #define BMODE_FLASH_ASYNC 0x0001 /* Boot from stacked parallel flash in asynchornous mode */ 1276 #define BMODE_FLASH_SYNC 0x0002 /* Boot from stacked parallel flash in synchornous mode */ 1277 #define BMODE_SPIMEM 0x0003 /* Boot from serial SPI memory (master mode) */ 1278 #define BMODE_SPIHOST 0x0004 /* Boot from SPI0 host (slave mode) */ 1279 #define BMODE_PPIHOST 0x0005 /* Boot from PPI host */ 1280 #define BMODE_UART0HOST 0x0007 /* Boot from UART0 host */ 1281 1282 #define BMODE 0x000F /* Boot Mode. Mirror of BMODE Mode Pins */ 1283 1284 #define BCODE 0x00F0 1285 #define BCODE_NORMAL 0x0000 /* normal boot, update PLL/VR, quickboot as by WURESET */ 1286 #define BCODE_NOBOOT 0x0010 /* bypass boot, don't update PLL/VR */ 1287 #define BCODE_QUICKBOOT 0x0020 /* quick boot, overrule WURESET, don't update PLL/VR */ 1288 #define BCODE_ALLBOOT 0x0040 /* no quick boot, overrule WURESET, don't update PLL/VR */ 1289 #define BCODE_FULLBOOT 0x0060 /* no quick boot, overrule WURESET, update PLL/VR */ 1290 1291 #define WURESET 0x1000 /* wakeup event since last hardware reset */ 1292 #define DFRESET 0x2000 /* recent reset was due to a double fault event */ 1293 #define WDRESET 0x4000 /* recent reset was due to a watchdog event */ 1294 #define SWRESET 0x8000 /* recent reset was issued by software */ 1295 1296 /********************************* SYSTEM INTERRUPT CONTROLLER MASKS *********************************************/ 1297 1298 /* Peripheral Masks For SIC_ISR0, SIC_IWR0, SIC_IMASK0 */ 1299 #define IRQ_PLL_WAKEUP 0x00000001 /* PLL Wakeup Interrupt */ 1300 #define IRQ_DMA_ERR0 0x00000002 /* Error Interrupt (DMA error interrupt (generic)) */ 1301 #define IRQ_PPI_ERR 0x00000004 /* Error Interrupt (PPI error interrupt) */ 1302 #define IRQ_SPORT0_ERR 0x00000008 /* Error Interrupt (SPORT0 status interrupt) */ 1303 #define IRQ_SPORT1_ERR 0x00000010 /* Error Interrupt (SPORT1 status interrupt) */ 1304 #define IRQ_UART0_ERR 0x00000020 /* Error Interrupt (UART0 status interrupt) */ 1305 #define IRQ_UART1_ERR 0x00000040 /* Error Interrupt (UART1 status interrupt) */ 1306 #define IRQ_SPI0_ERR 0x00000080 /* Error Interrupt (SPI0 status interrupt) */ 1307 #define IRQ_SPI1_ERR 0x00000100 /* Error Interrupt (SPI1 status interrupt) */ 1308 #define IRQ_CAN_ERR 0x00000200 /* Error Interrupt (CAN status interrupt) */ 1309 #define IRQ_RSI_INT0 0x00000400 /* RSI Mask 0 Interrupt */ 1310 /* Bit 11 is reserved */ 1311 #define IRQ_CNT0 0x00001000 /* GP Counter 0 Interrupt */ 1312 #define IRQ_CNT1 0x00002000 /* GP Counter 1 Interrupt */ 1313 #define IRQ_DMA0 0x00004000 /* DMA Channel 0 (PPI Rx/Tx) Interrupt */ 1314 #define IRQ_DMA1 0x00008000 /* DMA Channel 1 (RSI Rx/Tx) Interrupt */ 1315 #define IRQ_DMA2 0x00010000 /* DMA Channel 2 (SPORT0 Rx) Interrupt */ 1316 #define IRQ_DMA3 0x00020000 /* DMA Channel 3 (SPORT0 Tx) Interrupt */ 1317 #define IRQ_DMA4 0x00040000 /* DMA Channel 4 (SPORT1 Rx) Interrupt */ 1318 #define IRQ_DMA5 0x00080000 /* DMA Channel 5 (SPORT1 Tx) Interrupt */ 1319 #define IRQ_DMA6 0x00100000 /* DMA Channel 6 (SPI0 Rx/Tx) Interrupt */ 1320 #define IRQ_DMA7 0x00200000 /* DMA Channel 7 (SPI1 Rx/Tx) Interrupt */ 1321 #define IRQ_DMA8 0x00400000 /* DMA Channel 8 (UART0 Rx) Interrupt */ 1322 #define IRQ_DMA9 0x00800000 /* DMA Channel 9 (UART0 Tx) Interrupt */ 1323 #define IRQ_DMA10 0x01000000 /* DMA Channel 10 (UART1 Rx) Interrupt */ 1324 #define IRQ_DMA11 0x02000000 /* DMA Channel 11 (UART1 Tx) Interrupt */ 1325 #define IRQ_CAN_RX 0x04000000 /* CAN Rx Interrupt */ 1326 #define IRQ_CAN_TX 0x08000000 /* CAN Tx Interrupt */ 1327 #define IRQ_TWI 0x10000000 /* TWI Interrupt */ 1328 #define IRQ_PFA_PORTF 0x20000000 /* PF Port F Interrupt A */ 1329 #define IRQ_PFB_PORTF 0x40000000 /* PF Port F Interrupt B */ 1330 /* Bit 31 is reserved */ 1331 1332 1333 /* Peripheral Masks For SIC_ISR1, SIC_IWR1, SIC_IMASK1 */ 1334 #define IRQ_TIMER0 0x00000001 /* Timer 0 Interrupt */ 1335 #define IRQ_TIMER1 0x00000002 /* Timer 1 Interrupt */ 1336 #define IRQ_TIMER2 0x00000004 /* Timer 2 Interrupt */ 1337 #define IRQ_TIMER3 0x00000008 /* Timer 3 Interrupt */ 1338 #define IRQ_TIMER4 0x00000010 /* Timer 4 Interrupt */ 1339 #define IRQ_TIMER5 0x00000020 /* Timer 5 Interrupt */ 1340 #define IRQ_TIMER6 0x00000040 /* Timer 6 Interrupt */ 1341 #define IRQ_TIMER7 0x00000080 /* Timer 7 Interrupt */ 1342 #define IRQ_PFA_PORTG 0x00000100 /* PF Port G Interrupt A */ 1343 #define IRQ_PFB_PORTG 0x00000200 /* PF Port G Interrupt B */ 1344 #define IRQ_DMA12 0x00000400 /* DMA Channel 12 (MDMA0 Destination) Rx Interrupt */ 1345 #define IRQ_DMA13 0x00000400 /* DMA Channel 13 (MDMA0 Source) Tx Interrupt */ 1346 #define IRQ_DMA14 0x00000800 /* DMA Channels 14 (MDMA1 Destination) Rx Interrupt */ 1347 #define IRQ_DMA15 0x00000800 /* DMA Channels 15 (MDMA1 Source) Tx Interrupt */ 1348 #define IRQ_WDOG 0x00001000 /* Software Watchdog Timer Interrupt */ 1349 #define IRQ_PFA_PORTH 0x00002000 /* PF Port H Interrupt A */ 1350 #define IRQ_PFB_PORTH 0x00004000 /* PF Port H Interrupt B */ 1351 #define IRQ_ACM_ERR 0x00008000 /* Error Interrupt (ACM status interrupt) */ 1352 #define IRQ_ACM 0x00010000 /* ACM (ADC Controller Module) Interrupt */ 1353 /* Bit 49 is reserved */ 1354 /* Bit 50 is reserved */ 1355 #define IRQ_PWM0_TRIPINT 0x00080000 /* PWM 0 Trip Interrupt */ 1356 #define IRQ_PWM0_SYNCINT 0x00100000 /* PWM 0 Sync Interrupt */ 1357 #define IRQ_PWM1_TRIPINT 0x00200000 /* PWM 1 Trip Interrupt */ 1358 #define IRQ_PWM1_SYNCINT 0x00400000 /* PWM 1 Sync Interrupt */ 1359 #define IRQ_RSI_INT1 0x00800000 /* RSI Mask 1 interrupt */ 1360 /* Bits 63:56 are reserved */ 1361 1362 1363 /* Peripheral Masks For SIC_ISR, SIC_IWR, SIC_IMASK */ 1364 #define IWR_DISABLE_ALL 0x00000000 /* Wakeup Disable all peripherals */ 1365 #define IWR_ENABLE_ALL 0xFFFFFFFF /* Wakeup Enable all peripherals */ 1366 /* x = pos 0 to 31, for 32-63 use value-32 */ 1367 #define IWR_ENABLE(x) (1 << (x)) /* Wakeup Enable Peripheral #x */ 1368 #define IWR_DISABLE(x) (0xFFFFFFFF^(1<<(x))) /* Wakeup Disable Peripheral #x */ 1369 1370 #ifdef _MISRA_RULES 1371 #define _MF15 0xFu 1372 #define _MF7 7u 1373 #else 1374 #define _MF15 0xF 1375 #define _MF7 7 1376 #endif /* _MISRA_RULES */ 1377 1378 1379 /* SIC_IAR0 Macros*/ 1380 #define P0_IVG(x) (((x)&_MF15)-_MF7) /* Peripheral #0 assigned IVG #x */ 1381 #define P1_IVG(x) ((((x)&_MF15)-_MF7) << 0x4) /* Peripheral #1 assigned IVG #x */ 1382 #define P2_IVG(x) ((((x)&_MF15)-_MF7) << 0x8) /* Peripheral #2 assigned IVG #x */ 1383 #define P3_IVG(x) ((((x)&_MF15)-_MF7) << 0xC) /* Peripheral #3 assigned IVG #x */ 1384 #define P4_IVG(x) ((((x)&_MF15)-_MF7) << 0x10) /* Peripheral #4 assigned IVG #x */ 1385 #define P5_IVG(x) ((((x)&_MF15)-_MF7) << 0x14) /* Peripheral #5 assigned IVG #x */ 1386 #define P6_IVG(x) ((((x)&_MF15)-_MF7) << 0x18) /* Peripheral #6 assigned IVG #x */ 1387 #define P7_IVG(x) ((((x)&_MF15)-_MF7) << 0x1C) /* Peripheral #7 assigned IVG #x */ 1388 1389 /* SIC_IAR1 Macros*/ 1390 #define P8_IVG(x) (((x)&_MF15)-_MF7) /* Peripheral #8 assigned IVG #x */ 1391 #define P9_IVG(x) ((((x)&_MF15)-_MF7) << 0x4) /* Peripheral #9 assigned IVG #x */ 1392 #define P10_IVG(x) ((((x)&_MF15)-_MF7) << 0x8) /* Peripheral #10 assigned IVG #x */ 1393 #define P11_IVG(x) /* Reserved */ 1394 #define P12_IVG(x) ((((x)&_MF15)-_MF7) << 0x10) /* Peripheral #12 assigned IVG #x */ 1395 #define P13_IVG(x) ((((x)&_MF15)-_MF7) << 0x14) /* Peripheral #13 assigned IVG #x */ 1396 #define P14_IVG(x) ((((x)&_MF15)-_MF7) << 0x18) /* Peripheral #14 assigned IVG #x */ 1397 #define P15_IVG(x) ((((x)&_MF15)-_MF7) << 0x1C) /* Peripheral #15 assigned IVG #x */ 1398 1399 /* SIC_IAR2 Macros*/ 1400 #define P16_IVG(x) (((x)&_MF15)-_MF7) /* Peripheral #16 assigned IVG #x */ 1401 #define P17_IVG(x) ((((x)&_MF15)-_MF7) << 0x4) /* Peripheral #17 assigned IVG #x */ 1402 #define P18_IVG(x) ((((x)&_MF15)-_MF7) << 0x8) /* Peripheral #18 assigned IVG #x */ 1403 #define P19_IVG(x) ((((x)&_MF15)-_MF7) << 0xC) /* Peripheral #19 assigned IVG #x */ 1404 #define P20_IVG(x) ((((x)&_MF15)-_MF7) << 0x10) /* Peripheral #20 assigned IVG #x */ 1405 #define P21_IVG(x) ((((x)&_MF15)-_MF7) << 0x14) /* Peripheral #21 assigned IVG #x */ 1406 #define P22_IVG(x) ((((x)&_MF15)-_MF7) << 0x18) /* Peripheral #22 assigned IVG #x */ 1407 #define P23_IVG(x) ((((x)&_MF15)-_MF7) << 0x1C) /* Peripheral #23 assigned IVG #x */ 1408 1409 1410 /* SIC_IAR3 Macros*/ 1411 #define P24_IVG(x) (((x)&_MF15)-_MF7) /* Peripheral #24 assigned IVG #x */ 1412 #define P25_IVG(x) ((((x)&_MF15)-_MF7) << 0x4) /* Peripheral #25 assigned IVG #x */ 1413 #define P26_IVG(x) ((((x)&_MF15)-_MF7) << 0x8) /* Peripheral #26 assigned IVG #x */ 1414 #define P27_IVG(x) ((((x)&_MF15)-_MF7) << 0xC) /* Peripheral #27 assigned IVG #x */ 1415 #define P28_IVG(x) ((((x)&_MF15)-_MF7) << 0x10) /* Peripheral #28 assigned IVG #x */ 1416 #define P29_IVG(x) ((((x)&_MF15)-_MF7) << 0x14) /* Peripheral #29 assigned IVG #x */ 1417 #define P30_IVG(x) ((((x)&_MF15)-_MF7) << 0x18) /* Peripheral #30 assigned IVG #x */ 1418 #define P31_IVG(x) /* Reserved */ 1419 1420 /* SIC_IAR4 Macros*/ 1421 #define P32_IVG(x) (((x)&_MF15)-_MF7) /* Peripheral #32 assigned IVG #x */ 1422 #define P33_IVG(x) ((((x)&_MF15)-_MF7) << 0x4) /* Peripheral #33 assigned IVG #x */ 1423 #define P34_IVG(x) ((((x)&_MF15)-_MF7) << 0x8) /* Peripheral #34 assigned IVG #x */ 1424 #define P35_IVG(x) ((((x)&_MF15)-_MF7) << 0xC) /* Peripheral #35 assigned IVG #x */ 1425 #define P36_IVG(x) ((((x)&_MF15)-_MF7) << 0x10) /* Peripheral #36 assigned IVG #x */ 1426 #define P37_IVG(x) ((((x)&_MF15)-_MF7) << 0x14) /* Peripheral #37 assigned IVG #x */ 1427 #define P38_IVG(x) ((((x)&_MF15)-_MF7) << 0x18) /* Peripheral #38 assigned IVG #x */ 1428 #define P39_IVG(x) ((((x)&_MF15)-_MF7) << 0x1C) /* Peripheral #39 assigned IVG #x */ 1429 1430 /* SIC_IAR5 Macros*/ 1431 #define P40_IVG(x) (((x)&_MF15)-_MF7) /* Peripheral #40 assigned IVG #x */ 1432 #define P41_IVG(x) ((((x)&_MF15)-_MF7) << 0x4) /* Peripheral #41 assigned IVG #x */ 1433 #define P42_IVG(x) ((((x)&_MF15)-_MF7) << 0x8) /* Peripheral #42 assigned IVG #x */ 1434 #define P43_IVG(x) ((((x)&_MF15)-_MF7) << 0xC) /* Peripheral #43 assigned IVG #x */ 1435 #define P44_IVG(x) ((((x)&_MF15)-_MF7) << 0x10) /* Peripheral #44 assigned IVG #x */ 1436 #define P45_IVG(x) ((((x)&_MF15)-_MF7) << 0x14) /* Peripheral #45 assigned IVG #x */ 1437 #define P46_IVG(x) ((((x)&_MF15)-_MF7) << 0x18) /* Peripheral #46 assigned IVG #x */ 1438 #define P47_IVG(x) ((((x)&_MF15)-_MF7) << 0x1C) /* Peripheral #47 assigned IVG #x */ 1439 1440 /* SIC_IAR6 Macros*/ 1441 #define P48_IVG(x) (((x)&_MF15)-_MF7) /* Peripheral #48 assigned IVG #x */ 1442 #define P49_IVG(x) /* Reserved */ 1443 #define P50_IVG(x) /* Reserved */ 1444 #define P51_IVG(x) ((((x)&_MF15)-_MF7) << 0xC) /* Peripheral #51 assigned IVG #x */ 1445 #define P52_IVG(x) ((((x)&_MF15)-_MF7) << 0x10) /* Peripheral #52 assigned IVG #x */ 1446 #define P53_IVG(x) ((((x)&_MF15)-_MF7) << 0x14) /* Peripheral #53 assigned IVG #x */ 1447 #define P54_IVG(x) ((((x)&_MF15)-_MF7) << 0x18) /* Peripheral #54 assigned IVG #x */ 1448 #define P55_IVG(x) ((((x)&_MF15)-_MF7) << 0x1C) /* Peripheral #55 assigned IVG #x */ 1449 1450 1451 /* SIC_IMASK0 Masks*/ 1452 #define SIC_UNMASK0_ALL 0x00000000 /* Unmask all peripheral interrupts */ 1453 #define SIC_MASK0_ALL 0xEFFFF7FF /* Mask all peripheral interrupts */ 1454 1455 #if 0 /* scheduled for removal */ 1456 #ifdef _MISRA_RULES 1457 #define SIC_MASK0(x) (1 << ((x)&0x1Fu)) /* Mask Peripheral #x interrupt */ 1458 #define SIC_UNMASK0(x) (0xFFFFFFFFu ^ (1 << ((x)&0x1Fu)))/*Unmask Peripheral #x interrupt*/ 1459 #else 1460 #define SIC_MASK0(x) (1 << ((x)&0x1F)) /* Mask Peripheral #x interrupt */ 1461 #define SIC_UNMASK0(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F)))/* Unmask Peripheral #x interrupt */ 1462 #endif /* _MISRA_RULES */ 1463 #endif 1464 1465 /* SIC_IMASK1 Masks*/ 1466 #define SIC_UNMASK1_ALL 0x00000000 /* Unmask all peripheral interrupts */ 1467 #define SIC_MASK1_ALL 0x00F9FFFF /* Mask all peripheral interrupts */ 1468 1469 #if 0 /* scheduled for removal */ 1470 #ifdef _MISRA_RULES 1471 #define SIC_MASK1(x) (1 << ((x)&0x1Fu)) /* Mask Peripheral #x interrupt */ 1472 #define SIC_UNMASK1(x) (0xFFFFFFFFu ^ (1 << ((x)&0x1Fu)))/*Unmask Peripheral #x interrupt*/ 1473 #else 1474 #define SIC_MASK1(x) (1 << ((x)&0x1F)) /* Mask Peripheral #x interrupt */ 1475 #define SIC_UNMASK1(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F)))/* Unmask Peripheral #x interrupt */ 1476 #endif /* _MISRA_RULES */ 1477 #endif 1478 1479 1480 /* SIC_IWR0 Masks*/ 1481 #define IWR0_DISABLE_ALL 0x00000000 /* Wakeup Disable all peripherals */ 1482 #define IWR0_ENABLE_ALL 0xEFFFF7FF /* Wakeup Enable all peripherals */ 1483 1484 #if 0 /* scheduled for removal */ 1485 #ifdef _MISRA_RULES 1486 #define IWR0_ENABLE(x) (1 << ((x)&0x1Fu)) /* Wakeup Enable Peripheral #x */ 1487 #define IWR0_DISABLE(x) (0xFFFFFFFFu ^ (1 << ((x)&0x1Fu)))/*Wakeup Disable Peripheral #x */ 1488 #else 1489 #define IWR0_ENABLE(x) (1 << ((x)&0x1F)) /* Wakeup Enable Peripheral #x */ 1490 #define IWR0_DISABLE(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F)))/* Wakeup Disable Peripheral #x */ 1491 #endif /* _MISRA_RULES */ 1492 #endif 1493 1494 /* SIC_IWR1 Masks*/ 1495 #define IWR1_DISABLE_ALL 0x00000000 /* Wakeup Disable all peripherals */ 1496 #define IWR1_ENABLE_ALL 0x00F9FFFF /* Wakeup Enable all peripherals */ 1497 1498 #if 0 /* scheduled for removal */ 1499 #ifdef _MISRA_RULES 1500 #define IWR1_ENABLE(x) (1 << ((x)&0x1Fu)) /* Wakeup Enable Peripheral #x */ 1501 #define IWR1_DISABLE(x) (0xFFFFFFFFu ^ (1 << ((x)&0x1Fu)))/* Wakeup Disable Peripheral #x*/ 1502 #else 1503 #define IWR1_ENABLE(x) (1 << ((x)&0x1F)) /* Wakeup Enable Peripheral #x */ 1504 #define IWR1_DISABLE(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F)))/* Wakeup Disable Peripheral #x */ 1505 #endif /* _MISRA_RULES */ 1506 #endif 1507 1508 1509 /* ************************************** WATCHDOG TIMER MASKS ****************************************************/ 1510 1511 /* Watchdog Timer WDOG_CTL Register Masks */ 1512 #ifdef _MISRA_RULES 1513 #define WDEV(x) (((x)<<1) & 0x0006u) /* event generated on roll over */ 1514 #else 1515 #define WDEV(x) (((x)<<1) & 0x0006) /* event generated on roll over */ 1516 #endif /* _MISRA_RULES */ 1517 1518 #define WDEV_RESET 0x0000 /* generate reset event on roll over */ 1519 #define WDEV_NMI 0x0002 /* generate NMI event on roll over */ 1520 #define WDEV_GPI 0x0004 /* generate GP IRQ on roll over */ 1521 #define WDEV_NONE 0x0006 /* no event on roll over */ 1522 #define WDEN 0x0FF0 /* enable watchdog */ 1523 #define WDDIS 0x0AD0 /* disable watchdog */ 1524 #define WDRO 0x8000 /* watchdog rolled over latch */ 1525 1526 /* depreciated WDOG_CTL Register Masks for legacy code */ 1527 #define ICTL (WDEV) 1528 #define ENABLE_RESET (WDEV_RESET) 1529 #define WDOG_RESET (WDEV_RESET) 1530 #define ENABLE_NMI (WDEV_NMI) 1531 #define WDOG_NMI (WDEV_NMI) 1532 #define ENABLE_GPI (WDEV_GPI) 1533 #define WDOG_GPI (WDEV_GPI) 1534 #define DISABLE_EVT (WDEV_NONE) 1535 #define WDOG_NONE (WDEV_NONE) 1536 1537 #define TMR_EN (WDEN) 1538 #define TMR_DIS (WDDIS) 1539 #define TRO (WDRO) 1540 #define ICTL_P0 (0x01) 1541 #define ICTL_P1 (0x02) 1542 #define TRO_P (0x0F) 1543 1544 1545 /* ************************************ UART CONTROLLER MASKS *****************************************************/ 1546 1547 /* Bit masks for UARTx_LCR */ 1548 1549 #if 0 1550 /* conflicts with legacy one in last section */ 1551 #define WLS 0x3 /* Word Length Select */ 1552 #endif 1553 #define STB 0x4 /* Stop Bits */ 1554 #define nSTB 0x0 1555 #define PEN 0x8 /* Parity Enable */ 1556 #define nPEN 0x0 1557 #define EPS 0x10 /* Even Parity Select */ 1558 #define nEPS 0x0 1559 #define STP 0x20 /* Sticky Parity */ 1560 #define nSTP 0x0 1561 #define SB 0x40 /* Set Break */ 1562 #define nSB 0x0 1563 1564 /* for legacy compatibility */ 1565 1566 #ifdef _MISRA_RULES 1567 #define WLS(x) (((x)-5u) & 0x03u) /* Word Length Select */ 1568 #else 1569 #define WLS(x) (((x)-5) & 0x03) /* Word Length Select */ 1570 #endif /* _MISRA_RULES */ 1571 1572 /* Bit masks for UARTx_MCR */ 1573 1574 #define XOFF 0x1 /* Transmitter Off */ 1575 #define nXOFF 0x0 1576 #define MRTS 0x2 /* Manual Request To Send */ 1577 #define nMRTS 0x0 1578 #define RFIT 0x4 /* Receive FIFO IRQ Threshold */ 1579 #define nRFIT 0x0 1580 #define RFRT 0x8 /* Receive FIFO RTS Threshold */ 1581 #define nRFRT 0x0 1582 #define LOOP_ENA 0x10 /* Loopback Mode Enable */ 1583 #define nLOOP_ENA 0x0 1584 #define FCPOL 0x20 /* Flow Control Pin Polarity */ 1585 #define nFCPOL 0x0 1586 #define ARTS 0x40 /* Automatic Request To Send */ 1587 #define nARTS 0x0 1588 #define ACTS 0x80 /* Automatic Clear To Send */ 1589 #define nACTS 0x0 1590 1591 /* Bit masks for UARTx_LSR */ 1592 1593 #define DR 0x1 /* Data Ready */ 1594 #define nDR 0x0 1595 #define OE 0x2 /* Overrun Error */ 1596 #define nOE 0x0 1597 #define PE 0x4 /* Parity Error */ 1598 #define nPE 0x0 1599 #define FE 0x8 /* Framing Error */ 1600 #define nFE 0x0 1601 #define BI 0x10 /* Break Interrupt */ 1602 #define nBI 0x0 1603 #define THRE 0x20 /* THR Empty */ 1604 #define nTHRE 0x0 1605 #define TEMT 0x40 /* Transmitter Empty */ 1606 #define nTEMT 0x0 1607 #define TFI 0x80 /* Transmission Finished Indicator */ 1608 #define nTFI 0x0 1609 1610 /* Bit masks for UARTx_MSR */ 1611 1612 #define SCTS 0x1 /* Sticky CTS */ 1613 #define nSCTS 0x0 1614 #define CTS 0x10 /* Clear To Send */ 1615 #define nCTS 0x0 1616 #define RFCS 0x20 /* Receive FIFO Count Status */ 1617 #define nRFCS 0x0 1618 1619 /* Bit masks for UARTx_IER_SET and UARTx_IER_CLEAR */ 1620 1621 #define ERBFI 0x1 /* Enable Receive Buffer Full Interrupt */ 1622 #define nERBFI 0x0 1623 #define ETBEI 0x2 /* Enable Transmit Buffer Empty Interrupt */ 1624 #define nETBEI 0x0 1625 #define ELSI 0x4 /* Enable Receive Status Interrupt */ 1626 #define nELSI 0x0 1627 #define EDSSI 0x8 /* Enable Modem Status Interrupt */ 1628 #define nEDSSI 0x0 1629 1630 #define ETFI 0x20 /* Enable Transmission Finished Interrupt */ 1631 #define nETFI 0x0 1632 1633 #define ERFCI 0x40 /* Enable Receive FIFO Count Interrupt */ 1634 #define nERFCI 0x0 1635 1636 1637 /* Bit masks for UARTx_GCTL */ 1638 1639 #define UCEN 0x1 /* UART Enable */ 1640 #define nUCEN 0x0 1641 #define IREN 0x2 /* IrDA Mode Enable */ 1642 #define nIREN 0x0 1643 #define TPOLC 0x4 /* IrDA TX Polarity Change */ 1644 #define nTPOLC 0x0 1645 #define RPOLC 0x8 /* IrDA RX Polarity Change */ 1646 #define nRPOLC 0x0 1647 #define FPE 0x10 /* Force Parity Error */ 1648 #define nFPE 0x0 1649 #define FFE 0x20 /* Force Framing Error */ 1650 #define nFFE 0x0 1651 #define EDBO 0x40 /* Enable Divide-by-One */ 1652 #define nEDBO 0x0 1653 #define EGLSI 0x80 /* Enable Global LS Interrupt */ 1654 #define nEGLSI 0x0 1655 1656 /* UARTx_LCR bit field options */ 1657 1658 #define WLS_5 0x0000 /* 5 data bits */ 1659 #define WLS_6 0x0001 /* 6 data bits */ 1660 #define WLS_7 0x0002 /* 7 data bits */ 1661 #define WLS_8 0x0003 /* 8 data bits */ 1662 1663 1664 /******************************** SERIAL PERIPHERAL INTERFACE (SPI) MASKS ***************************************/ 1665 1666 /* SPI_CTL Masks*/ 1667 #define TIMOD 0x0003 /* Transfer Initiate Mode */ 1668 #define RDBR_CORE 0x0000 /* RDBR Read Initiates, IRQ When RDBR Full */ 1669 #define TDBR_CORE 0x0001 /* TDBR Write Initiates, IRQ When TDBR Empty */ 1670 #define RDBR_DMA 0x0002 /* DMA Read, DMA Until FIFO Empty */ 1671 #define TDBR_DMA 0x0003 /* DMA Write, DMA Until FIFO Full */ 1672 #define SZ 0x0004 /* Send Zero (When TDBR Empty, Send Zero/Last*) */ 1673 #define GM 0x0008 /* Get More (When RDBR Full, Overwrite/Discard*) */ 1674 #define PSSE 0x0010 /* Slave-Select Input Enable */ 1675 #define EMISO 0x0020 /* Enable MISO As Output */ 1676 #define SIZE 0x0100 /* Size of Words (16/8* Bits) */ 1677 #define LSBF 0x0200 /* LSB First */ 1678 #define CPHA 0x0400 /* Clock Phase */ 1679 #define CPOL 0x0800 /* Clock Polarity */ 1680 #define MSTR 0x1000 /* Master/Slave* */ 1681 #define WOM 0x2000 /* Write Open Drain Master */ 1682 #define SPE 0x4000 /* SPI Enable */ 1683 1684 /* SPI_FLG Masks*/ 1685 #define FLS1 0x0002 /* Enables SPI_FLOUT1 as SPI Slave-Select Output */ 1686 #define FLS2 0x0004 /* Enables SPI_FLOUT2 as SPI Slave-Select Output */ 1687 #define FLS3 0x0008 /* Enables SPI_FLOUT3 as SPI Slave-Select Output */ 1688 #define FLS4 0x0010 /* Enables SPI_FLOUT4 as SPI Slave-Select Output */ 1689 #define FLS5 0x0020 /* Enables SPI_FLOUT5 as SPI Slave-Select Output */ 1690 #define FLS6 0x0040 /* Enables SPI_FLOUT6 as SPI Slave-Select Output */ 1691 #define FLS7 0x0080 /* Enables SPI_FLOUT7 as SPI Slave-Select Output */ 1692 #define FLG1 0xFDFF /* Activates SPI_FLOUT1 */ 1693 #define FLG2 0xFBFF /* Activates SPI_FLOUT2 */ 1694 #define FLG3 0xF7FF /* Activates SPI_FLOUT3 */ 1695 #define FLG4 0xEFFF /* Activates SPI_FLOUT4 */ 1696 #define FLG5 0xDFFF /* Activates SPI_FLOUT5 */ 1697 #define FLG6 0xBFFF /* Activates SPI_FLOUT6 */ 1698 #define FLG7 0x7FFF /* Activates SPI_FLOUT7 */ 1699 1700 /* SPI_STAT Masks*/ 1701 #define SPIF 0x0001 /* SPI Finished (Single-Word Transfer Complete) */ 1702 #define MODF 0x0002 /* Mode Fault Error (Another Device Tried To Become Master) */ 1703 #define TXE 0x0004 /* Transmission Error (Data Sent With No New Data In TDBR) */ 1704 #define TXS 0x0008 /* SPI_TDBR Data Buffer Status (Full/Empty*) */ 1705 #define RBSY 0x0010 /* Receive Error (Data Received With RDBR Full) */ 1706 #define RXS 0x0020 /* SPI_RDBR Data Buffer Status (Full/Empty*) */ 1707 #define TXCOL 0x0040 /* Transmit Collision Error (Corrupt Data May Have Been Sent) */ 1708 1709 1710 /*********************************** GENERAL PURPOSE TIMER MASKS ************************************************/ 1711 /* TIMER_ENABLE Masks*/ 1712 #define TIMEN0 0x0001 /* Enable Timer 0 */ 1713 #define TIMEN1 0x0002 /* Enable Timer 1 */ 1714 #define TIMEN2 0x0004 /* Enable Timer 2 */ 1715 #define TIMEN3 0x0008 /* Enable Timer 3 */ 1716 #define TIMEN4 0x0010 /* Enable Timer 4 */ 1717 #define TIMEN5 0x0020 /* Enable Timer 5 */ 1718 #define TIMEN6 0x0040 /* Enable Timer 6 */ 1719 #define TIMEN7 0x0080 /* Enable Timer 7 */ 1720 1721 /* TIMER_DISABLE Masks*/ 1722 #define TIMDIS0 (TIMEN0) /* Disable Timer 0 */ 1723 #define TIMDIS1 (TIMEN1) /* Disable Timer 1 */ 1724 #define TIMDIS2 (TIMEN2) /* Disable Timer 2 */ 1725 #define TIMDIS3 (TIMEN3) /* Disable Timer 3 */ 1726 #define TIMDIS4 (TIMEN4) /* Disable Timer 4 */ 1727 #define TIMDIS5 (TIMEN5) /* Disable Timer 5 */ 1728 #define TIMDIS6 (TIMEN6) /* Disable Timer 6 */ 1729 #define TIMDIS7 (TIMEN7) /* Disable Timer 7 */ 1730 1731 /* TIMER_STATUS Masks*/ 1732 #define TIMIL0 0x00000001 /* Timer 0 Interrupt */ 1733 #define TIMIL1 0x00000002 /* Timer 1 Interrupt */ 1734 #define TIMIL2 0x00000004 /* Timer 2 Interrupt */ 1735 #define TIMIL3 0x00000008 /* Timer 3 Interrupt */ 1736 #define TOVF_ERR0 0x00000010 /* Timer 0 Counter Overflow */ 1737 #define TOVF_ERR1 0x00000020 /* Timer 1 Counter Overflow */ 1738 #define TOVF_ERR2 0x00000040 /* Timer 2 Counter Overflow */ 1739 #define TOVF_ERR3 0x00000080 /* Timer 3 Counter Overflow */ 1740 #define TRUN0 0x00001000 /* Timer 0 Slave Enable Status */ 1741 #define TRUN1 0x00002000 /* Timer 1 Slave Enable Status */ 1742 #define TRUN2 0x00004000 /* Timer 2 Slave Enable Status */ 1743 #define TRUN3 0x00008000 /* Timer 3 Slave Enable Status */ 1744 #define TIMIL4 0x00010000 /* Timer 4 Interrupt */ 1745 #define TIMIL5 0x00020000 /* Timer 5 Interrupt */ 1746 #define TIMIL6 0x00040000 /* Timer 6 Interrupt */ 1747 #define TIMIL7 0x00080000 /* Timer 7 Interrupt */ 1748 #define TOVF_ERR4 0x00100000 /* Timer 4 Counter Overflow */ 1749 #define TOVF_ERR5 0x00200000 /* Timer 5 Counter Overflow */ 1750 #define TOVF_ERR6 0x00400000 /* Timer 6 Counter Overflow */ 1751 #define TOVF_ERR7 0x00800000 /* Timer 7 Counter Overflow */ 1752 #define TRUN4 0x10000000 /* Timer 4 Slave Enable Status */ 1753 #define TRUN5 0x20000000 /* Timer 5 Slave Enable Status */ 1754 #define TRUN6 0x40000000 /* Timer 6 Slave Enable Status */ 1755 #define TRUN7 0x80000000 /* Timer 7 Slave Enable Status */ 1756 1757 /* Alternate Deprecated Macros Provided For Backwards Code Compatibility */ 1758 #define TOVL_ERR0 (TOVF_ERR0) 1759 #define TOVL_ERR1 (TOVF_ERR1) 1760 #define TOVL_ERR2 (TOVF_ERR2) 1761 #define TOVL_ERR3 (TOVF_ERR3) 1762 #define TOVL_ERR4 (TOVF_ERR4) 1763 #define TOVL_ERR5 (TOVF_ERR5) 1764 #define TOVL_ERR6 (TOVF_ERR6) 1765 #define TOVL_ERR7 (TOVF_ERR7) 1766 1767 /* TIMERx_CONFIG Masks */ 1768 #define PWM_OUT 0x0001 /* Pulse-Width Modulation Output Mode */ 1769 #define WDTH_CAP 0x0002 /* Width Capture Input Mode */ 1770 #define EXT_CLK 0x0003 /* External Clock Mode */ 1771 #define PULSE_HI 0x0004 /* Action Pulse (Positive/Negative*) */ 1772 #define PERIOD_CNT 0x0008 /* Period Count */ 1773 #define IRQ_ENA 0x0010 /* Interrupt Request Enable */ 1774 #define TIN_SEL 0x0020 /* Timer Input Select */ 1775 #define OUT_DIS 0x0040 /* Output Pad Disable */ 1776 #define CLK_SEL 0x0080 /* Timer Clock Select */ 1777 #define TOGGLE_HI 0x0100 /* PWM_OUT PULSE_HI Toggle Mode */ 1778 #define EMU_RUN 0x0200 /* Emulation Behavior Select */ 1779 #define ERR_TYP 0xC000 /* Error Type */ 1780 1781 1782 /* ************************************* GPIO PORTS F, G, H MASKS **********************************************/ 1783 1784 /* General Purpose IO (0xFFC00700 - 0xFFC007FF) Masks */ 1785 /* Port F Masks */ 1786 #define PF0 0x0001 1787 #define PF1 0x0002 1788 #define PF2 0x0004 1789 #define PF3 0x0008 1790 #define PF4 0x0010 1791 #define PF5 0x0020 1792 #define PF6 0x0040 1793 #define PF7 0x0080 1794 #define PF8 0x0100 1795 #define PF9 0x0200 1796 #define PF10 0x0400 1797 #define PF11 0x0800 1798 #define PF12 0x1000 1799 #define PF13 0x2000 1800 #define PF14 0x4000 1801 #define PF15 0x8000 1802 1803 /* Port G Masks */ 1804 #define PG0 0x0001 1805 #define PG1 0x0002 1806 #define PG2 0x0004 1807 #define PG3 0x0008 1808 #define PG4 0x0010 1809 #define PG5 0x0020 1810 #define PG6 0x0040 1811 #define PG7 0x0080 1812 #define PG8 0x0100 1813 #define PG9 0x0200 1814 #define PG10 0x0400 1815 #define PG11 0x0800 1816 #define PG12 0x1000 1817 #define PG13 0x2000 1818 #define PG14 0x4000 1819 #define PG15 0x8000 1820 1821 /* Port H Masks */ 1822 #define PH0 0x0001 1823 #define PH1 0x0002 1824 #define PH2 0x0004 1825 1826 1827 /* ************************************** SERIAL PORT MASKS *****************************************************/ 1828 /* SPORTx_TCR1 Masks */ 1829 #define TSPEN 0x0001 /* Transmit Enable */ 1830 #define ITCLK 0x0002 /* Internal Transmit Clock Select */ 1831 #define DTYPE_NORM 0x0004 /* Data Format Normal */ 1832 #define DTYPE_ULAW 0x0008 /* Compand Using u-Law */ 1833 #define DTYPE_ALAW 0x000C /* Compand Using A-Law */ 1834 #define TLSBIT 0x0010 /* Transmit Bit Order */ 1835 #define ITFS 0x0200 /* Internal Transmit Frame Sync Select */ 1836 #define TFSR 0x0400 /* Transmit Frame Sync Required Select */ 1837 #define DITFS 0x0800 /* Data-Independent Transmit Frame Sync Select */ 1838 #define LTFS 0x1000 /* Low Transmit Frame Sync Select */ 1839 #define LATFS 0x2000 /* Late Transmit Frame Sync Select */ 1840 #define TCKFE 0x4000 /* Clock Falling Edge Select */ 1841 1842 /* SPORTx_TCR2 Masks and Macro */ 1843 #ifdef _MISRA_RULES 1844 #define SLEN(x) ((x)&0x1Fu) /* SPORT TX Word Length (2 - 31) */ 1845 #else 1846 #define SLEN(x) ((x)&0x1F) /* SPORT TX Word Length (2 - 31) */ 1847 #endif /* _MISRA_RULES */ 1848 1849 #define TXSE 0x0100 /* TX Secondary Enable */ 1850 #define TSFSE 0x0200 /* Transmit Stereo Frame Sync Enable */ 1851 #define TRFST 0x0400 /* Left/Right Order (1 = Right Channel 1st) */ 1852 1853 /* SPORTx_RCR1 Masks */ 1854 #define RSPEN 0x0001 /* Receive Enable */ 1855 #define IRCLK 0x0002 /* Internal Receive Clock Select */ 1856 #define DTYPE_NORM 0x0004 /* Data Format Normal */ 1857 #define DTYPE_ULAW 0x0008 /* Compand Using u-Law */ 1858 #define DTYPE_ALAW 0x000C /* Compand Using A-Law */ 1859 #define RLSBIT 0x0010 /* Receive Bit Order */ 1860 #define IRFS 0x0200 /* Internal Receive Frame Sync Select */ 1861 #define RFSR 0x0400 /* Receive Frame Sync Required Select */ 1862 #define LRFS 0x1000 /* Low Receive Frame Sync Select */ 1863 #define LARFS 0x2000 /* Late Receive Frame Sync Select */ 1864 #define RCKFE 0x4000 /* Clock Falling Edge Select */ 1865 1866 /* SPORTx_RCR2 Masks */ 1867 #ifdef _MISRA_RULES 1868 #define SLEN(x) ((x)&0x1Fu) /* SPORT RX Word Length (2 - 31) */ 1869 #else 1870 #define SLEN(x) ((x)&0x1F) /* SPORT RX Word Length (2 - 31) */ 1871 #endif /* _MISRA_RULES */ 1872 1873 #define RXSE 0x0100 /* RX Secondary Enable */ 1874 #define RSFSE 0x0200 /* RX Stereo Frame Sync Enable */ 1875 #define RRFST 0x0400 /* Right-First Data Order */ 1876 1877 /* SPORTx_STAT Masks */ 1878 #define RXNE 0x0001 /* Receive FIFO Not Empty Status */ 1879 #define RUVF 0x0002 /* Sticky Receive Underflow Status */ 1880 #define ROVF 0x0004 /* Sticky Receive Overflow Status */ 1881 #define TXF 0x0008 /* Transmit FIFO Full Status */ 1882 #define TUVF 0x0010 /* Sticky Transmit Underflow Status */ 1883 #define TOVF 0x0020 /* Sticky Transmit Overflow Status */ 1884 #define TXHRE 0x0040 /* Transmit Hold Register Empty */ 1885 1886 /* SPORTx_MCMC1 Macros */ 1887 #ifdef _MISRA_RULES 1888 #define WOFF(x) ((x) & 0x3FFu) /* Multichannel Window Offset Field */ 1889 /* Only use WSIZE Macro With Logic OR While Setting Lower Order Bits*/ 1890 #define WSIZE(x) (((((x)>>0x3)-1u)&0xFu) << 0xC) /* Multichannel Window Size = (x/8)-1 */ 1891 #else 1892 #define WOFF(x) ((x) & 0x3FF) /* Multichannel Window Offset Field */ 1893 /* Only use WSIZE Macro With Logic OR While Setting Lower Order Bits */ 1894 #define WSIZE(x) (((((x)>>0x3)-1)&0xF) << 0xC) /* Multichannel Window Size = (x/8)-1 */ 1895 #endif /* _MISRA_RULES */ 1896 1897 /* SPORTx_MCMC2 Masks */ 1898 #define REC_BYPASS 0x0000 /* Bypass Mode (No Clock Recovery) */ 1899 #define REC_2FROM4 0x0002 /* Recover 2 MHz Clock from 4 MHz Clock */ 1900 #define REC_8FROM16 0x0003 /* Recover 8 MHz Clock from 16 MHz Clock */ 1901 #define MCDTXPE 0x0004 /* Multichannel DMA Transmit Packing */ 1902 #define MCDRXPE 0x0008 /* Multichannel DMA Receive Packing */ 1903 #define MCMEN 0x0010 /* Multichannel Frame Mode Enable */ 1904 #define FSDR 0x0080 /* Multichannel Frame Sync to Data Relationship */ 1905 #define MFD_0 0x0000 /* Multichannel Frame Delay = 0 */ 1906 #define MFD_1 0x1000 /* Multichannel Frame Delay = 1 */ 1907 #define MFD_2 0x2000 /* Multichannel Frame Delay = 2 */ 1908 #define MFD_3 0x3000 /* Multichannel Frame Delay = 3 */ 1909 #define MFD_4 0x4000 /* Multichannel Frame Delay = 4 */ 1910 #define MFD_5 0x5000 /* Multichannel Frame Delay = 5 */ 1911 #define MFD_6 0x6000 /* Multichannel Frame Delay = 6 */ 1912 #define MFD_7 0x7000 /* Multichannel Frame Delay = 7 */ 1913 #define MFD_8 0x8000 /* Multichannel Frame Delay = 8 */ 1914 #define MFD_9 0x9000 /* Multichannel Frame Delay = 9 */ 1915 #define MFD_10 0xA000 /* Multichannel Frame Delay = 10 */ 1916 #define MFD_11 0xB000 /* Multichannel Frame Delay = 11 */ 1917 #define MFD_12 0xC000 /* Multichannel Frame Delay = 12 */ 1918 #define MFD_13 0xD000 /* Multichannel Frame Delay = 13 */ 1919 #define MFD_14 0xE000 /* Multichannel Frame Delay = 14 */ 1920 #define MFD_15 0xF000 /* Multichannel Frame Delay = 15 */ 1921 1922 1923 /*********************************** ASYNCHRONOUS MEMORY CONTROLLER MASKS ***************************************/ 1924 1925 /* EBIU_AMGCTL Masks */ 1926 #define AMCKEN 0x0001 /* Enable CLKOUT */ 1927 #define AMBEN 0x0002 /* Enable Asynchronous memory bank */ 1928 #define AMBEN_NONE 0x0000 /* All Banks Disabled */ 1929 1930 #define AMBEN_B0 (AMBEN) /* Enable Async Memory Bank 0 only */ 1931 1932 #define AMBEN_ALL 0x0002 /* Enable Asynchronous memory bank */ 1933 #define CDPRIO 0x0100 /* DMA has priority over core for for external accesses */ 1934 1935 /* EBIU_AMBCTL Masks */ 1936 #define RDYEN 0x00000001 /* ARDY Enable */ 1937 #define RDYPOL 0x00000002 /* RDY Active High */ 1938 #define TT_1 0x00000004 /* Transition Time (Read to Write) = 1 cycle */ 1939 #define TT_2 0x00000008 /* Transition Time (Read to Write) = 2 cycles */ 1940 #define TT_3 0x0000000C /* Transition Time (Read to Write) = 3 cycles */ 1941 #define TT_4 0x00000000 /* Transition Time (Read to Write) = 4 cycles */ 1942 #define ST_1 0x00000010 /* Setup Time (AOE to Read/Write) = 1 cycle */ 1943 #define ST_2 0x00000020 /* Setup Time (AOE to Read/Write) = 2 cycles */ 1944 #define ST_3 0x00000030 /* Setup Time (AOE to Read/Write) = 3 cycles */ 1945 #define ST_4 0x00000000 /* Setup Time (AOE to Read/Write) = 4 cycles */ 1946 #define HT_1 0x00000040 /* Hold Time (~Read/Write to ~AOE) = 1 cycle */ 1947 #define HT_2 0x00000080 /* Hold Time (~Read/Write to ~AOE) = 2 cycles */ 1948 #define HT_3 0x000000C0 /* Hold Time (~Read/Write to ~AOE) = 3 cycles */ 1949 #define HT_0 0x00000000 /* Hold Time (~Read/Write to ~AOE) = 0 cycles */ 1950 #define RAT_1 0x00000100 /* Read Access Time = 1 cycle */ 1951 #define RAT_2 0x00000200 /* Read Access Time = 2 cycles */ 1952 #define RAT_3 0x00000300 /* Read Access Time = 3 cycles */ 1953 #define RAT_4 0x00000400 /* Read Access Time = 4 cycles */ 1954 #define RAT_5 0x00000500 /* Read Access Time = 5 cycles */ 1955 #define RAT_6 0x00000600 /* Read Access Time = 6 cycles */ 1956 #define RAT_7 0x00000700 /* Read Access Time = 7 cycles */ 1957 #define RAT_8 0x00000800 /* Read Access Time = 8 cycles */ 1958 #define RAT_9 0x00000900 /* Read Access Time = 9 cycles */ 1959 #define RAT_10 0x00000A00 /* Read Access Time = 10 cycles */ 1960 #define RAT_11 0x00000B00 /* Read Access Time = 11 cycles */ 1961 #define RAT_12 0x00000C00 /* Read Access Time = 12 cycles */ 1962 #define RAT_13 0x00000D00 /* Read Access Time = 13 cycles */ 1963 #define RAT_14 0x00000E00 /* Read Access Time = 14 cycles */ 1964 #define RAT_15 0x00000F00 /* Read Access Time = 15 cycles */ 1965 #define WAT_1 0x00001000 /* Write Access Time = 1 cycle */ 1966 #define WAT_2 0x00002000 /* Write Access Time = 2 cycles */ 1967 #define WAT_3 0x00003000 /* Write Access Time = 3 cycles */ 1968 #define WAT_4 0x00004000 /* Write Access Time = 4 cycles */ 1969 #define WAT_5 0x00005000 /* Write Access Time = 5 cycles */ 1970 #define WAT_6 0x00006000 /* Write Access Time = 6 cycles */ 1971 #define WAT_7 0x00007000 /* Write Access Time = 7 cycles */ 1972 #define WAT_8 0x00008000 /* Write Access Time = 8 cycles */ 1973 #define WAT_9 0x00009000 /* Write Access Time = 9 cycles */ 1974 #define WAT_10 0x0000A000 /* Write Access Time = 10 cycles */ 1975 #define WAT_11 0x0000B000 /* Write Access Time = 11 cycles */ 1976 #define WAT_12 0x0000C000 /* Write Access Time = 12 cycles */ 1977 #define WAT_13 0x0000D000 /* Write Access Time = 13 cycles */ 1978 #define WAT_14 0x0000E000 /* Write Access Time = 14 cycles */ 1979 #define WAT_15 0x0000F000 /* Write Access Time = 15 cycles */ 1980 1981 /* EBIU_AMBCTL0 Masks */ 1982 #define B0RDYEN (RDYEN) /* Bank 0 (B0) RDY Enable */ 1983 #define B0RDYPOL (RDYPOL) /* B0 RDY Active High */ 1984 #define B0TT_1 (TT_1) /* B0 Transition Time (Read to Write) = 1 cycle */ 1985 #define B0TT_2 (TT_2) /* B0 Transition Time (Read to Write) = 2 cycles */ 1986 #define B0TT_3 (TT_3) /* B0 Transition Time (Read to Write) = 3 cycles */ 1987 #define B0TT_4 (TT_4) /* B0 Transition Time (Read to Write) = 4 cycles */ 1988 #define B0ST_1 (ST_1) /* B0 Setup Time (AOE to Read/Write) = 1 cycle */ 1989 #define B0ST_2 (ST_2) /* B0 Setup Time (AOE to Read/Write) = 2 cycles */ 1990 #define B0ST_3 (ST_3) /* B0 Setup Time (AOE to Read/Write) = 3 cycles */ 1991 #define B0ST_4 (ST_4) /* B0 Setup Time (AOE to Read/Write) = 4 cycles */ 1992 #define B0HT_1 (HT_1) /* B0 Hold Time (~Read/Write to ~AOE) = 1 cycle */ 1993 #define B0HT_2 (HT_2) /* B0 Hold Time (~Read/Write to ~AOE) = 2 cycles */ 1994 #define B0HT_3 (HT_3) /* B0 Hold Time (~Read/Write to ~AOE) = 3 cycles */ 1995 #define B0HT_0 (HT_0) /* B0 Hold Time (~Read/Write to ~AOE) = 0 cycles */ 1996 #define B0RAT_1 (RAT_1) /* B0 Read Access Time = 1 cycle */ 1997 #define B0RAT_2 (RAT_2) /* B0 Read Access Time = 2 cycles */ 1998 #define B0RAT_3 (RAT_3) /* B0 Read Access Time = 3 cycles */ 1999 #define B0RAT_4 (RAT_4) /* B0 Read Access Time = 4 cycles */ 2000 #define B0RAT_5 (RAT_5) /* B0 Read Access Time = 5 cycles */ 2001 #define B0RAT_6 (RAT_6) /* B0 Read Access Time = 6 cycles */ 2002 #define B0RAT_7 (RAT_7) /* B0 Read Access Time = 7 cycles */ 2003 #define B0RAT_8 (RAT_8) /* B0 Read Access Time = 8 cycles */ 2004 #define B0RAT_9 (RAT_9) /* B0 Read Access Time = 9 cycles */ 2005 #define B0RAT_10 (RAT_10) /* B0 Read Access Time = 10 cycles */ 2006 #define B0RAT_11 (RAT_11) /* B0 Read Access Time = 11 cycles */ 2007 #define B0RAT_12 (RAT_12) /* B0 Read Access Time = 12 cycles */ 2008 #define B0RAT_13 (RAT_13) /* B0 Read Access Time = 13 cycles */ 2009 #define B0RAT_14 (RAT_14) /* B0 Read Access Time = 14 cycles */ 2010 #define B0RAT_15 (RAT_15) /* B0 Read Access Time = 15 cycles */ 2011 #define B0WAT_1 (WAT_1) /* B0 Write Access Time = 1 cycle */ 2012 #define B0WAT_2 (WAT_2) /* B0 Write Access Time = 2 cycles */ 2013 #define B0WAT_3 (WAT_3) /* B0 Write Access Time = 3 cycles */ 2014 #define B0WAT_4 (WAT_4) /* B0 Write Access Time = 4 cycles */ 2015 #define B0WAT_5 (WAT_5) /* B0 Write Access Time = 5 cycles */ 2016 #define B0WAT_6 (WAT_6) /* B0 Write Access Time = 6 cycles */ 2017 #define B0WAT_7 (WAT_7) /* B0 Write Access Time = 7 cycles */ 2018 #define B0WAT_8 (WAT_8) /* B0 Write Access Time = 8 cycles */ 2019 #define B0WAT_9 (WAT_9) /* B0 Write Access Time = 9 cycles */ 2020 #define B0WAT_10 (WAT_10) /* B0 Write Access Time = 10 cycles */ 2021 #define B0WAT_11 (WAT_11) /* B0 Write Access Time = 11 cycles */ 2022 #define B0WAT_12 (WAT_12) /* B0 Write Access Time = 12 cycles */ 2023 #define B0WAT_13 (WAT_13) /* B0 Write Access Time = 13 cycles */ 2024 #define B0WAT_14 (WAT_14) /* B0 Write Access Time = 14 cycles */ 2025 #define B0WAT_15 (WAT_15) /* B0 Write Access Time = 15 cycles */ 2026 2027 2028 /* Bit masks for EBIU_MODE */ 2029 2030 #define B0MODE 0x3 /* Async Memory Bank Access Mode */ 2031 2032 /* Bit masks for EBIU_MODE */ 2033 #define MODE_ASYNC 0x00000000 /* Access Mode - 00 - Asynchronous Mode */ 2034 #define MODE_FLASH 0x00000001 /* Access Mode - 01 - Asynchronous Flash Mode */ 2035 #define MODE_BURST 0x00000003 /* Access Mode - 11 - Synchronous (Burst) Mode */ 2036 2037 /* legacy bit fields (below) provided for backwards code compatibility */ 2038 #define B0MODE_ASYNC (MODE_ASYNC) 2039 #define B0MODE_FLASH (MODE_FLASH) 2040 #define B0MODE_BURST (MODE_BURST) 2041 2042 /* Bit masks for EBIU_FCTL (BCLK) */ 2043 #define BCLK2 0x00000002 /* Burst clock frequency: 01 - SCLK/2 */ 2044 #define BCLK3 0x00000004 /* Burst clock frequency: 10 - SCLK/3 */ 2045 #define BCLK4 0x00000006 /* Burst clock frequency: 11 - SCLK/4 */ 2046 2047 2048 /**************************************** DMA CONTROLLER MASKS **************************************************/ 2049 2050 /* DMAx_CONFIG, MDMA_yy_CONFIG Masks */ 2051 #define DMAEN 0x0001 /* DMA Channel Enable */ 2052 #define WNR 0x0002 /* Channel Direction (W/R*) */ 2053 #define WDSIZE_8 0x0000 /* Transfer Word Size = 8 */ 2054 #define WDSIZE_16 0x0004 /* Transfer Word Size = 16 */ 2055 #define WDSIZE_32 0x0008 /* Transfer Word Size = 32 */ 2056 #define DMA2D 0x0010 /* DMA Mode (2D/1D*) */ 2057 #define SYNC 0x0020 /* DMA Buffer Clear */ 2058 #define DI_SEL 0x0040 /* Data Interrupt Timing Select */ 2059 #define DI_EN 0x0080 /* Data Interrupt Enable */ 2060 #define NDSIZE_0 0x0000 /* Next Descriptor Size = 0 (Stop/Autobuffer) */ 2061 #define NDSIZE_1 0x0100 /* Next Descriptor Size = 1 */ 2062 #define NDSIZE_2 0x0200 /* Next Descriptor Size = 2 */ 2063 #define NDSIZE_3 0x0300 /* Next Descriptor Size = 3 */ 2064 #define NDSIZE_4 0x0400 /* Next Descriptor Size = 4 */ 2065 #define NDSIZE_5 0x0500 /* Next Descriptor Size = 5 */ 2066 #define NDSIZE_6 0x0600 /* Next Descriptor Size = 6 */ 2067 #define NDSIZE_7 0x0700 /* Next Descriptor Size = 7 */ 2068 #define NDSIZE_8 0x0800 /* Next Descriptor Size = 8 */ 2069 #define NDSIZE_9 0x0900 /* Next Descriptor Size = 9 */ 2070 #define FLOW_STOP 0x0000 /* Stop Mode */ 2071 #define FLOW_AUTO 0x1000 /* Autobuffer Mode */ 2072 #define FLOW_ARRAY 0x4000 /* Descriptor Array Mode */ 2073 #define FLOW_SMALL 0x6000 /* Small Model Descriptor List Mode */ 2074 #define FLOW_LARGE 0x7000 /* Large Model Descriptor List Mode */ 2075 2076 /* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks */ 2077 #define CTYPE 0x0040 /* DMA Channel Type Indicator (Memory/Peripheral) */ 2078 #define PMAP 0xF000 /* Peripheral Mapped To This Channel */ 2079 #define PMAP_PPI 0x0000 /* PPI Port DMA */ 2080 #define PMAP_RSI 0x1000 /* RSI DMA */ 2081 #define PMAP_SPORT0RX 0x2000 /* SPORT0 Receive DMA */ 2082 #define PMAP_SPORT0TX 0x3000 /* SPORT0 Transmit DMA */ 2083 #define PMAP_SPORT1RX 0x4000 /* SPORT1 Receive DMA */ 2084 #define PMAP_SPORT1TX 0x5000 /* SPORT1 Transmit DMA */ 2085 #define PMAP_SPI0 0x6000 /* SPI0 Transmit/Receive DMA */ 2086 #define PMAP_SPI1 0x7000 /* SPI1 Transmit/Receive DMA */ 2087 #define PMAP_UART0RX 0x8000 /* UART0 Port Receive DMA */ 2088 #define PMAP_UART0TX 0x9000 /* UART0 Port Transmit DMA */ 2089 #define PMAP_UART1RX 0xA000 /* UART1 Port Receive DMA */ 2090 #define PMAP_UART1TX 0xB000 /* UART1 Port Transmit DMA */ 2091 2092 /* DMAx_IRQ_STATUS, MDMA_yy_IRQ_STATUS Masks */ 2093 #define DMA_DONE 0x0001 /* DMA Completion Interrupt Status */ 2094 #define DMA_ERR 0x0002 /* DMA Error Interrupt Status */ 2095 #define DFETCH 0x0004 /* DMA Descriptor Fetch Indicator */ 2096 #define DMA_RUN 0x0008 /* DMA Channel Running Indicator */ 2097 2098 2099 /********************************* PARALLEL PERIPHERAL INTERFACE (PPI) MASKS *************************************/ 2100 2101 /* PPI_CONTROL Masks */ 2102 #define PORT_EN 0x0001 /* PPI Port Enable */ 2103 #define PORT_DIR 0x0002 /* PPI Port Direction */ 2104 #define XFR_TYPE 0x000C /* PPI Transfer Type */ 2105 #define PORT_CFG 0x0030 /* PPI Port Configuration */ 2106 #define FLD_SEL 0x0040 /* PPI Active Field Select */ 2107 #define PACK_EN 0x0080 /* PPI Packing Mode */ /* previous versions of defBF532.h erroneously included DMA32 (PPI 32-bit DMA Enable) */ 2108 #define SKIP_EN 0x0200 /* PPI Skip Element Enable */ 2109 #define SKIP_EO 0x0400 /* PPI Skip Even/Odd Elements */ 2110 #define DLEN_8 0x0000 /* Data Length = 8 Bits */ 2111 #define DLEN_10 0x0800 /* Data Length = 10 Bits */ 2112 #define DLEN_11 0x1000 /* Data Length = 11 Bits */ 2113 #define DLEN_12 0x1800 /* Data Length = 12 Bits */ 2114 #define DLEN_13 0x2000 /* Data Length = 13 Bits */ 2115 #define DLEN_14 0x2800 /* Data Length = 14 Bits */ 2116 #define DLEN_15 0x3000 /* Data Length = 15 Bits */ 2117 #define DLEN_16 0x3800 /* Data Length = 16 Bits */ 2118 #define POLC 0x4000 /* PPI Clock Polarity */ 2119 #define POLS 0x8000 /* PPI Frame Sync Polarity */ 2120 2121 /* PPI_STATUS Masks */ 2122 #define LT_ERR_OVR 0x0100 /* Line Track Overflow Error */ 2123 #define LT_ERR_UNDR 0x0200 /* Line Track Underflow Error */ 2124 #define FLD 0x0400 /* Field Indicator */ 2125 #define FT_ERR 0x0800 /* Frame Track Error */ 2126 #define OVR 0x1000 /* FIFO Overflow Error */ 2127 #define UNDR 0x2000 /* FIFO Underrun Error */ 2128 #define ERR_DET 0x4000 /* Error Detected Indicator */ 2129 #define ERR_NCOR 0x8000 /* Error Not Corrected Indicator */ 2130 2131 2132 /*************************************** TWO-WIRE INTERFACE (TWI) MASKS *****************************************/ 2133 2134 /* TWI_CLKDIV Macros (Use: *pTWI_CLKDIV = CLKLOW(x)|CLKHI(y); ) */ 2135 #ifdef _MISRA_RULES 2136 #define CLKLOW(x) ((x) & 0xFFu)/* Periods Clock Is Held Low */ 2137 #define CLKHI(y) (((y)&0xFFu)<<0x8)/* Periods Before New Clock Low */ 2138 #else 2139 #define CLKLOW(x) ((x) & 0xFF)/* Periods Clock Is Held Low */ 2140 #define CLKHI(y) (((y)&0xFF)<<0x8) /* Periods Before New Clock Low */ 2141 #endif /* _MISRA_RULES */ 2142 2143 /* TWI_PRESCALE Masks */ 2144 #define PRESCALE 0x007F /* SCLKs Per Internal Time Reference (10MHz) */ 2145 #define TWI_ENA 0x0080 /* TWI Enable */ 2146 #define SCCB 0x0200 /* SCCB Compatibility Enable */ 2147 2148 /* TWI_SLAVE_CTRL Masks */ 2149 #define SEN 0x0001 /* Slave Enable */ 2150 #define SADD_LEN 0x0002 /* Slave Address Length */ 2151 #define STDVAL 0x0004 /* Slave Transmit Data Valid */ 2152 #define NAK 0x0008 /* NAK/ACK* Generated At Conclusion Of Transfer */ 2153 #define GEN 0x0010 /* General Call Adrress Matching Enabled */ 2154 2155 /* TWI_SLAVE_STAT Masks */ 2156 #define SDIR 0x0001 /* Slave Transfer Direction (Transmit/Receive*) */ 2157 #define GCALL 0x0002 /* General Call Indicator */ 2158 2159 /* TWI_MASTER_CTRL Masks */ 2160 #define MEN 0x0001 /* Master Mode Enable */ 2161 #define MADD_LEN 0x0002 /* Master Address Length */ 2162 #define MDIR 0x0004 /* Master Transmit Direction (RX/TX*) */ 2163 #define FAST 0x0008 /* Use Fast Mode Timing Specs */ 2164 #define STOP 0x0010 /* Issue Stop Condition */ 2165 #define RSTART 0x0020 /* Repeat Start or Stop* At End Of Transfer */ 2166 #define DCNT 0x3FC0 /* Data Bytes To Transfer */ 2167 #define SDAOVR 0x4000 /* Serial Data Override */ 2168 #define SCLOVR 0x8000 /* Serial Clock Override */ 2169 2170 /* TWI_MASTER_STAT Masks */ 2171 #define MPROG 0x0001 /* Master Transfer In Progress */ 2172 #define LOSTARB 0x0002 /* Lost Arbitration Indicator (Xfer Aborted) */ 2173 #define ANAK 0x0004 /* Address Not Acknowledged */ 2174 #define DNAK 0x0008 /* Data Not Acknowledged */ 2175 #define BUFRDERR 0x0010 /* Buffer Read Error */ 2176 #define BUFWRERR 0x0020 /* Buffer Write Error */ 2177 #define SDASEN 0x0040 /* Serial Data Sense */ 2178 #define SCLSEN 0x0080 /* Serial Clock Sense */ 2179 #define BUSBUSY 0x0100 /* Bus Busy Indicator */ 2180 2181 /* TWI_INT_SRC and TWI_INT_ENABLE Masks */ 2182 #define SINIT 0x0001 /* Slave Transfer Initiated */ 2183 #define SCOMP 0x0002 /* Slave Transfer Complete */ 2184 #define SERR 0x0004 /* Slave Transfer Error */ 2185 #define SOVF 0x0008 /* Slave Overflow */ 2186 #define MCOMP 0x0010 /* Master Transfer Complete */ 2187 #define MERR 0x0020 /* Master Transfer Error */ 2188 #define XMTSERV 0x0040 /* Transmit FIFO Service */ 2189 #define RCVSERV 0x0080 /* Receive FIFO Service */ 2190 2191 /* TWI_FIFO_CTRL Masks */ 2192 #define XMTFLUSH 0x0001 /* Transmit Buffer Flush */ 2193 #define RCVFLUSH 0x0002 /* Receive Buffer Flush */ 2194 #define XMTINTLEN 0x0004 /* Transmit Buffer Interrupt Length */ 2195 #define RCVINTLEN 0x0008 /* Receive Buffer Interrupt Length */ 2196 2197 /* TWI_FIFO_STAT Masks */ 2198 #define XMTSTAT 0x0003 /* Transmit FIFO Status */ 2199 #define XMT_EMPTY 0x0000 /* Transmit FIFO Empty */ 2200 #define XMT_HALF 0x0001 /* Transmit FIFO Has 1 Byte To Write */ 2201 #define XMT_FULL 0x0003 /* Transmit FIFO Full (2 Bytes To Write) */ 2202 2203 #define RCVSTAT 0x000C /* Receive FIFO Status */ 2204 #define RCV_EMPTY 0x0000 /* Receive FIFO Empty */ 2205 #define RCV_HALF 0x0004 /* Receive FIFO Has 1 Byte To Read */ 2206 #define RCV_FULL 0x000C /* Receive FIFO Full (2 Bytes To Read) */ 2207 2208 2209 /************************************* STACKED FLASH REGISTER MASKS AND DEFINITIONS ******************************/ 2210 2211 #define FLASH_ENABLE 0x0001 /* Enable stacked flash for reads/writes or reset flash */ 2212 #define FLASH_UNPROTECT 0x0100 /* Protect/unprotect stacked flash from programming/erase */ 2213 #define FLASH_UNLOCK 0x8000 /* Enable/disable the setting of the upper byte of FLASH_CONTROL */ 2214 2215 #define FLASH_BASE_ADDRESS 0x20000000 2216 2217 2218 2219 /**************************************** COUNTER MASKS ******************************************************/ 2220 2221 /* Bit masks for CNT_CONFIG */ 2222 #define CNTE 0x1 /* Counter Enable */ 2223 #define nCNTE 0x0 2224 #define DEBE 0x2 /* Debounce Enable */ 2225 #define nDEBE 0x0 2226 #define CDGINV 0x10 /* CDG Pin Polarity Invert */ 2227 #define nCDGINV 0x0 2228 #define CUDINV 0x20 /* CUD Pin Polarity Invert */ 2229 #define nCUDINV 0x0 2230 #define CZMINV 0x40 /* CZM Pin Polarity Invert */ 2231 #define nCZMINV 0x0 2232 #define CNTMODE 0x700 /* Counter Operating Mode */ 2233 #define ZMZC 0x800 /* CZM Zeroes Counter Enable */ 2234 #define nZMZC 0x0 2235 #define BNDMODE 0x3000 /* Boundary register Mode */ 2236 #define INPDIS 0x8000 /* CUG and CDG Input Disable */ 2237 #define nINPDIS 0x0 2238 2239 /* Bit masks for CNT_IMASK */ 2240 #define ICIE 0x1 /* Illegal Gray/Binary Code Interrupt Enable */ 2241 #define nICIE 0x0 2242 #define UCIE 0x2 /* Up count Interrupt Enable */ 2243 #define nUCIE 0x0 2244 #define DCIE 0x4 /* Down count Interrupt Enable */ 2245 #define nDCIE 0x0 2246 #define MINCIE 0x8 /* Min Count Interrupt Enable */ 2247 #define nMINCIE 0x0 2248 #define MAXCIE 0x10 /* Max Count Interrupt Enable */ 2249 #define nMAXCIE 0x0 2250 #define COV31IE 0x20 /* Bit 31 Overflow Interrupt Enable */ 2251 #define nCOV31IE 0x0 2252 #define COV15IE 0x40 /* Bit 15 Overflow Interrupt Enable */ 2253 #define nCOV15IE 0x0 2254 #define CZEROIE 0x80 /* Count to Zero Interrupt Enable */ 2255 #define nCZEROIE 0x0 2256 #define CZMIE 0x100 /* CZM Pin Interrupt Enable */ 2257 #define nCZMIE 0x0 2258 #define CZMEIE 0x200 /* CZM Error Interrupt Enable */ 2259 #define nCZMEIE 0x0 2260 #define CZMZIE 0x400 /* CZM Zeroes Counter Interrupt Enable */ 2261 #define nCZMZIE 0x0 2262 2263 /* Bit masks for CNT_STATUS */ 2264 #define ICII 0x1 /* Illegal Gray/Binary Code Interrupt Identifier */ 2265 #define nICII 0x0 2266 #define UCII 0x2 /* Up count Interrupt Identifier */ 2267 #define nUCII 0x0 2268 #define DCII 0x4 /* Down count Interrupt Identifier */ 2269 #define nDCII 0x0 2270 #define MINCII 0x8 /* Min Count Interrupt Identifier */ 2271 #define nMINCII 0x0 2272 #define MAXCII 0x10 /* Max Count Interrupt Identifier */ 2273 #define nMAXCII 0x0 2274 #define COV31II 0x20 /* Bit 31 Overflow Interrupt Identifier */ 2275 #define nCOV31II 0x0 2276 #define COV15II 0x40 /* Bit 15 Overflow Interrupt Identifier */ 2277 #define nCOV15II 0x0 2278 #define CZEROII 0x80 /* Count to Zero Interrupt Identifier */ 2279 #define nCZEROII 0x0 2280 #define CZMII 0x100 /* CZM Pin Interrupt Identifier */ 2281 #define nCZMII 0x0 2282 #define CZMEII 0x200 /* CZM Error Interrupt Identifier */ 2283 #define nCZMEII 0x0 2284 #define CZMZII 0x400 /* CZM Zeroes Counter Interrupt Identifier */ 2285 #define nCZMZII 0x0 2286 2287 /* Bit masks for CNT_COMMAND */ 2288 #define W1LCNT 0xf /* Load Counter Register */ 2289 #define W1LMIN 0xf0 /* Load Min Register */ 2290 #define W1LMAX 0xf00 /* Load Max Register */ 2291 #define W1ZMONCE 0x1000 /* Enable CZM Clear Counter Once */ 2292 #define nW1ZMONCE 0x0 2293 2294 /* Bit masks for CNT_DEBOUNCE */ 2295 #define DPRESCALE 0xf /* Load Counter Register */ 2296 2297 2298 /********************************************** PWM Masks *******************************************************/ 2299 2300 /* Bit masks for PWM_CTRL */ 2301 #define PWM_EN 0x1 /* PWM Enable */ 2302 #define PWM_SYNC_EN 0X2 /* Enable Sync Enable */ 2303 #define PWM_DBL 0x4 /* Double Update Mode */ 2304 #define PWM_EXTSYNC 0x8 /* External Sync */ 2305 #define PWM_SYNCSEL 0x10 /* External Sync Select */ 2306 #define PWM_POLARITY 0x20 /* PWM Output Polarity */ 2307 #define PWM_SRMODE 0x40 /* PWM SR MODE */ 2308 #define PWMTRIPINT_EN 0x80 /* Trip Interrupt Enable */ 2309 #define PWMSYNCINT_EN 0x100 /* Sync Interrupt Enable */ 2310 #define PWMTRIP_DSBL 0x200 /* Trip Input Disable */ 2311 2312 /* Bit masks for PWM_STAT */ 2313 #define PWM_PHASE 0x1 /* PWM phase */ 2314 #define PWM_POL 0x2 /* PWM polarity */ 2315 #define PWM_SR 0x4 /* PWM SR mode */ 2316 #define PWM_TRIP 0x8 /* PWM Trip mode */ 2317 #define PWM_TRIPINT 0x100 /* PWM Trip Interrupt */ 2318 #define PWM_SYNCINT 0x200 /* PWM Sync Interrupt */ 2319 2320 /* Bit masks for PWMGATE Register */ 2321 2322 #define CHOPHI 0x100 /* Gate Chopping Enable High Side */ 2323 #define CHOPLO 0x200 /* Gate Chopping Enable Low Side */ 2324 2325 /* Bit masks for PWMSEG Register */ 2326 2327 #define CH_EN 0x1 /* CH output Enable */ 2328 #define CL_EN 0x2 /* CL output Enable */ 2329 #define BH_EN 0x4 /* BH output Enable */ 2330 #define BL_EN 0x8 /* BL output Enable */ 2331 #define AH_EN 0x10 /* AH output Enable */ 2332 #define AL_EN 0x20 /* AL output Enable */ 2333 #define CHCL_XOVR 0x40 /* Channel C output Crossover */ 2334 #define BHBL_XOVR 0x80 /* Channel B output Crossover */ 2335 #define AHAL_XOVR 0x100 /* Channel A output Crossover */ 2336 2337 /* Bit masks for PWMLSI Register */ 2338 #define PWM_SR_LSI_A 0x1 /* PWM SR Low Side Invert Channel A */ 2339 #define PWM_SR_LSI_B 0x2 /* PWM SR Low Side Invert Channel A */ 2340 #define PWM_SR_LSI_C 0x4 /* PWM SR Low Side Invert Channel A */ 2341 2342 /* Bit masks for PWM_STAT2 Register */ 2343 #define PWM_AL 0x1 /* pwm_al output signal for S/W observation */ 2344 #define PWM_AH 0x2 /* pwm_ah output signal for S/W observation */ 2345 #define PWM_BL 0x4 /* pwm_bl output signal for S/W observation */ 2346 #define PWM_BH 0x8 /* pwm_bh output signal for S/W observation */ 2347 #define PWM_CL 0x10 /* pwm_cl output signal for S/W observation */ 2348 #define PWM_CH 0x20 /* pwm_ch output signal for S/W observation */ 2349 2350 2351 /*********************************** RSI MASKS ************************************/ 2352 2353 /* Bit masks for RSI_PWR_CONTROL */ 2354 #define PWR_ON 0x3 /* Power On */ 2355 #define RSI_CMD_OD 0x40 /* Open Drain Output */ 2356 /* legacy bit mask (below) provided for backwards code compatibility */ 2357 #define SD_CMD_OD (RSI_CMD_OD) /* Open Drain Output */ 2358 /* legacy bit mask (below) provided for backwards code compatibility */ 2359 #define nSD_CMD_OD 0x0 2360 /* legacy bit mask (below) provided for backwards code compatibility */ 2361 #if 0 2362 #define TBD 0x3c /* TBD */ 2363 #endif 2364 /* legacy bit mask (below) provided for backwards code compatibility */ 2365 #define ROD_CTL 0x80 2366 /* legacy bit mask (below) provided for backwards code compatibility */ 2367 #define nROD_CTL 0x80 2368 2369 2370 /* Bit masks for RSI_CLK_CONTROL */ 2371 #define CLKDIV 0xff /* MC_CLK Divisor */ 2372 #define CLK_EN 0x100 /* MC_CLK Bus Clock Enable */ 2373 /* legacy bit mask (below) provided for backwards code compatibility */ 2374 #define CLK_E (CLK_EN) /* MC_CLK Bus Clock Enable */ 2375 /* legacy bit mask (below) provided for backwards code compatibility */ 2376 #define nCLK_E 0x0 2377 #define PWR_SV_EN 0x200 /* Power Save Enable */ 2378 /* legacy bit mask (below) provided for backwards code compatibility */ 2379 #define PWR_SV_E (PWR_SV_EN) /* Power Save Enable */ 2380 /* legacy bit mask (below) provided for backwards code compatibility */ 2381 #define nPWR_SV_E 0x0 2382 #define CLKDIV_BYPASS 0x400 /* Bypass Divisor */ 2383 /* legacy bit mask (below) provided for backwards code compatibility */ 2384 #define nCLKDIV_BYPASS 0x0 2385 #define BUS_MODE 0x1800 /* Bus width selection */ 2386 /* legacy bit mask (below) provided for backwards code compatibility */ 2387 #define WIDE_BUS 0x0800 /* Wide Bus Mode Enable */ 2388 /* legacy bit mask (below) provided for backwards code compatibility */ 2389 #define nWIDE_BUS 0x0 2390 2391 2392 /* Bit masks for RSI_COMMAND */ 2393 #define CMD_IDX 0x3f /* Command Index */ 2394 #define CMD_RSP_EN 0x40 /* Response */ 2395 /* legacy bit mask (below) provided for backwards code compatibility */ 2396 #define CMD_RSP (CMD_RSP_EN) /* Response */ 2397 /* legacy bit mask (below) provided for backwards code compatibility */ 2398 #define nCMD_RSP 0x0 2399 #define CMD_LRSP_EN 0x80 /* Long Response */ 2400 /* legacy bit mask (below) provided for backwards code compatibility */ 2401 #define CMD_L_RSP (CMD_LRSP_EN) /* Long Response */ 2402 /* legacy bit mask (below) provided for backwards code compatibility */ 2403 #define nCMD_L_RSP 0x0 2404 #define CMD_INT_EN 0x100 /* Command Interrupt */ 2405 /* legacy bit mask (below) provided for backwards code compatibility */ 2406 #define CMD_INT_E (CMD_INT_EN) /* Command Interrupt */ 2407 /* legacy bit mask (below) provided for backwards code compatibility */ 2408 #define nCMD_INT_E 0x0 2409 #define CMD_PEND_EN 0x200 /* Command Pending */ 2410 /* legacy bit mask (below) provided for backwards code compatibility */ 2411 #define CMD_PEND_E (CMD_PEND_EN) /* Command Pending */ 2412 /* legacy bit mask (below) provided for backwards code compatibility */ 2413 #define nCMD_PEND_E 0x0 2414 #define CMD_EN 0x400 /* Command Enable */ 2415 /* legacy bit mask (below) provided for backwards code compatibility */ 2416 #define CMD_E (CMD_EN) /* Command Enable */ 2417 /* legacy bit mask (below) provided for backwards code compatibility */ 2418 #define nCMD_E 0x0 2419 2420 2421 /* Bit masks for RSI_RESP_CMD */ 2422 #define RESP_CMD 0x3f /* Response Command */ 2423 2424 /* Bit masks for RSI_DATA_LGTH */ 2425 #define DATA_LENGTH 0xffff /* Data Length */ 2426 2427 2428 /* Bit masks for RSI_DATA_CONTROL */ 2429 #define DATA_EN 0x1 /* Data Transfer Enable */ 2430 /* legacy bit mask (below) provided for backwards code compatibility */ 2431 #define DTX_E (DATA_EN) /* Data Transfer Enable */ 2432 /* legacy bit mask (below) provided for backwards code compatibility */ 2433 #define nDTX_E 0x0 2434 #define DATA_DIR 0x2 /* Data Transfer Direction */ 2435 /* legacy bit mask (below) provided for backwards code compatibility */ 2436 #define DTX_DIR (DATA_DIR) /* Data Transfer Direction */ 2437 /* legacy bit mask (below) provided for backwards code compatibility */ 2438 #define nDTX_DIR 0x0 2439 #define DATA_MODE 0x4 /* Data Transfer Mode */ 2440 /* legacy bit mask (below) provided for backwards code compatibility */ 2441 #define DTX_MODE (DATA_MODE) /* Data Transfer Mode */ 2442 /* legacy bit mask (below) provided for backwards code compatibility */ 2443 #define nDTX_MODE 0x0 2444 #define DATA_DMA_EN 0x8 /* Data Transfer DMA Enable */ 2445 /* legacy bit mask (below) provided for backwards code compatibility */ 2446 #define DTX_DMA_E 0x8 /* Data Transfer DMA Enable */ 2447 /* legacy bit mask (below) provided for backwards code compatibility */ 2448 #define nDTX_DMA_E 0x0 2449 #define DATA_BLK_LGTH 0xf0 /* Data Transfer Block Length */ 2450 /* legacy bit mask (below) provided for backwards code compatibility */ 2451 #define DTX_BLK_LGTH 0xf0 /* Data Transfer Block Length */ 2452 #define CEATA_EN 0x100 /* CE-ATA operation mode enable */ 2453 #define CEATA_CCS_EN 0x200 /* CE-ATA CCS mode enable */ 2454 2455 /* Bit masks for RSI_DATA_CNT */ 2456 #define DATA_COUNT 0xffff /* Data Count */ 2457 2458 /* Bit masks for RSI_STATUS */ 2459 #define CMD_CRC_FAIL 0x1 /* CMD CRC Fail */ 2460 /* legacy bit mask (below) provided for backwards code compatibility */ 2461 #define nCMD_CRC_FAIL 0x0 2462 #define DAT_CRC_FAIL 0x2 /* Data CRC Fail */ 2463 /* legacy bit mask (below) provided for backwards code compatibility */ 2464 #define nDAT_CRC_FAIL 0x0 2465 #define CMD_TIMEOUT 0x4 /* CMD Time Out */ 2466 /* legacy bit mask (below) provided for backwards code compatibility */ 2467 #define nCMD_TIMEOUT 0x0 2468 #define DAT_TIMEOUT 0x8 /* Data Time Out */ 2469 /* legacy bit mask (below) provided for backwards code compatibility */ 2470 #define nDAT_TIMEOUT 0x0 2471 #define TX_UNDERRUN 0x10 /* Transmit Underrun */ 2472 /* legacy bit mask (below) provided for backwards code compatibility */ 2473 #define nTX_UNDERRUN 0x0 2474 #define RX_OVERRUN 0x20 /* Receive Overrun */ 2475 /* legacy bit mask (below) provided for backwards code compatibility */ 2476 #define nRX_OVERRUN 0x0 2477 #define CMD_RESP_END 0x40 /* CMD Response End */ 2478 /* legacy bit mask (below) provided for backwards code compatibility */ 2479 #define nCMD_RESP_END 0x0 2480 #define CMD_SENT 0x80 /* CMD Sent */ 2481 /* legacy bit mask (below) provided for backwards code compatibility */ 2482 #define nCMD_SENT 0x0 2483 #define DAT_END 0x100 /* Data End */ 2484 /* legacy bit mask (below) provided for backwards code compatibility */ 2485 #define nDAT_END 0x0 2486 #define START_BIT_ERR 0x200 /* Start Bit Error */ 2487 /* legacy bit mask (below) provided for backwards code compatibility */ 2488 #define nSTART_BIT_ERR 0x0 2489 #define DAT_BLK_END 0x400 /* Data Block End */ 2490 /* legacy bit mask (below) provided for backwards code compatibility */ 2491 #define nDAT_BLK_END 0x0 2492 #define CMD_ACT 0x800 /* CMD Active */ 2493 /* legacy bit mask (below) provided for backwards code compatibility */ 2494 #define nCMD_ACT 0x0 2495 #define TX_ACT 0x1000 /* Transmit Active */ 2496 /* legacy bit mask (below) provided for backwards code compatibility */ 2497 #define nTX_ACT 0x0 2498 #define RX_ACT 0x2000 /* Receive Active */ 2499 /* legacy bit mask (below) provided for backwards code compatibility */ 2500 #define nRX_ACT 0x0 2501 #define TX_FIFO_STAT 0x4000 /* Transmit FIFO Status */ 2502 /* legacy bit mask (below) provided for backwards code compatibility */ 2503 #define nTX_FIFO_STAT 0x0 2504 #define RX_FIFO_STAT 0x8000 /* Receive FIFO Status */ 2505 /* legacy bit mask (below) provided for backwards code compatibility */ 2506 #define nRX_FIFO_STAT 0x0 2507 #define TX_FIFO_FULL 0x10000 /* Transmit FIFO Full */ 2508 /* legacy bit mask (below) provided for backwards code compatibility */ 2509 #define nTX_FIFO_FULL 0x0 2510 #define RX_FIFO_FULL 0x20000 /* Receive FIFO Full */ 2511 /* legacy bit mask (below) provided for backwards code compatibility */ 2512 #define nRX_FIFO_FULL 0x0 2513 #define TX_FIFO_ZERO 0x40000 /* Transmit FIFO Empty */ 2514 /* legacy bit mask (below) provided for backwards code compatibility */ 2515 #define nTX_FIFO_ZERO 0x0 2516 #define RX_DAT_ZERO 0x80000 /* Receive FIFO Empty */ 2517 /* legacy bit mask (below) provided for backwards code compatibility */ 2518 #define nRX_DAT_ZERO 0x0 2519 #define TX_DAT_RDY 0x100000 /* Transmit Data Available */ 2520 /* legacy bit mask (below) provided for backwards code compatibility */ 2521 #define nTX_DAT_RDY 0x0 2522 #define RX_FIFO_RDY 0x200000 /* Receive Data Available */ 2523 /* legacy bit mask (below) provided for backwards code compatibility */ 2524 #define nRX_FIFO_RDY 0x0 2525 2526 /* Bit masks for RSI_STATCL */ 2527 2528 #define CMD_CRC_FAIL_STAT 0x1 /* CMD CRC Fail Status */ 2529 /* legacy bit mask (below) provided for backwards code compatibility */ 2530 #define nCMD_CRC_FAIL_STAT 0x0 2531 #define DAT_CRC_FAIL_STAT 0x2 /* Data CRC Fail Status */ 2532 /* legacy bit mask (below) provided for backwards code compatibility */ 2533 #define nDAT_CRC_FAIL_STAT 0x0 2534 #define CMD_TIMEOUT_STAT 0x4 /* CMD Time Out Status */ 2535 /* legacy bit mask (below) provided for backwards code compatibility */ 2536 #define nCMD_TIMEOUT_STAT 0x0 2537 #define DAT_TIMEOUT_STAT 0x8 /* Data Time Out status */ 2538 /* legacy bit mask (below) provided for backwards code compatibility */ 2539 #define nDAT_TIMEOUT_STAT 0x0 2540 #define TX_UNDERRUN_STAT 0x10 /* Transmit Underrun Status */ 2541 /* legacy bit mask (below) provided for backwards code compatibility */ 2542 #define nTX_UNDERRUN_STAT 0x0 2543 #define RX_OVERRUN_STAT 0x20 /* Receive Overrun Status */ 2544 /* legacy bit mask (below) provided for backwards code compatibility */ 2545 #define nRX_OVERRUN_STAT 0x0 2546 #define CMD_RESP_END_STAT 0x40 /* CMD Response End Status */ 2547 /* legacy bit mask (below) provided for backwards code compatibility */ 2548 #define nCMD_RESP_END_STAT 0x0 2549 #define CMD_SENT_STAT 0x80 /* CMD Sent Status */ 2550 /* legacy bit mask (below) provided for backwards code compatibility */ 2551 #define nCMD_SENT_STAT 0x0 2552 #define DAT_END_STAT 0x100 /* Data End Status */ 2553 /* legacy bit mask (below) provided for backwards code compatibility */ 2554 #define nDAT_END_STAT 0x0 2555 #define START_BIT_ERR_STAT 0x200 /* Start Bit Error Status */ 2556 /* legacy bit mask (below) provided for backwards code compatibility */ 2557 #define nSTART_BIT_ERR_STAT 0x0 2558 #define DAT_BLK_END_STAT 0x400 /* Data Block End Status */ 2559 /* legacy bit mask (below) provided for backwards code compatibility */ 2560 #define nDAT_BLK_END_STAT 0x0 2561 2562 /* Bit masks for RSI_MASKx */ 2563 2564 #define CMD_CRC_FAIL_MASK 0x1 /* CMD CRC Fail Mask */ 2565 /* legacy bit mask (below) provided for backwards code compatibility */ 2566 #define nCMD_CRC_FAIL_MASK 0x0 2567 #define DAT_CRC_FAIL_MASK 0x2 /* Data CRC Fail Mask */ 2568 /* legacy bit mask (below) provided for backwards code compatibility */ 2569 #define nDAT_CRC_FAIL_MASK 0x0 2570 #define CMD_TIMEOUT_MASK 0x4 /* CMD Time Out Mask */ 2571 /* legacy bit mask (below) provided for backwards code compatibility */ 2572 #define nCMD_TIMEOUT_MASK 0x0 2573 #define DAT_TIMEOUT_MASK 0x8 /* Data Time Out Mask */ 2574 /* legacy bit mask (below) provided for backwards code compatibility */ 2575 #define nDAT_TIMEOUT_MASK 0x0 2576 #define TX_UNDERRUN_MASK 0x10 /* Transmit Underrun Mask */ 2577 /* legacy bit mask (below) provided for backwards code compatibility */ 2578 #define nTX_UNDERRUN_MASK 0x0 2579 #define RX_OVERRUN_MASK 0x20 /* Receive Overrun Mask */ 2580 /* legacy bit mask (below) provided for backwards code compatibility */ 2581 #define nRX_OVERRUN_MASK 0x0 2582 #define CMD_RESP_END_MASK 0x40 /* CMD Response End Mask */ 2583 /* legacy bit mask (below) provided for backwards code compatibility */ 2584 #define nCMD_RESP_END_MASK 0x0 2585 #define CMD_SENT_MASK 0x80 /* CMD Sent Mask */ 2586 /* legacy bit mask (below) provided for backwards code compatibility */ 2587 #define nCMD_SENT_MASK 0x0 2588 #define DAT_END_MASK 0x100 /* Data End Mask */ 2589 /* legacy bit mask (below) provided for backwards code compatibility */ 2590 #define nDAT_END_MASK 0x0 2591 #define START_BIT_ERR_MASK 0x200 /* Start Bit Error Mask */ 2592 /* legacy bit mask (below) provided for backwards code compatibility */ 2593 #define nSTART_BIT_ERR_MASK 0x0 2594 #define DAT_BLK_END_MASK 0x400 /* Data Block End Mask */ 2595 /* legacy bit mask (below) provided for backwards code compatibility */ 2596 #define nDAT_BLK_END_MASK 0x0 2597 #define CMD_ACT_MASK 0x800 /* CMD Active Mask */ 2598 /* legacy bit mask (below) provided for backwards code compatibility */ 2599 #define nCMD_ACT_MASK 0x0 2600 #define TX_ACT_MASK 0x1000 /* Transmit Active Mask */ 2601 /* legacy bit mask (below) provided for backwards code compatibility */ 2602 #define nTX_ACT_MASK 0x0 2603 #define RX_ACT_MASK 0x2000 /* Receive Active Mask */ 2604 /* legacy bit mask (below) provided for backwards code compatibility */ 2605 #define nRX_ACT_MASK 0x0 2606 #define TX_FIFO_STAT_MASK 0x4000 /* Transmit FIFO Status Mask */ 2607 /* legacy bit mask (below) provided for backwards code compatibility */ 2608 #define nTX_FIFO_STAT_MASK 0x0 2609 #define RX_FIFO_STAT_MASK 0x8000 /* Receive FIFO Status Mask */ 2610 /* legacy bit mask (below) provided for backwards code compatibility */ 2611 #define nRX_FIFO_STAT_MASK 0x0 2612 #define TX_FIFO_FULL_MASK 0x10000 /* Transmit FIFO Full Mask */ 2613 /* legacy bit mask (below) provided for backwards code compatibility */ 2614 #define nTX_FIFO_FULL_MASK 0x0 2615 #define RX_FIFO_FULL_MASK 0x20000 /* Receive FIFO Full Mask */ 2616 /* legacy bit mask (below) provided for backwards code compatibility */ 2617 #define nRX_FIFO_FULL_MASK 0x0 2618 #define TX_FIFO_ZERO_MASK 0x40000 /* Transmit FIFO Empty Mask */ 2619 /* legacy bit mask (below) provided for backwards code compatibility */ 2620 #define nTX_FIFO_ZERO_MASK 0x0 2621 #define RX_DAT_ZERO_MASK 0x80000 /* Receive FIFO Empty Mask */ 2622 /* legacy bit mask (below) provided for backwards code compatibility */ 2623 #define nRX_DAT_ZERO_MASK 0x0 2624 #define TX_DAT_RDY_MASK 0x100000 /* Transmit Data Available Mask */ 2625 /* legacy bit mask (below) provided for backwards code compatibility */ 2626 #define nTX_DAT_RDY_MASK 0x0 2627 #define RX_FIFO_RDY_MASK 0x200000 /* Receive Data Available Mask */ 2628 /* legacy bit mask (below) provided for backwards code compatibility */ 2629 #define nRX_FIFO_RDY_MASK 0x0 2630 2631 /* Bit masks for RSI_FIFO_CNT */ 2632 #define FIFO_COUNT 0x7fff /* FIFO Count */ 2633 2634 /* Bit masks for RSI_CEATA_CONTROL */ 2635 #define CEATA_TX_CCSD 0x1 /* Send CE-ATA CCSD sequence */ 2636 2637 /* Bit masks for RSI_ESTAT */ 2638 #define SDIO_INT_DET 0x2 /* SDIO Int Detected */ 2639 /* legacy bit mask (below) provided for backwards code compatibility */ 2640 #define nSDIO_INT_DET 0x0 2641 #define SD_CARD_DET 0x10 /* SD Card Detect */ 2642 /* legacy bit mask (below) provided for backwards code compatibility */ 2643 #define nSD_CARD_DET 0x0 2644 #define CEATA_INT_DET 0x20 2645 2646 /* Bit masks for RSI_EMASK */ 2647 #define SDIO_INT_DET_MASK 0x2 /* Mask SDIO Int Detected */ 2648 /* legacy bit mask (below) provided for backwards code compatibility */ 2649 #define SDIO_MSK (SDIO_INT_DET_MASK)/* Mask SDIO Int Detected */ 2650 /* legacy bit mask (below) provided for backwards code compatibility */ 2651 #define nSDIO_MSK 0x0 2652 #define SD_CARD_DET_MASK 0x10 /* Mask Card Detect */ 2653 /* legacy bit mask (below) provided for backwards code compatibility */ 2654 #define SCD_MASK (SD_CARD_DET_MASK) /* Mask Card Detect */ 2655 /* legacy bit mask (below) provided for backwards code compatibility */ 2656 #define nSCD_MSK 0x0 2657 #define CEATA_INT_DET_MASK 0x20 2658 2659 2660 /* Bit masks for SDH_CFG */ 2661 2662 /* Left in for backwards compatibility */ 2663 #define RSI_CLK_EN 0x1 2664 /* legacy bit mask (below) provided for backwards code compatibility */ 2665 #define CLKS_EN (RSI_CLK_EN) /* Clocks Enable */ 2666 /* legacy bit mask (below) provided for backwards code compatibility */ 2667 #define nCLKS_EN 0x0 2668 #define SDIO4_EN 0x4 /* SDIO 4-Bit Enable */ 2669 /* legacy bit mask (below) provided for backwards code compatibility */ 2670 #define SD4E (SDIO4_EN) /* SDIO 4-Bit Enable */ 2671 /* legacy bit mask (below) provided for backwards code compatibility */ 2672 #define nSD4E 0x0 2673 #define MW_EN 0x8 /* Moving Window Enable */ 2674 /* legacy bit mask (below) provided for backwards code compatibility */ 2675 #define MWE (MW_EN) /* Moving Window Enable */ 2676 /* legacy bit mask (below) provided for backwards code compatibility */ 2677 #define nMWE 0x0 2678 #define RSI_RST 0x10 /* SDMMC Reset */ 2679 /* legacy bit mask (below) provided for backwards code compatibility */ 2680 #define SD_RST (RSI_RST) /* SDMMC Reset */ 2681 /* legacy bit mask (below) provided for backwards code compatibility */ 2682 #define nSD_RST 0x0 2683 #define PU_DAT 0x20 /* Pull-up SD_DAT */ 2684 /* legacy bit mask (below) provided for backwards code compatibility */ 2685 #define PUP_SDDAT (PU_DAT) /* Pull-up SD_DAT */ 2686 /* legacy bit mask (below) provided for backwards code compatibility */ 2687 #define nPUP_SDDAT 0x0 2688 #define PU_DAT3 0x40 /* Pull-up SD_DAT3 */ 2689 /* legacy bit mask (below) provided for backwards code compatibility */ 2690 #define PUP_SDDAT3 (PU_DAT3) /* Pull-up SD_DAT3 */ 2691 /* legacy bit mask (below) provided for backwards code compatibility */ 2692 #define nPUP_SDDAT3 0x0 2693 #define PD_DAT3 0x80 /* Pull-down SD_DAT3 */ 2694 /* legacy bit mask (below) provided for backwards code compatibility */ 2695 #define PD_SDDAT3 (PD_DAT3) /* Pull-down SD_DAT3 */ 2696 /* legacy bit mask (below) provided for backwards code compatibility */ 2697 #define nPD_SDDAT3 0x0 2698 2699 2700 /* Bit masks for RSI_RD_WAIT_EN */ 2701 #define SDIO_RWR 0x1 /* Read Wait Request */ 2702 /* legacy bit mask (below) provided for backwards code compatibility */ 2703 #define RWR (SDIO_RWR) /* Read Wait Request */ 2704 /* legacy bit mask (below) provided for backwards code compatibility */ 2705 #define nRWR 0x0 2706 2707 /* Bit masks for RSI_PIDx */ 2708 #define RSI_PID 0xff /* RSI Peripheral ID */ 2709 2710 2711 /* ************ CONTROLLER AREA NETWORK (CAN) MASKS ***************/ 2712 2713 /* CAN_CONTROL Masks */ 2714 #define SRS 0x0001 /* Software Reset */ 2715 #define DNM 0x0002 /* Device Net Mode */ 2716 #define ABO 0x0004 /* Auto-Bus On Enable */ 2717 #define WBA 0x0010 /* Wake-Up On CAN Bus Activity Enable */ 2718 #define SMR 0x0020 /* Sleep Mode Request */ 2719 #define CSR 0x0040 /* CAN Suspend Mode Request */ 2720 #define CCR 0x0080 /* CAN Configuration Mode Request */ 2721 2722 /* CAN_STATUS Masks */ 2723 #define WT 0x0001 /* TX Warning Flag */ 2724 #define WR 0x0002 /* RX Warning Flag */ 2725 #define EP 0x0004 /* Error Passive Mode */ 2726 #define EBO 0x0008 /* Error Bus Off Mode */ 2727 #define CSA 0x0040 /* Suspend Mode Acknowledge */ 2728 #define CCA 0x0080 /* Configuration Mode Acknowledge */ 2729 #define MBPTR 0x1F00 /* Mailbox Pointer */ 2730 #define TRM 0x4000 /* Transmit Mode */ 2731 #define REC 0x8000 /* Receive Mode */ 2732 2733 /* CAN_CLOCK Masks */ 2734 #define BRP 0x03FF /* Bit-Rate Pre-Scaler */ 2735 2736 /* CAN_TIMING Masks */ 2737 #define TSEG1 0x000F /* Time Segment 1 */ 2738 #define TSEG2 0x0070 /* Time Segment 2 */ 2739 #define SAM 0x0080 /* Sampling */ 2740 #define SJW 0x0300 /* Synchronization Jump Width */ 2741 2742 /* CAN_DEBUG Masks */ 2743 #define DEC 0x0001 /* Disable CAN Error Counters */ 2744 #define DRI 0x0002 /* Disable CAN RX Input */ 2745 #define DTO 0x0004 /* Disable CAN TX Output */ 2746 #define DIL 0x0008 /* Disable CAN Internal Loop */ 2747 #define MAA 0x0010 /* Mode Auto-Acknowledge Enable */ 2748 #define MRB 0x0020 /* Mode Read Back Enable */ 2749 #define CDE 0x8000 /* CAN Debug Enable */ 2750 2751 /* CAN_CEC Masks */ 2752 #define RXECNT 0x00FF /* Receive Error Counter */ 2753 #define TXECNT 0xFF00 /* Transmit Error Counter */ 2754 2755 /* CAN_INTR Masks */ 2756 #define MBRIRQ 0x0001 /* Mailbox Receive Interrupt */ 2757 #define MBRIF (MBRIRQ) /* legacy */ 2758 #define MBTIRQ 0x0002 /* Mailbox Transmit Interrupt */ 2759 #define MBTIF (MBTIRQ) /* legacy */ 2760 #define GIRQ 0x0004 /* Global Interrupt */ 2761 #define SMACK 0x0008 /* Sleep Mode Acknowledge */ 2762 #define CANTX 0x0040 /* CAN TX Bus Value */ 2763 #define CANRX 0x0080 /* CAN RX Bus Value */ 2764 2765 /* CAN_MBxx_ID1 and CAN_MBxx_ID0 Masks */ 2766 #define DFC 0xFFFF /* Data Filtering Code (If Enabled) (ID0) */ 2767 #define EXTID_LO 0xFFFF /* Lower 16 Bits of Extended Identifier (ID0) */ 2768 #define EXTID_HI 0x0003 /* Upper 2 Bits of Extended Identifier (ID1) */ 2769 #define BASEID 0x1FFC /* Base Identifier */ 2770 #define IDE 0x2000 /* Identifier Extension */ 2771 #define RTR 0x4000 /* Remote Frame Transmission Request */ 2772 #define AME 0x8000 /* Acceptance Mask Enable */ 2773 2774 /* CAN_MBxx_TIMESTAMP Masks */ 2775 #define TSV 0xFFFF /* Timestamp */ 2776 2777 /* CAN_MBxx_LENGTH Masks */ 2778 #define DLC 0x000F /* Data Length Code */ 2779 2780 /* CAN_AMxxH and CAN_AMxxL Masks */ 2781 #define DFM 0xFFFF /* Data Field Mask (If Enabled) (CAN_AMxxL) */ 2782 #define EXTID_LO 0xFFFF /* Lower 16 Bits of Extended Identifier (CAN_AMxxL) */ 2783 #define EXTID_HI 0x0003 /* Upper 2 Bits of Extended Identifier (CAN_AMxxH) */ 2784 #define BASEID 0x1FFC /* Base Identifier */ 2785 #define AMIDE 0x2000 /* Acceptance Mask ID Extension Enable */ 2786 #define FMD 0x4000 /* Full Mask Data Field Enable */ 2787 #define FDF 0x8000 /* Filter On Data Field Enable */ 2788 2789 /* CAN_MC1 Masks */ 2790 #define MC0 0x0001 /* Enable Mailbox 0 */ 2791 #define MC1 0x0002 /* Enable Mailbox 1 */ 2792 #define MC2 0x0004 /* Enable Mailbox 2 */ 2793 #define MC3 0x0008 /* Enable Mailbox 3 */ 2794 #define MC4 0x0010 /* Enable Mailbox 4 */ 2795 #define MC5 0x0020 /* Enable Mailbox 5 */ 2796 #define MC6 0x0040 /* Enable Mailbox 6 */ 2797 #define MC7 0x0080 /* Enable Mailbox 7 */ 2798 #define MC8 0x0100 /* Enable Mailbox 8 */ 2799 #define MC9 0x0200 /* Enable Mailbox 9 */ 2800 #define MC10 0x0400 /* Enable Mailbox 10 */ 2801 #define MC11 0x0800 /* Enable Mailbox 11 */ 2802 #define MC12 0x1000 /* Enable Mailbox 12 */ 2803 #define MC13 0x2000 /* Enable Mailbox 13 */ 2804 #define MC14 0x4000 /* Enable Mailbox 14 */ 2805 #define MC15 0x8000 /* Enable Mailbox 15 */ 2806 2807 /* CAN_MC2 Masks */ 2808 #define MC16 0x0001 /* Enable Mailbox 16 */ 2809 #define MC17 0x0002 /* Enable Mailbox 17 */ 2810 #define MC18 0x0004 /* Enable Mailbox 18 */ 2811 #define MC19 0x0008 /* Enable Mailbox 19 */ 2812 #define MC20 0x0010 /* Enable Mailbox 20 */ 2813 #define MC21 0x0020 /* Enable Mailbox 21 */ 2814 #define MC22 0x0040 /* Enable Mailbox 22 */ 2815 #define MC23 0x0080 /* Enable Mailbox 23 */ 2816 #define MC24 0x0100 /* Enable Mailbox 24 */ 2817 #define MC25 0x0200 /* Enable Mailbox 25 */ 2818 #define MC26 0x0400 /* Enable Mailbox 26 */ 2819 #define MC27 0x0800 /* Enable Mailbox 27 */ 2820 #define MC28 0x1000 /* Enable Mailbox 28 */ 2821 #define MC29 0x2000 /* Enable Mailbox 29 */ 2822 #define MC30 0x4000 /* Enable Mailbox 30 */ 2823 #define MC31 0x8000 /* Enable Mailbox 31 */ 2824 2825 /* CAN_MD1 Masks */ 2826 #define MD0 0x0001 /* Enable Mailbox 0 For Receive */ 2827 #define MD1 0x0002 /* Enable Mailbox 1 For Receive */ 2828 #define MD2 0x0004 /* Enable Mailbox 2 For Receive */ 2829 #define MD3 0x0008 /* Enable Mailbox 3 For Receive */ 2830 #define MD4 0x0010 /* Enable Mailbox 4 For Receive */ 2831 #define MD5 0x0020 /* Enable Mailbox 5 For Receive */ 2832 #define MD6 0x0040 /* Enable Mailbox 6 For Receive */ 2833 #define MD7 0x0080 /* Enable Mailbox 7 For Receive */ 2834 #define MD8 0x0100 /* Enable Mailbox 8 For Receive */ 2835 #define MD9 0x0200 /* Enable Mailbox 9 For Receive */ 2836 #define MD10 0x0400 /* Enable Mailbox 10 For Receive */ 2837 #define MD11 0x0800 /* Enable Mailbox 11 For Receive */ 2838 #define MD12 0x1000 /* Enable Mailbox 12 For Receive */ 2839 #define MD13 0x2000 /* Enable Mailbox 13 For Receive */ 2840 #define MD14 0x4000 /* Enable Mailbox 14 For Receive */ 2841 #define MD15 0x8000 /* Enable Mailbox 15 For Receive */ 2842 2843 /* CAN_MD2 Masks */ 2844 #define MD16 0x0001 /* Enable Mailbox 16 For Receive */ 2845 #define MD17 0x0002 /* Enable Mailbox 17 For Receive */ 2846 #define MD18 0x0004 /* Enable Mailbox 18 For Receive */ 2847 #define MD19 0x0008 /* Enable Mailbox 19 For Receive */ 2848 #define MD20 0x0010 /* Enable Mailbox 20 For Receive */ 2849 #define MD21 0x0020 /* Enable Mailbox 21 For Receive */ 2850 #define MD22 0x0040 /* Enable Mailbox 22 For Receive */ 2851 #define MD23 0x0080 /* Enable Mailbox 23 For Receive */ 2852 #define MD24 0x0100 /* Enable Mailbox 24 For Receive */ 2853 #define MD25 0x0200 /* Enable Mailbox 25 For Receive */ 2854 #define MD26 0x0400 /* Enable Mailbox 26 For Receive */ 2855 #define MD27 0x0800 /* Enable Mailbox 27 For Receive */ 2856 #define MD28 0x1000 /* Enable Mailbox 28 For Receive */ 2857 #define MD29 0x2000 /* Enable Mailbox 29 For Receive */ 2858 #define MD30 0x4000 /* Enable Mailbox 30 For Receive */ 2859 #define MD31 0x8000 /* Enable Mailbox 31 For Receive */ 2860 2861 /* CAN_RMP1 Masks */ 2862 #define RMP0 0x0001 /* RX Message Pending In Mailbox 0 */ 2863 #define RMP1 0x0002 /* RX Message Pending In Mailbox 1 */ 2864 #define RMP2 0x0004 /* RX Message Pending In Mailbox 2 */ 2865 #define RMP3 0x0008 /* RX Message Pending In Mailbox 3 */ 2866 #define RMP4 0x0010 /* RX Message Pending In Mailbox 4 */ 2867 #define RMP5 0x0020 /* RX Message Pending In Mailbox 5 */ 2868 #define RMP6 0x0040 /* RX Message Pending In Mailbox 6 */ 2869 #define RMP7 0x0080 /* RX Message Pending In Mailbox 7 */ 2870 #define RMP8 0x0100 /* RX Message Pending In Mailbox 8 */ 2871 #define RMP9 0x0200 /* RX Message Pending In Mailbox 9 */ 2872 #define RMP10 0x0400 /* RX Message Pending In Mailbox 10 */ 2873 #define RMP11 0x0800 /* RX Message Pending In Mailbox 11 */ 2874 #define RMP12 0x1000 /* RX Message Pending In Mailbox 12 */ 2875 #define RMP13 0x2000 /* RX Message Pending In Mailbox 13 */ 2876 #define RMP14 0x4000 /* RX Message Pending In Mailbox 14 */ 2877 #define RMP15 0x8000 /* RX Message Pending In Mailbox 15 */ 2878 2879 /* CAN_RMP2 Masks */ 2880 #define RMP16 0x0001 /* RX Message Pending In Mailbox 16 */ 2881 #define RMP17 0x0002 /* RX Message Pending In Mailbox 17 */ 2882 #define RMP18 0x0004 /* RX Message Pending In Mailbox 18 */ 2883 #define RMP19 0x0008 /* RX Message Pending In Mailbox 19 */ 2884 #define RMP20 0x0010 /* RX Message Pending In Mailbox 20 */ 2885 #define RMP21 0x0020 /* RX Message Pending In Mailbox 21 */ 2886 #define RMP22 0x0040 /* RX Message Pending In Mailbox 22 */ 2887 #define RMP23 0x0080 /* RX Message Pending In Mailbox 23 */ 2888 #define RMP24 0x0100 /* RX Message Pending In Mailbox 24 */ 2889 #define RMP25 0x0200 /* RX Message Pending In Mailbox 25 */ 2890 #define RMP26 0x0400 /* RX Message Pending In Mailbox 26 */ 2891 #define RMP27 0x0800 /* RX Message Pending In Mailbox 27 */ 2892 #define RMP28 0x1000 /* RX Message Pending In Mailbox 28 */ 2893 #define RMP29 0x2000 /* RX Message Pending In Mailbox 29 */ 2894 #define RMP30 0x4000 /* RX Message Pending In Mailbox 30 */ 2895 #define RMP31 0x8000 /* RX Message Pending In Mailbox 31 */ 2896 2897 /* CAN_RML1 Masks */ 2898 #define RML0 0x0001 /* RX Message Lost In Mailbox 0 */ 2899 #define RML1 0x0002 /* RX Message Lost In Mailbox 1 */ 2900 #define RML2 0x0004 /* RX Message Lost In Mailbox 2 */ 2901 #define RML3 0x0008 /* RX Message Lost In Mailbox 3 */ 2902 #define RML4 0x0010 /* RX Message Lost In Mailbox 4 */ 2903 #define RML5 0x0020 /* RX Message Lost In Mailbox 5 */ 2904 #define RML6 0x0040 /* RX Message Lost In Mailbox 6 */ 2905 #define RML7 0x0080 /* RX Message Lost In Mailbox 7 */ 2906 #define RML8 0x0100 /* RX Message Lost In Mailbox 8 */ 2907 #define RML9 0x0200 /* RX Message Lost In Mailbox 9 */ 2908 #define RML10 0x0400 /* RX Message Lost In Mailbox 10 */ 2909 #define RML11 0x0800 /* RX Message Lost In Mailbox 11 */ 2910 #define RML12 0x1000 /* RX Message Lost In Mailbox 12 */ 2911 #define RML13 0x2000 /* RX Message Lost In Mailbox 13 */ 2912 #define RML14 0x4000 /* RX Message Lost In Mailbox 14 */ 2913 #define RML15 0x8000 /* RX Message Lost In Mailbox 15 */ 2914 2915 /* CAN_RML2 Masks */ 2916 #define RML16 0x0001 /* RX Message Lost In Mailbox 16 */ 2917 #define RML17 0x0002 /* RX Message Lost In Mailbox 17 */ 2918 #define RML18 0x0004 /* RX Message Lost In Mailbox 18 */ 2919 #define RML19 0x0008 /* RX Message Lost In Mailbox 19 */ 2920 #define RML20 0x0010 /* RX Message Lost In Mailbox 20 */ 2921 #define RML21 0x0020 /* RX Message Lost In Mailbox 21 */ 2922 #define RML22 0x0040 /* RX Message Lost In Mailbox 22 */ 2923 #define RML23 0x0080 /* RX Message Lost In Mailbox 23 */ 2924 #define RML24 0x0100 /* RX Message Lost In Mailbox 24 */ 2925 #define RML25 0x0200 /* RX Message Lost In Mailbox 25 */ 2926 #define RML26 0x0400 /* RX Message Lost In Mailbox 26 */ 2927 #define RML27 0x0800 /* RX Message Lost In Mailbox 27 */ 2928 #define RML28 0x1000 /* RX Message Lost In Mailbox 28 */ 2929 #define RML29 0x2000 /* RX Message Lost In Mailbox 29 */ 2930 #define RML30 0x4000 /* RX Message Lost In Mailbox 30 */ 2931 #define RML31 0x8000 /* RX Message Lost In Mailbox 31 */ 2932 2933 /* CAN_OPSS1 Masks */ 2934 #define OPSS0 0x0001 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 0 */ 2935 #define OPSS1 0x0002 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 1 */ 2936 #define OPSS2 0x0004 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 2 */ 2937 #define OPSS3 0x0008 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 3 */ 2938 #define OPSS4 0x0010 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 4 */ 2939 #define OPSS5 0x0020 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 5 */ 2940 #define OPSS6 0x0040 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 6 */ 2941 #define OPSS7 0x0080 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 7 */ 2942 #define OPSS8 0x0100 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 8 */ 2943 #define OPSS9 0x0200 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 9 */ 2944 #define OPSS10 0x0400 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 10 */ 2945 #define OPSS11 0x0800 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 11 */ 2946 #define OPSS12 0x1000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 12 */ 2947 #define OPSS13 0x2000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 13 */ 2948 #define OPSS14 0x4000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 14 */ 2949 #define OPSS15 0x8000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 15 */ 2950 2951 /* CAN_OPSS2 Masks */ 2952 #define OPSS16 0x0001 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 16 */ 2953 #define OPSS17 0x0002 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 17 */ 2954 #define OPSS18 0x0004 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 18 */ 2955 #define OPSS19 0x0008 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 19 */ 2956 #define OPSS20 0x0010 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 20 */ 2957 #define OPSS21 0x0020 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 21 */ 2958 #define OPSS22 0x0040 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 22 */ 2959 #define OPSS23 0x0080 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 23 */ 2960 #define OPSS24 0x0100 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 24 */ 2961 #define OPSS25 0x0200 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 25 */ 2962 #define OPSS26 0x0400 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 26 */ 2963 #define OPSS27 0x0800 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 27 */ 2964 #define OPSS28 0x1000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 28 */ 2965 #define OPSS29 0x2000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 29 */ 2966 #define OPSS30 0x4000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 30 */ 2967 #define OPSS31 0x8000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 31 */ 2968 2969 /* CAN_TRR1 Masks */ 2970 #define TRR0 0x0001 /* Deny But Don't Lock Access To Mailbox 0 */ 2971 #define TRR1 0x0002 /* Deny But Don't Lock Access To Mailbox 1 */ 2972 #define TRR2 0x0004 /* Deny But Don't Lock Access To Mailbox 2 */ 2973 #define TRR3 0x0008 /* Deny But Don't Lock Access To Mailbox 3 */ 2974 #define TRR4 0x0010 /* Deny But Don't Lock Access To Mailbox 4 */ 2975 #define TRR5 0x0020 /* Deny But Don't Lock Access To Mailbox 5 */ 2976 #define TRR6 0x0040 /* Deny But Don't Lock Access To Mailbox 6 */ 2977 #define TRR7 0x0080 /* Deny But Don't Lock Access To Mailbox 7 */ 2978 #define TRR8 0x0100 /* Deny But Don't Lock Access To Mailbox 8 */ 2979 #define TRR9 0x0200 /* Deny But Don't Lock Access To Mailbox 9 */ 2980 #define TRR10 0x0400 /* Deny But Don't Lock Access To Mailbox 10 */ 2981 #define TRR11 0x0800 /* Deny But Don't Lock Access To Mailbox 11 */ 2982 #define TRR12 0x1000 /* Deny But Don't Lock Access To Mailbox 12 */ 2983 #define TRR13 0x2000 /* Deny But Don't Lock Access To Mailbox 13 */ 2984 #define TRR14 0x4000 /* Deny But Don't Lock Access To Mailbox 14 */ 2985 #define TRR15 0x8000 /* Deny But Don't Lock Access To Mailbox 15 */ 2986 2987 /* CAN_TRR2 Masks */ 2988 #define TRR16 0x0001 /* Deny But Don't Lock Access To Mailbox 16 */ 2989 #define TRR17 0x0002 /* Deny But Don't Lock Access To Mailbox 17 */ 2990 #define TRR18 0x0004 /* Deny But Don't Lock Access To Mailbox 18 */ 2991 #define TRR19 0x0008 /* Deny But Don't Lock Access To Mailbox 19 */ 2992 #define TRR20 0x0010 /* Deny But Don't Lock Access To Mailbox 20 */ 2993 #define TRR21 0x0020 /* Deny But Don't Lock Access To Mailbox 21 */ 2994 #define TRR22 0x0040 /* Deny But Don't Lock Access To Mailbox 22 */ 2995 #define TRR23 0x0080 /* Deny But Don't Lock Access To Mailbox 23 */ 2996 #define TRR24 0x0100 /* Deny But Don't Lock Access To Mailbox 24 */ 2997 #define TRR25 0x0200 /* Deny But Don't Lock Access To Mailbox 25 */ 2998 #define TRR26 0x0400 /* Deny But Don't Lock Access To Mailbox 26 */ 2999 #define TRR27 0x0800 /* Deny But Don't Lock Access To Mailbox 27 */ 3000 #define TRR28 0x1000 /* Deny But Don't Lock Access To Mailbox 28 */ 3001 #define TRR29 0x2000 /* Deny But Don't Lock Access To Mailbox 29 */ 3002 #define TRR30 0x4000 /* Deny But Don't Lock Access To Mailbox 30 */ 3003 #define TRR31 0x8000 /* Deny But Don't Lock Access To Mailbox 31 */ 3004 3005 /* CAN_TRS1 Masks */ 3006 #define TRS0 0x0001 /* Remote Frame Request For Mailbox 0 */ 3007 #define TRS1 0x0002 /* Remote Frame Request For Mailbox 1 */ 3008 #define TRS2 0x0004 /* Remote Frame Request For Mailbox 2 */ 3009 #define TRS3 0x0008 /* Remote Frame Request For Mailbox 3 */ 3010 #define TRS4 0x0010 /* Remote Frame Request For Mailbox 4 */ 3011 #define TRS5 0x0020 /* Remote Frame Request For Mailbox 5 */ 3012 #define TRS6 0x0040 /* Remote Frame Request For Mailbox 6 */ 3013 #define TRS7 0x0080 /* Remote Frame Request For Mailbox 7 */ 3014 #define TRS8 0x0100 /* Remote Frame Request For Mailbox 8 */ 3015 #define TRS9 0x0200 /* Remote Frame Request For Mailbox 9 */ 3016 #define TRS10 0x0400 /* Remote Frame Request For Mailbox 10 */ 3017 #define TRS11 0x0800 /* Remote Frame Request For Mailbox 11 */ 3018 #define TRS12 0x1000 /* Remote Frame Request For Mailbox 12 */ 3019 #define TRS13 0x2000 /* Remote Frame Request For Mailbox 13 */ 3020 #define TRS14 0x4000 /* Remote Frame Request For Mailbox 14 */ 3021 #define TRS15 0x8000 /* Remote Frame Request For Mailbox 15 */ 3022 3023 /* CAN_TRS2 Masks */ 3024 #define TRS16 0x0001 /* Remote Frame Request For Mailbox 16 */ 3025 #define TRS17 0x0002 /* Remote Frame Request For Mailbox 17 */ 3026 #define TRS18 0x0004 /* Remote Frame Request For Mailbox 18 */ 3027 #define TRS19 0x0008 /* Remote Frame Request For Mailbox 19 */ 3028 #define TRS20 0x0010 /* Remote Frame Request For Mailbox 20 */ 3029 #define TRS21 0x0020 /* Remote Frame Request For Mailbox 21 */ 3030 #define TRS22 0x0040 /* Remote Frame Request For Mailbox 22 */ 3031 #define TRS23 0x0080 /* Remote Frame Request For Mailbox 23 */ 3032 #define TRS24 0x0100 /* Remote Frame Request For Mailbox 24 */ 3033 #define TRS25 0x0200 /* Remote Frame Request For Mailbox 25 */ 3034 #define TRS26 0x0400 /* Remote Frame Request For Mailbox 26 */ 3035 #define TRS27 0x0800 /* Remote Frame Request For Mailbox 27 */ 3036 #define TRS28 0x1000 /* Remote Frame Request For Mailbox 28 */ 3037 #define TRS29 0x2000 /* Remote Frame Request For Mailbox 29 */ 3038 #define TRS30 0x4000 /* Remote Frame Request For Mailbox 30 */ 3039 #define TRS31 0x8000 /* Remote Frame Request For Mailbox 31 */ 3040 3041 /* CAN_AA1 Masks */ 3042 #define AA0 0x0001 /* Aborted Message In Mailbox 0 */ 3043 #define AA1 0x0002 /* Aborted Message In Mailbox 1 */ 3044 #define AA2 0x0004 /* Aborted Message In Mailbox 2 */ 3045 #define AA3 0x0008 /* Aborted Message In Mailbox 3 */ 3046 #define AA4 0x0010 /* Aborted Message In Mailbox 4 */ 3047 #define AA5 0x0020 /* Aborted Message In Mailbox 5 */ 3048 #define AA6 0x0040 /* Aborted Message In Mailbox 6 */ 3049 #define AA7 0x0080 /* Aborted Message In Mailbox 7 */ 3050 #define AA8 0x0100 /* Aborted Message In Mailbox 8 */ 3051 #define AA9 0x0200 /* Aborted Message In Mailbox 9 */ 3052 #define AA10 0x0400 /* Aborted Message In Mailbox 10 */ 3053 #define AA11 0x0800 /* Aborted Message In Mailbox 11 */ 3054 #define AA12 0x1000 /* Aborted Message In Mailbox 12 */ 3055 #define AA13 0x2000 /* Aborted Message In Mailbox 13 */ 3056 #define AA14 0x4000 /* Aborted Message In Mailbox 14 */ 3057 #define AA15 0x8000 /* Aborted Message In Mailbox 15 */ 3058 3059 /* CAN_AA2 Masks */ 3060 #define AA16 0x0001 /* Aborted Message In Mailbox 16 */ 3061 #define AA17 0x0002 /* Aborted Message In Mailbox 17 */ 3062 #define AA18 0x0004 /* Aborted Message In Mailbox 18 */ 3063 #define AA19 0x0008 /* Aborted Message In Mailbox 19 */ 3064 #define AA20 0x0010 /* Aborted Message In Mailbox 20 */ 3065 #define AA21 0x0020 /* Aborted Message In Mailbox 21 */ 3066 #define AA22 0x0040 /* Aborted Message In Mailbox 22 */ 3067 #define AA23 0x0080 /* Aborted Message In Mailbox 23 */ 3068 #define AA24 0x0100 /* Aborted Message In Mailbox 24 */ 3069 #define AA25 0x0200 /* Aborted Message In Mailbox 25 */ 3070 #define AA26 0x0400 /* Aborted Message In Mailbox 26 */ 3071 #define AA27 0x0800 /* Aborted Message In Mailbox 27 */ 3072 #define AA28 0x1000 /* Aborted Message In Mailbox 28 */ 3073 #define AA29 0x2000 /* Aborted Message In Mailbox 29 */ 3074 #define AA30 0x4000 /* Aborted Message In Mailbox 30 */ 3075 #define AA31 0x8000 /* Aborted Message In Mailbox 31 */ 3076 3077 /* CAN_TA1 Masks */ 3078 #define TA0 0x0001 /* Transmit Successful From Mailbox 0 */ 3079 #define TA1 0x0002 /* Transmit Successful From Mailbox 1 */ 3080 #define TA2 0x0004 /* Transmit Successful From Mailbox 2 */ 3081 #define TA3 0x0008 /* Transmit Successful From Mailbox 3 */ 3082 #define TA4 0x0010 /* Transmit Successful From Mailbox 4 */ 3083 #define TA5 0x0020 /* Transmit Successful From Mailbox 5 */ 3084 #define TA6 0x0040 /* Transmit Successful From Mailbox 6 */ 3085 #define TA7 0x0080 /* Transmit Successful From Mailbox 7 */ 3086 #define TA8 0x0100 /* Transmit Successful From Mailbox 8 */ 3087 #define TA9 0x0200 /* Transmit Successful From Mailbox 9 */ 3088 #define TA10 0x0400 /* Transmit Successful From Mailbox 10 */ 3089 #define TA11 0x0800 /* Transmit Successful From Mailbox 11 */ 3090 #define TA12 0x1000 /* Transmit Successful From Mailbox 12 */ 3091 #define TA13 0x2000 /* Transmit Successful From Mailbox 13 */ 3092 #define TA14 0x4000 /* Transmit Successful From Mailbox 14 */ 3093 #define TA15 0x8000 /* Transmit Successful From Mailbox 15 */ 3094 3095 /* CAN_TA2 Masks */ 3096 #define TA16 0x0001 /* Transmit Successful From Mailbox 16 */ 3097 #define TA17 0x0002 /* Transmit Successful From Mailbox 17 */ 3098 #define TA18 0x0004 /* Transmit Successful From Mailbox 18 */ 3099 #define TA19 0x0008 /* Transmit Successful From Mailbox 19 */ 3100 #define TA20 0x0010 /* Transmit Successful From Mailbox 20 */ 3101 #define TA21 0x0020 /* Transmit Successful From Mailbox 21 */ 3102 #define TA22 0x0040 /* Transmit Successful From Mailbox 22 */ 3103 #define TA23 0x0080 /* Transmit Successful From Mailbox 23 */ 3104 #define TA24 0x0100 /* Transmit Successful From Mailbox 24 */ 3105 #define TA25 0x0200 /* Transmit Successful From Mailbox 25 */ 3106 #define TA26 0x0400 /* Transmit Successful From Mailbox 26 */ 3107 #define TA27 0x0800 /* Transmit Successful From Mailbox 27 */ 3108 #define TA28 0x1000 /* Transmit Successful From Mailbox 28 */ 3109 #define TA29 0x2000 /* Transmit Successful From Mailbox 29 */ 3110 #define TA30 0x4000 /* Transmit Successful From Mailbox 30 */ 3111 #define TA31 0x8000 /* Transmit Successful From Mailbox 31 */ 3112 3113 /* CAN_MBTD Masks */ 3114 #define TDPTR 0x001F /* Mailbox To Temporarily Disable */ 3115 #define TDA 0x0040 /* Temporary Disable Acknowledge */ 3116 #define TDR 0x0080 /* Temporary Disable Request */ 3117 3118 /* CAN_RFH1 Masks */ 3119 #define RFH0 0x0001 /* Enable Automatic Remote Frame Handling For Mailbox 0 */ 3120 #define RFH1 0x0002 /* Enable Automatic Remote Frame Handling For Mailbox 1 */ 3121 #define RFH2 0x0004 /* Enable Automatic Remote Frame Handling For Mailbox 2 */ 3122 #define RFH3 0x0008 /* Enable Automatic Remote Frame Handling For Mailbox 3 */ 3123 #define RFH4 0x0010 /* Enable Automatic Remote Frame Handling For Mailbox 4 */ 3124 #define RFH5 0x0020 /* Enable Automatic Remote Frame Handling For Mailbox 5 */ 3125 #define RFH6 0x0040 /* Enable Automatic Remote Frame Handling For Mailbox 6 */ 3126 #define RFH7 0x0080 /* Enable Automatic Remote Frame Handling For Mailbox 7 */ 3127 #define RFH8 0x0100 /* Enable Automatic Remote Frame Handling For Mailbox 8 */ 3128 #define RFH9 0x0200 /* Enable Automatic Remote Frame Handling For Mailbox 9 */ 3129 #define RFH10 0x0400 /* Enable Automatic Remote Frame Handling For Mailbox 10 */ 3130 #define RFH11 0x0800 /* Enable Automatic Remote Frame Handling For Mailbox 11 */ 3131 #define RFH12 0x1000 /* Enable Automatic Remote Frame Handling For Mailbox 12 */ 3132 #define RFH13 0x2000 /* Enable Automatic Remote Frame Handling For Mailbox 13 */ 3133 #define RFH14 0x4000 /* Enable Automatic Remote Frame Handling For Mailbox 14 */ 3134 #define RFH15 0x8000 /* Enable Automatic Remote Frame Handling For Mailbox 15 */ 3135 3136 /* CAN_RFH2 Masks */ 3137 #define RFH16 0x0001 /* Enable Automatic Remote Frame Handling For Mailbox 16 */ 3138 #define RFH17 0x0002 /* Enable Automatic Remote Frame Handling For Mailbox 17 */ 3139 #define RFH18 0x0004 /* Enable Automatic Remote Frame Handling For Mailbox 18 */ 3140 #define RFH19 0x0008 /* Enable Automatic Remote Frame Handling For Mailbox 19 */ 3141 #define RFH20 0x0010 /* Enable Automatic Remote Frame Handling For Mailbox 20 */ 3142 #define RFH21 0x0020 /* Enable Automatic Remote Frame Handling For Mailbox 21 */ 3143 #define RFH22 0x0040 /* Enable Automatic Remote Frame Handling For Mailbox 22 */ 3144 #define RFH23 0x0080 /* Enable Automatic Remote Frame Handling For Mailbox 23 */ 3145 #define RFH24 0x0100 /* Enable Automatic Remote Frame Handling For Mailbox 24 */ 3146 #define RFH25 0x0200 /* Enable Automatic Remote Frame Handling For Mailbox 25 */ 3147 #define RFH26 0x0400 /* Enable Automatic Remote Frame Handling For Mailbox 26 */ 3148 #define RFH27 0x0800 /* Enable Automatic Remote Frame Handling For Mailbox 27 */ 3149 #define RFH28 0x1000 /* Enable Automatic Remote Frame Handling For Mailbox 28 */ 3150 #define RFH29 0x2000 /* Enable Automatic Remote Frame Handling For Mailbox 29 */ 3151 #define RFH30 0x4000 /* Enable Automatic Remote Frame Handling For Mailbox 30 */ 3152 #define RFH31 0x8000 /* Enable Automatic Remote Frame Handling For Mailbox 31 */ 3153 3154 /* CAN_MBTIF1 Masks */ 3155 #define MBTIF0 0x0001 /* TX Interrupt Active In Mailbox 0 */ 3156 #define MBTIF1 0x0002 /* TX Interrupt Active In Mailbox 1 */ 3157 #define MBTIF2 0x0004 /* TX Interrupt Active In Mailbox 2 */ 3158 #define MBTIF3 0x0008 /* TX Interrupt Active In Mailbox 3 */ 3159 #define MBTIF4 0x0010 /* TX Interrupt Active In Mailbox 4 */ 3160 #define MBTIF5 0x0020 /* TX Interrupt Active In Mailbox 5 */ 3161 #define MBTIF6 0x0040 /* TX Interrupt Active In Mailbox 6 */ 3162 #define MBTIF7 0x0080 /* TX Interrupt Active In Mailbox 7 */ 3163 #define MBTIF8 0x0100 /* TX Interrupt Active In Mailbox 8 */ 3164 #define MBTIF9 0x0200 /* TX Interrupt Active In Mailbox 9 */ 3165 #define MBTIF10 0x0400 /* TX Interrupt Active In Mailbox 10 */ 3166 #define MBTIF11 0x0800 /* TX Interrupt Active In Mailbox 11 */ 3167 #define MBTIF12 0x1000 /* TX Interrupt Active In Mailbox 12 */ 3168 #define MBTIF13 0x2000 /* TX Interrupt Active In Mailbox 13 */ 3169 #define MBTIF14 0x4000 /* TX Interrupt Active In Mailbox 14 */ 3170 #define MBTIF15 0x8000 /* TX Interrupt Active In Mailbox 15 */ 3171 3172 /* CAN_MBTIF2 Masks */ 3173 #define MBTIF16 0x0001 /* TX Interrupt Active In Mailbox 16 */ 3174 #define MBTIF17 0x0002 /* TX Interrupt Active In Mailbox 17 */ 3175 #define MBTIF18 0x0004 /* TX Interrupt Active In Mailbox 18 */ 3176 #define MBTIF19 0x0008 /* TX Interrupt Active In Mailbox 19 */ 3177 #define MBTIF20 0x0010 /* TX Interrupt Active In Mailbox 20 */ 3178 #define MBTIF21 0x0020 /* TX Interrupt Active In Mailbox 21 */ 3179 #define MBTIF22 0x0040 /* TX Interrupt Active In Mailbox 22 */ 3180 #define MBTIF23 0x0080 /* TX Interrupt Active In Mailbox 23 */ 3181 #define MBTIF24 0x0100 /* TX Interrupt Active In Mailbox 24 */ 3182 #define MBTIF25 0x0200 /* TX Interrupt Active In Mailbox 25 */ 3183 #define MBTIF26 0x0400 /* TX Interrupt Active In Mailbox 26 */ 3184 #define MBTIF27 0x0800 /* TX Interrupt Active In Mailbox 27 */ 3185 #define MBTIF28 0x1000 /* TX Interrupt Active In Mailbox 28 */ 3186 #define MBTIF29 0x2000 /* TX Interrupt Active In Mailbox 29 */ 3187 #define MBTIF30 0x4000 /* TX Interrupt Active In Mailbox 30 */ 3188 #define MBTIF31 0x8000 /* TX Interrupt Active In Mailbox 31 */ 3189 3190 /* CAN_MBRIF1 Masks */ 3191 #define MBRIF0 0x0001 /* RX Interrupt Active In Mailbox 0 */ 3192 #define MBRIF1 0x0002 /* RX Interrupt Active In Mailbox 1 */ 3193 #define MBRIF2 0x0004 /* RX Interrupt Active In Mailbox 2 */ 3194 #define MBRIF3 0x0008 /* RX Interrupt Active In Mailbox 3 */ 3195 #define MBRIF4 0x0010 /* RX Interrupt Active In Mailbox 4 */ 3196 #define MBRIF5 0x0020 /* RX Interrupt Active In Mailbox 5 */ 3197 #define MBRIF6 0x0040 /* RX Interrupt Active In Mailbox 6 */ 3198 #define MBRIF7 0x0080 /* RX Interrupt Active In Mailbox 7 */ 3199 #define MBRIF8 0x0100 /* RX Interrupt Active In Mailbox 8 */ 3200 #define MBRIF9 0x0200 /* RX Interrupt Active In Mailbox 9 */ 3201 #define MBRIF10 0x0400 /* RX Interrupt Active In Mailbox 10 */ 3202 #define MBRIF11 0x0800 /* RX Interrupt Active In Mailbox 11 */ 3203 #define MBRIF12 0x1000 /* RX Interrupt Active In Mailbox 12 */ 3204 #define MBRIF13 0x2000 /* RX Interrupt Active In Mailbox 13 */ 3205 #define MBRIF14 0x4000 /* RX Interrupt Active In Mailbox 14 */ 3206 #define MBRIF15 0x8000 /* RX Interrupt Active In Mailbox 15 */ 3207 3208 /* CAN_MBRIF2 Masks */ 3209 #define MBRIF16 0x0001 /* RX Interrupt Active In Mailbox 16 */ 3210 #define MBRIF17 0x0002 /* RX Interrupt Active In Mailbox 17 */ 3211 #define MBRIF18 0x0004 /* RX Interrupt Active In Mailbox 18 */ 3212 #define MBRIF19 0x0008 /* RX Interrupt Active In Mailbox 19 */ 3213 #define MBRIF20 0x0010 /* RX Interrupt Active In Mailbox 20 */ 3214 #define MBRIF21 0x0020 /* RX Interrupt Active In Mailbox 21 */ 3215 #define MBRIF22 0x0040 /* RX Interrupt Active In Mailbox 22 */ 3216 #define MBRIF23 0x0080 /* RX Interrupt Active In Mailbox 23 */ 3217 #define MBRIF24 0x0100 /* RX Interrupt Active In Mailbox 24 */ 3218 #define MBRIF25 0x0200 /* RX Interrupt Active In Mailbox 25 */ 3219 #define MBRIF26 0x0400 /* RX Interrupt Active In Mailbox 26 */ 3220 #define MBRIF27 0x0800 /* RX Interrupt Active In Mailbox 27 */ 3221 #define MBRIF28 0x1000 /* RX Interrupt Active In Mailbox 28 */ 3222 #define MBRIF29 0x2000 /* RX Interrupt Active In Mailbox 29 */ 3223 #define MBRIF30 0x4000 /* RX Interrupt Active In Mailbox 30 */ 3224 #define MBRIF31 0x8000 /* RX Interrupt Active In Mailbox 31 */ 3225 3226 /* CAN_MBIM1 Masks */ 3227 #define MBIM0 0x0001 /* Enable Interrupt For Mailbox 0 */ 3228 #define MBIM1 0x0002 /* Enable Interrupt For Mailbox 1 */ 3229 #define MBIM2 0x0004 /* Enable Interrupt For Mailbox 2 */ 3230 #define MBIM3 0x0008 /* Enable Interrupt For Mailbox 3 */ 3231 #define MBIM4 0x0010 /* Enable Interrupt For Mailbox 4 */ 3232 #define MBIM5 0x0020 /* Enable Interrupt For Mailbox 5 */ 3233 #define MBIM6 0x0040 /* Enable Interrupt For Mailbox 6 */ 3234 #define MBIM7 0x0080 /* Enable Interrupt For Mailbox 7 */ 3235 #define MBIM8 0x0100 /* Enable Interrupt For Mailbox 8 */ 3236 #define MBIM9 0x0200 /* Enable Interrupt For Mailbox 9 */ 3237 #define MBIM10 0x0400 /* Enable Interrupt For Mailbox 10 */ 3238 #define MBIM11 0x0800 /* Enable Interrupt For Mailbox 11 */ 3239 #define MBIM12 0x1000 /* Enable Interrupt For Mailbox 12 */ 3240 #define MBIM13 0x2000 /* Enable Interrupt For Mailbox 13 */ 3241 #define MBIM14 0x4000 /* Enable Interrupt For Mailbox 14 */ 3242 #define MBIM15 0x8000 /* Enable Interrupt For Mailbox 15 */ 3243 3244 /* CAN_MBIM2 Masks */ 3245 #define MBIM16 0x0001 /* Enable Interrupt For Mailbox 16 */ 3246 #define MBIM17 0x0002 /* Enable Interrupt For Mailbox 17 */ 3247 #define MBIM18 0x0004 /* Enable Interrupt For Mailbox 18 */ 3248 #define MBIM19 0x0008 /* Enable Interrupt For Mailbox 19 */ 3249 #define MBIM20 0x0010 /* Enable Interrupt For Mailbox 20 */ 3250 #define MBIM21 0x0020 /* Enable Interrupt For Mailbox 21 */ 3251 #define MBIM22 0x0040 /* Enable Interrupt For Mailbox 22 */ 3252 #define MBIM23 0x0080 /* Enable Interrupt For Mailbox 23 */ 3253 #define MBIM24 0x0100 /* Enable Interrupt For Mailbox 24 */ 3254 #define MBIM25 0x0200 /* Enable Interrupt For Mailbox 25 */ 3255 #define MBIM26 0x0400 /* Enable Interrupt For Mailbox 26 */ 3256 #define MBIM27 0x0800 /* Enable Interrupt For Mailbox 27 */ 3257 #define MBIM28 0x1000 /* Enable Interrupt For Mailbox 28 */ 3258 #define MBIM29 0x2000 /* Enable Interrupt For Mailbox 29 */ 3259 #define MBIM30 0x4000 /* Enable Interrupt For Mailbox 30 */ 3260 #define MBIM31 0x8000 /* Enable Interrupt For Mailbox 31 */ 3261 3262 /* CAN_GIM Masks */ 3263 #define EWTIM 0x0001 /* Enable TX Error Count Interrupt */ 3264 #define EWRIM 0x0002 /* Enable RX Error Count Interrupt */ 3265 #define EPIM 0x0004 /* Enable Error-Passive Mode Interrupt */ 3266 #define BOIM 0x0008 /* Enable Bus Off Interrupt */ 3267 #define WUIM 0x0010 /* Enable Wake-Up Interrupt */ 3268 #define UIAIM 0x0020 /* Enable Access To Unimplemented Address Interrupt */ 3269 #define AAIM 0x0040 /* Enable Abort Acknowledge Interrupt */ 3270 #define RMLIM 0x0080 /* Enable RX Message Lost Interrupt */ 3271 #define UCEIM 0x0100 /* Enable Universal Counter Overflow Interrupt */ 3272 #define EXTIM 0x0200 /* Enable External Trigger Output Interrupt */ 3273 #define ADIM 0x0400 /* Enable Access Denied Interrupt */ 3274 3275 /* CAN_GIS Masks */ 3276 #define EWTIS 0x0001 /* TX Error Count IRQ Status */ 3277 #define EWRIS 0x0002 /* RX Error Count IRQ Status */ 3278 #define EPIS 0x0004 /* Error-Passive Mode IRQ Status */ 3279 #define BOIS 0x0008 /* Bus Off IRQ Status */ 3280 #define WUIS 0x0010 /* Wake-Up IRQ Status */ 3281 #define UIAIS 0x0020 /* Access To Unimplemented Address IRQ Status */ 3282 #define AAIS 0x0040 /* Abort Acknowledge IRQ Status */ 3283 #define RMLIS 0x0080 /* RX Message Lost IRQ Status */ 3284 #define UCEIS 0x0100 /* Universal Counter Overflow IRQ Status */ 3285 #define EXTIS 0x0200 /* External Trigger Output IRQ Status */ 3286 #define ADIS 0x0400 /* Access Denied IRQ Status */ 3287 3288 /* CAN_GIF Masks */ 3289 #define EWTIF 0x0001 /* TX Error Count IRQ Flag */ 3290 #define EWRIF 0x0002 /* RX Error Count IRQ Flag */ 3291 #define EPIF 0x0004 /* Error-Passive Mode IRQ Flag */ 3292 #define BOIF 0x0008 /* Bus Off IRQ Flag */ 3293 #define WUIF 0x0010 /* Wake-Up IRQ Flag */ 3294 #define UIAIF 0x0020 /* Access To Unimplemented Address IRQ Flag */ 3295 #define AAIF 0x0040 /* Abort Acknowledge IRQ Flag */ 3296 #define RMLIF 0x0080 /* RX Message Lost IRQ Flag */ 3297 #define UCEIF 0x0100 /* Universal Counter Overflow IRQ Flag */ 3298 #define EXTIF 0x0200 /* External Trigger Output IRQ Flag */ 3299 #define ADIF 0x0400 /* Access Denied IRQ Flag */ 3300 3301 /* CAN_UCCNF Masks */ 3302 #define UCCNF 0x000F /* Universal Counter Mode */ 3303 #define UC_STAMP 0x0001 /* Timestamp Mode */ 3304 #define UC_WDOG 0x0002 /* Watchdog Mode */ 3305 #define UC_AUTOTX 0x0003 /* Auto-Transmit Mode */ 3306 #define UC_ERROR 0x0006 /* CAN Error Frame Count */ 3307 #define UC_OVER 0x0007 /* CAN Overload Frame Count */ 3308 #define UC_LOST 0x0008 /* Arbitration Lost During TX Count */ 3309 #define UC_AA 0x0009 /* TX Abort Count */ 3310 #define UC_TA 0x000A /* TX Successful Count */ 3311 #define UC_REJECT 0x000B /* RX Message Rejected Count */ 3312 #define UC_RML 0x000C /* RX Message Lost Count */ 3313 #define UC_RX 0x000D /* Total Successful RX Messages Count */ 3314 #define UC_RMP 0x000E /* Successful RX W/Matching ID Count */ 3315 #define UC_ALL 0x000F /* Correct Message On CAN Bus Line Count */ 3316 #define UCRC 0x0020 /* Universal Counter Reload/Clear */ 3317 #define UCCT 0x0040 /* Universal Counter CAN Trigger */ 3318 #define UCE 0x0080 /* Universal Counter Enable */ 3319 3320 /* CAN_ESR Masks */ 3321 #define ACKE 0x0004 /* Acknowledge Error */ 3322 #define SER 0x0008 /* Stuff Error */ 3323 #define CRCE 0x0010 /* CRC Error */ 3324 #define SA0 0x0020 /* Stuck At Dominant Error */ 3325 #define BEF 0x0040 /* Bit Error Flag */ 3326 #define FER 0x0080 /* Form Error Flag */ 3327 3328 /* CAN_EWR Masks */ 3329 #define EWLREC 0x00FF /* RX Error Count Limit (For EWRIS) */ 3330 #define EWLTEC 0xFF00 /* TX Error Count Limit (For EWTIS) */ 3331 3332 3333 /* ************ ADC Controller Module (ACM) MASKS ***************/ 3334 3335 /* Bit masks for ACM_CTL */ 3336 #define ACM_EN 0x0001 3337 #define ACM_TMR0_EN 0x0002 3338 #define ACM_TMR1_EN 0x0004 3339 #define ACM_TRG_SEL0 0x0018 3340 #define ACM_TRG_SEL1 0x0060 3341 #define ACM_TRG_POL0 0x0080 3342 #define ACM_TRG_POL1 0x0100 3343 #define ACM_CS_POL 0x0200 3344 #define ACM_CLK_POL 0x0400 3345 #define ACM_EPS 0xC000 3346 3347 /* Bit masks for ACM_STAT */ 3348 #define ACM_BSY 0x0001 3349 #define ACM_EMISS 0x0002 3350 #define ACM_ECOM 0x0004 3351 #define ACM_CEVNT 0x0078 3352 3353 /* Bit masks for ACM_ES */ 3354 #define ACM_ES0 0x0001 3355 #define ACM_ES1 0x0002 3356 #define ACM_ES2 0x0004 3357 #define ACM_ES3 0x0008 3358 #define ACM_ES4 0x0010 3359 #define ACM_ES5 0x0020 3360 #define ACM_ES6 0x0040 3361 #define ACM_ES7 0x0080 3362 #define ACM_ES8 0x0100 3363 #define ACM_ES9 0x0200 3364 #define ACM_ES10 0x0400 3365 #define ACM_ES11 0x0800 3366 #define ACM_ES12 0x1000 3367 #define ACM_ES13 0x2000 3368 #define ACM_ES14 0x4000 3369 #define ACM_ES15 0x8000 3370 3371 /* Bit masks for ACM_IMSK */ 3372 #define ACM_IE0 0x0001 3373 #define ACM_IE1 0x0002 3374 #define ACM_IE2 0x0004 3375 #define ACM_IE3 0x0008 3376 #define ACM_IE4 0x0010 3377 #define ACM_IE5 0x0020 3378 #define ACM_IE6 0x0040 3379 #define ACM_IE7 0x0080 3380 #define ACM_IE8 0x0100 3381 #define ACM_IE9 0x0200 3382 #define ACM_IE10 0x0400 3383 #define ACM_IE11 0x0800 3384 #define ACM_IE12 0x1000 3385 #define ACM_IE13 0x2000 3386 #define ACM_IE14 0x4000 3387 #define ACM_IE15 0x8000 3388 3389 /* Bit masks for ACM_MS */ 3390 #define ACM_EM0 0x0001 3391 #define ACM_EM1 0x0002 3392 #define ACM_EM2 0x0004 3393 #define ACM_EM3 0x0008 3394 #define ACM_EM4 0x0010 3395 #define ACM_EM5 0x0020 3396 #define ACM_EM6 0x0040 3397 #define ACM_EM7 0x0080 3398 #define ACM_EM8 0x0100 3399 #define ACM_EM9 0x0200 3400 #define ACM_EM10 0x0400 3401 #define ACM_EM11 0x0800 3402 #define ACM_EM12 0x1000 3403 #define ACM_EM13 0x2000 3404 #define ACM_EM14 0x4000 3405 #define ACM_EM15 0x8000 3406 3407 /* Bit masks for ACM_EMSK */ 3408 #define ACM_MIE0 0x0001 3409 #define ACM_MIE1 0x0002 3410 #define ACM_MIE2 0x0004 3411 #define ACM_MIE3 0x0008 3412 #define ACM_MIE4 0x0010 3413 #define ACM_MIE5 0x0020 3414 #define ACM_MIE6 0x0040 3415 #define ACM_MIE7 0x0080 3416 #define ACM_MIE8 0x0100 3417 #define ACM_MIE9 0x0200 3418 #define ACM_MIE10 0x0400 3419 #define ACM_MIE11 0x0800 3420 #define ACM_MIE12 0x1000 3421 #define ACM_MIE13 0x2000 3422 #define ACM_MIE14 0x4000 3423 #define ACM_MIE15 0x8000 3424 3425 /* Bit masks for ACM_ER0 & ACM_ER1 */ 3426 #define ACM_EVNT_EN 0x0001 3427 #define ACM_EVNT_PF 0x003E 3428 3429 /* Bit masks for ACM_ET0 & ACM_ET1 */ 3430 #define ACM_EVNT_TIME 0xFFFFFFFF 3431 3432 /* Bit masks for ACM_TC0 */ 3433 #define ACM_CLK_DIV 0x00FF 3434 #define ACM_SC 0xFF00 3435 3436 /* Bit masks for ACM_TC1 */ 3437 #define ACM_CSW 0x00FF 3438 #define ACM_HC 0x0F00 3439 #define ACM_ZC 0xF000 3440 3441 #ifdef _MISRA_RULES 3442 #pragma diag(pop) 3443 #endif /* _MISRA_RULES */ 3444 3445 #endif /* _DEF_BF50x_H */ 3446