1 /* GXemul: $Id: alpha_cpu.h,v 1.2 2006-09-01 16:40:57 debug Exp $ */
2 /* $NetBSD: alpha_cpu.h,v 1.48 2006/02/16 20:17:13 perry Exp $ */
3
4 #ifndef __ALPHA_ALPHA_CPU_H__
5 #define __ALPHA_ALPHA_CPU_H__
6
7 /*
8 * Copyright (c) 1996 Carnegie-Mellon University.
9 * All rights reserved.
10 *
11 * Author: Chris G. Demetriou
12 *
13 * Permission to use, copy, modify and distribute this software and
14 * its documentation is hereby granted, provided that both the copyright
15 * notice and this permission notice appear in all copies of the
16 * software, derivative works or modified versions, and any portions
17 * thereof, and that both notices appear in supporting documentation.
18 *
19 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
20 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
21 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
22 *
23 * Carnegie Mellon requests users of this software to return to
24 *
25 * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
26 * School of Computer Science
27 * Carnegie Mellon University
28 * Pittsburgh PA 15213-3890
29 *
30 * any improvements or extensions that they make and grant Carnegie the
31 * rights to redistribute these changes.
32 */
33
34 /*
35 * Alpha CPU + OSF/1 PALcode definitions for use by the kernel.
36 *
37 * Definitions for:
38 *
39 * Process Control Block
40 * Interrupt/Exception/Syscall Stack Frame
41 * Processor Status Register
42 * Machine Check Error Summary Register
43 * Machine Check Logout Area
44 * Per CPU state Management of Machine Check Handling
45 * Virtual Memory Management
46 * Kernel Entry Vectors
47 * MMCSR Fault Type Codes
48 * Translation Buffer Invalidation
49 *
50 * and miscellaneous PALcode operations.
51 */
52
53
54 /*
55 * Process Control Block definitions [OSF/1 PALcode Specific]
56 *
57 * GXemul note: all of these uint64_t were 'unsigned long' in the original
58 * NetBSD header file, and the uint32_t were 'unsigned int'.
59 */
60
61 struct alpha_pcb {
62 uint64_t apcb_ksp; /* kernel stack ptr */
63 uint64_t apcb_usp; /* user stack ptr */
64 uint64_t apcb_ptbr; /* page table base reg */
65 uint32_t apcb_cpc; /* charged process cycles */
66 uint32_t apcb_asn; /* address space number */
67 uint64_t apcb_unique; /* process unique value */
68 #define apcb_backup_ksp apcb_unique /* backup kernel stack ptr */
69 uint64_t apcb_flags; /* flags; see below */
70 uint64_t apcb_decrsv0; /* DEC reserved */
71 uint64_t apcb_decrsv1; /* DEC reserved */
72 };
73
74 #define ALPHA_PCB_FLAGS_FEN 0x0000000000000001
75 #define ALPHA_PCB_FLAGS_PME 0x4000000000000000
76
77 /*
78 * Interrupt/Exception/Syscall "Hardware" (really PALcode)
79 * Stack Frame definitions
80 *
81 * These are quadword offsets from the sp on kernel entry, i.e.
82 * to get to the value in question you access (sp + (offset * 8)).
83 *
84 * On syscall entry, A0-A2 aren't written to memory but space
85 * _is_ reserved for them.
86 */
87
88 #define ALPHA_HWFRAME_PS 0 /* processor status register */
89 #define ALPHA_HWFRAME_PC 1 /* program counter */
90 #define ALPHA_HWFRAME_GP 2 /* global pointer */
91 #define ALPHA_HWFRAME_A0 3 /* a0 */
92 #define ALPHA_HWFRAME_A1 4 /* a1 */
93 #define ALPHA_HWFRAME_A2 5 /* a2 */
94
95 #define ALPHA_HWFRAME_SIZE 6 /* 6 8-byte words */
96
97 /*
98 * Processor Status Register [OSF/1 PALcode Specific]
99 *
100 * Includes user/kernel mode bit, interrupt priority levels, etc.
101 */
102
103 #define ALPHA_PSL_USERMODE 0x0008 /* set -> user mode */
104 #define ALPHA_PSL_IPL_MASK 0x0007 /* interrupt level mask */
105
106 #define ALPHA_PSL_IPL_0 0x0000 /* all interrupts enabled */
107 #define ALPHA_PSL_IPL_SOFT 0x0001 /* software ints disabled */
108 #define ALPHA_PSL_IPL_IO 0x0004 /* I/O dev ints disabled */
109 #define ALPHA_PSL_IPL_CLOCK 0x0005 /* clock ints disabled */
110 #define ALPHA_PSL_IPL_HIGH 0x0006 /* all but mchecks disabled */
111
112 #define ALPHA_PSL_MUST_BE_ZERO 0xfffffffffffffff0
113
114 /* Convenience constants: what must be set/clear in user mode */
115 #define ALPHA_PSL_USERSET ALPHA_PSL_USERMODE
116 #define ALPHA_PSL_USERCLR (ALPHA_PSL_MUST_BE_ZERO | ALPHA_PSL_IPL_MASK)
117
118 /*
119 * Interrupt Type Code Definitions [OSF/1 PALcode Specific]
120 */
121
122 #define ALPHA_INTR_XPROC 0 /* interprocessor interrupt */
123 #define ALPHA_INTR_CLOCK 1 /* clock interrupt */
124 #define ALPHA_INTR_ERROR 2 /* correctable error or mcheck */
125 #define ALPHA_INTR_DEVICE 3 /* device interrupt */
126 #define ALPHA_INTR_PERF 4 /* performance counter */
127 #define ALPHA_INTR_PASSIVE 5 /* passive release */
128
129 /*
130 * Machine Check Error Summary Register definitions [OSF/1 PALcode Specific]
131 *
132 * The following bits are values as read. On write, _PCE, _SCE, and
133 * _MIP are "write 1 to clear."
134 */
135
136 #define ALPHA_MCES_IMP \
137 0xffffffff00000000 /* impl. dependent */
138 #define ALPHA_MCES_RSVD \
139 0x00000000ffffffe0 /* reserved */
140 #define ALPHA_MCES_DSC \
141 0x0000000000000010 /* disable system correctable error reporting */
142 #define ALPHA_MCES_DPC \
143 0x0000000000000008 /* disable processor correctable error reporting */
144 #define ALPHA_MCES_PCE \
145 0x0000000000000004 /* processor correctable error in progress */
146 #define ALPHA_MCES_SCE \
147 0x0000000000000002 /* system correctable error in progress */
148 #define ALPHA_MCES_MIP \
149 0x0000000000000001 /* machine check in progress */
150
151 /*
152 * Machine Check Error Summary Register definitions [OSF/1 PALcode Specific]
153 *
154 * Note that these are *generic* OSF/1 PALcode specific defines. There are
155 * platform variations to these entities.
156 *
157 * GXemul note: These uint32_t were 'unsigned int' in the original NetBSD
158 * header file.
159 */
160
161 struct alpha_logout_area {
162 uint32_t la_frame_size; /* frame size */
163 uint32_t la_flags; /* flags; see below */
164 uint32_t la_cpu_offset; /* offset to cpu area */
165 uint32_t la_system_offset; /* offset to system area */
166 };
167
168 #define ALPHA_LOGOUT_FLAGS_RETRY 0x80000000 /* OK to continue */
169 #define ALPHA_LOGOUT_FLAGS_SE 0x40000000 /* second error */
170 #define ALPHA_LOGOUT_FLAGS_SBZ 0x3fffffff /* should be zero */
171
172 #define ALPHA_LOGOUT_NOT_BUILT \
173 (struct alpha_logout_area *)0xffffffffffffffff)
174
175 #define ALPHA_LOGOUT_PAL_AREA(lap) \
176 (unsigned long *)((unsigned char *)(lap) + 16)
177 #define ALPHA_LOGOUT_PAL_SIZE(lap) \
178 ((lap)->la_cpu_offset - 16)
179 #define ALPHA_LOGOUT_CPU_AREA(lap) \
180 (unsigned long *)((unsigned char *)(lap) + (lap)->la_cpu_offset)
181 #define ALPHA_LOGOUT_CPU_SIZE(lap) \
182 ((lap)->la_system_offset - (lap)->la_cpu_offset)
183 #define ALPHA_LOGOUT_SYSTEM_AREA(lap) \
184 (unsigned long *)((unsigned char *)(lap) + (lap)->la_system_offset)
185 #define ALPHA_LOGOUT_SYSTEM_SIZE(lap) \
186 ((lap)->la_frame_size - (lap)->la_system_offset)
187
188 /* types of machine checks */
189 #define ALPHA_SYS_ERROR 0x620 /* System correctable error */
190 #define ALPHA_PROC_ERROR 0x630 /* Processor correctable error */
191 #define ALPHA_SYS_MCHECK 0x660 /* System machine check */
192 #define ALPHA_PROC_MCHECK 0x670 /* Processor machine check */
193
194 /*
195 * Virtual Memory Management definitions [OSF/1 PALcode Specific]
196 *
197 * Includes user and kernel space addresses and information,
198 * page table entry definitions, etc.
199 *
200 * NOTE THAT THESE DEFINITIONS MAY CHANGE IN FUTURE ALPHA CPUS!
201 */
202
203 #define ALPHA_PGSHIFT 13
204 #define ALPHA_PGBYTES (1 << ALPHA_PGSHIFT)
205
206 #define ALPHA_USEG_BASE 0 /* virtual */
207 #define ALPHA_USEG_END 0x000003ffffffffffULL
208
209 #define ALPHA_K0SEG_BASE 0xfffffc0000000000ULL /* direct-mapped */
210 #define ALPHA_K0SEG_END 0xfffffdffffffffffULL
211 #define ALPHA_K1SEG_BASE 0xfffffe0000000000ULL /* virtual */
212 #define ALPHA_K1SEG_END 0xffffffffffffffffULL
213
214 #define ALPHA_K0SEG_TO_PHYS(x) ((x) & ~ALPHA_K0SEG_BASE)
215 #define ALPHA_PHYS_TO_K0SEG(x) ((x) | ALPHA_K0SEG_BASE)
216
217 #define ALPHA_PTE_VALID 0x0001
218
219 #define ALPHA_PTE_FAULT_ON_READ 0x0002
220 #define ALPHA_PTE_FAULT_ON_WRITE 0x0004
221 #define ALPHA_PTE_FAULT_ON_EXECUTE 0x0008
222
223 #define ALPHA_PTE_ASM 0x0010 /* addr. space match */
224 #define ALPHA_PTE_GRANULARITY 0x0060 /* granularity hint */
225
226 #define ALPHA_PTE_PROT 0xff00
227 #define ALPHA_PTE_KR 0x0100
228 #define ALPHA_PTE_UR 0x0200
229 #define ALPHA_PTE_KW 0x1000
230 #define ALPHA_PTE_UW 0x2000
231
232 #define ALPHA_PTE_WRITE (ALPHA_PTE_KW | ALPHA_PTE_UW)
233
234 #define ALPHA_PTE_SOFTWARE 0x00000000ffff0000
235 #define ALPHA_PTE_PALCODE (~ALPHA_PTE_SOFTWARE) /* shorthand */
236
237 #define ALPHA_PTE_PFN 0xffffffff00000000
238
239 #define ALPHA_PTE_TO_PFN(pte) ((pte) >> 32)
240 #define ALPHA_PTE_FROM_PFN(pfn) ((pfn) << 32)
241
242 typedef unsigned long alpha_pt_entry_t;
243
244 /*
245 * Kernel Entry Vectors. [OSF/1 PALcode Specific]
246 */
247
248 #define ALPHA_KENTRY_INT 0
249 #define ALPHA_KENTRY_ARITH 1
250 #define ALPHA_KENTRY_MM 2
251 #define ALPHA_KENTRY_IF 3
252 #define ALPHA_KENTRY_UNA 4
253 #define ALPHA_KENTRY_SYS 5
254
255 /*
256 * MMCSR Fault Type Codes. [OSF/1 PALcode Specific]
257 */
258
259 #define ALPHA_MMCSR_INVALTRANS 0
260 #define ALPHA_MMCSR_ACCESS 1
261 #define ALPHA_MMCSR_FOR 2
262 #define ALPHA_MMCSR_FOE 3
263 #define ALPHA_MMCSR_FOW 4
264
265 /*
266 * Instruction Fault Type Codes. [OSF/1 PALcode Specific]
267 */
268
269 #define ALPHA_IF_CODE_BPT 0
270 #define ALPHA_IF_CODE_BUGCHK 1
271 #define ALPHA_IF_CODE_GENTRAP 2
272 #define ALPHA_IF_CODE_FEN 3
273 #define ALPHA_IF_CODE_OPDEC 4
274
275 #ifdef _KERNEL
276
277 /*
278 * Translation Buffer Invalidation definitions [OSF/1 PALcode Specific]
279 */
280
281 #define ALPHA_TBIA() alpha_pal_tbi(-2, 0) /* all TB entries */
282 #define ALPHA_TBIAP() alpha_pal_tbi(-1, 0) /* all per-process */
283 #define ALPHA_TBISI(va) alpha_pal_tbi(1, (va)) /* ITB entry for va */
284 #define ALPHA_TBISD(va) alpha_pal_tbi(2, (va)) /* DTB entry for va */
285 #define ALPHA_TBIS(va) alpha_pal_tbi(3, (va)) /* all for va */
286
287 #endif /* _KERNEL */
288
289 /*
290 * Bits used in the amask instruction [EV56 and later]
291 */
292
293 #define ALPHA_AMASK_BWX 0x0001 /* byte/word extension */
294 #define ALPHA_AMASK_FIX 0x0002 /* floating point conv. ext. */
295 #define ALPHA_AMASK_CIX 0x0004 /* count extension */
296 #define ALPHA_AMASK_MVI 0x0100 /* multimedia extension */
297 #define ALPHA_AMASK_PAT 0x0200 /* precise arith. traps */
298 #define ALPHA_AMASK_PMI 0x1000 /* prefetch w/ modify intent */
299
300 #define ALPHA_AMASK_ALL (ALPHA_AMASK_BWX|ALPHA_AMASK_FIX| \
301 ALPHA_AMASK_CIX|ALPHA_AMASK_MVI| \
302 ALPHA_AMASK_PAT|ALPHA_AMASK_PMI)
303
304 #define ALPHA_AMASK_BITS \
305 "\20\17PMI\12PAT\11MVI\3CIX\2FIX\1BWX"
306
307 /*
308 * Chip family IDs returned by implver instruction
309 */
310
311 #define ALPHA_IMPLVER_EV4 0 /* LCA/EV4/EV45 */
312 #define ALPHA_IMPLVER_EV5 1 /* EV5/EV56/PCA56 */
313 #define ALPHA_IMPLVER_EV6 2 /* EV6 */
314 #define ALPHA_IMPLVER_EV7 3 /* EV7/EV79 */
315
316 #ifdef _KERNEL
317
318 /*
319 * Maximum processor ID we allow from `whami', and related constants.
320 *
321 * XXX This is not really processor or PALcode specific, but this is
322 * a convenient place to put these definitions.
323 *
324 * XXX This is clipped at 63 so that we can use `long's for proc bitmasks.
325 */
326
327 #define ALPHA_WHAMI_MAXID 63
328 #define ALPHA_MAXPROCS (ALPHA_WHAMI_MAXID + 1)
329
330 /*
331 * Misc. support routines.
332 */
333 const char *alpha_dsr_sysname(void);
334
335 /*
336 * Stubs for Alpha instructions normally inaccessible from C.
337 */
338 unsigned long alpha_amask(unsigned long);
339 unsigned long alpha_implver(void);
340
341 #endif /* _KERNEL */
342
343 #if 0
344
345 /* XXX Expose the insn wrappers to userspace, for now. */
346
347 static __inline unsigned long
348 alpha_rpcc(void)
349 {
350 unsigned long v0;
351
352 __asm volatile("rpcc %0" : "=r" (v0));
353 return (v0);
354 }
355
356 #define alpha_mb() __asm volatile("mb" : : : "memory")
357 #define alpha_wmb() __asm volatile("mb" : : : "memory") /* XXX */
358
359 #endif
360
361 #if defined(_KERNEL) || defined(_STANDALONE)
362
363 /*
364 * Stubs for OSF/1 PALcode operations.
365 */
366 #include <machine/pal.h>
367
368 void alpha_pal_cflush(unsigned long);
369 void alpha_pal_halt(void) __attribute__((__noreturn__));
370 unsigned long _alpha_pal_swpipl(unsigned long); /* for profiling */
371 void alpha_pal_wrent(void *, unsigned long);
372 void alpha_pal_wrvptptr(unsigned long);
373
374 #define alpha_pal_draina() __asm volatile("call_pal %0 # PAL_draina" \
375 : : "i" (PAL_draina) : "memory")
376
377 #define alpha_pal_imb() __asm volatile("call_pal %0 # PAL_imb" \
378 : : "i" (PAL_imb) : "memory")
379
380 static __inline unsigned long
alpha_pal_rdmces(void)381 alpha_pal_rdmces(void)
382 {
383 register unsigned long v0 __asm("$0");
384
385 __asm volatile("call_pal %1 # PAL_OSF1_rdmces"
386 : "=r" (v0)
387 : "i" (PAL_OSF1_rdmces)
388 /* clobbers t0, t8..t11 */
389 : "$1", "$22", "$23", "$24", "$25");
390
391 return (v0);
392 }
393
394 static __inline unsigned long
alpha_pal_rdps(void)395 alpha_pal_rdps(void)
396 {
397 register unsigned long v0 __asm("$0");
398
399 __asm volatile("call_pal %1 # PAL_OSF1_rdps"
400 : "=r" (v0)
401 : "i" (PAL_OSF1_rdps)
402 /* clobbers t0, t8..t11 */
403 : "$1", "$22", "$23", "$24", "$25");
404
405 return (v0);
406 }
407
408 static __inline unsigned long
alpha_pal_rdunique(void)409 alpha_pal_rdunique(void)
410 {
411 register unsigned long v0 __asm("$0");
412
413 __asm volatile("call_pal %1 # PAL_rdunique"
414 : "=r" (v0)
415 : "i" (PAL_rdunique));
416
417 return (v0);
418 }
419
420 static __inline unsigned long
alpha_pal_rdusp(void)421 alpha_pal_rdusp(void)
422 {
423 register unsigned long v0 __asm("$0");
424
425 __asm volatile("call_pal %1 # PAL_OSF1_rdusp"
426 : "=r" (v0)
427 : "i" (PAL_OSF1_rdusp)
428 /* clobbers t0, t8..t11 */
429 : "$1", "$22", "$23", "$24", "$25");
430
431 return (v0);
432 }
433
434 static __inline unsigned long
alpha_pal_rdval(void)435 alpha_pal_rdval(void)
436 {
437 register unsigned long v0 __asm("$0");
438
439 __asm volatile("call_pal %1 # PAL_OSF1_rdval"
440 : "=r" (v0)
441 : "i" (PAL_OSF1_rdval)
442 /* clobbers t0, t8..t11 */
443 : "$1", "$22", "$23", "$24", "$25");
444
445 return (v0);
446 }
447
448 static __inline unsigned long
alpha_pal_swpctx(unsigned long ctx)449 alpha_pal_swpctx(unsigned long ctx)
450 {
451 register unsigned long a0 __asm("$16") = ctx;
452 register unsigned long v0 __asm("$0");
453
454 __asm volatile("call_pal %2 # PAL_OSF1_swpctx"
455 : "=r" (a0), "=r" (v0)
456 : "i" (PAL_OSF1_swpctx), "0" (a0)
457 /* clobbers t0, t8..t11, a0 (above) */
458 : "$1", "$22", "$23", "$24", "$25", "memory");
459
460 return (v0);
461 }
462
463 static __inline unsigned long
alpha_pal_swpipl(unsigned long ipl)464 alpha_pal_swpipl(unsigned long ipl)
465 {
466 register unsigned long a0 __asm("$16") = ipl;
467 register unsigned long v0 __asm("$0");
468
469 __asm volatile("call_pal %2 # PAL_OSF1_swpipl"
470 : "=r" (a0), "=r" (v0)
471 : "i" (PAL_OSF1_swpipl), "0" (a0)
472 /* clobbers t0, t8..t11, a0 (above) */
473 : "$1", "$22", "$23", "$24", "$25", "memory");
474
475 return (v0);
476 }
477
478 static __inline void
alpha_pal_tbi(unsigned long op,vaddr_t va)479 alpha_pal_tbi(unsigned long op, vaddr_t va)
480 {
481 register unsigned long a0 __asm("$16") = op;
482 register unsigned long a1 __asm("$17") = va;
483
484 __asm volatile("call_pal %2 # PAL_OSF1_tbi"
485 : "=r" (a0), "=r" (a1)
486 : "i" (PAL_OSF1_tbi), "0" (a0), "1" (a1)
487 /* clobbers t0, t8..t11, a0 (above), a1 (above) */
488 : "$1", "$22", "$23", "$24", "$25");
489 }
490
491 static __inline unsigned long
alpha_pal_whami(void)492 alpha_pal_whami(void)
493 {
494 register unsigned long v0 __asm("$0");
495
496 __asm volatile("call_pal %1 # PAL_OSF1_whami"
497 : "=r" (v0)
498 : "i" (PAL_OSF1_whami)
499 /* clobbers t0, t8..t11 */
500 : "$1", "$22", "$23", "$24", "$25");
501
502 return (v0);
503 }
504
505 static __inline void
alpha_pal_wrfen(unsigned long onoff)506 alpha_pal_wrfen(unsigned long onoff)
507 {
508 register unsigned long a0 __asm("$16") = onoff;
509
510 __asm volatile("call_pal %1 # PAL_OSF1_wrfen"
511 : "=r" (a0)
512 : "i" (PAL_OSF1_wrfen), "0" (a0)
513 /* clobbers t0, t8..t11, a0 (above) */
514 : "$1", "$22", "$23", "$24", "$25");
515 }
516
517 static __inline void
alpha_pal_wripir(unsigned long cpu_id)518 alpha_pal_wripir(unsigned long cpu_id)
519 {
520 register unsigned long a0 __asm("$16") = cpu_id;
521
522 __asm volatile("call_pal %1 # PAL_ipir"
523 : "=r" (a0)
524 : "i" (PAL_ipir), "0" (a0)
525 /* clobbers t0, t8..t11, a0 (above) */
526 : "$1", "$22", "$23", "$24", "$25");
527 }
528
529 static __inline void
alpha_pal_wrunique(unsigned long unique)530 alpha_pal_wrunique(unsigned long unique)
531 {
532 register unsigned long a0 __asm("$16") = unique;
533
534 __asm volatile("call_pal %1 # PAL_wrunique"
535 : "=r" (a0)
536 : "i" (PAL_wrunique), "0" (a0));
537 }
538
539 static __inline void
alpha_pal_wrusp(unsigned long usp)540 alpha_pal_wrusp(unsigned long usp)
541 {
542 register unsigned long a0 __asm("$16") = usp;
543
544 __asm volatile("call_pal %1 # PAL_OSF1_wrusp"
545 : "=r" (a0)
546 : "i" (PAL_OSF1_wrusp), "0" (a0)
547 /* clobbers t0, t8..t11, a0 (above) */
548 : "$1", "$22", "$23", "$24", "$25");
549 }
550
551 static __inline void
alpha_pal_wrmces(unsigned long mces)552 alpha_pal_wrmces(unsigned long mces)
553 {
554 register unsigned long a0 __asm("$16") = mces;
555
556 __asm volatile("call_pal %1 # PAL_OSF1_wrmces"
557 : "=r" (a0)
558 : "i" (PAL_OSF1_wrmces), "0" (a0)
559 /* clobbers t0, t8..t11 */
560 : "$1", "$22", "$23", "$24", "$25");
561 }
562
563 static __inline void
alpha_pal_wrval(unsigned long val)564 alpha_pal_wrval(unsigned long val)
565 {
566 register unsigned long a0 __asm("$16") = val;
567
568 __asm volatile("call_pal %1 # PAL_OSF1_wrval"
569 : "=r" (a0)
570 : "i" (PAL_OSF1_wrval), "0" (a0)
571 /* clobbers t0, t8..t11, a0 (above) */
572 : "$1", "$22", "$23", "$24", "$25");
573 }
574
575 #endif /* _KERNEL */
576
577 #endif /* __ALPHA_ALPHA_CPU_H__ */
578